Display device and method of manufacturing display device

Abstract

This display device includes: a substrate including a first surface, and a second surface located on the opposite side from the first surface; a through-hole penetrating between the first surface and the second surface; a conductor packed in the through-hole and having a first conductive material; a plurality of bumps having the first conductive material on the first surface; and a plurality of LED chips on the plurality of bumps. The conductor may be spaced apart from the plurality of bumps.

Description

Display device and method for manufacturing the same

[0001] One embodiment of the present invention relates to a display device and a method for manufacturing the same. In particular, it relates to a display device in which LED (Light Emitting Diode) chips are mounted and a method for manufacturing the same.

[0002] In recent years, as a next-generation display, development of a so-called micro-LED display in which minute micro-LEDs are arranged in pixels has been advanced. A micro-LED is a self-emitting element similar to an OLED (Organic Light Emitting Diode). However, unlike an OLED, since it is composed of a stable inorganic compound containing gallium (Ga) or indium (In) or the like, a micro-LED display is more likely to ensure high reliability as compared with an OLED display. Further, a micro-LED has high luminous efficiency and can achieve high brightness. Therefore, a micro-LED display is expected as a next-generation display having high reliability, high brightness, and high contrast.

[0003] In a display equipped with an OLED, an OLED is directly formed on a substrate including a backplane on which a thin film transistor (TFT: Thin Film Transistor) is manufactured. On the other hand, in a micro-LED display, an LED chip manufactured on a sapphire substrate or the like is taken out and mounted on a substrate including a backplane using bumps such as a conductive paste or a solder paste.

[0004] Japanese Patent Application Laid-Open No. 2021-015859

[0005] In addition to using a conductive paste or a solder paste or the like for the bumps, a metal film formed by an electroplating method can be used. When the bumps are formed by the electroplating method, a power supply electrode arranged on the outer peripheral portion of the substrate is used as an anode, and a seed layer arranged on the substrate is used as a cathode. The seed layer plays a role of ensuring conductivity and serving as a seed for growing a metal film.

[0006] However, because the seed layer is formed from a thin metal film, the growth rate of the plating can differ between the center and the periphery of the substrate due to the voltage drop caused by resistance. In other words, there is a difference in height between the bumps in the center of the substrate, which are far from the power supply electrodes, and the bumps near the outer edge of the substrate, which are close to the power supply electrodes, resulting in the bumps further away from the power supply electrodes being shorter.

[0007] One embodiment of the present invention aims to provide a display device in which the bump height is uniform within the plane of the substrate. Another embodiment of the present invention aims to provide a method for manufacturing a display device in which the bump height is uniform within the substrate.

[0008] One embodiment of the present invention is a display device. The display device includes a substrate including a first surface and a second surface located opposite the first surface, through holes penetrating between the first surface and the second surface, a conductor filling the through holes and having a first conductive material, a plurality of bumps on the first surface having the first conductive material, and a plurality of LED chips on the plurality of bumps.

[0009] One embodiment of the present invention is a method for manufacturing a display device. The method for manufacturing a display device involves forming through holes through a first surface of a substrate and a second surface located opposite the first surface, applying a conductor having a first conductive material continuous with the through holes from the second surface, forming a backplane and a power supply section on the first surface, forming a seed layer having a first conductive material on the first surface, forming a second conductive layer on the seed layer, removing the seed layer and the conductor on the second surface that are exposed from the second conductive layer on the first surface, and mounting a plurality of LED chips on the second conductive layer.

[0010] This is a plan view showing the general configuration of a display device according to one embodiment of the present invention. This is a block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. This is an example of a circuit diagram showing the configuration of the pixel circuit of a display device according to one embodiment of the present invention. This is a plan view showing the configuration of the pixels of a display device according to one embodiment of the present invention. This is an end view showing the configuration of the pixels of a display device according to one embodiment of the present invention. This is a flowchart showing the manufacturing method of a display device according to one embodiment of the present invention. This is an end view showing the manufacturing method of a display device according to one embodiment of the present invention. This is an end view showing the manufacturing method of a display device according to one embodiment of the present invention. This is an end view showing the manufacturing method of a display device according to one embodiment of the present invention. This is an end view showing the manufacturing method of a display device according to one embodiment of the present invention. This is an end view showing the manufacturing method of a display device according to one embodiment of the present invention. This is an end view showing the manufacturing method of a display device according to one embodiment of the present invention. This is an end view showing the manufacturing method of a display device according to one embodiment of the present invention. This is an end view showing the manufacturing method of a display device according to one embodiment of the present invention.

[0011] Embodiments of the present invention will be described below with reference to the drawings, etc. However, the present invention can be implemented in various forms without departing from its essence. The present invention is not to be interpreted as being limited to the embodiments described below. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the drawings are merely examples and do not limit the interpretation of the present invention.

[0012] When describing embodiments of the present invention, the direction from the substrate toward the LED chip is referred to as "up," and the opposite direction is referred to as "down." However, the expressions "up" or "down" merely describe the upper limit relationship of each element. For example, the expression that an LED chip is placed on a substrate includes cases where other components are interposed between the substrate and the LED chip. Furthermore, the expressions "up" or "down" include not only cases where each element overlaps in a plan view, but also cases where they do not overlap.

[0013] When describing embodiments of the present invention, elements having similar functions to those already described may be given the same reference numeral or the same reference numeral with an alphabet or other symbol attached, and their description may be omitted. Furthermore, if it is necessary to describe a certain element separately for each of the RGB colors, the symbol R, G, or B will be added after the reference numeral indicating that element to distinguish it. However, if it is not necessary to describe that element separately for each of the RGB colors, only the reference numeral indicating that element will be used for description.

[0014] <First Embodiment> In this embodiment, a display device 10, which is one embodiment of the present invention, will be described.

[0015] (Configuration of the display device) Figure 1 is a plan view showing the schematic configuration of a display device according to one embodiment of the present invention. The display device 10 has a substrate 100, a flexible printed circuit board 160 (FPC 160), and an IC chip 170. The display device 10 includes a display area 112, a peripheral area 114, and a terminal area 116.

[0016] The display area 112 is an area in which multiple pixels 110, including LED chips 202, are arranged in the row direction (D1 direction) and column direction (D2 direction). Specifically, in this embodiment, pixels 110R including a red LED chip 202R, pixels 110G including a green LED chip 202G, and pixels 110B including a blue LED chip 202B are arranged. Figure 1 shows an example in which pixels 110R, 110G, and 110B are used as sub-pixels and these constitute a single pixel 110. The display area 112 functions as an area for displaying an image corresponding to a video signal.

[0017] The display area 112 is provided with through-holes 106. The through-holes 106 are holes that penetrate the substrate 100, although details will be described later. The through-holes 106 are filled with a conductor 108. The through-holes 106 are preferably located near the center of the display area 112. The through-holes 106 include multiple through-holes 106, which are scattered throughout the display area 112. The through-holes 106 are located between multiple pixels 110. The through-holes 106 may be located between pixel 110-1 and pixel 110-2. The through-holes 106 may be located between the LED chip 202B of pixel 110-1 and the LED chip 202R of pixel 110-2. In Figure 1, the through-holes 106 are located between multiple adjacent pixels 110 in the D1 direction, but the through-holes may be located between multiple adjacent pixels 110 in the D2 direction. Alternatively, the through-hole 106 may be positioned between a plurality of sub-pixels (110R, 110G, 110B).

[0018] Figure 1 shows an example in which one through-hole 106 is provided for each pixel 110, but one through-hole 106 may be provided for multiple pixels 110, and there are no restrictions on the number or arrangement of the through-holes 106. Furthermore, the shape of the through-hole 106 may be circular or rectangular, and there are no restrictions on its shape.

[0019] The peripheral region 114 is the area surrounding the display region 112. The peripheral region 114 is an area where driver circuits (data driver circuit 130 and gate driver circuit 140 shown in Figure 2) for controlling the pixel circuits (pixel circuits 120 shown in Figure 2) provided in each pixel 110, and a power supply unit 118 that supplies current used when forming bumps by electroplating are provided.

[0020] The power supply unit 118 functions as a power source that conducts current between two electrodes, with the seed layer (described later) acting as the negative side (cathode) and the metal used for the bump acting as the positive side (anode). The power supply unit 118 includes multiple power supply units 118, which are arranged to surround the display area 112. In Figure 1, multiple power supply units 118 are arranged facing each other in the row direction (D1 direction) and multiple power supply units 118 are arranged on one side in the column direction (D2 direction). However, multiple power supply units 118 may also be arranged facing each other in the column direction, and the number of power supply units 118 is not limited.

[0021] The terminal area 116 is an area where multiple wires connected to the aforementioned driver circuit are concentrated. The flexible printed circuit board 160 is electrically connected to the multiple wires in the terminal area 116. Video signals (data signals) or control signals output from an external device (not shown) are input to the IC chip 170 via wiring (not shown) provided on the flexible printed circuit board 160. The IC chip 170 performs various signal processing on the video signals and generates control signals necessary for display control. The video signals and control signals output from the IC chip 170 are input to the display device 10 via the flexible printed circuit board 160.

[0022] (Circuit Configuration of Display Device) Figure 2 is a block diagram showing the circuit configuration of a display device 10 according to one embodiment of the present invention. As shown in Figure 2, a pixel circuit 120 is provided in the display area 112, corresponding to each pixel 110. In this embodiment, a pixel circuit 120R, a pixel circuit 120G, and a pixel circuit 120B are provided, corresponding to pixels 110R, 110G, and 110B, respectively. That is, a plurality of pixel circuits 120 are arranged in the row direction (D1 direction) and the column direction (D2 direction) in the display area 112.

[0023] Figure 3 is a circuit diagram showing the configuration of a pixel circuit 120 of a display device 10 according to one embodiment of the present invention. The pixel circuit 120 is arranged in the region surrounded by data lines 121, gate lines 122, anode power lines 123, and cathode power lines 124. The pixel circuit 120 of this embodiment includes a selection transistor 126, a drive transistor 127, a holding capacitor 128, and an LED 129. The LED 129 corresponds to the LED chip 202 shown in Figure 1. Of the pixel circuit 120, the circuit elements other than the LED 129 correspond to the drive circuit provided on the substrate 100. In other words, the pixel circuit 120 is completed when the LED chip 202 is mounted on the substrate 100.

[0024] As shown in Figure 3, the source electrode, gate electrode, and drain electrode of the selection transistor 126 are connected to the data line 121, gate line 122, and gate electrode of the drive transistor 127, respectively. The source electrode, gate electrode, and drain electrode of the drive transistor 127 are connected to the anode power line 123, the drain electrode of the selection transistor 126, and the LED 129, respectively. A retaining capacitor 128 is connected between the gate electrode and source electrode of the drive transistor 127. That is, the retaining capacitor 128 is connected to the drain electrode of the selection transistor 126. The anode and cathode of the LED 129 are connected to the drain electrode of the drive transistor 127 and the cathode power line 124, respectively.

[0025] Data line 121 is supplied with a gradation signal that determines the light intensity of LED 129. Gate line 122 is supplied with a gate signal to select the selection transistor 126 that writes the gradation signal. When the selection transistor 126 is turned ON, the gradation signal is stored in the holding capacitor 128. Then, when the drive transistor 127 is turned ON, a drive current corresponding to the gradation signal flows through the drive transistor 127. When the drive current output from the drive transistor 127 is input to LED 129, LED 129 lights up with a light intensity corresponding to the gradation signal.

[0026] Referring again to Figure 2, a data driver circuit 130 is positioned adjacent to the display area 112 in the column direction (D2 direction). A gate driver circuit 140 is positioned adjacent to the display area 112 in the row direction (D1 direction). In this embodiment, two gate driver circuits 140 are provided on both sides of the display area 112, but only one of them may be provided.

[0027] The data driver circuit 130 and the gate driver circuit 140 are both located in the peripheral region 114. However, the region in which the data driver circuit 130 is located is not limited to the peripheral region 114. For example, the data driver circuit 130 may be located on the flexible printed circuit board 160.

[0028] The data line 121 shown in Figure 3 extends from the data driver circuit 130 in the D2 direction and is connected to the source electrode of the selection transistor 126 in each pixel circuit 120. The gate line 122 extends from the gate driver circuit 140 in the D1 direction and is connected to the gate electrode of the selection transistor 126 in each pixel circuit 120.

[0029] A terminal section 150 is located in the terminal region 116. The terminal section 150 is connected to the data driver circuit 130 via connection wiring 151. Similarly, the terminal section 150 is connected to the gate driver circuit 140 via connection wiring 152. Furthermore, the terminal section 150 is connected to the flexible printed circuit board 160.

[0030] (Pixel Structure) Figure 4 is a plan view showing the pixel configuration of a display device according to one embodiment of the present invention. Specifically, it is an enlarged plan view of the portion 300 shown in Figure 1. An LED chip 202 and a bump 204 are arranged in the pixel 110. In Figure 4, the LED chip 202 is shown with a dashed line. As shown in Figure 4, the pixel 110 may include areas where a red LED chip 202R, a green LED chip 202G, and a blue LED chip 202B are arranged.

[0031] Bumps 204 are placed in the area where the LED chip 202 is positioned. The bumps 204 are electrodes for mounting the LED chip 202 onto the substrate 100. The shape of the bumps 204 in plan view is arbitrary and can be appropriately designed to suit the electrode shape and electrode arrangement of the LED chip 202.

[0032] As shown in Figure 4, the red LED chip 202R, green LED chip 202G, and blue LED chip 202B, which are arranged in the pixel 110, are arranged on bumps 204R, 204G, and 204B, respectively. Bump 204 includes a pair of bumps 204-1 and 204-2, as shown in Figure 4, with one bump 204-1 electrically connected to the cathode power line 124 and the other bump 204-2 electrically connected to the anode power line 123. The LED chip 202 shown in Figure 4 describes an LED chip 202 employing a flip-chip structure, but the LED chip according to one embodiment of the present invention is not limited to a flip-chip structure.

[0033] Bumps 204-1 connected to the red LED chip 202R, green LED chip 202G, and blue LED chip 202B can be formed on a common electrode 132. Bumps 204-2 connected to the red LED chip 202R, green LED chip 202G, and blue LED chip 202B can be formed on an electrode 134 that is electrically connected to the drive transistor 127 of each subpixel. In this case, the through-hole 106 may be placed between a plurality of common electrodes 132. The through-hole 106 may be placed between bumps 204 connected to the LED chips 202 of adjacent pixels 110. For example, a through-hole 106 may be placed between bump 204B-1 connected to the LED chip 202B of pixel 110-5 and bump 204R-1 connected to the LED chip 202R of pixel 110-6.

[0034] The bump 204 is formed of multiple layers. As shown in Figure 4, the bump 204R-1 may include a first conductive layer 206 and a second conductive layer 208. The second conductive layer 208 is laminated on top of the first conductive layer 206. The sizes of the first conductive layer 206 and the second conductive layer 208 in plan view may differ, and the first conductive layer 206 may be larger than the second conductive layer 208. That is, the outer peripheral edge (contour) of the first conductive layer 206 may be located outside the outer peripheral edge (contour) of the second conductive layer 208.

[0035] Next, with reference to Figure 5, the cross-sectional structure of the bump 204 and the substrate 100 will be described. Figure 5 is an end view showing the pixel configuration of a display device according to one embodiment of the present invention. Specifically, Figure 5 is an end view along the line A1-A2 in Figure 1. In Figure 5, the same reference numerals are used for the same components of the display device 10 shown in Figure 1, and redundant explanations are omitted.

[0036] The substrate 100 includes a first surface 101 and a second surface 102 located opposite the first surface. The substrate 100 can be made of alkali-free glass, quartz glass, soda-lime glass, alkali glass, or the like. The substrate 100 includes through holes 106, and a backplane 180, a power supply section 118, and an LED chip 202 are formed on the first surface 101.

[0037] The backplane 180 includes a circuit for controlling the LED chip 202, and for example, the configuration of the display device circuit and pixel circuit shown in Figures 2 and 3. Known configurations can be used for the display device circuit and pixel circuit. An opening 136 corresponding to the through hole 106 is formed in the backplane 180. A conductor 108 is filled in part of the opening 136.

[0038] The through-hole 106 penetrates between the first surface 101 and the second surface 102 of the substrate 100. In Figure 5, the through-hole 106 has the same width from the first surface 101 to the second surface 102, but the through-hole 106 only needs to penetrate between the first surface 101 and the second surface 102, and the width of the through-hole 106 on the first surface 101 and the second surface 102 may be large, while the width of the through-hole 106 between the first surface 101 and the second surface 102 may be small. Alternatively, the width of the through-hole 106 on the first surface 101 and the second surface 102 may be small, while the width of the through-hole 106 between the first surface 101 and the second surface 102 may be large. The through-hole 106 is filled with a conductor 108.

[0039] The conductor 108 is filled into the through-hole 106 so that conductivity can be established from the first surface 101 to the second surface 102 of the substrate 100. The conductor 108 filled into the through-hole 106 is continuous with the conductor 108 filled into a part of the opening 136. The conductor 108 is separated from the multiple bumps 204. The upper surface 1081 of the conductor 108 is recessed into the substrate 100 from the surface 1801 of the backplane 180 that faces the first surface 101 of the substrate 100. In the thickness direction of the substrate 100, the upper surface 1081 of the conductor 108 is lower than the surface 1801 of the backplane 180. The lower surface 1082 of the conductor 108 is recessed into the substrate 100 from the second surface 102 of the substrate 100. The lower surface 1082 of the conductor 108 is higher than the second surface 102 of the substrate 100 in the thickness direction of the substrate 100.

[0040] The conductor 108 has a conductive material that has electrical conductivity. The conductor 108 has a conductive material that is used as a seed layer when forming a metal thin film by electroplating. Preferably, the conductor 108 is a conductor in which metal nanoparticles of several to tens of nanometers in size, such as conductive copper nanoink, are dispersed in a liquid. Examples of conductive materials include copper (Cu). By providing the conductor 108 in through holes 106 that are scattered within the display area 112, it can contribute to the dissipation of heat generated by the light emission of the LED chip 202.

[0041] The LED chip 202 is mounted on the first surface 101. The LED chip 202 is mounted on a bump 204 on the first surface 101. The LED chip 202 may have a structure in which these layers are stacked, for example, including a p-type semiconductor layer, an active layer (emissive layer), and an n-type semiconductor layer, and an anode 210 and a cathode 212 are electrically connected to the p-type semiconductor layer and the n-type semiconductor layer, respectively. As shown in Figure 5, the anode 210 is located on bump 204-2 and the cathode 212 is located on bump 204-1.

[0042] The p-type semiconductor layer, the active layer, and the n-type semiconductor layer are formed from a compound semiconductor containing, for example, group 13 and group 15 elements. More specifically, the compound semiconductor contains at least one element selected from aluminum, gallium, and indium as the group 13 element, and at least one element selected from nitrogen, phosphorus, and arsenic as the group 15 element. For example, the p-type and n-type semiconductor layers may be formed from gallium nitride (GaN). Magnesium and beryllium can be used as dopants for the p-type semiconductor layer (p-type gallium nitride layer), and silicon, germanium, and oxygen can be used as dopants for the n-type semiconductor layer (n-type gallium nitride layer). The active layer may have a single-layer structure or a quantum well structure. A quantum well structure is a structure in which multiple thin films with different band gaps and thicknesses of approximately 1 to 5 nm are alternately stacked. Examples include alternating stacks of InGaN and GaN, alternating stacks of GaInAsP and InP, and alternating stacks of AlInAs and InGaAs.

[0043] The anode 210 is also called the p-electrode, and the cathode 212 is also called the n-electrode. The anode 210 and cathode 212 are formed using a metallic material and preferably have a metallic surface such as gold (Au) or silver (Ag).

[0044] The bump 204 is disposed on the first surface 101 of the substrate 100. The bump 204 is spaced apart from the conductor 108 of the through hole 106. The bump 204 electrically connects the LED chip 202 to the common electrode and the pixel electrode that are electrically connected to the cathode power line 124 and the anode power line 123. The bump 204 includes a laminated structure. The bump 204 includes a first conductive layer 206 and a second conductive layer as shown in FIG. 5. The first conductive layer 206 is formed on the first surface 101, and the second conductive layer 208 is formed on the first conductive layer 206. An anode 210 or a cathode 212 is disposed on the second conductive layer 208. The second conductive layer includes a laminated structure and includes a second conductive layer 208-1 and a second conductive layer-2. The second conductive layer 208-1 is formed on the first conductive layer 206, and the second conductive layer 208-2 is formed on the second conductive layer 208-1.

[0045] The first conductive layer 206 can use the same material as the conductor 108 and has the same material as the conductor 108. The second conductive layer 208 can use a conductive material capable of forming a metal thin film by an electroplating method. Examples of the conductive material of the metal thin film include copper (Cu), nickel (Ni), chromium (Cr), gold (Au), zinc (Zn), silver (Ag), tin (Sn), and the like. When the laminated structure is included in the second conductive layer 208, for example, a Ni metal thin film may be used for the second conductive layer 208-1 and a Sn metal thin film may be used for the second conductive layer 208-2.

[0046] In the display device 10, a through hole 106 is formed in the substrate 100 on which the LED chip 202 is mounted, and the through hole 106 is filled with the conductor 108, so that it can contribute to the heat dissipation accompanying the light emission of the LED chip 202.

[0047] <Second Embodiment> In this embodiment, a manufacturing method of the display device 10 according to one embodiment of the present invention will be described. Descriptions of configurations that are the same as or similar to those of the first embodiment may be omitted.

[0048] FIG. 6 is a flowchart showing a method for manufacturing the display device 10 of the present invention. Specifically, before forming the backplane on the substrate 100, through holes 106 are formed in the substrate 100, conductors are applied to the surfaces of the through holes 106 and the substrate 100, and after forming the bumps 204, the LED chips 202 are mounted. FIGS. 7 to 16 are end views showing a method for manufacturing a display device according to an embodiment of the present invention. In FIGS. 7 to 16, the detailed configuration of the backplane is omitted.

[0049] First, in step S110 of FIG. 6, through holes 106 are formed in the substrate 100. Examples of the method for forming the through holes 106 include, for example, micro through hole processing (TGV: Through-Glass Vias). First, a modified layer is formed from the first surface 101 and the second surface 102 of the substrate 100 using a laser, and then wet or dry etching is performed along the modified layer formed from the first surface 101 to the second surface 102 to form the through holes 106 shown in FIG. 7. Lasers used for forming the modified layer can include femtosecond lasers, picosecond lasers, and ultrashort pulse lasers. For etching the modified layer, a method capable of eroding a portion along the modified layer may be used, and hydrofluoric acid (HF) etching or the like can be used.

[0050] Next, in step S120 of FIG. 6, a conductor 108 is applied to the second surface 102 of the substrate 100 and to the through holes 106. First, an electrode layer 138 is formed on the second surface 102 of the substrate using a conductor 108-1 containing the same conductive material as the conductor 108-2 applied to the through holes 106. For forming the electrode layer 138, methods such as sputtering can be used. Next, using the electrode layer 138 as a seed layer, the conductor 108-2 is deposited and filled in the through holes 106 using an electroplating method. When the through holes 106 are filled with the conductor 108-2, the conductor 108-1 of the electrode layer 138 and the conductor 108-2 of the through holes 106 are continuous, and the electrode layer 138 and the conductor 108-2 are electrically connected. For the method of filling the through holes 106 with the conductor 108-2, a method other than electroplating, such as screen printing, may be used.

[0051] After applying the conductor 108 to the second surface 102 and through-holes 106 of the substrate 100, a protective film 142 may be formed on the conductor 108-1 (electrode layer 138) on the second surface 102, as shown in Figure 9. By forming the protective film 142, damage to the conductor 108-1 can be prevented. By using a conductor 108-1 with little or no damage for the formation of the second conductive layer 208 described later, current can be flowed evenly through the seed layer 144. A resin such as a UV-curing resin can be used for the protective film 142. The protective film 142 can be formed by applying a resin to the conductor 108-1 and irradiating the resin with ultraviolet light.

[0052] Next, in step S130 of Figure 6, the backplane 180 and the power supply unit 118 are formed on the first surface 101 of the substrate 100. As shown in Figure 10, the backplane 180 is formed on the first surface 101 of the substrate 100. The backplane 180 can be formed using a known manufacturing method. The power supply unit 118 is formed on the backplane 180. After the formation of the backplane 180 or the power supply unit 118, an opening 136 is formed at a location and size corresponding to the through hole 106. The opening 136 is formed to be continuous with the through hole 106.

[0053] Furthermore, in step S140 of Figure 6, a seed layer 144 is formed on the first surface 101 of the substrate 100. As shown in Figure 11, the seed layer 144 is formed on the backplane 180 and the power supply unit 118, as well as within the opening 136. The seed layer 144 is formed on the power supply unit 118 so as to be electrically connected to the power supply unit 118. By being formed within the opening 136, the seed layer 144 is continuous and electrically connected to the conductor 108-2 of the through hole 106. Due to the electrical connection between the seed layer 144 and the conductor 108-2 of the through hole 106, the power supply unit 118 and the conductor 108-2 of the through hole 106 are electrically connected. The same method as for the electrode layer 138 can be used to form the seed layer 144. Note that a part of the seed layer 144 corresponds to the first conductive layer 206 of the bump 204 which is formed later, and the seed layer 144 is formed using the same material as the first conductive layer 206.

[0054] In step S150 of Figure 6, a second conductive layer 208 is formed on the seed layer 144. As shown in Figure 12, the resist 146 is patterned to match the shape of the bumps 204. The patterning of the resist 146 includes the steps of exposure, film formation, and etching.

[0055] After patterning the resist 146, the protective film 142 is peeled off. Known removal methods can be used to peel off the protective film 142. For example, if a UV-curing resin is used for the protective film 142, it can be peeled off using a solvent that dissolves the resin. In addition to the solvent-based peeling method, the protective film 142 can be peeled off by irradiating it with light of a specific wavelength. In this case, it is preferable that the resin of the protective film 142 contains a component that causes phase separation when irradiated with the above-mentioned specific wavelength of light.

[0056] Next, a second conductive layer 208 is formed on the seed layer 144. Electroplating is used to form the second conductive layer 208.

[0057] As shown in Figure 14, the protective film 142 is removed and the substrate 100 is fixed with the fixing and power supply jig 400. The fixed substrate 100 is immersed in the plating solution. The plating solution used is a solution containing metal ions of the conductive material of the second conductive layer 208. Power is supplied from the fixing and power supply jig 400 to the power supply unit 118 and the electrode layer 138. At this time, current is supplied from the fixing and power supply jig 400 to the power supply unit 118 and the electrode layer 138 of the second surface 102 so that the power supply unit 118 and the electrode layer 138 of the second surface 102 become cathodes. Since the electrode layer 138 of the second surface 102 is electrically connected to the conductor 108-2 of the through hole 106, current from the fixing and power supply jig 400 also flows to the conductor 108-2. The entire surface of the electrode layer 138 is in contact with the fixing and power supply jig 400 on the back side of the substrate 100. Therefore, the in-plane potential of the electrode layer 138 is constant, and the effect of voltage drop can be ignored. As a result, current flows uniformly from the electrode layer 138 to the conductors 108-2 formed at each position on the substrate 100, and the metal film grows by plating without being affected by the resistance loss due to the seed layer 144. In other words, because current flows from the conductors 108-2 to the seed layer 144 via the electrode layer 138 provided on the back surface of the substrate 100, the seed layer 144 at a location far from the power supply unit 118 flows with a current of the same magnitude as the seed layer 144 at a location close to the power supply unit 118, thus reducing the variation in the seed layer 144 current. With less variation in the current supplied to the seed layer 144, the variation in the film thickness of the second conductive layer 208 growing on the seed layer 144 is also reduced.

[0058] If the second conductive layer 208 has a laminated structure and is composed of a second conductive layer 208-1 and a second conductive layer 208-2, the second conductive layer 208-1 can be formed by electroplating, and then the second conductive layer 208-2 can be formed. Similarly, when the second conductive layer 208 has a laminated structure, current is supplied to the seed layer 144 from both the power supply unit 118 and the conductor 108-2, so for example, there is little variation in the film thickness of the second conductive layer 208-1 and the second conductive layer 208-2.

[0059] After forming the second conductive layer 208, the resist 146 is peeled off. A known peeling method can be used to peel off the resist 146.

[0060] In step S160 of Figure 6, the seed layer 144 and the conductor 108-2 are removed. The seed layer 144 exposed from the second conductive layer 208 is removed by etching or the like. The seed layer 144 is etched using the second conductive layer 208 as a mask. By removing the seed layer 144 exposed from the second conductive layer 208, the seed layer 144 located below the second conductive layer 208 remains and becomes the first conductive layer 206 of the bump 204. By removing the seed layer 144 exposed from the second conductive layer 208, the conductor 108-2 is separated from the seed layer 144, and the separated seed layer 144 becomes the first conductive layer 206 of the bump 204. The conductive layer formed as the seed layer 144 functions as part of the bump 204.

[0061] Regarding the removal of the conductor 108-2, a portion of the conductor 108-2 in the opening 136 is removed along with the removal of the seed layer 144. Depending on the etching conditions of the seed layer 144, a portion of the conductor 108-2 filling the through hole 106 may also be removed. As a result of the removal of a portion of the conductor 108-2 in the opening 136, the upper surface 1081 of the conductor 108-2 is recessed into the substrate 100 from the surface 1801 of the backplane 180 that faces the first surface 101, as shown in Figure 16. If a portion of the conductor 108-2 filling the through hole 106 is removed as described above, the upper surface 1081 of the conductor 108-2 is recessed into the substrate 100 from the first surface 101 of the substrate 100.

[0062] In step S160 of Figure 6, the electrode layer 138 is removed in the same manner. Along with the removal of the electrode layer 138, a portion of the conductor 108-2 filling the through hole 106 is also removed, as shown in Figure 16. The lower surface 1082 of the conductor 108-2 is recessed into the substrate 100 from the second surface 102 of the substrate 100. In the thickness direction of the substrate 100, the lower surface 1082 of the conductor 108-2 is higher than the second surface 102 of the substrate 100.

[0063] The conductor 108-2 remains in the substrate 100, except for the portion removed in step S160.

[0064] Through the above process, a bump 204 including the first conductive layer 206 and the second conductive layer 208 is formed.

[0065] Finally, in step S170 of Figure 6, the LED chip 202 is mounted on the second conductive layer 208. Known mounting methods can be used to mount the LED chip 202. For example, the LED chip 202 can be mounted by transferring it onto the substrate 100 and applying pressure between the substrate 100 and the LED chip 202. The LED chip 202 can be manufactured using known manufacturing methods. For example, the LED chip 202 can be manufactured by using a crystalline substrate such as sapphire, forming electrodes on a crystal grown on the crystalline substrate, and then cutting it out.

[0066] As described above, the display device 10 can be manufactured. In the manufacturing method of the display device 10, a through hole 106 is formed in the substrate 100, and a conductor 108 that is electrically connected to the power supply unit 118 is provided in the through hole 106. This allows the conductor 108 to supply power to the seed layer 144 in the same way as the power supply unit 118, and a bump 204 of uniform height with little variation can be formed.

[0067] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, devices based on the display devices of each embodiment, in which a person skilled in the art has added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0068] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.

[0069] 10: Display device, 100: Substrate, 101: First surface, 102: Second surface, 106: Through hole, 108: Conductor, 108-1: Conductor, 108-2: Conductor, 110: Pixel, 110-1: Pixel, 110-2: Pixel, 110-5: Pixel, 110-6: Pixel, 110B: Sub-pixel, 110G: Sub-pixel, 110R: Sub-pixel, 112: Display area, 114: Peripheral area, 116: Terminal area Area, 118: Power supply section, 120: Pixel circuit, 120B: Pixel circuit, 120G: Pixel circuit, 120R: Pixel circuit, 121: Data line, 122: Gate line, 123: Anode power line, 124: Cathode power line, 126: Select transistor, 127: Drive transistor, 128: Holding capacitance, 130: Data driver circuit, 132: Electrode, 134: Electrode, 136: Aperture, 138: Electrode layer, 140: Gate driver circuit, 142: Protective film, 144: Seed layer, 146: Resist, 150: Terminal section, 151: Connection wiring, 152: Connection wiring, 160: Flexible printed circuit board, 170: Chip, 180: Backplane, 202: Chip, 202B: Chip, 202G: Chip, 202R: Chip, 204: Bump, 204-1: Bump 204-2: Bump, 204B: Bump, 204B-1: Bump, 204G: Bump, 204R: Bump, 204R-1: Bump, 206: First conductive layer, 208: Second conductive layer, 208-1: Second conductive layer, 208-2: Second conductive layer, 210: Anode, 212: Cathode, 300: Part, 400: Fixing / power supply jig, 1081: Top surface, 1082: Bottom surface, 1801: Surface

Claims

1. A display device comprising: a substrate including a first surface and a second surface located opposite the first surface; a through hole penetrating between the first surface and the second surface; a conductor filling the through hole and having a first conductive material; a plurality of bumps on the first surface having the first conductive material; and a plurality of LED chips on the plurality of bumps.

2. The display device according to claim 1, wherein the conductor is spaced apart from the plurality of bumps.

3. The display device according to claim 1, wherein the plurality of LED chips include a first LED chip and a second LED chip, the plurality of bumps include a first bump connected to the first LED chip and a second bump connected to the second LED chip, and the through hole is located between the first bump and the second bump.

4. The display device according to claim 1, wherein a backplane is included between the substrate and the plurality of bumps, and the upper surface of the conductor is recessed into the substrate compared to the surface of the backplane facing the first surface.

5. A method for manufacturing a display device, comprising: forming through holes penetrating a first surface of a substrate and a second surface located opposite the first surface; applying a conductor having a first conductive material continuous with the through holes from the second surface; forming a backplane and a power supply section on the first surface; forming a seed layer having the first conductive material on the first surface; forming a second conductive layer on the seed layer; removing the seed layer and the conductor on the second surface that are exposed from the second conductive layer on the first surface; and mounting a plurality of LED chips on the second conductive layer.

6. The method for manufacturing a display device according to claim 5, wherein after applying the conductor, a protective film is formed on the conductor on the second surface.

7. The method for manufacturing a display device according to claim 5, wherein, after forming the seed layer, a patterned resist is formed on the seed layer.

8. The method for manufacturing a display device according to claim 5, wherein the second conductive layer is formed by an electroplating method.

9. After removing the seed layer exposed from the second conductive layer on the first surface, the upper surface of the conductor is recessed into the substrate from the surface of the backplane facing the first surface, the method for manufacturing a display device according to claim 5.

Images