Semiconductor relay
The semiconductor relay design addresses insertion loss and miniaturization challenges by optimizing terminal arrangements and using a wide connecting conductor to reduce parasitic inductance and capacitance, enhancing high-frequency signal transmission.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
- Filing Date
- 2025-11-20
- Publication Date
- 2026-07-23
AI Technical Summary
Conventional semiconductor relays face challenges with increased insertion loss at higher frequencies and are difficult to miniaturize due to parasitic capacitance and inductance components, especially in high-frequency signal transmission.
The semiconductor relay design includes a configuration with overlapping MOSFET elements and a connecting conductor that reduces parasitic inductance and capacitance by arranging terminals and electrodes in a manner that minimizes signal path length and uses a wide, flat connecting conductor to reduce inductance components.
This design achieves reduced insertion loss and miniaturization by minimizing parasitic inductance and capacitance, improving signal transmission characteristics and reflection characteristics in high-frequency ranges.
Smart Images
Figure JP2025040582_23072026_PF_FP_ABST
Abstract
Description
Semiconductor relay
[0001] This disclosure relates to a semiconductor relay.
[0002] Conventionally, as a signal transmission means, a semiconductor relay also called a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) output photocoupler or an optical MOSFET is known. In such a semiconductor relay, with the increase in the frequency of the transmission signal, an increase in insertion loss has been an issue.
[0003] To solve this issue, for example, the configuration shown in Patent Document 1 has been proposed. In the semiconductor relay disclosed in Patent Document 1, a light-emitting element placed on an input terminal and a light-receiving element placed on an output terminal are arranged to face each other inside a housing. Both the input terminal and the output terminal are bent once in the middle, and their tip portions protrude outside the housing along the lower surface of the housing.
[0004] When this semiconductor relay is mounted on a circuit board on which a signal line and a ground line are respectively formed on the upper surface, the distance between the light-receiving element and the element mounting portion of the input terminal on which the light-receiving element is placed and the ground plane formed on the lower surface of the ground line or the circuit board can be increased. Note that both the ground line and the ground plane are electrically connected to the ground potential. By this, the capacitance value of the parasitic capacitance generated between each mounting portion of the semiconductor relay and the ground potential can be reduced, and the insertion loss can be reduced.
[0005] Also, as shown in Patent Document 2, in a semiconductor relay, a thin electrode plate exposed on the lower surface of a package that seals each component is provided, and a configuration in which a drain electrode provided on the lower surface of a MOSFET, which is an output-side element, is connected to the upper surface of the electrode plate is known. Also, in this configuration, a light-receiving element that constitutes a photocoupler on the input side is placed on the upper surface of another electrode plate, and a light-emitting element is placed on the upper surface of the light-receiving element. According to the configuration disclosed in Patent Document 2, the inductance component of the electrode plate can be reduced, and the transmission loss of the high-frequency signal in the electrode plate can be reduced.
[0006] Japanese Patent Publication No. 2011-166077 Japanese Patent Publication No. 2021-125670
[0007] In recent years, there has been a demand for further miniaturization of semiconductor relays. Furthermore, there is a need for higher frequencies for signals transmitted via semiconductor relays, and consequently, a need for further improvement in the signal transmission characteristics in the high-frequency range.
[0008] The semiconductor relay according to this disclosure includes a first input terminal, a second input terminal, a light-emitting element electrically connected to the first input terminal and the second input terminal, a light-receiving element that receives light output from the light-emitting element and outputs a drive signal according to the received light, a first MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) element having a first output terminal, a second output terminal, a first gate electrode to which the drive signal is input, a first source electrode electrically connected to the light-receiving element, and a first drain electrode electrically connected to the first output terminal, a second MOSFET element having a second gate electrode to which the drive signal is input, a second source electrode electrically connected to the light-receiving element, and a second drain electrode electrically connected to the second output terminal, and a connecting conductor electrically connected to the first source electrode and the second source electrode. The first MOSFET element has a first upper surface on which the first gate electrode and the first source electrode are provided, and a first lower surface opposite to the first upper surface. The second MOSFET element has a second upper surface on which the second gate electrode and the second source electrode are provided, and a second lower surface opposite to the second upper surface. The first upper surface of the first MOSFET element has a first mounting portion on which the light-receiving driving element is mounted, and a first non-mounting portion on which the first gate electrode is provided and the light-receiving driving element is not mounted. The second upper surface of the second MOSFET element has a second mounting portion on which the light-receiving driving element is mounted, and a second non-mounting portion on which the second gate electrode is provided and the light-receiving driving element is not mounted. In a top view, the connecting conductor has a first connecting conductor portion that overlaps with the first MOSFET element, a second connecting conductor portion that overlaps with the second MOSFET element, and a third connecting conductor portion that electrically connects the first connecting conductor portion to the second connecting conductor portion and does not overlap with the first MOSFET element or the second MOSFET element. The connecting conductor is provided on the lower surface of the light-receiving driving element, and the light-emitting element is placed on the upper surface of the light-receiving driving element via a light-transmitting material.
[0009] According to this disclosure, semiconductor relays can be miniaturized. Furthermore, insertion losses can be reduced.
[0010] This is a perspective view of a semiconductor relay according to Embodiment 1. This is a view of the semiconductor relay according to Embodiment 1 from above. This is a view of the semiconductor relay according to Embodiment 1 from below. This is a view of the semiconductor relay according to Embodiment 1 along the X direction. This is a view of the semiconductor relay according to Embodiment 1 along the Y direction. This is an exploded perspective view of the semiconductor relay according to Embodiment 1. This is a perspective view of the light-emitting element. This is a perspective view of the light-receiving driving element. This is a perspective view of the first MOSFET element. This is an equivalent circuit diagram of the semiconductor relay. This is a perspective view of a semiconductor relay according to Embodiment 2. This is a view of the semiconductor relay according to Embodiment 2 from above. This is a view of the semiconductor relay according to Embodiment 2 from below. This is a view of the semiconductor relay according to Embodiment 2 along the X direction. This is a view of the semiconductor relay according to Embodiment 2 along the Y direction. This is a view of a modified semiconductor relay along the X direction. This is a view of another modified semiconductor relay along the X direction. This is a view of a semiconductor relay according to Embodiment 3 along the X direction. This is a view of the light-emitting element and light-receiving driving element from above. This is a view of an electrical component unit according to Embodiment 4 from above. This is a cross-sectional view taken along line XI-XI in Figure 10.
[0011] Embodiments of the present disclosure will be described below with reference to the drawings. The following description of preferred embodiments is illustrative in nature and is not intended to limit the present disclosure, its applications, or its uses.
[0012] (Embodiment 1) [Configuration of Semiconductor Relay] Figure 1A is a perspective view of the semiconductor relay according to Embodiment 1. Figure 1B is a view of the semiconductor relay according to Embodiment 1 from above. Figure 1C is a view of the semiconductor relay according to Embodiment 1 from below. Figure 1D is a view of the semiconductor relay according to Embodiment 1 along the X direction. Figure 1E is a view of the semiconductor relay according to Embodiment 1 along the Y direction.
[0013] Figure 2 is an exploded perspective view of a semiconductor relay according to Embodiment 1. Figure 3A is a perspective view of the light-emitting element. Figure 3B is a perspective view of the light-receiving driving element. Figure 3C is a perspective view of the first MOSFET element.
[0014] For the sake of clarity, the outlines of the housing 10 and the light-shielding resin 10a constituting it are shown with dashed lines in Figures 1A to 1E. Also, the housing 10 is not shown in Figure 2.
[0015] In the following explanation, the direction in which the first input terminal 6 and the first output terminal 8 face each other may be referred to as the first direction or the X direction. The first direction or the X direction is also the direction in which the second input terminal 7 and the second output terminal 9 face each other.
[0016] Furthermore, the direction in which the first input terminal 6 and the second input terminal 7 are aligned is sometimes called the second direction or the Y direction. The second direction or Y direction is also the direction in which the first output terminal 8 and the second output terminal 9 are aligned.
[0017] The direction perpendicular to the first and second directions is sometimes referred to as the third direction or the Z direction. In the third direction, the side where the light-emitting element 2 is located is sometimes referred to as the top or upper side, and the side where the first input terminal 6 and the first output terminal 8 are located is sometimes referred to as the bottom or lower side. In this specification, the terms "top" and "bottom" are purely relative and do not indicate absolute directions such as "up" or "down" along the vertical direction. Furthermore, the view of the semiconductor relay 1 or its components from above is referred to as a "top view."
[0018] In this specification, "orthogonal" or "parallel" means that the processing tolerances and manufacturing tolerances of each component constituting the semiconductor relay 1, as well as the assembly tolerances between the components, are orthogonal or parallel. It does not mean that the comparison objects themselves are orthogonal or parallel in a strict sense.
[0019] As shown in Figures 1A to 1E, the semiconductor relay 1 comprises a light-emitting element 2, a light-receiving driving element 5, a first MOSFET element 3, and a second MOSFET element 4. The semiconductor relay 1 also comprises a first input terminal 6, a second input terminal 7, a first output terminal 8, a second output terminal 9, and a housing 10.
[0020] The light-emitting element 2 is a known LED (Light Emitting Diode) element. As shown in Figure 3A, an anode electrode 2c and a cathode electrode 2d are formed on the upper surface 2a of the light-emitting element. As shown in Figures 1A, 1B, 1D, and 1E, the anode electrode 2c and the second wire connection portion 72 are electrically connected via a wire 11, which is a conductor. The upper surface of the second input terminal 7 corresponds to the second wire connection portion 72. Also, the cathode electrode 2d and the first wire connection portion 62 are electrically connected via a wire 11, which is a conductor. The upper surface of the first input terminal 6 corresponds to the first wire connection portion 62.
[0021] The light-receiving driving element 5 includes a light-receiving element 51 and a driving circuit 52 (see Figure 4). The light-receiving element 51 is, for example, made up of an array of known photodiodes. As shown in Figure 3B, a source electrode 5c and a drain electrode 5d are formed on the upper surface 5a of the light-receiving driving element 5. The drain electrode 5d is provided at two locations on the upper surface 5a that are spaced apart from each other. Although a light-receiving element 51 is also formed on the upper surface 5a of the light-receiving driving element 5, its illustration is omitted for the sake of explanation.
[0022] Furthermore, as shown in Figures 1C to 1E and Figure 3B, a connecting conductor 12 is formed on the lower surface 5b of the light-receiving driving element 5. The connecting conductor 12 is formed over the entire lower surface 5b of the light-receiving driving element 5. The connecting conductor 12 consists of one or more conductive films and is a layered or sheet-like conductive member. The structure and function of the connecting conductor 12 will be explained later.
[0023] As shown in Figure 1B, the source electrode 5c of the light-receiving driving element 5 and the second source electrode 4d of the second MOSFET element 4 are electrically connected via the wire 11. One of the two drain electrodes 5d, 5d of the light-receiving driving element 5 is electrically connected to the first gate electrode 3c of the first MOSFET element 3 via the wire 11. The other of the two drain electrodes 5d, 5d is electrically connected to the second gate electrode 4c of the second MOSFET element 4 via the wire 11.
[0024] Furthermore, as shown in Figure 1D, the light-emitting element 2 is mounted on the upper surface 5a of the light-receiving driving element 5, between two drain electrodes 5d, 5d via a light-transmitting resin 10b.
[0025] The first MOSFET element 3 is formed by forming a known vertical MOSFET on a semiconductor substrate. The first MOSFET element 3 is usually composed of multiple vertical MOSFETs connected in series or in parallel. However, it may also be a single vertical MOSFET. The upper surface 3a of the first MOSFET element 3 is sometimes called the first upper surface 3a, and the upper surface 4a of the second MOSFET element 4 is sometimes called the second upper surface 4a. The lower surface 3b of the first MOSFET element 3 is sometimes called the first lower surface 3b, and the lower surface 4b of the second MOSFET element 4 is sometimes called the second lower surface 4b.
[0026] As shown in Figure 3C, a first gate electrode 3c and a first source electrode 3d are formed on the first upper surface 3a of the first MOSFET element 3, and a first drain electrode 3e is formed on the first lower surface 3b. The first drain electrode 3e is formed over the entire surface of the first lower surface 3b of the first MOSFET element 3.
[0027] As shown in Figure 3C, the first source electrode 3d has a first electrode body portion 3d1 and a first enlarged electrode portion 3d2. The first enlarged electrode portion 3d2 is formed continuously with the first electrode body portion 3d1. Also, inside the semiconductor relay 1, when viewed along the Z direction, the first electrode body portion 3d1 has a portion that overlaps with the light-receiving driving element 5 (see Figures 1A and 1B).
[0028] Furthermore, the second MOSFET element 4 has the same structure as the first MOSFET element 3 (see Figure 3C). Therefore, the arrangement and shape of the second gate electrode 4c, the second source electrode 4d, and the second drain electrode 4e are the same as those of the first MOSFET element 3. In other words, the second source electrode 4d also has a second electrode body portion 4d1 and a second expanded electrode portion 4d2, and their shapes and arrangements are the same as those of the first electrode body portion 3d1 and the first expanded electrode portion 3d2, respectively. For example, when viewed along the Z direction, the second electrode body portion 4d1 has a portion that overlaps with the light-receiving driving element 5 (see Figures 1A and 1B). Also, the second source electrode 4d is formed on the second upper surface 4a of the second MOSFET element 4, and the second drain electrode 4e is formed on the second lower surface 4b of the second MOSFET element 4.
[0029] Furthermore, as shown in Figures 1D and 2, a first connector 13 is provided on the upper surface of the first electrode body 3d1 of the first source electrode 3d. A second connector 14 is provided on the upper surface of the second electrode body 4d1 of the second source electrode 4d.
[0030] Furthermore, as shown in Figures 1D and 2, the light-receiving driving element 5 is mounted on the first upper surface 3a and the second upper surface 4a via the first connector 13 and the second connector 14, respectively. Of the first upper surface 3a and the second upper surface 4a, the parts on which the light-receiving driving element 5 is mounted are sometimes called the first mounting section 3a1 and the second mounting section 4a1, respectively, and the parts on which the light-receiving driving element 5 is not mounted are sometimes called the first non-mounting section 3a2 and the second non-mounting section 4a2, respectively (see Figures 1B and 3C).
[0031] The first mounting portion 3a1 is provided with the first electrode body portion 3d1 of the first source electrode 3d, and the second mounting portion 4a1 is provided with the second electrode body portion 4d1 of the second source electrode 4d. The first non-mounting portion 3a2 is provided with the first enlarged electrode portion 3d2 and the first gate electrode portion 3c of the first source electrode 3d, and the second mounting portion 4a1 is provided with the second enlarged electrode portion 4d2 and the second gate electrode portion 4c of the second source electrode 4d.
[0032] Furthermore, the first drain electrode 3e of the first MOSFET element 3 is fixed to the first MOSFET mounting portion 82, which is the upper surface of the first output terminal 8, with a conductive adhesive material such as silver paste (not shown). The second drain electrode 4e of the second MOSFET element 4 is fixed to the second MOSFET mounting portion 92, which is the upper surface of the second output terminal 9, with a conductive adhesive material.
[0033] The first connector 13 and the second connector 14 are each made of a conductor, such as solder. However, the material and shape of the first connector 13 and the second connector 14 are not particularly limited, and for example, the first connector 13 and the second connector 14 may be bump electrodes or pillar electrodes. In this case, a plurality of first connectors 13 may be formed on the upper surface of the first electrode body portion 3d1 of the first source electrode 3d. A plurality of second connectors 14 may be formed on the upper surface of the second electrode body portion 4d1 of the second source electrode 4d.
[0034] The first connector 13 and the second connector 14 are electrically connected to the connecting conductor 12 formed on the lower surface 5b of the light-receiving driving element 5. More specifically, the first source electrode 3d of the first MOSFET element 3 and the second source electrode 4d of the second MOSFET element 4 are electrically connected via the connecting conductor 12, the first connector 13, and the second connector 14.
[0035] As shown in Figure 1D, the connecting conductor 12 has first to third connecting conductor portions 12a to 12c. The first connecting conductor portion 12a is the portion of the connecting conductor 12 that is positioned between the light-receiving driving element 5 and the first electrode body portion 3d1 of the first source electrode 3d, and is electrically connected to the first connector 13. The second connecting conductor portion 12b is the portion of the connecting conductor 12 that is positioned between the light-receiving driving element 5 and the second electrode body portion 4d1 of the second source electrode 4d, and is electrically connected to the second connector 14. The third connecting conductor portion 12c is the portion of the connecting conductor 12 that electrically connects the first connecting conductor portion 12a and the second connecting conductor portion 12b, and overlaps with the light-receiving driving element 5 when viewed along the Z direction.
[0036] In this embodiment, the connecting conductor 12, that is, the first to third connecting conductor portions 12a to 12c, is a continuous sheet-like conductive material. However, it is not limited to this, and the shapes and thicknesses of the first to third connecting conductor portions 12a to 12c may differ.
[0037] Furthermore, the size of the connecting conductor 12 is such that it is necessary to electrically connect the first connector 13 and the second connector 14. In other words, the width of the connecting conductor 12 in the Y direction is the same as or wider than the distance between the first connector 13 and the second connector 14 along the Y direction. This distance may be the distance D1, the distance D2, or the distance D3 shown in Figure 1D. Distance D1 is the distance along the Y direction between the side surface of the first connector 13 and the side surface of the second connector 14 that is adjacent to it. Distance D2 is the distance along the Y direction between the center line of the first connector 13 and the center line of the second connector 14. These center lines are imaginary lines that pass through the centers of the first connector 13 and the second connector 14, respectively, and extend in the Z direction. The spacing D3 is the distance along the Y direction between the side surface of the first connector 13 that is furthest from the second connector 14 along the Y direction and the side surface of the second connector 14 that is furthest from the first connector 13 along the Y direction.
[0038] Preferably, the width of the connecting conductor 12 along the X direction is the same as or wider than the length of the first connector 13 and the second connector 14 along the X direction. However, it is not limited to this, and if the connection resistance between the connecting conductor 12 and the first connector 13 and the second connector 14 is sufficiently low, the width of the connecting conductor 12 along the X direction may be narrower than the length of the first connector 13 and the second connector 14 along the X direction.
[0039] The first input terminal 6 and the second input terminal 7, as well as the first output terminal 8 and the second output terminal 9, are each thin metal plates formed by plating. The metal to be plated may be copper. Alternatively, another metal, such as nickel, may be further plated onto the surface of the copper.
[0040] In the semiconductor relay 1, the first input terminal 6 is arranged side by side with the second input terminal 7 in the Y direction, while being spaced apart from the second input terminal 7. The lower surface of the first input terminal 6 corresponds to the first input-side external terminal 61, and the upper surface of the first input terminal 6 corresponds to the first wire connection portion 62. Similarly, the lower surface of the second input terminal 7 corresponds to the second input-side external terminal 71, and the upper surface of the second input terminal 7 corresponds to the second wire connection portion 72.
[0041] One end of wire 11 is connected to the first wire connection portion 62 of the first input terminal 6, and the other end of wire 11 is connected to the cathode electrode 2d of the light-emitting element 2, as shown in Figure 1B. One end of wire 11 is connected to the second wire connection portion 72 of the second input terminal 7, and the other end of wire 11 is connected to the anode electrode 2c of the light-emitting element 2, as shown in Figure 1B.
[0042] The first output terminal 8 is positioned alongside the second output terminal 9 in the Y direction, but spaced apart from it. The lower surface of the first output terminal 8 corresponds to the first output-side external terminal 81, and the first MOSFET element 3 is mounted on its upper surface. In other words, the upper surface of the first output terminal 8 corresponds to the first MOSFET mounting section 82. Similarly, the lower surface of the second output terminal 9 corresponds to the second output-side external terminal 91, and the second MOSFET element 4 is mounted on its upper surface. In other words, the upper surface of the second output terminal 9 corresponds to the second MOSFET mounting section 92.
[0043] The first input-side external terminal 61 and the second input-side external terminal 71 are exposed on the lower surface of the housing 10. The first output-side external terminal 81 and the second output-side external terminal 91 are also exposed on the lower surface of the housing 10. This allows the semiconductor relay 1 to be surface-mounted on the circuit board 40 (see Figures 10 and 11). On the other hand, the first wire connection portion 62 and the second wire connection portion 72, as well as the first MOSFET mounting portion 82 and the second MOSFET mounting portion 92, are located inside the housing 10.
[0044] The housing 10 fixes the respective positions of the first input terminal 6, the second input terminal 7, the first output terminal 8, and the second output terminal 9. Further, the first MOSFET element 3 placed on the first MOSFET mounting portion 82 of the first output terminal 8 and the second MOSFET element 4 placed on the second MOSFET mounting portion 92 of the second output terminal 9 are sealed by the housing 10, and their respective positions are fixed. Further, the light receiving drive element 5 placed across the first mounting portion 3a1 of the first MOSFET element 3 and the second mounting portion 4a1 of the second MOSFET element 4, and the light emitting element 2 placed on the upper surface 5a of the light receiving drive element 5 are sealed by the housing 10, and their respective positions are fixed.
[0045] As shown in FIGS. 1D and 1E, the housing 10 is composed of an insulating light-shielding resin 10a and a light-transmitting resin 10b. The light-shielding resin 10a is, for example, an epoxy resin containing a black pigment. However, it is not particularly limited thereto, and any material that can shield light may be used. The light-transmitting resin 10b is provided between the light receiving drive element 5 and the light emitting element 2 and is sealed by the light-shielding resin 10a. The light-transmitting resin 10b is, for example, a transparent silicone resin. However, it is not particularly limited thereto, and any insulating resin that is at least transparent to the light emitted by the light emitting element 2 may be used. The light-transmitting resin 10b constitutes a light coupling portion that optically couples the light receiving element 51 of the light receiving drive element 5 and the light emitting element 2. [[ID=*]] [[ID=*]]
[0046] Further, the first input terminal 6 and the second input terminal 7, and the first output terminal 8 and the second output terminal 9 are electrically insulated from each other by the housing 10. Further, the light emitting element 2 and the light receiving drive element 5 are optically coupled. That is, the semiconductor relay 1 is an input / output insulation type semiconductor relay that turns on and off the output signal by optical coupling in a state where the input signal and the output signal are electrically insulated.
[0047] [Operation of Semiconductor Relay] FIG.
[0048] When an input signal is input between the first input terminal 6 and the second input terminal 7, the light-emitting element 2 outputs light of a predetermined wavelength. The light generated by the light-emitting element 2 propagates inside the translucent resin 10b and is received by the light-receiving element 51.
[0049] In the light-receiving element 51, a current is generated by photoelectric conversion, and based on this current, the drive circuit 52 operates. Through the wire 11, drive signals, which are voltage signals corresponding to the light amount of the light-emitting element 2, are applied to the first gate electrode 3c of the first MOSFET element 3 and the second gate electrode 4c of the second MOSFET element 4, respectively.
[0050] When the voltage of the drive signal exceeds the respective threshold voltages of the first MOSFET element 3 and the second MOSFET element 4, the source (S)-drain (D) between the first MOSFET element 3 and the source (S)-drain (D) between the second MOSFET element 4 are each in an on state. Further, through the first MOSFET element 3 and the second MOSFET element 4, the first output terminal 8 and the second output terminal 9 are in a conductive state. As a result, a signal is transmitted between the first output terminal 8 and the second output terminal 9.
[0051] When the input signal is no longer input between the first input terminal 6 and the second input terminal 7, the light emission from the light-emitting element 2 also stops. Accordingly, no current is generated in the light-receiving element 51, and the drive circuit 52 stops.
[0052] As a result, the voltages of the drive signals applied to the first gate electrode 3c of the first MOSFET element 3 and the second gate electrode 4c of the second MOSFET element 4 decrease. When the voltage of the drive signal falls below the above-described threshold voltage, the source (S)-drain (D) between the first MOSFET element 3 and the source (S)-drain (D) between the second MOSFET element 4 are each in an off state. Further, the first output terminal 8 and the second output terminal 9 are in a non-conductive state. As a result, the transmission of the signal between the first output terminal 8 and the second output terminal 9 is interrupted.
[0053] [Effects, etc.] As described above, the semiconductor relay 1 according to this embodiment comprises at least a light-emitting element 2, a first MOSFET element 3, a second MOSFET element 4, a light-receiving driving element 5, a first input terminal 6, a second input terminal 7, a first output terminal 8, a second output terminal 9, a housing 10, and a connecting conductor 12.
[0054] The light-emitting element 2 is electrically connected to the first input terminal 6 and the second input terminal 7.
[0055] The light-receiving driving element 5 has a light-receiving element 51 that receives light output from the light-emitting element 2, and outputs a driving signal according to the received light.
[0056] The first MOSFET element 3 has a first gate electrode 3c, a first source electrode 3d, and a first drain electrode 3e. The first gate electrode 3c receives a drive signal output from the photodetector driving element 5, the first source electrode 3d is electrically connected to the photodetector driving element 5, and the first drain electrode 3e is electrically connected to the first output terminal 8.
[0057] The second MOSFET element 4 has a second gate electrode 4c, a second source electrode 4d, and a second drain electrode 4e. The second gate electrode 4c receives a drive signal output from the photodetector driving element 5, the second source electrode 4d is electrically connected to the photodetector driving element 5, and the second drain electrode 4e is electrically connected to the second output terminal 9.
[0058] The connecting conductor 12 is electrically connected to the first source electrode 3d and the second source electrode 4d.
[0059] The first MOSFET element 3 has a first upper surface 3a on which a first gate electrode 3c and a first source electrode 3d are provided, and a first lower surface 3b located on the opposite side of the first upper surface 3a along the Z direction.
[0060] The first upper surface 3a has a first mounting portion 3a1 and a first non-mounting portion 3a2. The light-receiving driving element 5 is mounted on the first mounting portion 3a1. The first gate electrode 3c is formed on the first non-mounting portion 3a2, while the light-receiving driving element 5 is not mounted there.
[0061] The second MOSFET element 4 has a second upper surface 4a on which a second gate electrode 4c and a second source electrode 4d are provided, and a second lower surface 4b located on the opposite side of the second upper surface 4a along the Z direction.
[0062] The second upper surface 4a has a second mounting portion 4a1 and a second non-mounting portion 4a2. The light-receiving driving element 5 is mounted on the second mounting portion 4a1. The second gate electrode 4c is formed on the second non-mounting portion 4a2, while the light-receiving driving element 5 is not mounted there.
[0063] The light-receiving driving element 5, the first MOSFET element 3, and the second MOSFET element 4 are arranged in a line along the Y direction.
[0064] The connecting conductor 12 has a first connecting conductor portion 12a, a second connecting conductor portion 12b, and a third connecting conductor portion 12c. When viewed along the Z direction, that is, the vertical direction, the first connecting conductor portion 12a overlaps with the first MOSFET element 3, and the second connecting conductor portion 12b overlaps with the second MOSFET element 4. The third connecting conductor portion 12c electrically connects the first connecting conductor portion 12a to the second connecting conductor portion 12b and does not overlap with the first MOSFET element 3 and the second MOSFET element 4 when viewed along the Z direction.
[0065] The connecting conductor 12 is provided on the lower surface 5b of the light-receiving driving element 5.
[0066] The light-emitting element 2 is located above the light-receiving element 51 along the Z-direction. Specifically, the light-emitting element 2 is mounted on the upper surface 5a of the light-receiving driving element 5 via a light-transmitting resin 10b.
[0067] By configuring the semiconductor relay 1 in this way, the parasitic inductance component on the output side of the semiconductor relay 1 can be reduced, thereby reducing insertion loss. Furthermore, the semiconductor relay 1 can be miniaturized. These points will be further explained in comparison with the conventional configurations disclosed in Patent Documents 1 and 2.
[0068] First, in the conventional semiconductor relay disclosed in Patent Document 1, the lead frame on which the input element, the light-emitting element, is mounted is bent at a right angle inside the housing and has a structure that stands upright relative to the bottom surface of the housing. Similarly, the lead frame on which the output element, the MOSFET element, is mounted is also bent at a right angle inside the housing and has a structure that stands upright relative to the bottom surface of the housing. The lead frame on which the light-emitting element is mounted and the lead frame on which the MOSFET element is mounted are positioned opposite each other with a gap between them.
[0069] However, in this configuration, the signal path length between the pair of output terminals via the two MOSFET elements becomes longer, which increases the inductance along the signal path and thus increases insertion loss.
[0070] Furthermore, both the input and output sides have an upright lead frame structure on which the elements are mounted inside the housing. This requires a bending region for the lead frame, and a certain amount of air gap between the input and output lead frames, making it difficult to miniaturize semiconductor relays.
[0071] On the other hand, according to the semiconductor relay 1 of this embodiment, since both the first output terminal 8 and the second output terminal 9 are thin plate-shaped conductors provided substantially parallel to the lower surface of the housing 10, the signal path length flowing through the first output terminal 8 and the second output terminal 9 can be shortened compared to the conventional semiconductor relay disclosed in Patent Document 1. In other words, the signal path length flowing between the first output terminal 8 and the second output terminal 9 via the first MOSFET element 3 and the second MOSFET element 4 can be shortened. As a result, the inductance along the signal path, and consequently the insertion loss, can be reduced compared to the conventional semiconductor relay disclosed in Patent Document 1.
[0072] Furthermore, according to the semiconductor relay 1 of this embodiment, the aforementioned bending regions are unnecessary at each of the first input terminal 6, the second input terminal 7, the first output terminal 8, and the second output terminal 9, and miniaturization can be achieved in the Z direction.
[0073] Furthermore, in the conventional semiconductor relay disclosed in Patent Document 2, the source terminals of the two MOSFET elements arranged on the output side are connected by an Au wire. Also, when viewed from above, the photodetector is mounted on the package substrate or on top of the MOSFET elements.
[0074] However, in this configuration, the parasitic inductance component caused by the Au wire becomes large, increasing the insertion loss.
[0075] Furthermore, in this configuration, a lead frame on which the light-receiving driving element is mounted and a separate lead frame on which each of the two MOSFET elements is mounted are provided. These lead frames are also spaced apart along the lower surface of the housing, which in this embodiment means they are spaced apart in the X direction. This makes miniaturization of the semiconductor relay difficult.
[0076] On the other hand, the semiconductor relay 1 according to this embodiment can reduce insertion loss compared to the conventional configuration disclosed in Patent Document 2. This will be explained further below.
[0077] The inductance per unit length of a wire along a signal path is roughly proportional to the logarithm of the reciprocal of the wire diameter. On the other hand, if the connecting conductor 12 is considered as a flat plate conductor, the width of the connecting conductor 12 in the X direction (the width in the direction intersecting the signal path in the connecting conductor 12) can be made larger than the width of the connecting conductor 12 in the Z direction (the thickness of the flat plate conductor).
[0078] Furthermore, the width of the connecting conductor 12 in the X direction can be made several times to more than ten times larger than the wire diameter of a typical wire used to connect electronic components. Therefore, in this case, the inductance per unit length of the connecting conductor 12 along the signal path is less affected by the width of the connecting conductor 12 in the X direction (thickness of the flat conductor), and the component proportional to the logarithm of the reciprocal of the width in the X direction becomes the main component. In other words, because the width of the connecting conductor 12 in the X direction is several times to more than ten times larger than the wire diameter of a wire, the inductance per unit length along the signal path is smaller for the semiconductor relay 1 of this embodiment using a connecting conductor 12 than for the conventional semiconductor relay disclosed in Patent Document 2 which uses a wire.
[0079] In other words, the semiconductor relay 1 of this embodiment can reduce the parasitic inductance component compared to the conventional semiconductor relay disclosed in Patent Document 2, and as a result, insertion loss can be reduced. Furthermore, by reducing the inductance along the signal path, the mismatch in the characteristic impedance of the signal path can be reduced. This improves the reflection characteristics within the signal path, and consequently reduces insertion loss.
[0080] Furthermore, according to this embodiment, the light-receiving driving element 5 is arranged across the first upper surface 3a of the first MOSFET element 3 and the second upper surface 4a of the second MOSFET element 4, and the light-emitting element 2 is arranged so as to overlap with the light-receiving driving element 5 when viewed from above.
[0081] In this way, the semiconductor relay 1 of this embodiment can be made smaller than the conventional semiconductor relay disclosed in Patent Document 2, particularly with respect to the X direction.
[0082] Preferably, the connecting conductor 12 is formed over the entire lower surface 5b of the light-receiving driving element 5.
[0083] This configuration allows for the widest possible width of the connecting conductor 12 in the Z-direction within the signal path. As a result, the parasitic inductance component is reduced, thereby lowering insertion loss. Furthermore, the mismatch in characteristic impedance within the signal path is reduced, improving the reflection characteristics within the signal path and ultimately reducing insertion loss.
[0084] Furthermore, from the standpoint of reducing impedance along the signal path, it is preferable that the width of the connecting conductor 12 in the X direction be greater than or equal to the length of the first connector 13 and the second connector 14 in the X direction.
[0085] Furthermore, the width of the connecting conductor 12 in the Y direction should be the same as or wider than the distance between the first connector 13 and the second connector 14 along the Y direction. In this way, the connecting conductor 12 can be reliably electrically connected to the first connector 13 and the second connector 14.
[0086] The semiconductor relay 1 further includes a connector that connects the connecting conductor 12 to the first source electrode 3d of the first MOSFET element 3 and the second source electrode 4d of the second MOSFET element 4.
[0087] The connector includes a first connector 13 and a second connector 14. The first connector 13 is a conductor formed on the upper surface of the first source electrode 3d, and the second connector 14 is a conductor formed on the upper surface of the second source electrode 4d.
[0088] In this way, by providing the first connector 13 and the second connector 14, the connecting conductor 12 and the first source electrode 3d and the second source electrode 4d can be reliably connected.
[0089] Furthermore, when mounting the light-receiving driving element 5 on the first upper surface 3a of the first MOSFET element 3 and the second upper surface 4a of the second MOSFET element 4, the first connector 13 and the second connector 14 act as buffers, thereby mitigating the pressure exerted on the first MOSFET element 3 and the second MOSFET element 4 during mounting.
[0090] If pressure exceeding a predetermined level is applied to both the first MOSFET element 3 and the second MOSFET element 4, the characteristics of the MOSFETs contained in each may change, or in extreme cases, the first MOSFET element 3 or the second MOSFET element 4 may be damaged.
[0091] On the other hand, according to this embodiment, by providing the first connector 13 and the second connector 14, the aforementioned problems can be avoided, and the characteristics of the first MOSFET element 3 and the second MOSFET element 4 can be stabilized. Furthermore, problems in the assembly process can be reduced, and the manufacturing yield of the semiconductor relay 1 can be improved.
[0092] The first connector 13 and the second connector 14 are arranged side by side along the Y direction, spaced apart from each other. Furthermore, the width of the connecting conductor 12 in the Y direction should be the same as or wider than the distance between the first connector 13 and the second connector 14 along the Y direction. In this way, the connecting conductor 12 can be reliably electrically connected to the first connector 13 and the second connector 14.
[0093] The semiconductor relay 1 further comprises a housing 10 that accommodates a first input terminal 6, a second input terminal 7, a light-emitting element 2, a light-receiving driving element 5, a first output terminal 8, a second output terminal 9, a first MOSFET element 3, a second MOSFET element 4, and a connecting conductor 12.
[0094] The first input terminal 6 is a thin plate-shaped conductor, and its lower surface, the first input-side external terminal 61, is located on the lower surface of the housing 10 and is exposed to the lower surface of the housing 10. In addition, the cathode electrode 2d of the light-emitting element 2 is electrically connected to the first wire connection portion 62, which is the upper surface of the first input terminal 6, via a wire 11.
[0095] The second input terminal 7 is a thin plate-shaped conductor, and its lower surface, the second input-side external terminal 71, is located on the lower surface of the housing 10 and is exposed to the lower surface of the housing 10. In addition, the anode electrode 2c of the light-emitting element 2 is electrically connected to the second wire connection portion 72, which is the upper surface of the second input terminal 7, via a wire 11.
[0096] The first output terminal 8 is a thin plate-shaped conductor, with its lower surface being the first output-side external terminal 81 and its upper surface being the first MOSFET mounting portion 82. The first output-side external terminal 81 is located on the lower surface of the housing 10 and is exposed on the lower surface of the housing 10. The first MOSFET mounting portion 82 is provided above the first output-side external terminal 81, and the first MOSFET element 3 is mounted on the first MOSFET mounting portion 82.
[0097] The second output terminal 9 is a thin plate-shaped conductor, with its lower surface being the second output-side external terminal 91 and its upper surface being the second MOSFET mounting section 92. The second output-side external terminal 91 is located on the lower surface of the housing 10 and is exposed to the lower surface of the housing 10. The second MOSFET mounting section 92 is provided above the second output-side external terminal 91, and the second MOSFET element 4 is mounted on the second MOSFET mounting section 92.
[0098] In this way, a surface-mount type semiconductor relay 1 can be realized with the lower surface of the housing 10 as the mounting surface.
[0099] Furthermore, since both the first output terminal 8 and the second output terminal 9 are thin, plate-shaped conductors provided almost parallel to the lower surface of the housing 10, the signal path length between the first output terminal 8 and the second output terminal 9 via the first MOSFET element 3 and the second MOSFET element 4 can be shortened. As a result, the inductance along the signal path and, consequently, the insertion loss can be reduced in the semiconductor relay 1.
[0100] (Embodiment 2) Figure 5A is a perspective view of the semiconductor relay according to Embodiment 2. Figure 5B is a view of the semiconductor relay according to Embodiment 2 from above. Figure 5C is a view of the semiconductor relay according to Embodiment 2 from below. Figure 5D is a view of the semiconductor relay according to Embodiment 2 along the X direction. Figure 5E is a view of the semiconductor relay according to Embodiment 2 along the Y direction.
[0101] In addition, for the sake of convenience of explanation, in Figures 5A to 5E and the subsequent drawings, the same reference numerals are used for parts that are the same as in Embodiment 1, and detailed explanations are omitted.
[0102] The semiconductor relay 1 of this embodiment shown in Figures 5A to 5E differs from the semiconductor relay 1 of Embodiment 1 shown in Figures 1A to 1E in that a package substrate 20 (hereinafter simply referred to as substrate 20) is provided in contact with the lower surface of the housing 10.
[0103] The substrate 20 is made of, for example, a low dielectric constant insulating substrate with four via holes formed through the substrate 20. The four via holes are each exposed on the side surface of the insulating substrate and have a semicircular shape when viewed from above. In other words, four half-via holes are formed in the substrate 20. The first input terminal 6, the second input terminal 7, the first output terminal 8, and the second output terminal 9 are provided so as to cover the four half-via holes, respectively.
[0104] Specifically, the first input terminal 6, the second input terminal 7, the first output terminal 8, and the second output terminal 9 are each provided penetrating the circuit board 20. The first input terminal 6 has a first input-side external terminal 63 located on the lower surface of the circuit board 20 and a first wire connection portion 64 located on the upper surface of the circuit board 20. The first input terminal 6 also has a first input-side half via 65 that covers the inner wall surface of the half via hole and is connected to the first input-side external terminal 63 and the first wire connection portion 64.
[0105] The second input terminal 7 includes a second input-side external terminal 73 located on the lower surface of the circuit board 20 and a second wire connection portion 74 located on the upper surface of the circuit board 20. The second input terminal 7 also includes a second input-side half via 75 that covers the inner wall surface of the half via hole and is connected to the second input-side external terminal 73 and the second wire connection portion 74.
[0106] The first output terminal 8 includes a first output-side external terminal 83 located on the lower surface of the substrate 20, and a first MOSFET mounting section 84 located on the upper surface of the substrate 20 on which the first MOSFET element 3 is mounted. The first output terminal 8 also includes a first output-side half via 85 that covers the inner wall surface of the half via hole and is connected to the first output-side external terminal 83 and the first MOSFET mounting section 84.
[0107] The second output terminal 9 includes a second output-side external terminal 93 located on the lower surface of the substrate 20, and a second MOSFET mounting section 94 located on the upper surface of the substrate 20 on which the second MOSFET element 4 is mounted. The second output terminal 9 also includes a second output-side half via 95 that covers the inner wall surface of the half via hole and is connected to the second output-side external terminal 93 and the second MOSFET mounting section 94.
[0108] According to this embodiment, the first input terminal 6, the second input terminal 7, the first output terminal 8, and the second output terminal 9 are provided on the substrate 20, and each of them has a half-via structure, which improves the mountability when mounting the semiconductor relay 1 on the circuit board 40 (see Figure 10).
[0109] Furthermore, this embodiment can achieve the same effects as the configuration shown in Embodiment 1. Specifically, the parasitic inductance component on the output side of the semiconductor relay 1 can be reduced, thereby reducing insertion loss. In addition, the semiconductor relay 1 can be miniaturized.
[0110] <Modification> Figure 6 is a view of the semiconductor relay according to the modification along the X direction. Figure 7 is a view of another semiconductor relay according to the modification along the X direction.
[0111] The semiconductor relay 1 shown in Figure 6 differs from the semiconductor relay 1 shown in Embodiment 1 in that a third connecting body 15 is provided in contact with the lower surface of the connecting conductor 12.
[0112] The third connector 15 is a layered or sheet-like conductor that electrically connects the first connector 13 and the second connector 14 together with the connecting conductor 12. The widths of the third connector 15 in the X and Y directions are approximately the same as the widths of the connecting conductor 12 in the X and Y directions.
[0113] In this modified configuration, a third connector 15, which is a conductor, is provided in parallel with the connecting conductor 12, and the first source electrode 3d of the first MOSFET element 3 and the second source electrode 4d of the second MOSFET element 4 are electrically connected via the first connector 13 and the second connector 14. This reduces the inductance along the signal path and reduces insertion loss.
[0114] Furthermore, because the third connector 15 is layered or sheet-like, it is possible to suppress the length of the connection distance along the Z direction between the light-receiving driving element 5 and the first MOSFET element 3 and the second MOSFET element 4. This reduces the inductance along the signal path and thus reduces insertion loss.
[0115] In this modified example, the third connector 15 is a conductive die attach film, that is, a semiconductor adhesive film mixed with a conductive filler, but is not limited to this. For example, the third connector 15 may be a metal film. If the third connector 15 is a conductive die attach film, there is no need to separately provide adhesive or the like when connecting it to the first connector 13, the second connector 14, and the connecting conductor 12. In addition, the third connector 15 acts as a buffer when mounting the light-receiving driving element 5 to the first MOSFET element 3 and the second MOSFET element 4, and can reduce the effect of pressure applied to the first MOSFET element 3 and the second MOSFET element 4 during mounting.
[0116] Furthermore, the semiconductor relay 1 shown in Figure 7 differs from the semiconductor relay 1 shown in Embodiment 1 in that an insulating adhesive sheet 16 is bonded to the lower surface 5b of the light-receiving driving element 5, and a connecting conductor 12 is provided in contact with the lower surface of the insulating adhesive sheet 16.
[0117] By providing an insulating adhesive sheet 16 between the light-receiving driving element 5 and the connecting conductor 12, the adhesion between the light-receiving driving element 5 and the connecting conductor 12 can be improved, and the insulation between the light-receiving driving element 5 and the connecting conductor 12 can be improved. Note that the width of the connecting conductor 12 in the X and Y directions may be greater than the width of the insulating adhesive sheet 16 in the X and Y directions.
[0118] Furthermore, this modified configuration can achieve the same effects as the configuration shown in Embodiment 1. Specifically, the parasitic inductance component on the output side of the semiconductor relay 1 can be reduced, thereby reducing insertion loss. In addition, the semiconductor relay 1 can be miniaturized.
[0119] (Embodiment 3) Figure 8 is a view of the semiconductor relay according to Embodiment 3 along the X direction. Figure 9 is a view of the light-emitting element and the light-receiving driving element from above. For the sake of explanation, the anode electrode 2c and cathode electrode 2d of the light-emitting element 2 are omitted from the illustration in Figure 9. The wire 11 is also omitted from the illustration.
[0120] The semiconductor relay 1 of this embodiment, shown in Figures 8 and 9, differs from the semiconductor relay 1 shown in Embodiment 1 in that a transparent plate 10d is provided between the light-emitting element 2 and the light-receiving element 51 of the light-receiving driving element 5. Furthermore, a light-transmitting adhesive 10c is provided between the upper surface of the transparent plate 10d and the lower surface 2b, which is the light-emitting surface of the light-emitting element 2. In addition, a light-transmitting adhesive 10c is also provided between the upper surface 5a of the light-receiving driving element 5 and the lower surface of the transparent plate 10d.
[0121] In other words, considering embodiments 1 to 3 and their modifications, it can be said that the light-emitting element 2 disclosed in this specification is mounted on the upper surface 5a of the light-receiving driving element 5 via a light-transmitting material.
[0122] The transparent plate 10d and the translucent adhesive 10c are both materials that are transparent to the output light from the light-emitting element 2. The transparent plate 10d is preferably a glass material that is harder than the translucent adhesive 10c, such as borosilicate glass, from the viewpoint of low dielectric constant and strength. However, it is not limited to this, and other translucent materials may be used.
[0123] According to this embodiment, capacitive coupling between the light-emitting element and the photodetector 51 can be reduced compared to the configuration shown in Embodiment 1. This reduces the parasitic capacitance component on the input side of the semiconductor relay 1, thereby reducing insertion loss.
[0124] Furthermore, according to this embodiment, the amount of resin interposed between the light-emitting element and the light-receiving element 51 can be reduced. By doing so, fluctuations in the characteristics of the light-emitting element 2 and the light-receiving element 51 due to stress when the resin hardens can be suppressed. As a result, fluctuations in the input / output characteristics of the semiconductor relay 1 can be suppressed, and signals can be transmitted at a speed within a set range.
[0125] Furthermore, as shown in Figure 9, when viewed from above, the area of the light-receiving element 51 is larger than that of the light-emitting element 2, and the area of the transparent plate 10d is larger than that of the light-receiving element 51. The light-receiving element 51 has a structure in which photodiode cells are arranged in a matrix.
[0126] By defining the relative sizes of the areas of the light-emitting element 2, the light-receiving element 51, and the transparent plate 10d as described above, the light output from the light-emitting element 2 can be received across the entire cell area of the light-receiving element 51. This makes it possible to improve the ON operation speed of the first MOSFET element 3 and the second MOSFET element 4, which constitute the output section of the semiconductor relay 1.
[0127] Furthermore, this embodiment can achieve the same effects as the configuration shown in Embodiment 1. Specifically, the parasitic inductance component on the output side of the semiconductor relay 1 can be reduced, thereby reducing insertion loss. In addition, the semiconductor relay 1 can be miniaturized.
[0128] (Embodiment 4) Figure 10 is a view of the electrical component unit according to Embodiment 4 from above. Figure 11 is a cross-sectional view taken along the line XI-XI in Figure 10. Although three lines XI-XI are shown in Figure 10, their cross-sectional shapes are similar, so they are shown together in Figure 11.
[0129] The electrical component unit 100 comprises at least a semiconductor relay 1 and a circuit board 40. The circuit board 40 is a so-called printed wiring board (Printed Wiring Board) formed on the surface of a dielectric substrate 40a made of a dielectric material having a predetermined relative permittivity, with first to third wirings 41, 42, and 43 formed thereon. As shown in Figure 11, a ground plane 45 is formed on the lower surface of the dielectric substrate 40a. The ground plane 45 is formed over the entire lower surface of the dielectric substrate 40a. The first to third wirings 41, 42, and 43 and the ground plane 45 are formed by applying copper plating or the like to the upper or lower surface of the dielectric substrate 40a.
[0130] As shown in Figure 11, the third wiring 43 and the ground plane 45 are electrically connected via conductive vias 44 that penetrate the dielectric substrate 40a in the thickness direction, in this case the Z direction. The ground plane 45 is also electrically connected to the ground potential of the electrical component unit 100. In order to reduce transmission loss of the transmission signal, the relative permittivity of the dielectric substrate 40a is set low. Note that the position and number of conductive vias 44 on the circuit board 40 are not particularly limited to the example shown in Figure 10 and can be changed as appropriate.
[0131] The first wiring 41 is provided with a gap in the Y direction and consists of a pair of parallel wires 41a and 41b, each with its longitudinal direction in the X direction. The first wiring 41 is an input signal line for inputting an input signal to the semiconductor relay 1. One end of each of the pair of wires 41a and 41b constituting the first wiring 41 is connected to the first input-side external terminal 61 of the first input terminal 6 and the second input-side external terminal 71 of the second input terminal 7, respectively. Specifically, the first input-side external terminal 61 and the second input-side external terminal 71 are connected to the first wiring such that their respective lower surfaces are in contact with the upper surfaces of the pair of wires 41a and 41b constituting the first wiring 41. On the other hand, as shown in Figure 8, the other ends of the pair of wires 41a and 41b constituting the first wiring 41 are open ends.
[0132] The second wiring 42 is provided with a gap in the Y direction and consists of a pair of wires 42a and 42b whose longitudinal direction is the Y direction. The second wiring 42 is the output signal line of the output signal output from the semiconductor relay 1. One end of each of the pair of wires 42a and 42b that make up the second wiring 42 is connected to the first output side external terminal 81 of the first output terminal 8 and the second output side external terminal 91 of the second output terminal 9. Specifically, the first output side external terminal 81 and the second output side external terminal 91 are connected to the second wiring 42 such that their respective lower surfaces are in contact with the upper surfaces of the pair of wires 42a and 42b that make up the second wiring 42. The second wiring 42 is designed as a transmission line with impedance matching to 50Ω. Note that the second wiring 42 may also consist of a pair of wires 42a and 42b that extend in a long, narrow manner with the longitudinal direction being the X direction.
[0133] The third wiring 43 includes two wires 43a and 43b that are provided so as to sandwich the ends of the pair of wires 41a and 41b that constitute the first wiring 41, and a wire 43c that is provided on the opposite side in the X direction from the two wires 43a and 43b and the second wiring 42. The longitudinal direction of the three wires 43a, 43b, and 43c is the Y direction. As mentioned above, the three wires 43a, 43b, and 43c included in the third wiring 43 are also electrically connected to the ground potential via the ground plane 45. In other words, the third wiring 43 is provided so as to be spaced apart from the second wiring 42, which is the output signal line, and surrounds the second wiring 42, and plays a role in shielding against radiated noise and the like that incident on the second wiring 42.
[0134] Although Figure 10 shows an example in which only the semiconductor relay 1 shown in Embodiment 1 is mounted on the circuit board 40, other elements may also be mounted on the circuit board 40. Furthermore, the semiconductor relay 1 shown in Embodiment 2, or the semiconductor relay 1 shown in Embodiment 3 and Modifications 1 and 2 may also be mounted on the circuit board 40.
[0135] As described above, the electrical component unit 100 according to this embodiment comprises at least a semiconductor relay 1 and a circuit board 40. The circuit board 40 has a first wiring (wiring layer) 41, a second wiring (wiring layer) 42, and a third wiring (ground layer) 43 formed on the surface of a dielectric substrate (dielectric layer) 40a, and a ground plane (ground layer) 45 formed on the lower surface of the dielectric substrate (dielectric layer) 40a.
[0136] The first wiring 41 is connected to the first input terminal 6 and the second input terminal 7 of the semiconductor relay 1, respectively. The second wiring 42 is connected to the first output terminal 8 and the second output terminal 9 of the semiconductor relay 1, respectively.
[0137] The first wiring 41 is an input wiring for the signal input to the semiconductor relay 1, and the second wiring 42 is an output wiring (signal line) for the signal output from the semiconductor relay 1.
[0138] According to the electrical component unit 100 of this embodiment, the passing and blocking of signals output from the semiconductor relay 1 can be performed with a simple configuration.
[0139] Furthermore, when the semiconductor relay 1 is mounted on the circuit board 40, parasitic capacitance occurs between the light-receiving driving element 5 and the ground potential of the circuit board 40. On the other hand, according to this embodiment, when viewed from above, the connecting conductor 12 that connects the first source electrode 3d of the first MOSFET element 3 and the second source electrode 4d of the second MOSFET element 4 can be positioned to overlap with the light-receiving driving element 5.
[0140] In other words, according to this embodiment, the connecting conductor 12 can reduce this parasitic capacitance. As a result, compared to, for example, the case where a conventional semiconductor relay disclosed in Patent Document 1 is mounted on a circuit board 40, the impedance along the signal path and, consequently, the insertion loss in the semiconductor relay 1 can be reduced.
[0141] Furthermore, a third wiring 43 is formed on the upper surface of the circuit board 40, spaced apart from the second wiring 42 and surrounding the second wiring 42. The third wiring 43 is electrically connected to a ground plane 45 formed on the lower surface of the circuit board 40, and the ground plane 45 is electrically connected to the ground potential.
[0142] By arranging the third wiring 43, which is connected to ground potential, so as to surround the second wiring 42, the intrusion of radiated noise and other interference into the transmission signal propagating through the second wiring 42 can be suppressed. Furthermore, the propagation of radiated noise and other interference from the second wiring 42 to other electronic components mounted on the circuit board 40 can be suppressed. In addition, a signal transmission circuit that transmits high-frequency signals to be passed through or blocked by the semiconductor relay 1 can be easily configured.
[0143] (Other Embodiments) New embodiments can be created by appropriately combining the components shown in Embodiments 1 to 4 and their modified forms. For example, in the semiconductor relay 1 shown in Embodiment 2 and its modified form, a laminated structure of a transparent plate 10d and a translucent adhesive 10c as shown in Embodiment 3 may be applied instead of the translucent resin 10b.
[0144] Furthermore, the third connector 15 and insulating adhesive sheet 16 shown in the modified example may be applied to the semiconductor relay 1 shown in embodiments 2 and 3.
[0145] The semiconductor relay described herein is useful as a device for passing and blocking high-frequency signals because it can be miniaturized and insertion loss can be reduced.
[0146] 1 Semiconductor relay 2 Light-emitting element 2c Anode electrode 2d Cathode electrode 3 First MOSFET element 3a First upper surface 3a1 First mounting portion 3a2 First non-mounting portion 3b First lower surface 3c First gate electrode 3d First source electrode 3d1 First electrode body portion 3d2 First enlarged electrode portion 3e First drain electrode 4 Second MOSFET element 4a Second upper surface 4a1 Second mounting portion 4a2 Second non-mounting portion 4b Second lower surface 4c Second gate electrode 4d Second source electrode 4d1 Second electrode body portion 4d2 Second enlarged electrode portion 4e Second drain electrode 5 Light-receiving driving element 5a Upper surface 5b Lower surface 51 Light-receiving element 52 Driving circuit 6 First input terminal 61 First input side external terminal 62 First wire connection portion 63 64 First input external terminal 65 First wire connection 65 First input half via 7 Second input terminal 71 Second input external terminal 72 Second wire connection 73 Second input external terminal 74 Second wire connection 75 Second input half via 8 First output terminal 81 First output external terminal 82 First MOSFET mounting section 83 First output external terminal 84 First MOSFET mounting section 85 First output half via 9 Second output terminal 91 Second output external terminal 92 Second MOSFET mounting section 93 Second output external terminal 94 Second MOSFET mounting section 95 Second output half via 10 Housing 10a Light-shielding resin 10b Light-transmitting resin (light-transmitting material) 10c Light-transmitting adhesive (light-transmitting material) 10d Transparent plate (light-transmitting material) 11 Wire 12 Connecting conductor 12a First connecting conductor section 12b Second connecting conductor section 12c Third connecting conductor section 13 First connector 14 Second connector 15 Third connector 16 Insulating adhesive sheet 20 Package substrate (substrate) 40 Circuit board 40a Dielectric substrate (dielectric layer) 41 First wiring (wiring layer) 42 Second wiring (wiring layer) 43 Third wiring (ground layer) 44 Conductive via 45 Ground plane (ground layer) 100 Electrical component unit
Claims
1. A first input terminal, a second input terminal, a light-emitting element electrically connected to the first input terminal and the second input terminal, a light-receiving element that receives light output from the light-emitting element and outputs a drive signal according to the received light, a first output terminal, a second output terminal, a first MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) element having a first gate electrode to which the drive signal is input, a first source electrode electrically connected to the light-receiving element, and a first drain electrode electrically connected to the first output terminal, a second MOSFET element having a second gate electrode to which the drive signal is input, a second source electrode electrically connected to the light-receiving element, and a second drain electrode electrically connected to the second output terminal, and a connecting conductor electrically connected to the first source electrode and the second source electrode. The first MOSFET element has a first upper surface on which the first gate electrode and the first source electrode are provided, and a first lower surface opposite to the first upper surface. The second MOSFET element has a second upper surface on which the second gate electrode and the second source electrode are provided, and a second lower surface opposite to the second upper surface. The first upper surface of the first MOSFET element has a first mounting portion on which the light-receiving driving element is mounted, and a first non-mounting portion on which the first gate electrode is provided and the light-receiving driving element is not mounted. The second upper surface of the second MOSFET element has a second mounting portion on which the light-receiving driving element is mounted, and a second non-mounting portion on which the second gate electrode is provided and the light-receiving driving element is not mounted. In a top view, the connecting conductor has a first connecting conductor portion that overlaps with the first MOSFET element, A semiconductor relay comprising: a second connecting conductor portion that overlaps with the second MOSFET element; and a third connecting conductor portion that electrically connects the first connecting conductor portion to the second connecting conductor portion and does not overlap the first MOSFET element and the second MOSFET element, wherein the connecting conductor is provided on the lower surface of the light-receiving driving element, and the light-emitting element is placed on the upper surface of the light-receiving driving element via a light-transmitting material.
2. The semiconductor relay according to claim 1, wherein the connecting conductor is provided over the entire lower surface of the light-receiving driving element.
3. The semiconductor relay according to claim 1, further comprising: a first connector provided on the upper surface of the first source electrode; and a second connector provided on the upper surface of the second source electrode, wherein the first connector electrically connects the first source electrode to the first connecting conductor portion of the connecting conductor; and the second connector electrically connects the second source electrode to the second connecting conductor portion of the connecting conductor.
4. The semiconductor relay according to claim 3, wherein the width of the connecting conductor in the direction in which the first connecting body and the second connecting body are aligned is greater than or equal to the distance between the first connecting body and the second connecting body in the direction in which the first connecting body and the second connecting body are aligned.
5. The semiconductor relay according to claim 1, wherein a plate material transparent to light is disposed between the lower surface of the light-emitting element and the light-receiving element via an adhesive that is transparent to light emitted from the light-emitting element.
6. The semiconductor relay according to claim 5, wherein, in a top view, the area of the light-receiving element is larger than the area of the light-emitting element, and the area of the plate material is larger than the area of the light-receiving element.
7. A semiconductor relay according to claim 1, further comprising a housing that houses the first input terminal, the second input terminal, the light-emitting element, the light-receiving driving element, the first output terminal, the second output terminal, the first MOSFET element, the second MOSFET element, and the connecting conductor, wherein the first input terminal has a first input-side external terminal disposed on the lower surface of the housing, the second input terminal has a second input-side external terminal disposed on the lower surface of the housing, the first output terminal has a first output-side external terminal disposed on the lower surface of the housing, and a first MOSFET mounting portion provided above the first output-side external terminal on which the first MOSFET element is mounted, and the second output terminal has a second output-side external terminal disposed on the lower surface of the housing, and a second MOSFET mounting portion provided above the second output-side external terminal on which the second MOSFET element is mounted.
8. A housing that houses the light-emitting element, the light-receiving driving element, the first MOSFET element, the second MOSFET element, and the connecting conductor; a substrate that is in contact with the entire lower surface of the housing and is disposed below the housing; each of the first input terminal, the second input terminal, the first output terminal, and the second output terminal is provided penetrating the substrate; the first input terminal has a first input-side external terminal disposed on the lower surface of the substrate; the second input terminal has a second input-side external terminal disposed on the lower surface of the substrate; the first output terminal has a first output-side external terminal disposed on the lower surface of the substrate; and a first MOSFET mounting portion disposed on the upper surface of the substrate, connected to the first output-side external terminal and on which the first MOSFET element is mounted; the second output terminal has a second output-side external terminal disposed on the lower surface of the substrate; The semiconductor relay according to claim 1, comprising: a second MOSFET mounting portion disposed on the upper surface of the substrate, connected to the second output side external terminal, and on which the second MOSFET element is mounted.
9. An electrical component unit comprising: a semiconductor relay according to claim 1; and a circuit board on which the semiconductor relay is mounted, wherein the circuit board has a dielectric layer; a wiring layer formed on the dielectric layer; and a ground layer formed on the dielectric layer; the wiring layer has two first wires and two second wires; one of the two first wires is connected to the first input terminal; the other of the two first wires is connected to the second input terminal; one of the two second wires is connected to the first output terminal; and the other of the two second wires is connected to the second output terminal.