Multilayer ceramic electronic component
The tapered external electrode and plating layer design addresses capacitance and mechanical strength issues in multilayer ceramic components, ensuring reliable performance and reduced size.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- MURATA MFG CO LTD
- Filing Date
- 2025-11-25
- Publication Date
- 2026-07-23
AI Technical Summary
Existing multilayer ceramic electronic components face challenges in achieving desired capacitance and mechanical strength due to non-uniform thickness of external electrodes and plating layers, leading to bulging and reduced heat resistance.
The design includes an external electrode with an extended portion that tapers in thickness from the tip to the base, with a thinner plating layer on the base side, ensuring uniform thickness and improved mechanical strength.
This configuration maintains desired capacitance and mechanical strength while reducing the overall size of the component, enhancing reliability and performance.
Smart Images
Figure JP2025040930_23072026_PF_FP_ABST
Abstract
Description
Multilayer ceramic electronic component
[0001] The present invention relates to a multilayer ceramic electronic component.
[0002] In a multilayer ceramic electronic component, when an external electrode is applied by a DIP (dip coating) method, a thickness with a gentle slope is formed from the tip side to the base end side (corner part of the end face) of the side face part of the external electrode. After application, the external electrode is fired, and after firing, a Ni plating layer and a Sn plating layer are formed on the external electrode. The Ni plating layer and the Sn plating layer are usually formed so that the thickness is uniform in any part.
[0003] By the way, a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component, is required to be small-sized and large-capacity. Patent Document 1 discloses a technique for manufacturing a small-sized and large-capacity multilayer ceramic capacitor by adding a rolling process to the manufacturing process.
[0004] Japanese Patent Application Laid-Open No. 5-326319
[0005] In order to reduce the outer dimensions of a multilayer ceramic electronic component, it is preferable to reduce the overall size including the external electrode and the plating layer formed on the external electrode.
[0006] The plating layer is not affected by the thickness of the external electrode and is formed with a uniform thickness. As a result, in a part where the external electrode is thick, the total dimension of the external electrode, the Ni plating layer, and the Sn plating layer becomes large. That is, in a part where the thickness of the external electrode is thick, the multilayer ceramic electronic component bulges and the outer dimension in the stacking direction becomes large. As a result, when the multilayer ceramic electronic component is a multilayer ceramic capacitor, it is impossible to sufficiently secure the required capacitance, and the capacitance is limited.
[0007] Also, when trying to reduce the thickness of the Ni plating layer in a thick part of the external electrode, the thickness of the entire Ni plating layer decreases. As a result, the heat resistance of the solder may decrease. Furthermore, the mechanical strength may decrease due to a decrease in the compressive stress applied to the end part of the Ni plating layer.
[0008] Therefore, the present invention aims to provide highly reliable multilayer ceramic electronic components that ensure desired capacitance and mechanical strength of the plating layer.
[0009] The multilayer ceramic electronic component of the present invention includes a dielectric layer and an internal electrode layer stacked in the stacking direction, and comprises a laminate having a first main surface and a second main surface facing the stacking direction, a first side surface and a second side surface facing the width direction intersecting the stacking direction, and a first end surface and a second end surface facing the length direction intersecting the stacking direction and the width direction; an external electrode provided on the first end surface and the second end surface and connected to the internal electrode layer; a first plating layer provided on the external electrode; and a second plating layer provided on the first plating layer, wherein the external electrode has an extended portion extending to at least a part of the first main surface, the second main surface, the first side surface, and the second side surface, and the thickness of the first plating layer provided on the extended portion is thinner on the base end side than on the tip side in the length direction of the extended portion.
[0010] According to the present invention, it is possible to ensure the desired capacitance and mechanical strength of the plating layer, and to provide highly reliable multilayer ceramic electronic components.
[0011] Figure 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 is a cross-sectional view taken along line 101-101 in Figure 1. Figure 3 is a cross-sectional view taken along line 102-102 in Figure 1. Figure 4 is a cross-sectional view taken along line 103-103 in Figure 1. Figure 5A is a diagram corresponding to the cross-sectional view taken along line 101-101 in Figure 1, showing an example of the arrangement of the floating internal electrode layer. Figure 5B is a diagram corresponding to the cross-sectional view taken along line 101-101 in Figure 1, showing another example of the arrangement of the floating internal electrode layer. Figure 5C is a diagram corresponding to the cross-sectional view taken along line 101-101 in Figure 1, showing another example of the arrangement of the floating internal electrode layer. Figure 6 is a cross-sectional view of the external electrode, etc., corresponding to an enlarged view of the framed area 260 in Figure 2.
[0012] (Multilayer Ceramic Capacitor) A multilayer ceramic capacitor 1 according to one embodiment of the present disclosure will be described with reference to the drawings. The multilayer ceramic capacitor 1 is an example of a multilayer ceramic electronic component. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 according to an embodiment of the present disclosure.
[0013] As shown in Figure 1, the shape of the multilayer ceramic capacitor 1 is approximately a rectangular parallelepiped. The multilayer ceramic capacitor 1 consists of a laminate 2, an external electrode 40, and a plating layer. The shape of the laminate 2 is approximately a rectangular parallelepiped. The plating layer is not shown in Figure 1. The plating layer will be explained later with reference to Figure 2 and other figures.
[0014] The external electrode 40 consists of a first external electrode 41 and a second external electrode 42. The external electrodes 40 are positioned at opposite ends of the laminate 2, separated from each other. The external electrode 40 positioned at one end is defined as the first external electrode 41. The external electrode 40 positioned at the other end is defined as the second external electrode 42.
[0015] (Laminate) The laminate 2 will be described with reference to Figure 1, as well as Figures 2, 3, and 4. Figure 2 is a cross-sectional view taken along line 101-101 of Figure 1. Figure 3 is a cross-sectional view taken along line 102-102 of Figure 1. Figure 3 shows the first internal electrode layer 31. Figure 4 is a cross-sectional view taken along line 103-103 of Figure 1.
[0016] As shown in Figure 2, the laminate 2 is composed of dielectric layers 20 and internal electrode layers 30. Multiple dielectric layers 20 and multiple internal electrode layers 30 are stacked on top of each other. The internal electrode layer 30 is composed of a first internal electrode layer 31 and a second internal electrode layer 32.
[0017] The directions in the multilayer ceramic capacitor 1 and the laminate 2 are described below. As shown in Figure 2, the direction in which the dielectric layer 20 and the internal electrode layer 30 are stacked is defined as the stacking direction T. In the multilayer ceramic capacitor 1, the direction that intersects the stacking direction T and in which the first external electrode 41 and the second external electrode 42 face each other is defined as the length direction L. The direction that intersects both the stacking direction T and the length direction L is defined as the width direction W. Note that the stacking direction T is sometimes also called the stacking direction.
[0018] In this embodiment, the stacking direction T, the length direction L, and the width direction W are mutually orthogonal. The stacking direction T, the length direction L, and the width direction W are the same directions as described above in figures other than Figure 2.
[0019] Regarding the cross-section of the multilayer ceramic capacitor 1 or the laminate 2, the cross-section parallel to the length direction L and the lamination direction T is defined as the LT cross-section. Regarding the cross-section of the multilayer ceramic capacitor 1 or the laminate 2, the cross-section parallel to the length direction L and the width direction W is defined as the LW cross-section. Regarding the cross-section of the multilayer ceramic capacitor 1 or the laminate 2, the cross-section parallel to the width direction W and the lamination direction T is defined as the WT cross-section.
[0020] Figure 2 shows the LT cross-section of the multilayer ceramic capacitor 1. Figure 3 shows the LW cross-section of the multilayer ceramic capacitor 1. Figure 4 shows the WT cross-section of the multilayer ceramic capacitor 1.
[0021] Two surfaces of the laminate 2 facing each other in the stacking direction T are defined as the first main surface 3 and the second main surface 4. Two surfaces of the laminate 2 facing each other in the width direction W are defined as the first side surface 5 and the second side surface 6. Two surfaces of the laminate 2 facing each other in the length direction L are defined as the first end surface 7 and the second end surface 8.
[0022] The portions where two surfaces of the laminate 2 intersect are defined as edges. The portions where three surfaces of the laminate 2 intersect are defined as corners. It is preferable that the corners and edges are rounded. The rectangular parallelepiped shape of the laminate 2 includes the shape of a rectangular parallelepiped in which the edges and corners are rounded. Furthermore, the rectangular parallelepiped shape of the laminate 2 includes all members having a first main surface 3, a second main surface 4, a first side surface 5, a second side surface 6, a first end surface 7, and a second end surface 8. In addition, some or all of the main surfaces, side surfaces, and end surfaces may have irregularities or other features formed on them.
[0023] As shown in Figure 2, the central position of the laminate 2 in the stacking direction T is defined as the center in the stacking direction 111. The central position of the laminate 2 in the length direction L is defined as the center in the length direction 112. The central position of the laminate 2 in the width direction W is defined as the center in the width direction 113.
[0024] (Dielectric layer) The total number of dielectric layers 20 included in the laminate 2 is preferably 15 to 700.
[0025] An example of a ceramic material included in the dielectric layer 20 is BaTiO ３ CaTiO ３ SrTiO ３CaZrO ３ These are dielectric ceramics whose main components are these elements. The ceramic material may also have minor components such as Mg, Mn, Si, Ni, Fe, Cr, Co, or compounds containing these elements added to these main components.
[0026] The multilayer ceramic capacitor described in this embodiment is an example of a multilayer ceramic electronic component. When a piezoelectric ceramic is used in the multilayer structure, the multilayer ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) based ceramic materials.
[0027] Furthermore, when semiconductor ceramics are used in the laminate, the multilayer ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include spinel-based ceramic materials.
[0028] Furthermore, when magnetic ceramics are used in the laminate, the multilayer ceramic electronic component functions as an inductor element.
[0029] Furthermore, when multilayer ceramic electronic components function as inductors, the internal electrode layers become coil-shaped conductors. Specific examples of magnetic ceramic materials include ferrite ceramic materials.
[0030] The thickness of the dielectric layer 20 is preferably, for example, 0.5 μm or more and 10 μm or less.
[0031] The dimensions of the laminate 2 are not particularly limited. The length L of the laminate 2 can be, for example, 0.2 mm or more and 10 mm or less. The width W of the laminate 2 can be, for example, 0.1 mm or more and 10 mm or less. The stacking direction T of the laminate 2 can be, for example, 0.1 mm or more and 5 mm or less.
[0032] (Internal Electrode Layer) The internal electrode layer 30 will now be described. As mentioned above, the internal electrode layer 30 is composed of a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The internal electrode layer 30 exposed on the first end face 7 is defined as the first internal electrode layer 31. The internal electrode layer 30 exposed on the second end face 8 is defined as the second internal electrode layer 32.
[0033] The first internal electrode layer 31 is exposed on the first end face 7, but not on the first main surface 3, the second main surface 4, the first side surface 5, the second side surface 6, and the second end face 8. The second internal electrode layer 32 is exposed on the second end face 8, but not on the first main surface 3, the second main surface 4, the first side surface 5, the second side surface 6, and the first end face 7.
[0034] Furthermore, the ends of the first internal electrode layer 31 and the second internal electrode layer 32 may be positioned slightly recessed from the first end face 7 or the second end face 8.
[0035] Inside the laminate 2, a plurality of roughly rectangular first internal electrode layers 31 and second internal electrode layers 32 are arranged alternately at equal intervals along the stacking direction T. Each of the first internal electrode layers 31 and the second internal electrode layers 32 is substantially parallel to the first main surface 3 and the second main surface 4. In the stacking direction T, the first internal electrode layers 31 and the second internal electrode layers 32 face each other via the dielectric layer 20.
[0036] The first internal electrode layer 31 is composed of a first opposing portion 33 and a first leading portion 35. The portion of the first internal electrode layer 31 that faces the second internal electrode layer 32 is defined as the first opposing portion 33. The portion of the first internal electrode layer 31 that is led out from the first opposing portion 33 to the first end face 7 is defined as the first leading portion 35. Similarly, the second internal electrode layer 32 is composed of a second opposing portion 34 and a second leading portion 36. The portion of the second internal electrode layer 32 that faces the first internal electrode layer 31 is defined as the second opposing portion 34. The portion of the second internal electrode layer 32 that is led out from the second opposing portion 34 to the second end face 8 is defined as the second leading portion 36.
[0037] The shape of the first opposing portion 33 is not particularly limited. The shape of the first opposing portion 33 is preferably rectangular. The corner portions of the first opposing portion 33 can be formed by rounding, and the corner portions of the first opposing portion 33 can be formed diagonally in a tapered shape. Similarly, the shape of the second opposing portion 34 is not particularly limited. The shape of the second opposing portion 34 is preferably rectangular. The corner portions of the second opposing portion 34 can be formed by rounding, and the corner portions of the second opposing portion 34 can be formed diagonally in a tapered shape. The taper may have an inclination in thickness toward the end.
[0038] The shape of the first extraction portion 35 is not particularly limited. The shape of the first extraction portion 35 is preferably rectangular. The corner portions of the first extraction portion 35 can be formed by rounding, and the corner portions of the first extraction portion 35 can be formed diagonally in a tapered shape. Similarly, the shape of the second extraction portion 36 is not particularly limited. The shape of the second extraction portion 36 is preferably rectangular. The corner portions of the second extraction portion 36 can be formed by rounding, and the corner portions of the second extraction portion 36 can be formed diagonally in a tapered shape. The taper may have an inclination in thickness toward the end.
[0039] The corner portion refers to the portion located at the corner of the outer shape of the internal electrode layer 30 when the internal electrode layer 30 is viewed in a cross-section in the length direction L and the width direction W.
[0040] The width of the first opposing portion 33 in the width direction W and the width of the first extraction portion 35 in the width direction W may be the same width, or either width may be narrower. The width of the second opposing portion 34 in the width direction W and the width of the second extraction portion 36 in the width direction W may be the same width, or either width may be narrower.
[0041] The internal electrode layer 30 contains at least one of Ni, Cu, Ag, Pd, Ag - Pd alloy, and Au. The main component of the internal electrode layer 30 is preferably Ni.
[0042] The metal constituting the internal electrode layer 30 forms a compound with the metal contained in the external electrode 40 or the metal constituting the conductive filler contained in the external electrode 40.
[0043] It is preferable that the total number of the first internal electrode layer 31 and the second internal electrode layer 32 is 15 or more and 200 or less.
[0044] The thickness of the first internal electrode layer 31 and the thickness of the second internal electrode layer 32 are preferably, for example, 0.2 μm or more and 2.0 μm or less.
[0045] (Division in the stacking direction) The division of the laminate 2 in the stacking direction T will be described. As shown in FIGS. 2 and 4, the laminate 2 can be divided into an inner layer portion 10 and an outer layer portion 11 along the stacking direction T. The outer layer portion 11 is composed of a first outer layer portion 12 and a second outer layer portion 13.
[0046] (Inner layer portion) In the stacking direction T, the portion of the laminate 2 located between the position of the internal electrode layer closest to the first main surface 3 and the position of the internal electrode layer closest to the second main surface 4 is defined as the inner layer portion 10.
[0047] Specifically, the inner layer portion 10 is a portion in which the first internal electrode layer 31, the second internal electrode layer 32, and the dielectric layer 20 are alternately stacked, and is a portion from the first internal electrode layer 31 or the second internal electrode layer 32 closest to the first main surface 3 to the first internal electrode layer 31 or the second internal electrode layer 32 closest to the second main surface 4.
[0048] (Outer layer portion) In the stacking direction T, the portion of the laminate 2 located between the position of the internal electrode layer closest to the first main surface 3 and the first main surface 3 is defined as the first outer layer portion 12. The first outer layer portion 12 is a portion of the laminate 2 located between the inner layer portion 10 and the first main surface 3.
[0049] In the stacking direction T, the portion of the laminate 2 located between the position of the internal electrode layer closest to the second main surface 4 and the second main surface 4 is defined as the second outer layer portion 13. The second outer layer portion 13 is a portion of the laminate 2 located between the inner layer portion 10 and the second main surface 4.
[0050] That is, the outer layer portion 11 is a portion disposed so as to sandwich the inner layer portion 10 in the stacking direction T. The dielectric layer 20 constituting the outer layer portion 11 is particularly, as a main material, BaTiO ３ or CaZrO３ It is preferable that it contains [a certain element], and it is also preferable that it contains Si, V, Mn, Mg, or Ni as an additive.
[0051] (Division in the width direction) The division of the laminate 2 in the width direction W will now be explained. As shown in Figures 3 and 4, the laminate 2 can be divided along the width direction W into a core portion 25 and a side gap 14. The side gap 14 consists of a first side gap 15 and a second side gap 16.
[0052] (Core portion) In the width direction W, the portion of the laminate 2 in which the internal electrode layer 30 is provided is defined as the core portion 25.
[0053] (Side gap) In the width direction W, the portion of the laminate 2 located between the core portion 25 and the first side surface 5 is defined as the first side gap 15. In the width direction W, the portion of the laminate 2 located between the core portion 25 and the second side surface 6 is defined as the second side gap 16. No internal electrode layer is provided in the side gap 14. Only the dielectric layer 20 is provided in the side gap 14. The side gap is also called a W gap or side gap.
[0054] (Classification of the core portion) The classification of the core portion 25 in the stacking direction T will be explained. As shown in Figure 4, the core portion 25 can be divided into an effective portion 26 and an ineffective portion 27 along the stacking direction T. The ineffective portion 27 consists of a first ineffective portion 28 and a second ineffective portion 29.
[0055] (Effective portion) In the stacking direction T, the portion of the core 25 in which the first internal electrode layer 31 or the second internal electrode layer 32 is located is defined as the effective portion 26. That is, the effective portion 26 is the portion of the core 25 from the internal electrode layer 30 closest to the first main surface 3 to the internal electrode layer 30 closest to the second main surface 4. The effective portion 26 in the multilayer ceramic capacitor 1 provided with the floating internal electrode layer 38, which will be described later, will be defined later.
[0056] (Inactive portion) In the stacking direction T, the portion of the core 25 located between the effective portion 26 and the first main surface 3 is defined as the first inactive portion 28. In the stacking direction T, the portion of the core 25 located between the effective portion 26 and the second main surface 4 is defined as the second inactive portion 29. The inactive portion 27 does not have an internal electrode layer 30. The inactive portion 27 is provided only with a dielectric layer 20.
[0057] (Opposite electrode portion) The portion where the first internal electrode layer 31 and the second internal electrode layer 32 overlap is defined as the opposite electrode portion 37. In the opposite electrode portion 37, the first opposing portion 33 and the second opposing portion 34 overlap. In the multilayer ceramic capacitor 1, capacitance is formed when the opposing portions of the internal electrode layers 30 face each other via the dielectric layer 20. That is, capacitance is formed in the opposite electrode portion 37. Capacitance is expressed in the multilayer ceramic capacitor 1 due to this capacitance.
[0058] (End Face Gap) The end face gap 17 will be described with reference to Figures 2 and 3. In the laminate 2, the portion located between the electrode facing portion 37 and the end face, and including the pull-out portion of either the first internal electrode layer 31 or the second internal electrode layer 32, is defined as the end face gap 17. The end face gap 17 is also called the L gap.
[0059] The end face gap 17 is composed of a first end face gap 18 and a second end face gap 19. The portion located between the electrode facing portion 37 and the first end face 7, including the first lead-out portion 35, is defined as the first end face gap 18. Similarly, the portion located between the electrode facing portion 37 and the second end face 8, including the second lead-out portion 36, is defined as the second end face gap 19.
[0060] (Floating Internal Electrode Layer) The floating internal electrode layer 38 will be described with reference to Figures 5A to 5C. Figures 5A to 5C correspond to the cross-sectional view along line 102-102 in Figure 1. However, the external electrode 40 is not shown in Figures 5A to 5C.
[0061] An internal electrode layer 30 that is not drawn out to either the first end face 7 or the second end face 8 is defined as a floating internal electrode layer 38. As shown in Figures 5A to 5C, a floating internal electrode layer 38 may be formed as the internal electrode layer 30 in the laminate 2.
[0062] (Floating electrode opposing portion) The floating electrode opposing portion 39 is defined as the portion where the floating internal electrode layers 38 face each other in the stacking direction T, the portion where the floating internal electrode layer 38 and the first internal electrode layer 31 face each other in the stacking direction T, and the portion where the floating internal electrode layer 38 and the second internal electrode layer 32 face each other in the stacking direction T.
[0063] In the example shown in Figures 5A to 5C, no electrode opposing portion 37 is formed where the first internal electrode layer 31 and the second internal electrode layer 32 face each other in the stacking direction T. However, in the example shown in Figures 5A to 5C, a floating electrode opposing portion 39 is formed. Multiple floating electrode opposing portions 39 may be formed in the longitudinal direction L. The formation of the floating electrode opposing portions 39 creates capacitance in the multilayer ceramic capacitor 1.
[0064] In the example shown in Figure 5A, the first internal electrode layer 31 and the second internal electrode layer 32 are formed in the same layer. A floating internal electrode layer 38 is formed between the layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed and another layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed.
[0065] In the example shown in Figure 5B, a floating internal electrode layer 38 is formed in both the layer where the first internal electrode layer 31 is formed and the layer where the second internal electrode layer 32 is formed.
[0066] In the example shown in Figure 5C, the first internal electrode layer 31 and the second internal electrode layer 32 are formed in the same layer. A floating internal electrode layer 38 is formed in the layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed. In addition, a floating internal electrode layer 38 is formed between the layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed and another layer in which the first internal electrode layer 31 and the second internal electrode layer 32 are formed. The floating internal electrode layer 38 is not limited to being formed in two consecutive rows in the same layer along the length L, as shown in Figure 5C. Needless to say, structures in which three, four, or five or more rows are formed are also possible.
[0067] As shown in Figures 5A to 5C, by forming a floating internal electrode layer 38, a structure can be realized in which the floating electrode opposing portion 39 is divided and arranged in multiple parts. This structure forms multiple capacitor components between the internal electrode layers 30 facing each other in the stacking direction T. The formed capacitor components are then connected in series. As a result, the voltage applied to each capacitor component becomes lower, and the voltage withstand capability of the multilayer ceramic capacitor 1 can be increased.
[0068] (Effective portion) The effective portion 26 in the multilayer ceramic capacitor 1 in which the floating internal electrode layer 38 is formed is as follows. Specifically, in the core portion 25, the effective portion 26 is defined as the portion in which the first internal electrode layers connected to the first external electrode are arranged facing each other in the stacking direction, the portion in which the second internal electrode layers connected to the second external electrode are arranged facing each other in the stacking direction, the portion in which the first internal electrode layer 31 or the second internal electrode layer 32 and the floating internal electrode layer 38 are arranged facing each other in the stacking direction T, and the portion in which the floating internal electrode layers 38 are arranged facing each other in the stacking direction T. Specifically, the effective portion 26 refers to the portion in the core portion 25 from the internal electrode layer 30 closest to the first main surface 3 to the internal electrode layer 30 closest to the second main surface 4.
[0069] (External Electrode) The external electrode 40 consists of a first external electrode 41 and a second external electrode 42. The external electrode 40 that is positioned on the first end face 7 and connected to the first internal electrode layer 31 is defined as the first external electrode 41. In addition to the first end face 7, the first external electrode 41 may be positioned on a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6. In this embodiment, the first external electrode 41 is positioned to extend from the first end face 7 to a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6.
[0070] An external electrode 40 positioned on the second end face 8 and connected to the second internal electrode layer 32 is defined as the second external electrode 42. The second external electrode 42 may be positioned not only on the second end face 8, but also on a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6. In this embodiment, the second external electrode 42 is positioned to extend from the second end face 8 to a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6.
[0071] The external electrode 40 is composed of a base electrode layer 50. The base electrode layer 50 that constitutes the first external electrode 41 is defined as the first base electrode layer 51. The base electrode layer 50 that constitutes the second external electrode 42 is defined as the second base electrode layer 52.
[0072] The base electrode layer 50 may include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.
[0073] (Underlayment electrode layer) The following describes the case where the underlayment electrode layer 50 is a baked layer. The baked layer contains glass components and metals. The glass components include at least one element such as B, Si, Ba, Mg, Al, and Li. The metal components include at least one such element such as Cu, Ni, Ag, Pd, Ag-Pd alloy, and Au.
[0074] The baked layer may consist of multiple layers. The baked layer is formed by applying a conductive paste containing glass components and metal to the laminate 2 and baking it. The baking process can be performed simultaneously with the baking of the internal electrode layer 30 and the dielectric layer 20, or after their baking. When the baked layer is baked simultaneously with the baking of the internal electrode layer and the dielectric layer, it is preferable to add a dielectric material instead of glass components to form the baked layer.
[0075] The thickness L in the longitudinal direction at the center 111 in the lamination direction of the baked layer located at the first end face 7 and the second end face 8 is preferably, for example, 3 μm or more and 160 μm or less.
[0076] Furthermore, when forming a baked layer as a base electrode layer 50 on a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6, it is preferable that the thickness of the base electrode layer 50 located on the first main surface 3, the second main surface 4, the first side surface 5, and the second side surface 6 at the central position in the longitudinal direction L is, for example, 3 μm or more and 40 μm or less.
[0077] (Conductive resin layer) The base electrode layer 50 may be composed of a baked layer and a conductive resin layer. In this case, the base electrode layer 50 has a two-layer structure in which the baked layer and the conductive resin layer are laminated in order. The conductive resin layer is arranged, for example, to cover the base electrode layer 50.
[0078] Specifically, the conductive resin layer is placed on the base electrode layer 50 located on the first end face 7 and the second end face 8. Preferably, the conductive resin layer is placed so as to extend to the base electrode layer 50 located on the first main surface 3, the second main surface 4, the first side surface 5, and the second side surface 6. However, the conductive resin layer may be placed only on the base electrode layer 50 located on the first end face 7 and the second end face 8.
[0079] The conductive resin layer is more flexible than the baked-on layer because it contains resin and metal. The conductive resin layer functions as a buffer layer. Therefore, even if flexural stress is applied to the mounting substrate and a physical force is applied to the multilayer ceramic capacitor 1 due to this stress, cracks are less likely to occur in the multilayer ceramic capacitor 1.
[0080] Furthermore, even when forces caused by thermal cycling act on the multilayer ceramic capacitor 1, cracks are less likely to occur in the multilayer ceramic capacitor 1.
[0081] The resin contained in the conductive resin layer is preferably a thermosetting resin such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the suitable resins because it has excellent heat resistance, moisture resistance, and adhesion. In addition, multiple types of resins, such as epoxy resin and phenolic resin, can be used in the conductive resin layer. The resin contained in the conductive resin layer is preferably present in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.
[0082] The conductive resin layer preferably contains a curing agent in addition to the resin. When epoxy resin is used as the resin, the curing agent is preferably a compound such as a phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, or amide-imide-based compound.
[0083] The conductive resin layer contains metal. The presence of metal in the conductive resin layer makes it electrically conductive. The metal contained in the conductive resin layer is included in the conductive resin layer as metal powder, i.e., conductive filler. The shape of the conductive filler is, for example, flattened. Contact between conductive fillers creates an electrical pathway within the conductive resin layer. This formed electrical pathway makes the conductive resin layer electrically conductive.
[0084] The metal contained in the conductive resin layer is preferably Ag, Cu, Ni, Sn, Bi, or an alloy containing these. The metal is particularly preferably Ag. The Ag may be pure Ag, or the Ag may be an alloy containing Ag. For example, the metal is preferably at least one of Ag, Ag-coated Cu, Ag-coated Ni, and Ag-coated alloy powder.
[0085] When using a material in which the surface of the metal powder is coated with Ag, it is preferable to use copper powder or Ni powder as the metal powder. Antioxidant treated Cu can also be used. The reason for using Ag-coated metal is that it allows for the use of an inexpensive metal as the base material while maintaining the properties of Ag.
[0086] The metal content in the conductive resin layer is preferably 35 vol% to 75 vol% relative to the total volume of the conductive resin layer. The shape of the conductive filler is not limited to the flattened shape described above, and may be spherical or other shapes. Furthermore, a mixture of spherical metal powder and flattened metal powder can be used. The average particle size of the conductive filler is also not particularly limited, but is preferably, for example, 0.3 μm to 10 μm.
[0087] The thickness of the conductive resin layer is preferably 10 μm or more and 200 μm or less.
[0088] Furthermore, the base electrode layer 50 may consist only of a conductive resin layer and not include a baking layer. In other words, it is also possible to form a conductive resin layer directly on the laminate 2 without forming a baking layer.
[0089] If the underlying electrode layer 50 is a thin film layer, the thin film layer can be formed by a thin film formation method such as sputtering or vapor deposition, and can be a layer of 1 μm or less in thickness on which metal particles are deposited.
[0090] (Plating layer) A plating layer 60 is provided on the surface of the external electrode 40. The plating layer 60 provided on the surface of the first external electrode 41 is defined as the first end-face side plating layer 61. The plating layer 60 provided on the surface of the second external electrode 42 is defined as the second end-face side plating layer 62.
[0091] The first end-face plating layer 61 is positioned to cover the first base electrode layer 51. The second end-face plating layer 62 is positioned to cover the second base electrode layer 52.
[0092] The material of the plating layer 60 includes at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, and Au.
[0093] The plating layer 60 may be composed of multiple layers. In this embodiment, the first end-face side plating layer 61 and the second end-face side plating layer 62 are each composed of two plating layers. When the plating layer 60 is composed of two plating layers, each plating layer is defined as the first plating layer 63 and the second plating layer 66, in order from the surface of the external electrode 40.
[0094] When the plating layer 60 is composed of a first plating layer 63 and a second plating layer 66, the first plating layer 63 is preferably a Ni plating layer. Furthermore, the second plating layer 66 is preferably a Sn plating layer.
[0095] If the first plating layer 63 is a Ni plating layer and the second plating layer 66 is a Sn plating layer, the first plating layer 63 included in the first end-face plating layer 61 is defined as the first Ni plating layer 64. The first plating layer 63 included in the second end-face plating layer 62 is defined as the second Ni plating layer 65.
[0096] The second plating layer 66 included in the first end-face plating layer 61 is defined as the first Sn plating layer 67. The second plating layer 66 included in the second end-face plating layer 62 is defined as the second Sn plating layer 68.
[0097] The first Ni plating layer 64 and the second Ni plating layer 65 prevent the underlying electrode layer 50 from being eroded by the solder when mounting the multilayer ceramic capacitor 1.
[0098] The first Sn plating layer 67 and the second Sn plating layer 68 improve the wettability of the solder when mounting the multilayer ceramic capacitor 1. The formation of the first Sn plating layer 67 and the second Sn plating layer 68 makes mounting easier.
[0099] Based on the above, it is preferable that the plating layers 60 in contact with the base electrode layer 50 be a Ni plating layer and a Sn plating layer in that order. The plating layer 60 may consist of three or more layers. The main component of the plating layer 60 may be a metal species other than Ni and Sn.
[0100] The preferred thickness of each layer of the plating layer 60 is 2 μm or more and 15 m or less.
[0101] (Dimensions of the multilayer ceramic capacitor) The dimensions of the multilayer ceramic capacitor 1, including the laminate 2, external electrodes 40, and plating layer 60, will be described below.
[0102] The length L of the multilayer ceramic capacitor 1 is defined as dimension L. Dimension L can be, for example, 0.2 mm or more and 10.0 mm or less. Preferably, dimension L is 3.0 mm or less, and more preferably 0.2 mm or less.
[0103] The dimension in the stacking direction T of the multilayer ceramic capacitor 1 is defined as the T dimension. The T dimension can be, for example, 0.1 mm or more and 5.0 mm or less. Preferably, the T dimension is 1.5 mm or less, and more preferably 0.1 mm or less.
[0104] The width dimension W of the multilayer ceramic capacitor 1 is defined as the W dimension. The W dimension can be, for example, 0.1 mm or more and 10.0 mm or less. Preferably, the W dimension is 1.5 mm or less, and more preferably 0.1 mm or less.
[0105] The L dimension of the multilayer ceramic capacitor 1 can be made larger than the W and T dimensions of the multilayer ceramic capacitor 1.
[0106] (Plating layer in the extended portion) The thickness of the plating layer 60 in the multilayer ceramic capacitor 1 of this embodiment will be described. Before describing the plating layer 60, the extended portion 401 of the external electrode 40 will be described.
[0107] (Extended portion) As shown in Figures 2 to 4, the first external electrode 41 is positioned to extend from the first end face 7 to a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6. The second external electrode 42 is positioned to extend from the second end face 8 to a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6. In this way, the portion of the first external electrode 41 located on the first main surface 3, the second main surface 4, the first side surface 5, or the second side surface 6 is defined as the extended portion 401. Similarly, the portion of the second external electrode 42 located on the first main surface 3, the second main surface 4, the first side surface 5, or the second side surface 6 is defined as the extended portion 401.
[0108] Referring to Figure 6, the thickness of the plating layer 60 in the multilayer ceramic capacitor 1 of this embodiment will be described. Figure 6 is an LT cross-sectional view of the external electrode 40, etc., which corresponds to an enlarged view of the framed area 260 in Figure 2. Specifically, Figure 6 shows the extended portion 401 on the first main surface 3 of the second external electrode 42. Hereafter, when referring to Figure 6, the thickness refers to the length T in the stacking direction unless otherwise noted.
[0109] (Tip and base of the extension) The tip 203 and base 207 of the extension 401 will be described with reference to Figure 6. For the extension 401 on the first main surface 3 of the second external electrode 42 shown in Figure 6, the tip 203 is defined as the portion at the end in the direction from the second end surface 8 toward the first end surface 7 (not shown in Figure 6). For the extension 401 on the first main surface 3 of the second external electrode 42, the base 207 is defined as the position at the intersection of the first main surface 3 and the second end surface 8.
[0110] The tip 203 and base 207 of the extension 401 on the first main surface 3 of the second external electrode 42 have been described above. The matters described for the extension 401 on the first main surface 3 of the second external electrode 42 also apply similarly to other extensions 401. For example, for the extension 401 on the second side surface 6 of the first external electrode 41, the tip 203 is defined as the portion at the end in the direction from the first end surface 7 (not shown in Figure 6) toward the second end surface 8. Also, for example, for the extension 401 on the second side surface 6 of the first external electrode 41, the base 207 is defined as the position at the intersection of the second side surface 6 and the first end surface 7.
[0111] (Plating layer thickness at the tip and base) In the multilayer ceramic capacitor 1 of this embodiment, the thickness of the first plating layer 63 provided on the extension portion 401 is thinner on the base end 207 side than on the tip end 203 side in the longitudinal direction L of the extension portion 401.
[0112] The thickness of the first plating layer 63 at the tip 203 is defined as the tip first plating thickness T11. The thickness of the first plating layer 63 at the base end 207 is defined as the base first plating thickness T1. The thickness of the extension 401 is defined as the extension thickness T3. The thickness of the first plating layer 63 is defined as the first plating layer thickness T20.
[0113] In the multilayer ceramic capacitor 1 of this embodiment, the first plating thickness T1 at the base end is thinner than the first plating thickness T11 at the tip end. This relaxes the limitation on the number of layers of the dielectric layer 20 and the internal electrode layer 30, making it easier to obtain the desired capacitance. The details will be explained below in order.
[0114] The thickness T3 of the extended portion increases from the tip 203 towards the base 207. Typically, the thickness T3 is greatest at the base 207.
[0115] Therefore, if the first plating layer thickness T20 is constant, the sum of the extended portion thickness T3 and the first plating layer thickness T20 will be maximum at the base end 207. In contrast, in the multilayer ceramic capacitor 1 of this embodiment, the base end first plating thickness T1 is thinner than the tip first plating thickness T11. Therefore, the sum of the extended portion thickness T3 and the first plating layer thickness T20 can be reduced.
[0116] This suppresses the increase in dimensions of parts of the multilayer ceramic capacitor 1 other than the laminate 2. As a result, the dimensions of the laminate 2 can be increased, and the number of layers of the dielectric layer 20 and the internal electrode layer 30 can be increased. Consequently, the capacitance can be increased.
[0117] Furthermore, by making the first plating thickness T11 at the tip relatively thicker than the first plating thickness T1 at the base, the thermomechanical strength of the multilayer ceramic capacitor 1 can be increased. These will be explained in detail below.
[0118] As mentioned above, if the thickness of the Ni plating layer is reduced, the heat resistance of the solder may decrease. Also, if the thickness of the Ni plating layer is reduced, the compressive stress applied to the edges of the Ni plating layer decreases, which may reduce the mechanical strength. In the multilayer ceramic capacitor 1 of this embodiment, the thinning of the first plating layer thickness T20 at the tip 203 of the extended portion 401, that is, the first plating thickness T11 at the tip, is suppressed. Therefore, it becomes easier to apply strong compressive stress to the Ni plating layer at the tip 203 of the extended portion 401, and as a result, it becomes easier to maintain strong thermomechanical strength.
[0119] As described above, in the multilayer ceramic capacitor 1 of this embodiment, by maintaining the first plating thickness T11 at the tip and thinning only the first plating thickness T1 at the base, it is possible to increase the capacitance while maintaining strong thermomechanical strength.
[0120] The ratio or proportion between the first plating thickness T11 at the tip and the first plating thickness T1 at the base is not particularly limited. For example, the ratio between the first plating thickness T11 at the tip and the first plating thickness T1 at the base can be, for example, 2:1. Alternatively, the ratio between the first plating thickness T11 at the tip and the first plating thickness T1 at the base can be, for example, 1 < (first plating thickness T11 at the tip / first plating thickness T1 at the base) < 3.
[0121] (Trend of change in the thickness of the extended portion) In the multilayer ceramic capacitor 1 of this embodiment, the first plating layer thickness T20 of the first plating layer 63 provided on the extended portion 401 becomes thinner in the length direction L of the extended portion 401 from the tip 203 side to the base end 207 side.
[0122] The central position in the longitudinal direction L between the tip 203 and the base 207 is defined as the center 209. The thickness of the first plating layer 63 at the center 209 is defined as the center first plating thickness T21.
[0123] The first plating thickness T11 at the tip, the first plating thickness T21 in the center, and the first plating thickness T1 at the base end are progressively thinner in this order. This makes it easier to reduce the sum of the thickness T3 of the extended portion and the thickness T20 of the first plating layer.
[0124] As mentioned above, the thickness T3 of the extended portion tends to increase from the tip 203 towards the base 207. Therefore, the thickness T20 of the first plating layer is made thinner from the tip 203 towards the base 207. As a result, the sum of the thickness T3 of the extended portion and the thickness T20 of the first plating layer can be reduced, and the capacitance of the multilayer ceramic capacitor 1 can be increased further.
[0125] Furthermore, the statement that the thickness T3 of the extended portion thins from the tip 203 side to the base 207 side does not mean that the thickness T3 of the extended portion decreases strictly monotonically. Rather, the statement that the thickness T3 of the extended portion thins from the tip 203 side to the base 207 side means that, as an overall trend from the tip 203 side to the base 207 side, there is a tendency for it to thin.
[0126] (Thickness of the first and second plating layers) In the multilayer ceramic capacitor 1 of this embodiment, at the tip 203 side in the longitudinal direction L of the extension 401, the thickness of the first plating layer 63 and the thickness of the second plating layer 66 provided on the extension 401 can be made substantially the same. In addition, at the base end 207 side in the longitudinal direction L of the extension 401, the thickness of the first plating layer 63 provided on the extension 401 is substantially half the thickness of the second plating layer 66. For example, the thickness of the first plating layer 63 is 40% to 60% of the thickness of the second plating layer 66, and more preferably 45% to 55%.
[0127] The thickness of the second plating layer 66 at the tip 203 is defined as the tip second plating thickness T12. The thickness of the second plating layer 66 at the base end 207 is defined as the base end second plating thickness T2. The thickness of the second plating layer 66 is also defined as the second plating layer thickness T30.
[0128] In the multilayer ceramic capacitor 1 of this embodiment, the first plating thickness T11 at the tip is approximately the same as the second plating thickness T12 at the tip. In addition, the first plating thickness T1 at the base is approximately half the second plating thickness T2 at the base.
[0129] In the multilayer ceramic capacitor 1, the portion where the extended portion 401, the first plating layer 63, and the second plating layer 66 overlap is a bulging portion, that is, a portion with a larger external dimension.
[0130] In this embodiment, the first plating layer thickness T20 and the second plating layer thickness T30 are set to a predetermined relationship at the tip 203 and base 207 of the larger external dimensions. This makes it easier to obtain the desired capacitance by relaxing the limitation on the number of layers (dimensional limitation) between the dielectric layer 20 and the internal electrode layer 30 in the laminate 2, while maintaining strong thermomechanical strength.
[0131] The above-mentioned relationship between the first tip plating thickness T11 and the second tip plating thickness T12, and the relationship between the first base platen thickness T1 and the second base platen thickness T2 are examples. The relationship between the first tip plating thickness T11 and the second tip plating thickness T12 can be, for example, 0.5 < (first tip plating thickness T11 / second tip plating thickness T12) < 1. Similarly, the relationship between the first base platen thickness T1 and the second base platen thickness T2 can be, for example, 1 < (first base platen thickness T1 / second base platen thickness T2) < 3.
[0132] (Total thickness in the extended portion) In the multilayer ceramic capacitor 1 of this embodiment, the sum of the thickness of the extended portion 401, the thickness of the first plating layer 63, and the thickness of the second plating layer 66 is substantially uniform along the entire length L of the extended portion 401.
[0133] The total thickness of the extended portion T31 is defined as the sum of the thickness of the extended portion T3, the thickness of the first plating layer T20, and the thickness of the second plating layer T30 in the extended portion 401.
[0134] The total thickness T31 of the extended portion is approximately uniform, or nearly constant, over the length L from the tip 203 to the base 207. This suppresses the formation of particularly bulging areas (areas with larger external dimensions) in the extended portion 401. As a result, it becomes easier to obtain the desired capacitance.
[0135] The above-mentioned specifications regarding the sum of the extension thickness T3, the first plating layer thickness T20, and the second plating layer thickness T30 are merely examples. In the longitudinal direction L from the tip 203 to the base end 207, the ratio of the maximum thickness of the extension to the minimum thickness of the total extension thickness T31 is preferably 1 or more and 3 or less.
[0136] (Near-tip region and near-base region) With respect to the extension portion 401 on the first main surface 3 of the second external electrode 42, the tip portion of the first plating layer 63 covering the extension portion 401 in the direction from the second end face 8 toward the first end face 7 (not shown in Figure 6) is defined as the first plating end 201. From the first plating end 201, a range of 100 μm in the length direction L toward the second end face 8 is defined as the near-tip region 251.
[0137] The base end vicinity region 253 is defined as the 80 μm range of the second plating layer 66, extending from the surface 205 on the second end face 8 side in the length direction L toward the first end face 7 (not shown in Figure 6) in the length direction L.
[0138] The length L1 of the tip-near region 251 shown in Figure 6 is 100 μm. The length L2 of the base-near region 253 shown in Figure 6 is 80 μm.
[0139] In the multilayer ceramic capacitor 1 of this embodiment, the average value of the first plating layer thickness T20 in the tip-near region 251 is more than twice the average value of the first plating layer thickness T20 in the base-near region 253. As a result, the thickness of the first plating layer 63 near the first plated edge 201, in other words, near the tip 203, is thicker than the thickness of the first plating layer 63 near the second end face 8. As a result, the occurrence of cracks in the multilayer ceramic capacitor 1 can be suppressed. Regarding the thickness of the first plating layer 63 in the base-near region 253, in the range from the second end face 8 to the surface 205 of the second plating layer 66, the thickness of the first plating layer 63 in the direction perpendicular to the surface of the base electrode layer 50 is defined as the first plating layer thickness. The thickness of the first plating layer 63 in the direction perpendicular to the surface of the base electrode layer 50 is shown as the first plating layer thickness T201.
[0140] According to the above configuration, the mechanical strength near the tip 203 of the extended portion 401, where cracks are prone to occur due to stress concentration, can be improved. As a result, the occurrence of cracks due to stress concentration that are prone to occur at the tip 203 of the extended portion 401 can be suppressed.
[0141] In addition, the above configuration allows for control of the outer diameter of the multilayer ceramic capacitor 1. In particular, the dimensions in the stacking direction T or the width direction W, which determine the height of the multilayer ceramic capacitor 1, can be adjusted. This is because the first plating layer thickness T20 in the base end vicinity region 253, which often defines the height of the multilayer ceramic capacitor 1, can be adjusted to an appropriate range. As a result, more internal electrode layers 30 and dielectric layers 20 can be stacked on the laminate 2, making it easier to secure the desired capacitance.
[0142] (Measurement Method) The method for measuring the thickness (length) of the multilayer ceramic capacitor 1 of this embodiment will be described below. The thickness of the plating layer, etc., is measured in the cross-section of the multilayer ceramic capacitor 1. The cross-section shall be one of the LT cross-section, WT cross-section, or LW cross-section. In the case of the LT cross-section, the cross-section shall be at the center 113 in the width direction; in the case of the WT cross-section, the cross-section shall be at the center 112 in the length direction; and in the case of the LW cross-section, the cross-section shall be at the center 111 in the stacking direction.
[0143] The following explanation uses the LT cross-section as an example. The multilayer ceramic capacitor 1 is polished on surfaces parallel to the length direction L and the stacking direction T. Then, the LT cross-section at the center position in the width direction W is exposed. The thickness of the plating layer, etc., is measured at the exposed cross-section. The cross-section can be observed, for example, using SEM images.
[0144] The provisions regarding the thickness of the plating layer in this application shall be deemed satisfied if a value within the specified range is measured in any of the LT, WT, and LW cross-sections.
[0145] (Method for Manufacturing Multilayer Ceramic Capacitors) The method for manufacturing the multilayer ceramic capacitor 1 will be described below. However, the method for manufacturing the multilayer ceramic capacitor 1 is not limited to the method described below.
[0146] Prepare a conductive paste for the dielectric sheet and internal electrode layer. The conductive paste for the dielectric sheet and internal electrode layer contains a binder and a solvent. Known binders and solvents can be used. The dielectric sheet is also called a ceramic green sheet.
[0147] A dielectric sheet with an internal electrode layer pattern is prepared. Specifically, a conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern to prepare a dielectric sheet with a first internal electrode layer pattern and a dielectric sheet with a second internal electrode layer pattern. Printing is performed, for example, by screen printing or gravure printing.
[0148] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first outer layer. On top of this, dielectric sheets with printed first internal electrode layer patterns and dielectric sheets with printed second internal electrode layer patterns are sequentially stacked to form the inner layer. Furthermore, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the inner layer to form the second outer layer. This completes the production of the laminated sheet.
[0149] Next, the prepared laminated sheets are pressed in the lamination direction using a hydrostatic press or similar method to create laminated blocks.
[0150] Laminated blocks are cut into individual pieces to produce laminated chips. Specifically, laminated blocks are cut with a cutting blade to create individual pieces, and a pre-firing laminate is produced.
[0151] The laminated chips are fired to create the laminated structure. Before firing, the corners and edges of the laminated chips may be rounded using barrel polishing or other methods. The firing temperature depends on the dielectric and internal electrode layer materials, but a temperature of 900°C to 1400°C is desirable. Barrel polishing and other methods can also be performed on the laminated structure after firing.
[0152] Next, the external electrodes are formed. First, a conductive paste, which will serve as the base electrode layer, is applied to both end faces of the laminate 2 to form the base electrode layer. In forming the baked layer as the base electrode layer, a conductive paste containing glass components and metal is applied by dipping or other means, and then baked. The baking temperature at this time is preferably 700°C to 900°C.
[0153] When forming the base electrode layer with a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer. As a method for forming the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the baked layer or the laminate. Then, heat treatment is performed at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably a nitrogen gas atmosphere. In addition, in order to prevent the scattering of resin and to prevent oxidation of various metal components, it is preferable to keep the oxygen concentration below 100 ppm.
[0154] Furthermore, when forming the underlying electrode layer as a thin film layer, the underlying electrode layer can be formed by a thin film formation method such as sputtering or vapor deposition. The underlying electrode layer formed as a thin film layer can be a layer of 1 μm or less in thickness with metal particles deposited on it.
[0155] Subsequently, a plating layer is formed on the surface of the external electrode, such as the surface of the base electrode layer or the surface of the conductive resin layer. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer which serves as the base electrode layer.
[0156] In this embodiment, in order to form the plating layer to have the desired thickness described above, the plating layer can be formed using, for example, a so-called differential thickness plating method. Specifically, the following plating methods (1) to (3) are examples.
[0157] (1) A method for forming a plating layer using a plating bath type that allows plating to concentrate at a desired location. For example, by adjusting the flow rate of the plating solution, the temperature of the plating solution, the configuration of the electrodes, and the arrangement of the electrodes in electroplating, a plating layer of a desired thickness can be formed at a desired location.
[0158] (2) A method of plating in which the parts to be plated are arranged in an orderly manner, and a shielding plate is placed in the area where the thickness of the plating layer is to be reduced before plating.
[0159] (3) A method in which a conductive medium comes into contact with an area where the thickness of the plating layer is to be reduced, so that the thickness of the plating layer does not increase near the area (surface) in contact with the conductive medium.
[0160] As described above, a multilayer ceramic capacitor having a plating layer of a desired thickness can be manufactured.
[0161] Embodiments of the present invention have been described above. However, the present invention is not limited to the embodiments described above, and various modifications, variations, and combinations are possible.
[0162] For example, multilayer ceramic capacitors are not limited to having two terminals; they can also be multilayer ceramic capacitors with three or more terminals.
[0163] Furthermore, multilayer ceramic capacitors are an example of multilayer ceramic electronic components. The technology described above can also be applied to other multilayer ceramic electronic components besides multilayer ceramic capacitors.
[0164] As described above, the multilayer ceramic capacitor 1 of this embodiment has a structure in which the thickness of the Ni plating formed on the external electrodes 40 on the first main surface 3, the second main surface 4, the first side surface 5, and the second side surface 6 gradually decreases from the end of the external electrode 40 toward the end face.
[0165] This makes it possible to suppress the increase in the thickness of the area that has been the most bulging in the multilayer ceramic capacitor 1 (the area where the thickness of the external electrode, the thickness of the Ni plating layer, and the thickness of the Sn plating layer are added together). As a result, the limit on the number of layers is relaxed, and it becomes easier to obtain the desired capacitance. In addition, strong compressive stress can be generated at the ends of the external electrode 40, making it possible to maintain strong thermomechanical strength.
[0166] 1 Multilayer ceramic capacitor 2 Laminate 3 First main surface 4 Second main surface 5 First side surface 6 Second side surface 7 First end surface 8 Second end surface 20 Dielectric layer 30 Internal electrode layer 40 External electrode 50 Underlay electrode layer 60 Plating layer 63 First plating layer 64 First Ni plating layer 65 Second Ni plating layer 66 Second plating layer 67 First Sn plating layer 68 Second Sn plating layer 111 Center in the lamination direction 112 Center in the length direction 113 Center in the width direction 201 First plated end 203 Tip 205 Surface 207 Base end 209 Center 251 Region near tip 253 Region near base end 260 Enclosed frame 401 Extension L Length direction T Lamination direction T1 Base end first plating thickness T11 Tip first plating thickness T12 Tip second plating thickness T2 Base end second plating thickness T20 First plating layer thickness T21 Center first plating thickness T3 Extension thickness T30 Second plating layer thickness T31 Total thickness of extension W Width direction
Claims
1. A multilayer ceramic electronic component comprising: a laminate including a dielectric layer and an internal electrode layer stacked in the stacking direction, having a first main surface and a second main surface facing the stacking direction, a first side surface and a second side surface facing the width direction intersecting the stacking direction, and a first end surface and a second end surface facing the length direction intersecting the stacking direction and the width direction; an external electrode provided on the first end surface and the second end surface and connected to the internal electrode layer; a first plating layer provided on the external electrode; and a second plating layer provided on the first plating layer, wherein the external electrode has an extended portion extending to at least a part of the first main surface, the second main surface, the first side surface, and the second side surface, and the thickness of the first plating layer provided on the extended portion is thinner on the base end side than on the tip side in the length direction of the extended portion.
2. The multilayer ceramic electronic component according to claim 1, wherein the thickness of the first plating layer provided on the extended portion decreases from the tip end to the base end in the longitudinal direction of the extended portion.
3. The multilayer ceramic electronic component according to claim 1 or 2, wherein the thickness of the first plating layer provided on the extended portion is substantially the same as that of the second plating layer at the leading end of the extended portion in the longitudinal direction, while at the base end of the extended portion in the longitudinal direction, it is substantially half the thickness of that of the second plating layer.
4. The multilayer ceramic electronic component according to claim 1 or 2, wherein the sum of the thickness of the extension, the thickness of the first plating layer, and the thickness of the second plating layer is substantially uniform over the entire length of the extension.