Electronic circuit, comparator, and imaging device

Abstract

The present invention prevents GIDL generated by a clamp circuit from propagating to an input voltage.　This electronic circuit comprises: a transistor that amplifies an input signal; a clamp circuit that clamps the input signal; and a switch that is connected between the clamp circuit and an input of the transistor. The electronic circuit may further comprise a detection circuit that opens and closes the switch on the basis of the detection result of the output of the transistor. When the input signal exceeds a prescribed voltage, the switch may be turned off, and when the input signal is equal to or less than the prescribed voltage, the switch may be turned on.

Description

Electronic Circuit, Comparator, and Imaging Device

[0008] , ,

[0007] ,

[0001] This technology relates to an electronic circuit, a comparator, and an imaging device. Specifically, this technology relates to an electronic circuit, a comparator, and an imaging device provided with a clamping circuit that clamps an input voltage.

[0002] In an electronic circuit, a clamping circuit that clamps an input voltage may be provided. For example, a memory control device capable of reducing gate-induced drain leakage current is disclosed (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2010-187162

[0004] However, in the above-described conventional technology, although GIDL (Gate Induced Drain Leakage current) caused by the potential difference between the bulk and the source can be suppressed, there is a possibility that it may not be able to cope with the clamping of an arbitrary input voltage.

[0005] This technology has been created in view of such a situation, and an object thereof is to prevent GIDL generated by the clamping circuit from propagating to the input voltage.

[0006] This technology has been made to solve the above-described problems, and a first aspect thereof is an electronic circuit including a transistor that amplifies an input signal, a clamping circuit that clamps the input signal, and a switch connected between the clamping circuit and the input of the transistor. This brings about an effect of preventing GIDL from the clamping circuit from propagating to the input signal based on the opening and closing operation of the switch.

[0007] Also, in the first aspect, a detection circuit that opens and closes the switch based on the detection result of the output of the transistor may be provided. This brings about an effect that the switch is opened and closed while the clamping function of the input signal operates properly.

[0008] Also, in the first aspect, the detection circuit may be an inverter. This brings about an effect that the switch is opened and closed based on the detection result of the output of the transistor.

[0009] Furthermore, in the first aspect, a current source for driving the inverter may be provided. This has the effect of suppressing sharp current fluctuations to the power supply and ground when an inverter is used in the detection circuit.

[0010] Furthermore, in the first aspect, the detection circuit may be a NAND circuit. This results in the switch being opened and closed and the effectiveness of the clamping function being controlled based on the detection result of the transistor output.

[0011] Furthermore, in the first aspect, a current source for driving the NAND circuit may be provided. This has the effect of suppressing sharp current fluctuations to the power supply and ground when a NAND circuit is used in the detection circuit.

[0012] Furthermore, in the first aspect, the transistor and the switch may be PMOS transistors. This provides the effect of preventing GIDL from the clamp circuit from propagating to the input signal while corresponding to the polarity of the transistor.

[0013] Furthermore, in the first aspect, the transistor and the switch may be NMOS transistors. This provides the effect of preventing GIDL from the clamp circuit from propagating to the input signal while corresponding to the polarity of the transistor.

[0014] Furthermore, in the first aspect, the switch may be turned off when the input signal exceeds a predetermined voltage, and turned on when the input signal is below the predetermined voltage. This results in the switch being opened and closed while the input signal clamping function works appropriately according to the magnitude of the input signal.

[0015] Furthermore, the second aspect is a comparator comprising a differential amplifier to which an input signal and a reference signal are input, a subsequent amplifier connected to the differential amplifier, a clamping circuit that clamps the input of the subsequent amplifier, and a switch connected between the clamping circuit and the input of the subsequent amplifier. This provides the effect of preventing GIDL from the clamping circuit from propagating to the input of the comparator's subsequent amplifier based on the opening and closing operation of the switch.

[0016] Furthermore, the third aspect is an imaging device comprising a pixel array section in which pixels are arranged in a matrix in the row direction and column direction, and a comparator that compares the pixel signals read from the pixels with a reference signal, wherein the comparator comprises a differential amplifier into which the pixel signals and the reference signal are input, a downstream amplifier connected to the downstream of the differential amplifier, a clamp circuit that clamps the input of the downstream amplifier, and a switch connected between the clamp circuit and the input of the downstream amplifier. This results in the pixel signals being digitized while preventing GIDL from the clamp circuit from propagating to the input of the downstream amplifier of the comparator based on the opening and closing operation of the switch.

[0017] This is a diagram showing an example of the configuration of an electronic circuit according to the first embodiment. This is a diagram showing an example of the configuration of an electronic circuit according to the second embodiment. This is a diagram showing an example of the configuration of an electronic circuit according to the third embodiment. This is a diagram showing an example of the configuration of an electronic circuit according to the fourth embodiment. This is a diagram showing an example of the configuration of an electronic circuit according to the fifth embodiment. This is a diagram showing an example of the configuration of an electronic circuit according to the sixth embodiment. This is a block diagram showing an example of the configuration of an imaging device according to the seventh embodiment. This is a block diagram showing an example of the configuration of a solid-state imaging device according to the seventh embodiment. This is a block diagram showing an example of the configuration of a signal readout circuit for one column according to the seventh embodiment. This is a diagram showing an example of the configuration of a comparator to which a clamp circuit is applied, to which the clamping operation is limited based on the opening and closing of a switch according to the seventh embodiment. This is a block diagram showing a schematic example of the configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of the imaging unit.

[0018] The following describes embodiments for implementing this technology (hereinafter referred to as "embodiments"). The description will be in the following order: 1. First embodiment (an example in which a switch is connected between a clamp circuit that clamps an input signal and the input of a PMOS transistor) 2. Second embodiment (an example in which a switch is connected between a clamp circuit that clamps an input signal and the input of a PMOS transistor, and an inverter is used in the detection circuit) 3. Third embodiment (an example in which a switch is connected between a clamp circuit that clamps an input signal and the input of a PMOS transistor, and a NAND circuit is used in the detection circuit) 4. Fourth embodiment (an example in which a switch is connected between a clamp circuit that clamps an input signal and the input of a PMOS transistor, and an inverter driven via a current source is used in the detection circuit) 5. Fifth embodiment (an example in which a switch is connected between a clamp circuit that clamps an input signal and the input of a PMOS transistor, and a NAND circuit driven via a current source is used in the detection circuit) 6. Sixth embodiment (an example in which a switch is connected between a clamp circuit that clamps an input signal and the input of an NMOS transistor) 7. Seventh embodiment (an example in which a clamp circuit in which the clamping operation is limited based on the opening and closing of a switch is applied to an imaging device) 8. Examples of applications to mobile devices

[0019] <1. First Embodiment> Figure 1 is a diagram showing an example of the configuration of an electronic circuit according to the first embodiment.

[0020] In the figure, this electronic circuit includes a PMOS transistor 12, a clamp circuit 13, a switch 10, and a detection circuit 14.

[0021] The gate of the PMOS transistor 12 is subjected to the input signal SIN. At this time, the PMOS transistor 12 can amplify the input signal SIN and output the output signal SOUT. The source of the PMOS transistor 12 is connected to the power supply potential VDD.

[0022] The clamp circuit 13 clamps the input signal SIN. The clamp circuit 13 is connected to the gate of the PMOS transistor 12 via the switch 10. In this case, the clamp circuit 13 can fix the gate potential of the PMOS transistor 12 to a predetermined potential so that the voltage of the input signal SIN does not drop too low when the voltage of the input signal SIN drops.

[0023] Switch 10 is connected between the clamp circuit 13 and the gate of the PMOS transistor 12. When switch 10 is turned off, it is possible to prevent GIDL and off-leak from the clamp circuit 13 from propagating to the input signal SIN. Switch 10 can be opened and closed based on the detection result of the detection circuit 14. When the input signal SIN exceeds a predetermined voltage, switch 10 is turned off, and when the input signal SIN is below the predetermined voltage, switch 10 is turned on.

[0024] The switch 10 includes a PMOS transistor 11. The gate of the PMOS transistor 11 is connected to the detection output of the detection circuit 14. The source of the PMOS transistor 11 is connected to the clamp circuit 13. The drain of the PMOS transistor 11 is connected to the gate of the PMOS transistor 12. The bulk of the PMOS transistor 11 is connected to the power supply potential VDD.

[0025] The detection circuit 14 opens and closes the switch 10 based on the detection result of the output signal SOUT of the PMOS transistor 12. At this time, if the input signal SIN exceeds a predetermined voltage, the detection circuit 14 sets the gate voltage of the PMOS transistor 11 to a high level and turns off the PMOS transistor 11. This prevents GIDL and off-leak generated by the clamp circuit 13 from propagating to the input voltage SIN. In addition, since the potential difference between the gate and bulk of the PMOS transistor 11 does not become a large negative potential, GIDL between the bulk and drain can also be suppressed.

[0026] On the other hand, the detection circuit 14 sets the gate voltage of the PMOS transistor 11 to a low level and turns on the PMOS transistor 11 when the input signal SIN is below a predetermined voltage. This allows the clamp circuit 13 and the gate of the PMOS transistor 12 to be connected via the PMOS transistor 11, and the gate potential of the PMOS transistor 12 can be fixed at a predetermined potential to prevent the voltage of the input signal SIN from dropping too low.

[0027] As described above, in the first embodiment, a switch 10 is connected between the clamp circuit 13, which clamps the input signal SIN, and the input of the PMOS transistor 12. This prevents GIDL from the clamp circuit 13 from propagating to the input signal SIN based on the opening and closing operation of the switch 10.

[0028] <2. Second Embodiment> In the first embodiment described above, a switch 10 was connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12. In this second embodiment, a switch 10 is connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12, and an inverter is used in the detection circuit 14.

[0029] Figure 2 shows an example of the configuration of an electronic circuit according to the second embodiment.

[0030] In the figure, this electronic circuit includes an inverter 24 as the detection circuit 14 of the first embodiment described above. Furthermore, this electronic circuit includes an NMOS transistor 23 as the clamp circuit 13 of the first embodiment described above. The other configurations of this electronic circuit are the same as those of the electronic circuit of the first embodiment described above.

[0031] The NMOS transistor 23 is connected in series with the PMOS transistor 11. The drain of the NMOS transistor 23 is connected to the power supply potential VDD. The gate of the NMOS transistor 23 is connected to the drain of the PMOS transistor 12. In this configuration, the NMOS transistor 23 can clamp the input signal SIN of the PMOS transistor 12 based on the output signal SOUT of the PMOS transistor 12.

[0032] In this case, when the NMOS transistor 23 is used as the clamp circuit 13, when the potential of the input signal SIN drops to a level where the NMOS transistor 23 turns on sufficiently relative to the output signal SOUT, current flows from the input signal SIN through the NMOS transistor 23 to the power supply potential VDD, and a clamp operation is achieved where the potential of the input signal SIN stops dropping.

[0033] On the other hand, at high voltages, when the input signal SIN does not require clamping, a large potential difference is generated between the bulk and source of the NMOS transistor 23, increasing GIDL and propagating to the input signal SIN, thus degrading signal quality. Also, when the input signal SIN begins to decrease from a high voltage, the potential difference between the power supply potential VDD and the input signal SIN gradually increases, causing the NMOS transistor 23 to off-leak before the clamping operation, resulting in degraded signal quality.

[0034] The inverter 24 includes a PMOS transistor 21 and an NMOS transistor 22. The PMOS transistor 21 and the NMOS transistor 22 are connected in series with each other. The gates of the PMOS transistor 21 and the NMOS transistor 22 are connected to the drains of the PMOS transistor 12. The connection point of the PMOS transistor 21 and the NMOS transistor 22 is connected to the gate of the PMOS transistor 11. Here, the output signal SOUT from the drain of the PMOS transistor 12 can change from the power supply potential VDD to the ground potential in accordance with the input signal SIN. Therefore, the inverter 24 can improve the stability of the on / off switching of the PMOS transistor 11 by controlling the gate potential of the PMOS transistor 11 based on the output signal SOUT.

[0035] Here, the inverter 24 sets the gate voltage of the PMOS transistor 11 to a high level and turns off the PMOS transistor 11 when the output signal SOUT is below a predetermined voltage. This prevents GIDL and off-leak generated by the NMOS transistor 23 from propagating to the input voltage SIN.

[0036] On the other hand, when the output signal SOUT exceeds a predetermined voltage, the inverter 24 sets the gate voltage of the PMOS transistor 11 to a low level and turns on the PMOS transistor 11. This allows the gates of the NMOS transistor 23 and the PMOS transistor 12 to be connected via the PMOS transistor 11, and the gate potential of the PMOS transistor 12 can be fixed at a predetermined potential to prevent the voltage of the input signal SIN from dropping too low.

[0037] Thus, in the second embodiment described above, a PMOS transistor 11 is connected between the input of the NMOS transistor 23 that clamps the input signal SIN and the input of the PMOS transistor 12, and an inverter 24 is used in the detection circuit 14. This makes it possible to set the PMOS transistor 11 on or off based on the output signal SOUT of the PMOS transistor 12, and prevents GIDL from the NMOS transistor 23 from propagating to the input signal SIN.

[0038] <3. Third Embodiment> In the second embodiment described above, a switch 10 was connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12, and an inverter 24 was used as the detection circuit. In this third embodiment, a switch 10 is connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12, and a NAND circuit is used as the detection circuit 14.

[0039] Figure 3 shows an example of the configuration of an electronic circuit according to the third embodiment.

[0040] In the figure, this electronic circuit includes a NAND circuit 34 instead of the inverter 24 of the second embodiment described above. The other configurations of this electronic circuit are the same as those of the electronic circuit of the second embodiment described above.

[0041] The NAND circuit 34 comprises PMOS transistors 31 and 35 and NMOS transistors 32 and 33. The PMOS transistors 31 and NMOS transistors 32 and 33 are connected in series in that order. The gates of PMOS transistor 31 and NMOS transistor 32 are connected to the drain of PMOS transistor 12. The connection point of PMOS transistor 31 and NMOS transistor 32 is connected to the gate of PMOS transistor 11. PMOS transistor 35 is connected in parallel with PMOS transistor 31. A control signal CNT is applied to the gates of NMOS transistor 33 and PMOS transistor 35. The control signal CNT can control the effectiveness of the clamping function.

[0042] In this case, if the clamping function of the NMOS transistor 23 is to be activated, the control signal CNT is set to a high level. At this time, the NMOS transistor 33 is turned on and the PMOS transistor 35 is turned off, and the NAND circuit 34 can operate in the same way as the inverter 24 in the second embodiment described above.

[0043] On the other hand, if the clamping function of the NMOS transistor 23 is to be disabled, the control signal CNT is set to a low level. In this case, the NMOS transistor 33 is off, the PMOS transistor 35 is on, and the gate potential of the PMOS transistor 11 is fixed at a high level. As a result, the NMOS transistor 23 is disconnected from the gate of the PMOS transistor 12, and the clamping of the input signal SIN is disabled.

[0044] Thus, in the third embodiment described above, a PMOS transistor 11 is connected between the input of the NMOS transistor 23 and the PMOS transistor 12, which clamp the input signal SIN, and a NAND circuit 34 is used in the detection circuit 14. This makes it possible to set the PMOS transistor 11 on or off based on the output signal SOUT of the PMOS transistor 12, preventing GIDL from the NMOS transistor 23 from propagating to the input signal SIN, and also allowing control of the effectiveness of the clamping function.

[0045] <4. Fourth Embodiment> In the above-described second embodiment, the switch 10 is connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12, and the inverter 24 is used for the detection circuit 14. In this fourth embodiment, the switch 10 is connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12, and the inverter 24 driven via a current source is used for the detection circuit 14.

[0046] FIG. 4 is a diagram showing a configuration example of an electronic circuit according to the fourth embodiment.

[0047] In this figure, a current source 41 is added to the electronic circuit of the above-described second embodiment in this electronic circuit. The other configuration of this electronic circuit is the same as the configuration of the electronic circuit of the above-described second embodiment.

[0048] The current source 41 drives the inverter 24. The current source 41 is connected in series to the NMOS transistor 22. At this time, the current source 41 can maintain the constancy of the current flowing through the inverter 24.

[0049] Thus, in the above-described fourth embodiment, the switch 10 is connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12, and the inverter 24 driven via the current source 41 is used for the detection circuit 14. Thereby, while suppressing steep current fluctuations to the power supply and the ground, based on the output signal SOUT of the PMOS transistor 12, the PMOS transistor 11 can be set to on or off, and the GIDL from the NMOS transistor 23 can be prevented from propagating to the input signal SIN.

[0050] <5. Fifth Embodiment> In the above-described third embodiment, the switch 10 is connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12, and the NAND circuit 34 is used for the detection circuit 14. In this fifth embodiment, the switch 10 is connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12, and the NAND circuit 34 driven via a current source is used for the detection circuit 14.

[0051] Figure 5 shows an example of the configuration of an electronic circuit according to the fifth embodiment.

[0052] In the figure, this electronic circuit has a current source 41 added to the electronic circuit of the third embodiment described above. The other configurations of this electronic circuit are the same as those of the electronic circuit of the third embodiment described above.

[0053] The current source 41 drives the NAND circuit 34. The current source 41 is connected in series with the NMOS transistor 33. In this configuration, the current source 41 can maintain the steady state of the current flowing through the NAND circuit 34.

[0054] Thus, in the fifth embodiment described above, a switch 10 is connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12, and a NAND circuit 34 driven via a current source 41 is used as the detection circuit 14. This makes it possible to set the PMOS transistor 11 on or off based on the output signal SOUT of the PMOS transistor 12 while suppressing sharp current fluctuations to the power supply and ground, thereby preventing GIDL from the NMOS transistor 23 from propagating to the input signal SIN, and also allowing control of the effectiveness of the clamp function.

[0055] <6. Sixth Embodiment> In the first embodiment described above, a switch 10 was connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12. In this sixth embodiment, a switch is connected between the clamp circuit that clamps the input signal and the input of the NMOS transistor.

[0056] Figure 6 shows an example of the configuration of an electronic circuit according to the sixth embodiment.

[0057] In the figure, this electronic circuit includes an NMOS transistor 62, a clamp circuit 63, a switch 60, and a detection circuit 64.

[0058] The gate of the NMOS transistor 62 is subjected to the input signal SIN. At this time, the NMOS transistor 62 amplifies the input signal SIN and outputs the output signal SOUT. The source of the NMOS transistor 62 is connected to ground potential GND.

[0059] The clamp circuit 63 clamps the input signal SIN. The clamp circuit 63 is connected to the gate of the NMOS transistor 62 via the switch 60. In this case, the clamp circuit 63 can fix the gate potential of the NMOS transistor 62 to a predetermined potential so that the voltage of the input signal SIN does not rise too high when the voltage of the input signal SIN rises.

[0060] Switch 60 is connected between the clamp circuit 63 and the gate of the NMOS transistor 62. When switch 60 is turned off, it is possible to prevent GIDL and off-leak signals from the clamp circuit 63 from propagating to the input signal SIN. Switch 60 can be opened or closed based on the detection result from the detection circuit 64.

[0061] The switch 60 includes an NMOS transistor 61. The gate of the NMOS transistor 61 is connected to the detection output of the detection circuit 64. The source of the NMOS transistor 61 is connected to the clamp circuit 63. The drain of the NMOS transistor 61 is connected to the gate of the NMOS transistor 62.

[0062] The detection circuit 64 opens and closes the switch 60 based on the detection result of the output signal SOUT of the NMOS transistor 62. At this time, if the input signal SIN exceeds a predetermined voltage, the detection circuit 64 sets the gate voltage of the NMOS transistor 61 to a high level and turns on the NMOS transistor 61. This allows the clamp circuit 63 and the gate of the NMOS transistor 62 to be connected via the NMOS transistor 61, and the gate potential of the NMOS transistor 62 can be fixed at a predetermined potential to prevent the voltage of the input signal SIN from rising too high.

[0063] On the other hand, the detection circuit 64 sets the gate voltage of the NMOS transistor 61 to a low level and turns off the NMOS transistor 61 when the input signal SIN is below a predetermined voltage. This prevents GIDL and off-leak generated by the clamp circuit 63 from propagating to the input voltage SIN.

[0064] Thus, in the sixth embodiment described above, a switch 60 is connected between the clamp circuit 63, which clamps the input signal SIN, and the input of the NMOS transistor 62. This prevents GIDL from the clamp circuit 63 from propagating to the input signal SIN based on the opening and closing operation of the switch 60.

[0065] <7. Seventh Embodiment> In the first embodiment described above, a switch 10 was connected between the clamp circuit 13 that clamps the input signal SIN and the input of the PMOS transistor 12. In this seventh embodiment, the clamp circuit 13, whose clamping operation is restricted based on the opening and closing of the switch 10, is applied to the imaging device.

[0066] Figure 7 is a block diagram showing an example configuration of an imaging device according to the seventh embodiment.

[0067] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, and operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into a vehicle or drone.

[0068] The optical system 101 directs light from the subject into the solid-state imager 102, forming an image of the subject on the light-receiving surface of the solid-state imager 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0069] The solid-state imaging device 102 converts light from the subject into an electrical signal for each pixel, and outputs that electrical signal digitized. The solid-state imaging device 102 may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a CCD (Charge Coupled Device), or an event-based vision sensor.

[0070] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging timing of the solid-state imaging device 102.

[0071] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and grayscale conversion processing. The image processing unit 104 may also include a processor that performs processing based on software.

[0072] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0073] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display or an organic EL (Electro-Luminescence) display.

[0074] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0075] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may be omitted, or conversely, it may have additional functions that are not disclosed.

[0076] Figure 8 is a block diagram showing an example configuration of a solid-state imaging device according to the seventh embodiment.

[0077] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116.

[0078] The pixel array section 111 comprises a plurality of pixels PIX. The pixels PIX are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel PIX can form a source follower with the column readout circuit 113 when reading a signal. Each pixel PIX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PIX row by row when reading a signal from each pixel PIX. The vertical signal line VSL transmits the signals read from the pixel PIX to the column signal processing unit 114 for each column. The pixels PIX may form a Bayer array or a quad Bayer array. The light received by each pixel PIX may be visible light, near-infrared light (NIR), short-wavelength infrared light (SWIR), ultraviolet light, or X-rays, etc.

[0079] The vertical scanning circuit 112 scans the pixels to be read out in the column direction. The vertical scanning circuit 112 may include a vertical register. Here, the vertical scanning circuit 112 can drive each pixel PIX row by row via the horizontal drive line HSL when reading signals from each pixel PIX.

[0080] The column readout circuit 113 can configure a source follower with each pixel PIX when reading a signal from each pixel PIX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL based on the charge held in the pixel PIX.

[0081] The column signal processing unit 114 processes the signals transmitted from each pixel PIX in the column direction. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted from each pixel PIX in the column direction. The column signal processing unit 114 can also perform analog-to-digital (AD) conversion processing based on the signals transmitted from each pixel PIX in the column direction and output an imaging signal Gout.

[0082] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PIX and the reference signal.

[0083] The horizontal scanning circuit 115 scans the pixels to be read out in the row direction. The horizontal scanning circuit 115 may also include a horizontal register.

[0084] The control circuit 116 controls the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column reading circuit 113, and the processing timing of the column signal processing unit 114. In this case, the control circuit 116 can coordinate the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

[0085] Figure 9 is a block diagram showing an example of a pixel circuit configuration provided in a solid-state imaging device according to the seventh embodiment.

[0086] In the figure, the pixel PIX comprises a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.

[0087] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to the power supply VDD via the reset transistor 123. The power supply VDD is connected to the vertical signal line VSL via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0088] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, the reset signal RST, and the selection signal SEL can be transmitted to each pixel PIX via the horizontal drive line HSL shown in Figure 2.

[0089] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD. Then, when the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is then applied to the vertical signal line VSL via the selection transistor 125 and transmitted through the vertical signal line VSL. Furthermore, when the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0090] Figure 10 shows an example of the configuration of a signal readout circuit for one column according to the seventh embodiment.

[0091] In the figure, the signal readout circuit includes a current source 131 and a comparator 132 for each column.

[0092] The current source 131 can form a source follower with the pixel PIX via the vertical signal line VSL during signal readout. The current source 131 is connected to the vertical signal line VSL. The current source 131 may also be a MOS transistor.

[0093] Comparator 132 can compare the pixel signal input via the vertical signal line VSL with the reference signal DAC. The vertical signal line VSL is connected to the inverting input of comparator 132. The reference signal DAC is input to the non-inverting input of comparator 132. The reference signal DAC can include, for example, a ramp signal. An auto-zero signal AZ is also input to comparator 132. The auto-zero signal AZ activates auto-zero operation during the auto-zero period. Auto-zero operation allows control of the charge accumulated in the capacitance of comparator 132 so that the non-inverting and inverting inputs are balanced.

[0094] Figure 11 shows an example of a comparator configuration to which a clamping circuit is applied, in which the clamping operation is restricted based on the opening and closing of a switch according to the seventh embodiment.

[0095] In the figure, the comparator 132 includes a differential amplifier 501 and a downstream amplifier 502. The downstream amplifier 502 is connected downstream of the differential amplifier 501.

[0096] The differential amplifier 501 balances the comparator inputs DV1 and DV2 based on auto-zero operation and then outputs a voltage corresponding to the difference between the comparator inputs DV1 and DV2. At this time, the differential amplifier 501 generates a voltage corresponding to the difference between the comparator inputs DV1 and DV2 as the input signal SIN of the subsequent amplifier 502. The differential amplifier 501 includes PMOS transistors 511, 521, 551, 561, 571, 581 and NMOS transistors 531, 541, 591.

[0097] PMOS transistor 511 and NMOS transistor 531 are connected in series with each other. PMOS transistor 521 and NMOS transistor 541 are also connected in series with each other. The sources of each PMOS transistor 511 and 521 are connected to the power supply potential VDD, and the gates of each PMOS transistor 511 and 521 are connected to the drain of PMOS transistor 521. In this configuration, PMOS transistors 511 and 521 can form a current mirror.

[0098] PMOS transistors 551 and 561 are connected in series between the gate and drain of NMOS transistor 531, and PMOS transistors 571 and 581 are connected in series between the gate and drain of NMOS transistor 541. The sources of each NMOS transistor 531 and 541 are grounded via NMOS transistor 591.

[0099] The pixel signal SPX is applied to the gate of NMOS transistor 531 via capacitor C1. The reference signal DAC is applied to the gate of NMOS transistor 541 via capacitor C2. The auto-zero signal AZP is applied to the gates of each PMOS transistor 551 and 571. The fixed voltage FX1 is applied to the gates of each PMOS transistor 561 and 581. In this state, each PMOS transistor 561 and 581 can be kept on. The bias voltage BIAS is applied to the gate of NMOS transistor 591. NMOS transistor 591 can operate as a constant current source based on the bias voltage BIAS.

[0100] The subsequent amplifier 502 amplifies the output of the differential amplifier 501. The subsequent amplifier 502 includes PMOS transistors 11, 512, NMOS transistors 23, 522, 532, 542 and a detection circuit 14. The detection circuit 14 may be the inverter 24 of the second embodiment described above, or the NAND circuit 34 of the third embodiment described above.

[0101] PMOS transistor 512 and NMOS transistor 522 are connected in series with each other. The source of PMOS transistor 512 is connected to the power supply potential VDD, and the gate of PMOS transistor 512 is connected to the drain of PMOS transistor 511. NMOS transistors 532 and 542 are connected in series between the gate and drain of NMOS transistor 522. The source of NMOS transistor 522 is grounded. Capacitor C3 is connected to the gate of NMOS transistor 522.

[0102] An auto-zero signal AZN is applied to the gate of NMOS transistor 532. A fixed voltage FX2 is applied to the gate of NMOS transistor 542. In this state, each NMOS transistor 542 can be kept on at all times. The auto-zero signal AZN is the inverted auto-zero signal AZP.

[0103] During the auto-zero period, PMOS transistors 551 and 571 turn on based on the auto-zero signal AZP, and NMOS transistor 532 also turns on. At this time, current flows through PMOS transistors 551 and 571 based on the current mirror operation of PMOS transistors 511 and 521. Charge is then accumulated in capacitors C1 and C2 so that the non-inverting and inverting inputs of comparator 132 are balanced. Also, based on the auto-zero signal AZN, NMOS transistor 532 turns on, and charge is accumulated in capacitor C3.

[0104] An input signal SIN is applied to the gate of the PMOS transistor 512. At this time, the PMOS transistor 512 can amplify the input signal SIN and output the output signal SOUT.

[0105] The NMOS transistor 23 clamps the input signal SIN. The NMOS transistor 23 is connected to the gate of the PMOS transistor 512 via the PMOS transistor 11. In this case, when the voltage of the input signal SIN drops, the NMOS transistor 23 can fix the gate potential of the PMOS transistor 512 to a predetermined potential so that the voltage does not drop too low. This prevents the operating point of the differential amplifier 501 from being crushed and improves the operational stability of the differential amplifier 501.

[0106] The PMOS transistor 11 is connected between the NMOS transistor 23 and the gate of the PMOS transistor 512. When the PMOS transistor 11 is turned off, it is possible to prevent GIDL and off-leak from the NMOS transistor 23 from propagating to the input signal SIN.

[0107] The detection circuit 14 sets the gate voltage of the PMOS transistor 11 to a high level and turns off the PMOS transistor 11 when the input signal SIN exceeds a predetermined voltage. This prevents GIDL and off-leak generated by the NMOS transistor 23 from propagating to the input voltage SIN.

[0108] On the other hand, the detection circuit 14 sets the gate voltage of the PMOS transistor 11 to a low level and turns on the PMOS transistor 11 when the input signal SIN is below a predetermined voltage. This allows the gate of the NMOS transistor 23 and the gate of the PMOS transistor 512 to be connected via the PMOS transistor 11, and the gate potential of the PMOS transistor 512 can be fixed at a predetermined potential to prevent the voltage of the input signal SIN from dropping too low.

[0109] Thus, in the seventh embodiment described above, an NMOS transistor 23 whose clamping operation is limited based on the on / off state of the PMOS transistor 11 is applied to the subsequent amplifier 502. This prevents GIDL from the NMOS transistor 23 from propagating to the input signal SIN of the subsequent amplifier 502 based on the on / off state of the PMOS transistor 11.

[0110] <8. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0111] Figure 12 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0112] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 12, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0113] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0114] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0115] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0116] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0117] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0118] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0119] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0120] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0121] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 12, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0122] Figure 13 shows an example of the installation position of the imaging unit 12031.

[0123] In Figure 13, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0124] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0125] Figure 13 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0126] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0127] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0128] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0129] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0130] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, each electronic circuit of the above embodiment can be applied to the imaging unit 12031. By applying the technology of this disclosure to the vehicle control system 12000, the signal quality of the imaging unit 12031 can be improved.

[0131] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0132] Furthermore, this technology can also take the following configurations: (1) An electronic circuit comprising a transistor for amplifying an input signal, a clamp circuit for clamping the input signal, and a switch connected between the clamp circuit and the input of the transistor. (2) The electronic circuit according to (1), further comprising a detection circuit for opening and closing the switch based on the detection result of the output of the transistor. (3) The electronic circuit according to (2), wherein the detection circuit is an inverter. (4) The electronic circuit according to (3), further comprising a current source for driving the inverter. (5) The electronic circuit according to (2), wherein the detection circuit is a NAND circuit. (6) The electronic circuit according to (5), further comprising a current source for driving the NAND circuit. (7) The electronic circuit according to any one of (1) to (6), wherein the transistor and the switch are PMOS transistors. (8) The electronic circuit according to any one of (1) to (6), wherein the transistor and the switch are NMOS transistors. (9) An electronic circuit according to any one of (1) to (7) above, wherein the switch is turned off when the input signal exceeds a predetermined voltage, and the switch is turned on when the input signal is less than or equal to the predetermined voltage. (10) A comparator comprising a differential amplifier to which an input signal and a reference signal are input, a downstream amplifier connected to the downstream of the differential amplifier, a clamp circuit for clamping the input of the downstream amplifier, and a switch connected between the clamp circuit and the input of the downstream amplifier. (11) An imaging device comprising a pixel array section in which pixels are arranged in a matrix in the row direction and column direction, and a comparator for comparing a pixel signal read from the pixels with a reference signal, wherein the comparator comprises a differential amplifier to which the pixel signal and the reference signal are input, a downstream amplifier connected to the downstream of the differential amplifier, a clamp circuit for clamping the input of the downstream amplifier, and a switch connected between the clamp circuit and the input of the downstream amplifier.

[0133] 10 Switch 11, 12 PMOS transistor 13 Clamp circuit 14 Detection circuit

Claims

1. An electronic circuit comprising a transistor for amplifying an input signal, a clamping circuit for clamping the input signal, and a switch connected between the clamping circuit and the input of the transistor.

2. The electronic circuit according to claim 1, further comprising a detection circuit that opens and closes the switch based on the detection result of the output of the transistor.

3. The electronic circuit according to claim 2, wherein the detection circuit is an inverter.

4. The electronic circuit according to claim 3, comprising a current source for driving the inverter.

5. The electronic circuit according to claim 2, wherein the detection circuit is a NAND circuit.

6. The electronic circuit according to claim 5, further comprising a current source for driving the NAND circuit.

7. The electronic circuit according to claim 1, wherein the transistor and the switch are PMOS transistors.

8. The electronic circuit according to claim 1, wherein the transistor and the switch are NMOS transistors.

9. The electronic circuit according to claim 1, wherein the switch is turned off when the input signal exceeds a predetermined voltage, and the switch is turned on when the input signal is less than or equal to the predetermined voltage.

10. A comparator comprising: a differential amplifier to which an input signal and a reference signal are input; a subsequent amplifier connected to the differential amplifier; a clamping circuit for clamping the input of the subsequent amplifier; and a switch connected between the clamping circuit and the input of the subsequent amplifier.

11. An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in the row direction and column direction; and a comparator for comparing pixel signals read from the pixels with a reference signal, wherein the comparator comprises: a differential amplifier to which the pixel signals and the reference signal are input; a downstream amplifier connected to the downstream stage of the differential amplifier; a clamping circuit for clamping the input of the downstream amplifier; and a switch connected between the clamping circuit and the input of the downstream amplifier.

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