Semiconductor device

Abstract

A semiconductor device according to one embodiment of the present disclosure is provided with: a substrate; a nitride semiconductor layer that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer in that order from a first surface side of the substrate; and a gate electrode, a source electrode, and a drain electrode that are in contact with the nitride semiconductor layer. The third semiconductor layer includes a semi-insulating dopant that has an acceptor level deeper than that of magnesium. In the nitride semiconductor layer, the source-gate sheet resistance Rsg, the below-gate sheet resistance Rg at a gate voltage of 0 V, and the gate-drain sheet resistance Rgd satisfy formula (1) or formula (2).　Formula (1): Rsg < Rg; formula (2): Rsg < Rgd.

Description

Semiconductor equipment

[0001] This disclosure relates to semiconductor devices.

[0002] In recent years, research and development of HEMTs (High Electron Mobility Transistors) using nitride semiconductors has been actively pursued (see, for example, Patent Document 1).

[0003] Japanese Patent Publication No. 2006-339561

[0004] Incidentally, HEMTs using nitride semiconductors require good high-frequency characteristics and reliability. It is desirable to provide semiconductor devices capable of achieving good high-frequency characteristics and reliability.

[0005] A semiconductor device relating to the first aspect of this disclosure comprises a substrate, a nitride semiconductor layer containing a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer in that order from the first surface side of the substrate, and a gate electrode, a source electrode, and a drain electrode in contact with the nitride semiconductor layer. The second semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer. The third semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer and less than or equal to the band gap of the second semiconductor layer, and includes a semi-insulating dopant having an acceptor level deeper than Mg. In the nitride semiconductor layer, the source-gate sheet resistance Rsg, the gate-under sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy the following equation (1) or equation (2): Rsg < Rg ... (1) Rsg < Rgd ... (2)

[0006] In the semiconductor device relating to the first aspect of this disclosure, the third semiconductor layer includes a semi-insulating dopant having an acceptor level deeper than Mg. In the nitride semiconductor layer, the source-gate sheet resistance Rsg, the under-gate sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy equation (1) or equation (2) above. This makes it possible to shorten the distance between the gate electrode and the 2DEG (Two-Dimensional Electron Gas) region generated in the nitride semiconductor layer compared to the case where the third semiconductor layer includes Mg as a dopant. Furthermore, it is possible to suppress the number of defect levels compared to the case where the gate electrode is in contact with the nitride semiconductor layer via an insulating film.

[0007] A semiconductor device relating to a second aspect of this disclosure comprises a substrate, a nitride semiconductor layer comprising a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer in that order from the first surface side of the substrate, and a gate electrode, a source electrode, and a drain electrode in contact with the nitride semiconductor layer. The second semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer. The third semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer and less than or equal to the band gap of the second semiconductor layer, and contains a dopant having an acceptor level deeper than Mg. The total thickness of the second and third semiconductor layers satisfies the following equation (3) or equation (4) in terms of the source-gate thickness Tsg, gate-under thickness Tg, and gate-drain thickness Tgd: Tsg < Tg ... (3) Tsg < Tgd ... (4)

[0008] In the semiconductor device relating to the second aspect of this disclosure, the third semiconductor layer includes a semi-insulating dopant having an acceptor level deeper than Mg. In the nitride semiconductor layer, the source-gate sheet resistance Rsg, the gate-under-gate sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy equation (3) or equation (4) above. This makes it possible to shorten the distance between the gate electrode and the 2DEG region generated in the nitride semiconductor layer compared to the case where the third semiconductor layer includes Mg as a dopant. Furthermore, it is possible to suppress the number of defect levels compared to the case where the gate electrode is in contact with the nitride semiconductor layer via an insulating film.

[0009] Figure 1 is a diagram showing an example of the cross-sectional configuration of a semiconductor device according to the first embodiment of this disclosure. Figure 2 is a diagram showing an example of the band gaps of the channel layer, barrier layer, and cap layer of Figure 1. Figure 3 is a diagram showing an example of the relationship between barrier film thickness and cutoff frequency. Figure 4 is a diagram showing an example of the relationship between C concentration and sheet resistance. Figure 5 is a diagram showing an example of the relationship between C concentration and 2DEG sheet density. Figure 6 is a diagram showing an example of the relationship between C concentration and mobility. Figure 8 is a diagram showing an example of the relationship between C sheet concentration and the decrease in 2DEG sheet density. Figure 8 is a diagram showing an example of the relationship between C concentration, mean square roughness obtained from an AFM image in the range of 10 μm × 10 μm, and 2DEG sheet density. Figure 9A is a diagram illustrating an example of the manufacturing procedure of the semiconductor device of Figure 1. Figure 9B is a diagram illustrating an example of the manufacturing procedure following Figure 9A. Figure 10 is a diagram showing a modified example of the cross-sectional configuration of the semiconductor device of Figure 1. Figure 11A is a diagram illustrating an example of the manufacturing procedure of the semiconductor device of Figure 11. Figure 11B is a diagram illustrating an example of the manufacturing procedure following Figure 11A. Figure 12 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 1. Figure 13A is a diagram illustrating an example of the manufacturing procedure for the semiconductor device shown in Figure 12. Figure 13B is a diagram illustrating an example of the manufacturing procedure following Figure 13A. Figure 13C is a diagram illustrating an example of the manufacturing procedure following Figure 13B. Figure 13D is a diagram illustrating an example of the manufacturing procedure following Figure 13C. Figure 13E is a diagram illustrating an example of the manufacturing procedure following Figure 13D. Figure 13F is a diagram illustrating an example of the manufacturing procedure following Figure 13E. Figure 13G is a diagram illustrating an example of the manufacturing procedure following Figure 13F. Figure 14 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 1. Figure 15 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 1. Figure 16 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 1. Figure 17 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 1. Figure 18 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 1. Figure 19 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 1. Figure 20 shows a modified example of the cross-sectional configuration of the semiconductor device shown in Figure 1. Figure 21 shows an example of the cross-sectional configuration of a semiconductor device according to a second embodiment of the present disclosure. Figure 22 shows an example of the relationship between C concentration and sheet resistance.Figure 23 is a diagram showing an example of the relationship between C concentration and mobility. Figure 24 is a diagram showing an example of the relationship between C concentration and 2DEG sheet density. Figure 25A is a diagram illustrating an example of the manufacturing procedure for the semiconductor device shown in Figure 21. Figure 25B is a diagram illustrating an example of the manufacturing procedure following Figure 25A. Figure 27 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 21. Figure 27 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 21. Figure 28 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 21. Figure 29 is a diagram showing one modified cross-sectional configuration of the semiconductor device shown in Figure 21. Figure 30 is a diagram showing an example of the cross-sectional configuration of a semiconductor device according to a third embodiment of this disclosure. Figure 31A is a diagram illustrating an example of the manufacturing procedure for the semiconductor device shown in Figure 30. Figure 31B is a diagram illustrating an example of the manufacturing procedure following Figure 31A. Figure 32 is a perspective view showing an example of the configuration of a wireless communication device. Figure 33 is a block diagram showing an example of the configuration of a wireless communication device.

[0010] <Background> In recent years, research and development of HEMTs (High Electron Mobility Transistors) using nitride semiconductors has been actively pursued. Nitride semiconductors have a larger band gap compared to Si and GaAs, and possess polarization characteristic of hexagonal crystals. Therefore, HEMTs using nitride semiconductors are expected to be transistors capable of low resistance, high voltage resistance, and high-speed operation. Specifically, HEMTs are expected to be applied to power devices or radio frequency (RF) devices.

[0011] Incidentally, normally-on transistors are typically used in HEMTs (Heat-Electron Microconductors) that utilize nitride semiconductors. However, normally-off transistors are desirable for safety reasons and to simplify circuit design. Currently, achieving normally-off operation is generally achieved by providing a pGaN capping layer between the gate electrode and the barrier layer, or by incorporating a recessed MIS (Metal-Insulator-Semiconductor) structure.

[0012] When a pGaN cap layer is provided between the gate electrode and the barrier layer, a pn junction is formed between the pGaN cap layer and the channel layer. Therefore, due to the built-in potential of these layers, the two-dimensional electron gas (2DEG) directly under the gate electrode decreases, and the threshold voltage of the HEMT becomes positive. When the pGaN cap layer is provided only directly under the gate electrode, 2DEG is formed between the source and the gate and between the gate and the drain. Therefore, the 2DEG contributes to the low on-resistance of the HEMT. At this time, the pGaN cap layer is doped with Mg as an acceptor impurity.

[0013] In order to completely compensate for the 2DEG directly under the gate electrode, the sheet hole density of the pGaN cap layer must be about the same as the sheet density of the 2DEG. For example, since the sheet density of the 2DEG is generally about 10 １３ cm －２ , the hole density of the pGaN cap layer is set to 10 １８ cm －３ , and by setting the thickness of the pGaN cap layer to 100 nm, the 2DEG can be compensated. However, for Mg doped in pGaN, the activation rate is as low as about 10%. Also, when Mg is doped at a high concentration (for example, 5×10 １９ cm －３ or more), crystal defects occur, and in this case, the activation rate further decreases. Therefore, it is difficult to obtain a hole density higher than 10 １８ cm －３ with Mg-doped pGaN. Thus, when the pGaN cap layer is formed thick, the distance between the gate electrode and the 2DEG becomes far, and the high-frequency characteristics of the HEMT are limited.

[0014] When a recessed MIS structure is provided between the gate electrode and the barrier layer, an insulating film is provided between the gate electrode and the barrier layer. In nitride semiconductors, many defect levels exist at the interface between the insulating film and the semiconductor. Therefore, the reliability of the HEMT is likely to deteriorate.

[0015] Next, the relationship between the high-frequency characteristics and the film thickness of the GaN barrier layer (barrier film thickness t ｂａｒ ) will be described. Here, the barrier film thickness tｂａｒ This refers to a broad definition of film thickness, including not only the barrier layer but also the capping layer, and the distance between the gate metal and the 2DEG. HEMT cutoff frequency f Ｔ Ideally, it satisfies the following equation (a): f Ｔ = v ｓａｔ / 2πL ｇ …(a)

[0016] Here, v ｓａｔ L is the saturation electron velocity of GaN, ｇ L is the gate length. ｇ As we decrease the value, the short channel effect occurs, resulting in f Ｔ This value is lower than the value given by equation (a). Also, when short-channel effects occur, the threshold voltage V ｔｈ L ｇ The addiction becomes stronger, and that is, L ｇ The threshold voltage V varies depending on the variation. ｔｈ This also means that variations will occur. Therefore, short-channel effects are undesirable. To suppress short-channel effects, L ｇ At the same time, barrier film thickness t ｂａｒ It needs to be made thinner. ｇ or, different from each other ｂａｒ Based on the measurement results of multiple HEMT samples, the following conclusions can be drawn.

[0017] According to Non-Patent Document 1, a standard aspect ratio (L) for reducing short-channel effects ｇ / t ｂａｒ The minimum value of f is 15. Ｔ and L ｇ The product of these is the aspect ratio (L ｇ / t ｂａｒ ) is given by the following empirical formula (b). f Ｔ ×L ｇ = (L ｇ / t ｂａｒ ) / (L ｇ / t ｂａｒ +5.1)×19.8 (GHz・μm)…(b)

[0018] Non-Patent Document 1 Short-Channel Effect Limitations on High-Frequency Operation of AlGaN / GaN HEMTs for T-Gate Devices GH Jessen, RC Fitch, JK Gillespie, G. Via, A. Crespo, D. Langley, et al. IEEE Transactions on Electron Devices 2007 Vol. 54 Issue 10 Pages 2589-2597 DOI: 10.1109 / ted.2007.904476

[0019] Here, f Ｔ The unit is GHz, and t ｂａｒ and L ｇ The unit is μm. L is used to suppress short channel effects. ｇ / t ｂａｒ If we design while maintaining = 15, empirical formula (b) is transformed into the following formula (c): f Ｔ = (1 / L) ｇ )×(15 / (15+5.1))×19.8(GHz・μm) =14.8 / L ｇ (GHz・μm)=14.8 / 15t ｂａｒ (GHz・μm)…(c)

[0020] This ｂａｒ A graph plotted against this is shown in Figure 3 below. In a conventional normally-off type HEMT equipped with a Mg-doped pGaN cap layer, the thickness of the pGaN cap layer is about 50-100 nm, and the thickness of the AlGaN barrier layer is about 20 nm, so the cutoff frequency f Ｔ It appears that this is limited to around 10 GHz.

[0021] Thus, conventionally, it is difficult to obtain good high-frequency characteristics and reliability. Therefore, the applicant conceived of a semiconductor device capable of obtaining good high-frequency characteristics and reliability, as well as electrical circuits and electronic devices equipped with such a semiconductor device.

[0022] Preferred embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0023] Furthermore, in this specification and drawings, multiple components having substantially identical or similar functional configurations may be distinguished by adding different numbers after the same reference numeral. However, if there is no need to particularly distinguish each of multiple components having substantially identical or similar functional configurations, only the same reference numeral will be used. Also, similar components of different embodiments may be distinguished by adding different letters after the same reference numeral. However, if there is no need to particularly distinguish each of similar components, only the same reference numeral will be used.

[0024] Furthermore, the drawings referenced in the following description are for illustrating and facilitating understanding of one embodiment of this disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from those of the actual product. In addition, the semiconductor device shown in the drawings may be modified in design as appropriate, taking into consideration the following description and known technology. Also, in the description using a cross-sectional view of the semiconductor device, the vertical direction of the stacked structure of the semiconductor device corresponds to the direction in which the substrate and electrodes in the semiconductor device face each other, and may differ from the vertical direction according to the actual gravitational acceleration.

[0025] Furthermore, in the following explanation, expressions relating to size and shape do not refer only to mathematically defined numerical values ​​or geometrically defined shapes, but also include differences that are industrially acceptable in the manufacturing process of semiconductor devices, as well as shapes that are similar to those defined.

[0026] The explanation will proceed in the following order: 1. First Embodiment (Semiconductor Device) 2. Modified Example of the First Embodiment (Semiconductor Device) 3. Second Embodiment (Semiconductor Device) 4. Modified Example of the Second Embodiment (Semiconductor Device) 5. Third Embodiment (Semiconductor Device) 6. Application Example (Wireless Communication Device)

[0027] <1. First Embodiment> (Configuration) A semiconductor device 1 according to the first embodiment of the present disclosure will be described. Figure 1 shows an example of the cross-sectional configuration of the semiconductor device 1. The semiconductor device 1 is a HEMT using a nitride semiconductor. The semiconductor device 1 comprises a substrate 10 and a nitride semiconductor layer formed on the substrate 10 as a crystal growth substrate. For crystal growth of the nitride semiconductor layer, for example, the MOCVD (metal organic chemical vapor deposition) method is used. The nitride semiconductor layer is composed of, for example, a buffer layer 20, a channel layer 30, a barrier layer 40 and a cap layer 50 in this order from the substrate 10 side.

[0028] The substrate 10 corresponds to a specific example of the "substrate" in one embodiment of the present disclosure. The channel layer 30 corresponds to a specific example of the "first semiconductor layer" in one embodiment of the present disclosure. The barrier layer 40 corresponds to a specific example of the "second semiconductor layer" in one embodiment of the present disclosure. The cap layer 50 corresponds to a specific example of the "third semiconductor layer" in one embodiment of the present disclosure.

[0029] The semiconductor device 1 further comprises a gate electrode 60 provided on the cap layer 50, and a source electrode 70 and a drain electrode 80 provided on the barrier layer 40 at locations facing each other with respect to the gate electrode 60. The gate electrode 60, source electrode 70, and drain electrode 80 are in contact with the surface of the nitride semiconductor layer described above. The gate electrode 60 is in contact with the surface of the cap layer 50. The source electrode 70 and drain electrode 80 are in contact with the surface of the barrier layer 40.

[0030] The semiconductor device 1 is a high electron mobility transistor (HEMT) with a two-dimensional electron gas (2DEG) region 31 as the channel. The semiconductor device 1 is a HEMT using a nitride semiconductor, and for example, has a Ga polar crystal structure. The 2DEG region 31 arises from the difference between the polarization magnitude of the channel layer 30 and the polarization magnitude of the barrier layer 40. The 2DEG region 31 arises at the heterointerface between the channel layer 30 and the barrier layer 40. The 2DEG region 31 arises in the access region (the region between the source electrode 70 and the gate electrode 60, and the region between the gate electrode 60 and the drain electrode 80).

[0031] The substrate 10 is made of, for example, a semi-insulating single-crystal gallium nitride (GaN), which is a group III-V compound semiconductor. By mitigating the lattice constant mismatch with the buffer layer 20, a substrate with a different lattice constant from the channel layer 30 can be used for the substrate 10. Examples of substrates with a different lattice constant from the channel layer 30 include silicon (Si) substrates, silicon carbide (SiC) substrates, and sapphire substrates. As a Si substrate, for example, a single-crystal Si(111) substrate with the (111) plane as the main plane is preferred.

[0032] The buffer layer 20 is composed of an epitaxially grown compound semiconductor. The buffer layer 20 is Al ｘ１ Ga （１－ｘ１－ｙ１） In ｙ１ It is composed of a nitride semiconductor consisting of N (0 ≤ x1 ≤ 1, 0 ≤ y1 < 1, 0 < x1 + y1 ≤ 1). The buffer layer 20 contains, for example, carbon atoms (C) or iron atoms (Fe) as impurities. The buffer layer 20 is composed of, for example, a laminate. The buffer layer 20 is composed of, for example, a laminate containing a first buffer layer, a second buffer layer, and a third buffer layer in this order from the substrate 10 side. When the substrate 10 is made of a Si single crystal and the channel layer 30 is made of gallium nitride (GaN), the first buffer layer is made of, for example, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), or aluminum indium gallium nitride (AlInGaN), etc. The first buffer layer is, for example, 1E + 17 cm －３ The following impurity concentrations are present. The second buffer layer is composed of, for example, gallium nitride (GaN). The second buffer layer is composed of, for example, 1E+17cm －３ Larger size: 5E + 18cm －３ The following impurity concentrations are present. The third buffer layer is composed of, for example, gallium nitride (GaN). The third buffer layer is composed of, for example, 5E + 18 cm². －３ Larger size: 1E + 20cm －３ It has the following impurity concentrations.

[0033] The channel layer 30 is located further from the surface S1 of the substrate 10 than the buffer layer 20. The channel layer 30 constitutes part of the current path between the source electrode 70 and the drain electrode 80. The channel layer 30 is a region where carriers (two-dimensional electron gas) accumulate due to the difference in polarization charge between it and the barrier layer 40. The channel layer 30 is made of an epitaxially grown nitride semiconductor, Al ｘ２ Ga （１－ｘ２－ｙ２） In ｙ２ The channel layer is composed of N (0 ≤ x² < 1, 0 ≤ y² < 1, x² + y² ≤ 1). The channel layer 30 is composed of, for example, gallium nitride (GaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN). The channel layer 30 may also be composed of undoped gallium nitride (GaN) without added impurities. This suppresses impurity scattering of carriers in the channel layer 30, enabling carrier transport at high mobility.

[0034] The channel layer 30 may be composed of at least one of indium gallium nitride (InGaN), indium nitride (InN), aluminum gallium nitride (AlGaN), and aluminum indium gallium nitride (AlInGaN). The channel layer 30 may also be a laminated structure consisting of multiple layers with different compositions. In these cases, the channel layer 30 can suppress impurity scattering of carriers. Therefore, the channel layer 30 can further increase the mobility of carriers.

[0035] The barrier layer 40 is provided at a position further from the surface S1 of the substrate 10 than the channel layer 30. The barrier layer 40 is made of a nitride semiconductor having a band gap greater than or equal to the band gap of the channel layer 30, as shown in Figure 2, for example. The barrier layer 40 can accumulate carriers in the region of the channel layer 30 near the barrier layer 40 by spontaneous polarization or piezoelectric polarization. As a result, the semiconductor device 1 can generate a 2DEG region 31 with high mobility and high carrier concentration in the region near the interface between the channel layer 30 and the barrier layer 40.

[0036] The barrier layer 40 is made of a nitride semiconductor in which a two-dimensional electron gas is accumulated in the region near the interface between the channel layer 30 and the barrier layer 40 due to the difference in polarization charge between the channel layer 30 and the barrier layer 40. The barrier layer 40 is made of an epitaxially grown nitride semiconductor, for example, one containing Al. The barrier layer 40 may also be made of an AlInN semiconductor further containing In. The barrier layer 40 is Al ｘ３ Ga （１－ｘ３－ｙ３） In ｙ３ N is composed of (0.6 ≤ x³ ≤ 1, 0 ≤ y³ ≤ 1, x³ + y³ ≤ 1). The barrier layer 40 is composed of, for example, indium aluminum nitride (AlInN) containing 60% or more Al, gallium aluminum nitride (AlGaN) containing 60% or more Al, or indium aluminum nitride (AlInGaN) containing 60% or more Al.

[0037] The barrier layer 40 may also be made to contain n-type impurities such as silicon (Si) or germanium (Ge). By adding n-type impurities to the barrier layer 40, the concentration of the two-dimensional electron gas can be increased.

[0038] AlInN is lattice-matched with GaN at a composition of 82% Al (18% In). Therefore, when using an AlInN barrier layer, an Al composition ratio that is lattice-matched with GaN is preferred. As a barrier layer, an AlGaInN quaternary mixed crystal system containing even more GaN may also be used to enhance crystallinity. Phase separation is likely to occur in mixed crystals containing InN, and if the film thickness is thick, crystal defects will occur. For this reason, the thickness of the barrier layer is preferably 30 nm or less, more preferably 20 nm or less, and most preferably 10 nm or less.

[0039] The cap layer 50 is provided at a position further from the surface S1 of the substrate 10 than the barrier layer 40. The cap layer 50 is provided between the gate electrode 60 and the barrier layer 40. The cap layer 50 is not provided in the region between the source electrode 70 and the gate electrode 60 (access region), nor in the region between the gate electrode 60 and the drain electrode 80 (access region). The cap layer 50 is made of a nitride semiconductor having a band gap greater than or equal to the band gap of the channel layer 30 and less than or equal to the band gap of the barrier layer 40, as shown in Figure 2, for example. The cap layer 50 is a layer for suppressing oxidation of the barrier layer 40. The cap layer 50 is provided on top of the barrier layer 40. The cap layer 50 is made of, for example, epitaxially grown gallium nitride (GaN).

[0040] The gate electrode 60 is provided on the cap layer 50. The width of the gate electrode 60 that contacts the cap layer 50 is defined as the gate length. The gate electrode 60 has a laminated structure in which nickel (Ni) layers and gold (Au) layers are sequentially stacked from the cap layer 50 side. The gate electrode 60 may be Schottky or ohmic. The gate electrode 60 may be made of, for example, Mo, Ti, Al, TiN, W, WSiN, or Pd.

[0041] Both the source electrode 70 and the drain electrode 80 are made of conductive material. The source electrode 70 and the drain electrode 80 are each provided on the barrier layer 40. The source electrode 70 and the drain electrode 80 have a laminated structure in which, for example, a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer are sequentially stacked from the barrier layer 40 side. The source electrode 70 and the drain electrode 80 are heat-treated as needed.

[0042] Incidentally, in the nitride semiconductor layer described above, the source-gate sheet resistance Rsg, the under-gate sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy either equation (d) or equation (e) below: Rsg < Rg ... (d) Rsg < Rgd ... (e)

[0043] The source-gate sheet resistance Rsg can be calculated, for example, from the resistance when current flows between the source electrode 70 and the gate electrode 60, and the distance between the source electrode 70 and the gate electrode 60. The gate-drain sheet resistance Rgd can be calculated, for example, from the resistance when current flows between the gate electrode 60 and the drain electrode 80, and the distance between the gate electrode 60 and the drain electrode 80. The gate-under-gate sheet resistance Rg when the gate voltage is 0V can be calculated from the resistance when current flows between the source electrode 70 and the drain electrode 80 while 0V is applied to the gate electrode 60, the gate length Lg, the source-gate sheet resistance Rsg, and the gate-drain sheet resistance Rgd. However, it is also necessary to consider the contact resistance between the electrode and the semiconductor in these calculations. When there are multiple structures with different inter-electrode distances and gate lengths, the TLM (Transmission Line Model) method can be used to evaluate both the sheet resistance and the contact resistance.

[0044] Furthermore, the total thickness of the barrier layer 40 and the cap layer 50 (barrier film thickness t) ｂａｒ The following equation (f) or (g) is satisfied in the source-gate film thickness Tsg, gate-under film thickness Tg, and gate-drain film thickness Tgd. In this embodiment, the source-gate film thickness Tsg and gate-drain film thickness Tgd are the thicknesses of the barrier layer 40. The gate-under film thickness Tg is the total thickness of the barrier layer 40 and the cap layer 50. Semiconductor device. Tsg < Tg ... (f) Tsg < Tgd ... (g)

[0045] Next, the material, dopant, and film thickness of the cap layer 50 will be described.

[0046] The cap layer 50 contains a semi-insulating dopant having a deeper acceptor level than Mg. Examples of semi-insulating dopants include C, Fe, Mn, or other transition metals. Compared to Mg, which is prone to crystal defects, semi-insulating dopants can be doped to high concentrations. The applicant conducted experiments using GaN:C doped with C as the semi-insulating dopant as the cap layer 50, and found that a cap layer 50 with a thickness of only 1.7 nm could achieve 10 １３ cm－２ We found that 2 DEGs with the above sheet densities can be compensated for.

[0047] According to Non-Patent Document 1, in order to suppress the short channel effect, the barrier film thickness t ｂａｒ and gate length L ｇ Aspect ratio (L ｇ / t ｂａｒ ) should preferably be 15 or more. Non-patent document 1 states that t ｂａｒ and L ｇ An empirical formula (b) for the cutoff frequency f has also been proposed. Figure 3 shows the results using empirical formula (b) for L ｇ / t ｂａｒ = While maintaining 15 L ｇ When the total thickness of the barrier layer 40 and the cap layer 50 is reduced (barrier film thickness t) ｂａｒ ) and cutoff frequency f Ｔ This shows an example of the relationship. From Figure 3, barrier film thickness t ｂａｒ The thinner it becomes, the cutoff frequency f Ｔ It can be seen that the value will increase.

[0048] Generally, AlInN has a higher spontaneous polarization than AlGaN, so by using AlInN as a barrier layer, it is possible to induce high 2DEG with a thin film thickness. To improve heat resistance, quaternary mixed crystal AlGaInN, which contains Ga, may also be used as a barrier layer. To produce a sufficient 2DEG sheet density, a film thickness of 20 nm to 30 nm is required for AlGaN, while a film thickness of 5 to 10 nm or less is sufficient for AlInN.

[0049] By using a cap layer 50 doped with a semi-insulating dopant and a barrier layer 40 composed of AlGaN, AlInN, or AlGaInN, a cutoff frequency f above 10 GHz can be achieved, as shown in the area enclosed by the rectangle in Figure 3. Ｔ This can be obtained. Specifically, the barrier film thickness t when the barrier layer 40 is made of AlGaN or AlGaInN. ｂａｒ When the value is 35 nm, for example, the cutoff frequency f is 20 GHz to 50 GHz. Ｔis obtained. At this time, the film thickness of the barrier layer 40 is, for example, 30 nm, and the thickness of the cap layer 50 is, for example, 5 nm. When the barrier layer 40 is made of AlGaN or AlGaInN, the barrier film thickness t ｂａｒ is 25 nm, and a cutoff frequency f Ｔ is obtained. At this time, the film thickness of the barrier layer 40 is, for example, 20 nm, and the thickness of the cap layer 50 is, for example, 5 nm. When the barrier layer 40 is made of AlInN, the barrier film thickness t ｂａｒ is 15 nm, and a cutoff frequency f Ｔ is obtained. At this time, the film thickness of the barrier layer 40 is, for example, 10 nm, and the thickness of the cap layer 50 is, for example, 5 nm.

[0050] Incidentally, C incorporated in GaN is likely to substitute for N, and C (C Ｎ ) that has substituted for N has a deep donor level and a deep acceptor level, and it is predicted from first-principles calculations that the deep acceptor level is at a position 0.9 eV from the upper end of the valence band (E Ｖ ) (see Non-Patent Document 2). As shown in Non-Patent Document 2, in a semiconductor where the Fermi level (E Ｆ ) is higher than E Ｖ + 0.9 eV, C Ｎ is negatively charged, and accordingly, the number of free electrons as carriers decreases. GaN is known to become an n-type semiconductor even when not intentionally doped with impurities. However, in applications such as HEMT, unintentional electrical conduction in the buffer layer is not preferable. In such a case, a method of doping C to semi-insulate GaN is well known. As can be seen from the high activation energy of 0.9 eV, GaN:C does not exhibit p-type conductivity.

[0051] Non-Patent Document 2 "Effects of carbon on the electrical and optical properties of InN, GaN, and AlN", J. L. Lyons, A. Janotti and C. G. Van de Walle, Physical Review B 2014 Vol. 89 Pages 035204.

[0052] When C is included in the cap layer, the point defects in the cap layer have a deep acceptor level of E + 0.9 eV. If this level is lower than E, the cap layer becomes negatively charged and compensates for the 2DEG. From a typical band structure, the E + 0.9 eV of the cap layer is lower than E. That is, it can be said that even impurities with deep acceptor levels such as C can compensate for the 2DEG, not just shallow acceptors such as Mg. Different from Mg, C does not cause defects in the crystal even when doped at a high concentration, so it is expected to compensate for the 2DEG with a thinner cap film thickness.

[0053] The applicant of the present application conducted an experiment to confirm whether it is possible to compensate for the 2DEG by doping C into the cap layer 50. A buffer layer composed of AlN, AlGaN, and GaN, a GaN channel layer, an AlInGaN barrier layer, and a GaN:C cap layer were grown in order on a Si(111) substrate by the MOCVD method. The thickness of the barrier layer is 6.5 nm, and the thickness of the cap layer is 1.7 nm. The average composition ratio of the barrier layer is Al 68%, In 7%, and Ga 25%. A so-called AlInN-based barrier was used to increase the spontaneous polarization by increasing the Al composition and to relieve the lattice mismatch with GaN by In. A plurality of samples with different C concentrations in the GaN:C cap layer were fabricated, and the sheet resistance, mobility, and 2DEG sheet density Ns were evaluated by Hall effect measurement. For the Hall effect measurement, a non-contact measurement device was used, and the average value in the wafer plane excluding the edge portion was taken. When C is not intentionally doped, the C concentration in GaN is about 1×10 １６ cm －３ ​​​​​​​​​​Therefore, using carbon contained in organometallic gases, which are the raw materials for Ga, NH ３ The concentration of C doping was controlled by changing the molar ratio of organometallic gases.

[0054] Figures 4, 5, and 6 show the experimental results of the relationship between C concentration and sheet resistance Rs, 2DEG sheet density Ns, and mobility. Figure 7 shows the relationship between the sheet concentration of C in the GaN:C cap layer and the undoping (1 × 10⁻¹⁰) １６ cm －３ This shows the experimental results relating to the decrease in 2DEG sheet density Ns (ΔNs) from ) ). It can be seen that increasing the C concentration can efficiently reduce the 2DEG sheet density Ns. As the C sheet concentration in the GaN:C cap layer increases, the compensation rate (the ratio that one C atom compensates for 2DEG) decreases, but when the C sheet concentration in the GaN:C cap layer is 10 １４ cm －２ The compensation rate is high at 10% in the following cases. Even with high concentrations of C doping, no deterioration in mobility was observed, suggesting that the crystallinity was not deteriorated. The mobility was actually 3 × 10⁻⁶. ２０ cm －３ Although it has increased to this extent, this is thought to be because the phonon scattering probability has decreased due to the decrease in the 2DEG sheet density Ns. Thus, it has been shown that 2DEG can be compensated for with a GaN:C cap layer of a few nm in thickness, without degradation of mobility, instead of the GaN:Mg cap layer that was conventionally required to be 50-100 nm thick.

[0055] Next, we will discuss the preferred design values ​​regarding doping levels.

[0056] The upper limit of C concentration is 4.5 × 10 ２１ cm －３ It is approximately 3 × 10⁻⁶. As shown in Figures 4, 5, and 6, the C concentration per unit volume is 3 × 10⁻⁶. ２０ cm －３The 2DEG sheet density Ns is minimized at a certain concentration, and beyond that concentration, the 2DEG sheet density Ns begins to increase. Figure 8 shows the experimental results of the relationship between the C concentration, the surface roughness RMS evaluated by AFM (Atomic Force Microscopy), and the 2DEG sheet density Ns for these samples. It can be seen that the surface roughness increases simultaneously at the concentration where the 2DEG sheet density Ns begins to increase. Therefore, it is thought that the increase in 2DEG sheet density Ns is due to the introduction of unintended donor point defects due to surface roughness and deterioration of crystallinity, which contribute to the 2DEG sheet density Ns.

[0057] By the way, the atomic density of GaN is approximately 9 × 10⁻¹⁶. ２２ atom / cm ３ Therefore, if all C is replaced by N, a C composition ratio of 10% would result in a concentration of 4.5 × 10⁻⁶. ２１ cm －３ This corresponds to a concentration of 4.5 × 10⁻⁶. ２０ cm －３ This corresponds to C being an atom with a different number of valence electrons than both Ga and N. It is difficult to dope with impurities that have a different number of valence electrons than the host atom in the order of percentage. It seems that it may be possible to increase the concentration to some extent by optimizing the growth conditions. However, according to common technical knowledge, for example, a concentration of 4.5 × 10⁻¹⁶, which corresponds to a composition ratio of 10%, is difficult. ２１ cm －３ The above seems difficult. Therefore, the concentration of C is 4.5 × 10 ２１ cm －３ (Preferably a composition ratio of 10% or less, 4.5 × 10 ２０ cm －３ (A composition ratio of 1% or less is more preferable.)

[0058] The lower limit of C concentration is 1 × 10 １７ cm －３ It is approximately 10. As shown in Figures 4, 5, and 6, the concentration at which the 2DEG sheet density Ns begins to decrease is 10 １９ cm －３ This is because the cap film thickness is thin, and the C sheet density is on the same order as the 2DEG sheet density Ns. １９ cm －３ Therefore (1 x 10 １９cm －３ ×1.7nm=1.7×10 １２ cm －２ Therefore, 1 x 10 １９ cm －３ This is not the lower limit; even if the concentration is below this, if the film thickness is thick and the sheet C density is about the same as the 2DEG sheet density Ns, the 2DEG sheet density Ns reduction effect will occur. However, it is known that unintended impurities and point defects are introduced into nitride semiconductors during growth, and their concentration is generally 1 × 10⁻⁶ １６ cm －３ It is approximately 1 × 10⁻⁶. If the concentration of unintended impurities is higher than the concentration of C, the effect will not be achieved, so the concentration of C should be 1 × 10⁻⁶. １７ cm －３ The above is preferable.

[0059] The lower limit of the C sheet concentration is 1 × 10⁻⁶ １２ cm －２ This is the extent of the problem. The semiconductor device 1 is a normally-off type HEMT that completely depletes the area directly beneath the gate electrode 60. Alternatively, as will be described later, the semiconductor device 1 may be a normally-on type HEMT that reduces the gate-drain capacitance by partially depleting the area between the gate and drain. In this case, the 2DEG sheet density Ns in a typical HEMT is 1 × 10⁻⁶. １３ cm －３ Considering the extent of this, in order to significantly change the device characteristics, it is necessary to compensate for approximately 10% of the 2DEG sheet density Ns. Therefore, the sheet density of C is 1 × 10⁻⁶. １２ cm －２ It is desirable that the above conditions are met. For example, if the cap thickness is 1 nm, the C concentration is 1 × 10⁻¹⁶. １９ cm －３ That's all. If the film thickness is 10 nm, then 1 × 10 １８ cm －３ The above corresponds to the above. Note that there is no particular upper limit for the C sheet concentration. In Figure 7, 1 × 10 １４ cm －２ As shown above, ΔNs has decreased, which is because, as shown in Figure 8, the volume concentration is 3 × 10⁻⁶. ２０ cm －３ This is because the surface begins to become rough after exceeding a certain limit, and does not directly represent the limit in terms of sheet density.

[0060] The concentration of C contained in the cap layer 50 can be evaluated, for example, using a three-dimensional atom probe.

[0061] (Manufacturing Method) Next, the manufacturing method of the semiconductor device 1 will be described.

[0062] Figures 9A and 9B show an example of the manufacturing procedure for the semiconductor device 1. First, a nitride semiconductor layer is formed on a substrate 10, for example, using the MOCVD method, including a buffer layer 20, a channel layer 30, a barrier layer 40, and a cap layer 50 in that order from the substrate 10 side (Figure 9A). At this time, a 2DEG region 31 is formed at the heterointerface between the channel layer 30 and the barrier layer 40. Next, a mask 210 is formed on a predetermined location on the surface of the nitride semiconductor layer (Figure 9A). Subsequently, dry etching is performed using the mask 210 as a mask to selectively etch the parts of the cap layer 50 that are not covered by the mask 210 (Figure 9B). As a result, the 2DEG region 31 that had formed in the area facing the remaining cap layer 50 is compensated by the cap layer 50. After that, the mask 210 is removed, and a gate electrode 60, a source electrode 70, and a drain electrode 80 that are in contact with the surface of the nitride semiconductor layer are formed. In this way, the semiconductor device 1 is manufactured.

[0063] In this embodiment, GaN:C is used as the cap layer 50. Therefore, the annealing treatment specific to pGaN:Mg is unnecessary. The absence of annealing treatment is particularly useful in AlInN-based barriers. In the pGaN:Mg layer, Mg-H composite defects occur, and after growth, N is used to activate the acceptor level. ２ Annealing must be performed under atmospheric conditions. AlInN-based barriers have lower heat resistance compared to AlGaN because they contain InN, which has a high vapor pressure. Therefore, the GaN:Mg annealing process is undesirable for AlInN barriers. In addition, Mg remains in the crystal growth furnace and can contaminate the next growing wafer. On the other hand, this problem does not occur with GaN:C.

[0064] The above explanation described the case where carbon (C) was used as the dopant for the cap layer 50. However, similar effects can be obtained with any atom that has a deep acceptor level in GaN, such as Fe, Mn, or other transition metals. Furthermore, similar effects can be expected even with intrinsic defects such as interstitial atoms, antisites, and vacancies, as long as they have a deep acceptor level. The intentional introduction of intrinsic defects can also be achieved, for example, by electron beam irradiation, ion irradiation, or annealing treatment.

[0065] (Effects) Next, we will explain the effects of the semiconductor device 1.

[0066] In this embodiment, the cap layer 50 includes a semi-insulating dopant having an acceptor level deeper than Mg. In the nitride semiconductor layer described above, the source-gate sheet resistance Rsg, the under-gate sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy equation (d) or equation (e) above. This makes it possible to achieve normally-off operation while keeping the on-resistance low. Furthermore, the number of defect levels can be suppressed compared to the case where the gate electrode 60 is in contact with the nitride semiconductor layer described above via an insulating film. As a result, good high-frequency characteristics and reliability can be obtained.

[0067] In this embodiment, the cap layer 50 contains a semi-insulating dopant having a deeper acceptor level than Mg. This makes it possible to shorten the distance between the gate electrode 60 and the 2DEG region 31 generated in the nitride semiconductor layer compared to the case where the cap layer 50 contains Mg as a dopant. The total thickness of the barrier layer 40 and the cap layer 50 (barrier film thickness t) ｂａｒ The above equation (f) or equation (g) is satisfied in the source-gate film thickness Tsg, gate-under film thickness Tg, and gate-drain film thickness Tgd. This makes it possible to achieve normally-off operation while keeping the on-resistance low. In addition, the number of defect levels can be suppressed compared to the case where the gate electrode 60 is in contact with the nitride semiconductor layer via an insulating film. As a result, good high-frequency characteristics and reliability can be obtained.

[0068] In this embodiment, the concentration of the semi-insulating dopant is 1 × 10⁻⁶. １７ cm －３ The above 4.5 x 10 ２１ cm －３ The following is the explanation. This makes it possible to compensate for the 2DEG directly below the gate electrode 60 even if the cap layer 50 is thin. As a result, good high-frequency characteristics can be obtained.

[0069] In this embodiment, the concentration of the semi-insulating dopant is 1 × 10⁻⁶. １７ cm －３ The above 4.5 x 10 ２０ cm －３ The following is the explanation. This makes it possible to compensate for the 2DEG directly below the gate electrode 60 even if the cap layer 50 is thin. As a result, good high-frequency characteristics can be obtained.

[0070] In this embodiment, the sheet concentration of the semi-insulating dopant is 1 × 10⁻⁶. １２ cm －２ This concludes the explanation. As a result, even if the capping layer 50 is thin, the 2DEG directly below the gate electrode 60 can be compensated for. Consequently, good high-frequency characteristics can be obtained.

[0071] In this embodiment, the semi-insulating dopant is C. This allows for compensation of the 2DEG directly beneath the gate electrode 60, even if the cap layer 50 is thin. As a result, good high-frequency characteristics can be obtained.

[0072] In this embodiment, the semi-insulating dopant is Fe or Mn. This allows for compensation of the 2DEG directly beneath the gate electrode 60, even if the cap layer 50 is thin. As a result, good high-frequency characteristics can be obtained.

[0073] In this embodiment, the barrier layer 40 is made of an AlInN-based semiconductor. This allows for a cutoff frequency f of, for example, 20 GHz to 110 GHz. Ｔ This can be achieved. As a result, semiconductor device 1 can be used as a power amplifier or the like in next-generation wireless communication devices.

[0074] In this embodiment, the barrier layer 40 is made of AlGaN. The barrier film thickness tｂａｒ This results in a cutoff frequency f of, for example, 20 GHz to 110 GHz. Ｔ This can be achieved. As a result, semiconductor device 1 can be used as a power amplifier or the like in next-generation wireless communication devices.

[0075] In this embodiment, the barrier layer 40 is composed of AlInN or AlGaInN. The barrier film thickness t ｂａｒ This is 25 nm or less, or 15 nm. As a result, the cutoff frequency f is, for example, 20 GHz to 110 GHz. Ｔ This can be achieved. As a result, semiconductor device 1 can be used as a power amplifier or the like in next-generation wireless communication devices.

[0076] In this embodiment, the cap layer 50 is made of a GaN-based semiconductor. This suppresses oxidation of the barrier layer 40 and damage during the process, contributing to the stability of the device characteristics. Furthermore, gate leakage can be suppressed.

[0077] In this embodiment, the substrate 10 is a Si substrate, and a buffer layer 20 is provided between the substrate 10 and the channel layer 30. By using the buffer layer 20 in this way, an inexpensive substrate (for example, a Si substrate) that does not lattice match with GaN can be used as the substrate 10. As a result, an inexpensive semiconductor device 1 can be provided.

[0078] In this embodiment, the gate electrode 60 is in contact with the cap layer 50, and the source electrode 70 and drain electrode 80 are in contact with the barrier layer 40. This allows for compensation of the 2DEG directly beneath the gate electrode 60 by thinning the cap layer 50. As a result, good high-frequency characteristics can be obtained.

[0079] Incidentally, the first reported normally-off HEMT with a pGaN cap layer between the gate electrode and the barrier layer was in Patent Document 1 and Non-Patent Document 3 below. As described in these documents, normally-off technology using a pn junction in the gate portion has been known conventionally in GaAs systems, and the pGaN gate technology is based on the same technical concept. Utilizing such pn junctions is common in semiconductor technology. However, as in this embodiment, it is not common to functionally use a junction between a semi-insulating semiconductor layer containing a semi-insulating dopant and an n-type semiconductor layer.

[0080] Non-Patent Document 3 Y. Uemoto, M. Hikita, H. Ueno, H. Matsuo, H. Ishida, M. Yanagihara, et al., "Gate Injection Transistor (GIT)-A Normally-Off AlGaN / GaN Power Transistor Using Conductivity Modulation", IEEE Transactions on Electron Devices 2007 Vol. 54 Issue 12 Pages 3393-3399.

[0081] In GaN systems, carbon (C) is used for insulation. However, doping with carbon impurities is known to have adverse effects such as degraded crystallinity, the formation of non-luminescent centers, and current collapse in HEMT. Therefore, it is unlikely that a person skilled in the art would actively utilize a semiconductor layer doped with carbon impurities as a functional layer near the gate. The applicant has confirmed that current collapse does not worsen even when a GaN:C capping layer is used.

[0082] Incidentally, even if a C-doped sample is prepared, a simple sheet resistance evaluation alone is likely to be misinterpreted as a deterioration of mobility, based on the common technical understanding that "crystallinity deteriorates with C." In this regard, the applicant conceived the idea that 2DEG compensation is possible even with deep acceptor levels based on theoretical considerations, and proceeded with development, demonstrating through Hall effect measurement that compensation is possible without deterioration of mobility. Furthermore, the applicant has developed a solution that is 10, which is much higher than Mg. ２０ cm －３ It was demonstrated that doping exceeding a certain level is possible, and that 2DEG can be sufficiently compensated even with a film thickness of several nm. To the best of the applicant's knowledge, there are no experimental reports showing significant effects from using GaN:C in the cap layer 50. By using GaN:C in the cap layer 50, the cap layer 50 can be significantly thinned to 1 / 50 to 1 / 10 of its original thickness, resulting in remarkable effects such as a 10-fold improvement in high-frequency characteristics and improved controllability, such as reducing the etching film thickness in the cap layer removal process to about 1 / 10. Furthermore, it also exhibits unique effects such as reduced development costs due to the absence of Mg, and improved reliability by enabling the 2DEG sheet density Ns of the access region to be increased again without etching. From the above, the applicant believes that the semiconductor device 1 according to this embodiment has sufficient inventive step in relation to the prior art.

[0083] <2. Modifications of the First Embodiment> Next, a modification of the semiconductor device 1 according to the first embodiment will be described.

[0084] (Modification 2-1) In the first embodiment, the semiconductor device 1 may further include an etching stop layer 90 between the cap layer 50 and the barrier layer 40, as shown in Figure 10. The etching stop layer 90 is composed of, for example, AlGaN or InGaN. By providing the etching stop layer 90 in this way, it becomes possible to stop etching at the surface of the etching stop layer 90 when selectively etching the cap layer 50 during the manufacturing process of the semiconductor device 1. As a result, the controllability of etching during the manufacturing process of the semiconductor device 1 can be improved.

[0085] (Modification 2-2) In the first embodiment, the cap layer 50 may be formed by regrowth. Figures 11A and 11B show an example of the manufacturing procedure for the semiconductor device 1 according to this modification. First, for example, using the MOCVD method, a nitride semiconductor layer including a buffer layer 20, a channel layer 30, and a barrier layer 40 in that order from the substrate 10 side is formed on the substrate 10 (Figure 11A). Next, a mask 220 having an opening H1 at a predetermined location on the surface of the nitride semiconductor layer is formed (Figure 11A). Subsequently, for example, using the MOCVD method, the cap layer 50 is regrowthed in the opening H1 using the mask 220 as a mask (Figure 11B). After that, the mask 200 is removed and a gate electrode 60, a source electrode 70, and a drain electrode 80 that are in contact with the surface of the nitride semiconductor layer are formed. In this way, the semiconductor device 1 according to this modification is manufactured.

[0086] In this modified example, the cap layer 50 is formed by regrowth. Even in this case, good high-frequency characteristics and reliability can be obtained, similar to the above embodiment.

[0087] (Modification 2-3) In the first embodiment, for example, as shown in Figure 12, recesses are provided in the nitride semiconductor layer described above at locations facing each other with the cap layer 50 in between, one of the two recesses provided in the nitride semiconductor layer described above is filled with a regrowth layer 110 made of n-type nitride semiconductor, and the other of the two recesses provided in the nitride semiconductor layer described above is filled with a regrowth layer 120 made of n-type nitride semiconductor. In this case, the source electrode 70 is in ohmic contact with the surface of the regrowth layer 110, and the drain electrode 80 is in ohmic contact with the surface of the regrowth layer 120. For example, as shown in Figure 12, each recess provided in the nitride semiconductor layer described above has a depth that reaches the channel layer 30, and the regrowth layers 110 and 120 are in contact with the channel layer 30.

[0088] In this modified example, the cap layer 50 is provided between the gate electrode 60 and the barrier layer 40. The cap layer 50 is not provided in the region between the source electrode 70 and the gate electrode 60 (access region), nor in the region between the gate electrode 60 and the drain electrode 80 (access region). Furthermore, regrowth layers 110 and 120 with a depth reaching the channel layer 30 are provided directly beneath the source electrode 70 and the drain electrode 80 in the nitride semiconductor layer described above. As a result, 2DEG regions 31 are formed in the region between the source electrode 70 and the gate electrode 60 (access region) and the region between the gate electrode 60 and the drain electrode 80 (access region) of the nitride semiconductor layer described above, but 2DEG regions 31 are not formed directly beneath the gate electrode 60 or directly beneath the source electrode 70 or the drain electrode 80 in the nitride semiconductor layer described above.

[0089] Next, a method for manufacturing the semiconductor device 1 according to this modified example will be described.

[0090] Figures 13A to 13G show an example of the manufacturing procedure for the semiconductor device 1 according to this modified example. First, for example, using the MOCVD method, a nitride semiconductor layer is formed on the substrate 10, including a buffer layer 20, a channel layer 30, and a barrier layer 40 in that order from the substrate 10 side (Figure 13A). At this time, a 2DEG region 31 is formed at the heterointerface between the channel layer 30 and the barrier layer 40. Next, a mask 230 having openings H2 and H3 at predetermined locations on the surface of the nitride semiconductor layer is formed (Figure 13A). Subsequently, by performing a dry etching process using the mask 230 as a mask, the portions of the nitride semiconductor layer not covered by the mask 230 are selectively etched (Figure 13B). As a result, a groove H4 with a depth reaching the channel layer 30 is formed directly below opening H2, and a groove H5 with a depth reaching the channel layer 30 is formed directly below opening H3. Next, regrowth is performed to form a regrowth layer 110 that fills the groove H4, and a regrowth layer 120 that fills the groove H5 (Figure 13C). After that, the mask 230 is removed (Figure 13D).

[0091] Next, a mask 240 having an opening H6 at a predetermined location on the surface of the nitride semiconductor layer described above is formed (Figure 13E). Subsequently, a regrowth layer (cap layer 50) that fills the opening H6 is formed by regrowth (Figure 13F). At this time, the 2DEG region 31 that had occurred in the location opposite the cap layer 50 is compensated by the cap layer 50. After that, the mask 240 is removed (Figure 13G). Then, a gate electrode 60, a source electrode 70, and a drain electrode 80 that are in contact with the surface of the nitride semiconductor layer described above are formed. In this way, the semiconductor device 1 according to this modified example is manufactured.

[0092] In this modified example, the cap layer 50 is provided between the gate electrode 60 and the barrier layer 40, and is not provided in the region between the gate electrode 60 and the drain electrode 80 (access region), nor in the region between the source electrode 70 and the gate electrode 60 (access region). By making the cap layer 50 thinner, the 2DEG directly below the gate electrode 60 can be compensated. As a result, normally-off operation and good high-frequency characteristics can be obtained.

[0093] (Modification 2-4) In the first embodiment, the cap layer 50 is provided between the gate electrode 60 and the barrier layer 40, as shown in Figure 14, and also in the region between the gate electrode 60 and the drain electrode 80 (access region), and may not be provided in the region between the source electrode 70 and the gate electrode 60 (access region). In this case, the gate electrode 60 and the drain electrode 80 are in contact with the surface of the cap layer 50, and the source electrode 70 is in contact with the barrier layer 40. By making the cap layer 50 thinner, the 2DEG directly below the gate electrode 60 and in the region between the gate electrode 60 and the drain electrode 80 (access region) can be compensated. As a result, normally-off operation and good high-frequency characteristics can be obtained. Furthermore, by compensating for the 2DEG in the access region, high-frequency characteristics are improved by increasing the breakdown voltage and reducing the gate-drain capacitance.

[0094] Incidentally, as described in Non-Patent Document 4, a technique is known in which the breakdown voltage is improved by providing 2DHG (Two-Dimensional Hole Gas) or pGaN in the access region between the gate and drain to mitigate the electric field. This disclosure can apply such a technique. That is, by forming a cap layer 50 containing a semi-insulating dopant in the access region, good breakdown voltage can be obtained. Furthermore, high-frequency characteristics are also improved because the gate-drain capacitance Cgd is reduced. Compared to conventional methods using pGaN or 2DHG, 2DEG can be sufficiently compensated with a thinner cap film thickness, thus expanding the freedom of device design. In addition, since Mg is not used, the activation annealing process is unnecessary, no memory effect occurs, and development costs are reduced.

[0095] Non-patent document 4 Low cost high voltage GaN polarization superjunction field effect transistors H. Kawai, S. Yagi, S. Hirata, F. Nakamura, T. Saito, Y. Kamiyama, et al. physica status solidi (a) 2017 Vol. 214 Issue 8 DOI: 10.1002 / pssa.201600834

[0096] (Modification 2-5) In Modification 2-4, for example, as shown in Figure 15, recesses are provided in the nitride semiconductor layer described above at locations facing each other with the cap layer 50 in between, one of the two recesses provided in the nitride semiconductor layer described above is filled with a regrowth layer 130 made of n-type nitride semiconductor, and the other of the two recesses provided in the nitride semiconductor layer described above is filled with a regrowth layer 140 made of n-type nitride semiconductor. In this case, the source electrode 70 is in ohmic contact with the surface of the regrowth layer 130, and the drain electrode 80 is in ohmic contact with the surface of the regrowth layer 140. For example, as shown in Figure 15, each recess provided in the nitride semiconductor layer described above has a depth that reaches the channel layer 30, and the regrowth layers 130 and 140 are in contact with the channel layer 30.

[0097] In this modified example, the cap layer 50 is provided between the gate electrode 60 and the barrier layer 40, as well as in the region between the gate electrode 60 and the drain electrode 80 (access region), but not in the region between the source electrode 70 and the gate electrode 60 (access region). As a result, a 2DEG region 31 is created in the nitride semiconductor layer between the source electrode 70 and the gate electrode 60 (access region), but not directly beneath the gate electrode 60 or in the region between the gate electrode 60 and the drain electrode 80 (access region). Therefore, similar to modified example 2-4, normally-off operation and good high-frequency characteristics and reliability can be obtained. Furthermore, by compensating for the 2DEG in the access region, high-frequency characteristics are improved by increasing the breakdown voltage and reducing the gate-drain capacitance.

[0098] (Modification 2-6) In the first embodiment, the cap layer 50 may be provided in the region between the gate electrode 60 and the drain electrode 80 (access region), for example, as shown in Figure 16. In this case, the drain electrode 80 is in contact with the surface of the cap layer 50, and the gate electrode 60 and the source electrode 70 are in contact with the barrier layer 40. In this case, the semiconductor device 1 according to this modification functions as a normally-on type HEMT. By making the cap layer 50 thinner, the 2DEG in the region between the gate electrode 60 and the drain electrode 80 (access region) can be compensated. As a result, normally-on operation and good high-frequency characteristics can be obtained. Furthermore, by compensating for the 2DEG in the access region, high-frequency characteristics are improved by increasing the breakdown voltage and reducing the gate-drain capacitance.

[0099] (Modification 2-7) In Modification 2-6, for example, as shown in Figure 17, recesses are provided in the nitride semiconductor layer described above at locations facing each other with the cap layer 50 in between, one of the two recesses provided in the nitride semiconductor layer described above is filled with a regrowth layer 150 made of n-type nitride semiconductor, and the other of the two recesses provided in the nitride semiconductor layer described above is filled with a regrowth layer 160 made of n-type nitride semiconductor. In this case, the source electrode 70 is in ohmic contact with the surface of the regrowth layer 150, and the drain electrode 80 is in ohmic contact with the surface of the regrowth layer 160. For example, as shown in Figure 17, each recess provided in the nitride semiconductor layer described above has a depth that reaches the channel layer 30, and the regrowth layers 150 and 160 are in contact with the channel layer 30.

[0100] In this modified example, the cap layer 50 is provided in the region between the gate electrode 60 and the drain electrode 80 (access region). The cap layer 50 is not provided between the gate electrode 60 and the barrier layer 40, or in the region between the source electrode 70 and the gate electrode 60 (access region). Furthermore, regrowth layers 110 and 120, reaching a depth of the channel layer 30, are provided directly beneath the source electrode 70 and the drain electrode 80 in the nitride semiconductor layer described above. As a result, a 2DEG region 31 is created in the region between the source electrode 70 and the gate electrode 60 (access region) and directly beneath the gate electrode 60 in the nitride semiconductor layer described above, while a 2DEG region 31 is not created in the region between the gate electrode 60 and the drain electrode 80 (access region) in the nitride semiconductor layer described above. As a result, normally-on operation and good high-frequency characteristics and reliability can be obtained. Furthermore, by compensating for the 2DEG in the access region, high-frequency characteristics are improved by increasing the breakdown voltage and reducing the gate-drain capacitance.

[0101] (Modification 2-8) In the first embodiment, the cap layer 50 may be provided in the region between the gate electrode 60 and the drain electrode 80 (access region), for example, as shown in Figure 18. In this case, the cap layer 50 is in contact with the surface, the gate electrode 60, the source electrode 70, and the drain electrode 80 are in contact with the barrier layer 40, and the cap layer 50 is provided between the gate electrode 60 and the drain electrode 80. As a result, a 2DEG region 31 is created in the region between the source electrode 70 and the gate electrode 60 (access region) and directly below the gate electrode 60 of the nitride semiconductor layer, while a 2DEG region 31 is not created in the region between the gate electrode 60 and the drain electrode 80 (access region) of the nitride semiconductor layer. As a result, normally-on operation and good high-frequency characteristics and reliability can be obtained. Furthermore, by compensating for the 2DEG in the access region, high-frequency characteristics are improved by increasing the breakdown voltage and reducing the gate-drain capacitance.

[0102] (Modification 2-9) In Modification 2-8, for example, as shown in Figure 19, recesses are provided in the nitride semiconductor layer described above at locations facing each other with the cap layer 50 in between, one of the two recesses provided in the nitride semiconductor layer described above is filled with a regrowth layer 170 made of n-type nitride semiconductor, and the other of the two recesses provided in the nitride semiconductor layer described above is filled with a regrowth layer 180 made of n-type nitride semiconductor. In this case, the source electrode 70 is in ohmic contact with the surface of the regrowth layer 170, and the drain electrode 80 is in ohmic contact with the surface of the regrowth layer 180. For example, as shown in Figure 19, each recess provided in the nitride semiconductor layer described above has a depth that reaches the channel layer 30, and the regrowth layers 170 and 180 are in contact with the channel layer 30.

[0103] In this modified example, the cap layer 50 is provided in the region between the gate electrode 60 and the drain electrode 80 (access region). The cap layer 50 is not provided directly beneath the gate electrode 60 or in the region between the source electrode 70 and the gate electrode 60 (access region). Furthermore, regrowth layers 170 and 180, reaching a depth of the channel layer 30, are provided directly beneath the source electrode 70 and the drain electrode 80 in the nitride semiconductor layer described above. As a result, a 2DEG region 31 is created in the nitride semiconductor layer directly beneath the gate electrode 60 and in the region between the source electrode 70 and the gate electrode 60 (access region), while a 2DEG region 31 is not created in the region between the gate electrode 60 and the drain electrode 80 (access region) in the nitride semiconductor layer described above. As a result, normally-on operation and good high-frequency characteristics and reliability can be obtained. Furthermore, by compensating for the 2DEG in the access region, high-frequency characteristics are improved by increasing the breakdown voltage and reducing the gate-drain capacitance.

[0104] (Modification 2-10) In the first embodiment and its modification, the semiconductor device 1 may have an N-polar crystal structure. In this case, the positional relationship between the barrier layer 30 and the channel layer 30 is reversed compared to the case where the semiconductor device 1 has a Ga-polar crystal structure. The 2DEG region 31 occurs in the channel layer 30 near the interface between it and the barrier layer 30. The 2DEG region 31 occurs, for example, as shown in Figure 20, in the channel layer 30 near the interface between it and the barrier layer 30, and in the channel layer 30 at a location that is not facing the cap layer 50. Even when the semiconductor device 1 is configured with an N-polar crystal structure, and the positional relationship between the barrier layer 30 and the channel layer 30 is reversed compared to the case where the semiconductor device 1 has a Ga-polar crystal structure, good high-frequency characteristics and reliability can be obtained, similar to the above embodiment and its modification.

[0105] <3. Second Embodiment> (Configuration) A semiconductor device 2 according to a second embodiment of the present disclosure will be described. Figure 21 shows an example of the cross-sectional configuration of the semiconductor device 2. The semiconductor device 2 is a HEMT using a nitride semiconductor. The semiconductor device 2 comprises a substrate 10 and a nitride semiconductor layer formed on the substrate 10 as a crystal growth substrate. For example, MOCVD is used for crystal growth of the nitride semiconductor layer. The nitride semiconductor layer is composed of, for example, a buffer layer 20, a channel layer 30, a barrier layer 40 and a cap layer 50 in this order from the substrate 10 side.

[0106] The semiconductor device 2 further includes a gate electrode 60 provided on the cap layer 50, and a source electrode 70 and a drain electrode 80 provided on the cap layer 50 at locations facing each other with respect to the gate electrode 60. The gate electrode 60, source electrode 70, and drain electrode 80 are in contact with the surface of the nitride semiconductor layer described above. The gate electrode 60, source electrode 70, and drain electrode 80 are in contact with the surface of the cap layer 50.

[0107] The semiconductor device 2 is a high electron mobility transistor (HEMT) with a two-dimensional electron gas (2DEG) region 31 as its channel. The semiconductor device 2 is a HEMT using a nitride semiconductor, and for example, has a Ga polar crystal structure. The 2DEG region 31 arises from the difference between the polarization magnitude of the channel layer 30 and the polarization magnitude of the barrier layer 40. The 2DEG region 31 occurs at the heterointerface between the channel layer 30 and the barrier layer 40.

[0108] In the nitride semiconductor layer described above, the source-gate sheet resistance Rsg, the gate-under-gate sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy either equation (d) or equation (e) below. The material, dopant, and film thickness of the cap layer 50 are the same as those of the cap layer 50 in the first embodiment described above. Rsg < Rg ... (d) Rsg < Rgd ... (e)

[0109] The source-gate sheet resistance Rsg can be calculated, for example, from the resistance when current flows between the source electrode 70 and the gate electrode 60, and the distance between the source electrode 70 and the gate electrode 60. The gate-drain sheet resistance Rgd can be calculated, for example, from the resistance when current flows between the gate electrode 60 and the drain electrode 80, and the distance between the gate electrode 60 and the drain electrode 80. The gate-under-gate sheet resistance Rg when the gate voltage is 0V can be calculated from the resistance when current flows between the source electrode 70 and the drain electrode 80 while 0V is applied to the gate electrode 60, the gate length Lg, the source-gate sheet resistance Rsg, and the gate-drain sheet resistance Rgd. However, it is also necessary to consider the contact resistance between the electrode and the semiconductor in these calculations. When there are multiple structures with different inter-electrode distances and gate lengths, the TLM (Transmission Line Model) method can be used to evaluate both the sheet resistance and the contact resistance.

[0110] In this embodiment, the portion of the surface of the cap layer 50 that is in contact with the source electrode 70 and the drain electrode 80 is a surface-treated region 51 in which the semi-insulating effect of the semi-insulating dopant is canceled out. The surface-treated region 51 is not provided in the region of the surface of the cap layer 50 between the gate electrode 60 and the barrier layer 40. The surface-treated region 51 is a region in which the cap layer 50 has been altered by a low-damage process treatment different from dry etching. Examples of low-damage process treatments (alteration treatments for the cap layer 50) include a treatment that evaporates the semi-insulating dopant to eliminate deep acceptor levels, or a treatment that introduces donor-like point defects above deep acceptor levels by adding other atoms to form composite defects. Note that in the manufacturing process of the semiconductor device 2, the C concentration and 2DEG sheet density Ns of the cap layer 50 before the surface-treated region 51 is formed are the same as those of the cap layer 50 in the first embodiment described above.

[0111] Figures 22, 23, and 24 show experimental results of the relationship between carbon concentration and sheet resistance Rs, 2DEG sheet density Ns, and mobility when multiple samples with different carbon concentrations were subjected to plasma treatment with oxygen gas. It can be seen that the 2DEG sheet density Ns of the sample whose 2DEG sheet density Ns decreased due to carbon doping increased after plasma treatment. Furthermore, since there was no deterioration in mobility in each sample, it can be seen that damage to the crystal was kept to a minimum. Note that undoping (10 １６ cm －３ Regarding the sample, the 2DEG sheet density Ns did not increase before and after processing, indicating that the Places treatment itself does not have an effect of increasing the 2DEG sheet density Ns. Specifically, the alteration of the cap layer 50 in this experiment is thought to be due to the removal of carbon in the cap layer 50 by bonding with oxygen and the introduction of donor point defects originating from oxygen.

[0112] Specifically, Figures 22, 23, and 24 show that the 2DEG compensation amount can be controlled by a low-damage process other than dry etching. By controlling 2DEG with a low-damage process, crystal damage caused by dry etching can be suppressed, thus contributing to improved properties. Furthermore, since there is no reduction in film thickness due to dry etching, fluctuations in properties such as capacitance can be suppressed. Generally, dry etching is difficult to perform on wafers with exposed metal due to equipment contamination and other factors, but this is possible with low-damage processes such as plasma processing. Therefore, the flexibility of the process steps is improved.

[0113] (Manufacturing Method) Next, the manufacturing method for the semiconductor device 2 will be described.

[0114] Figures 25A and 25B illustrate an example of the manufacturing procedure for the semiconductor device 2. First, a nitride semiconductor layer is formed on a substrate 10, for example, using the MOCVD method, including a buffer layer 20, a channel layer 30, a barrier layer 40, and a cap layer 50 in that order from the substrate 10 side (Figure 25A). Next, a mask 230 is formed on a predetermined location on the surface of the nitride semiconductor layer (Figure 25A). Subsequently, a surface treatment area 51 is formed on the cap layer 50 in the area not covered by the mask 230 by performing plasma treatment using the mask 230 as a mask (Figure 25B). After that, the mask 230 is removed, and a gate electrode 60, a source electrode 70, and a drain electrode 80 are formed in contact with the surface of the nitride semiconductor layer. In this way, the semiconductor device 2 is manufactured.

[0115] (Effects) Next, we will explain the effects of the semiconductor device 2.

[0116] In this embodiment, the cap layer 50 includes a semi-insulating dopant having an acceptor level deeper than Mg. In the nitride semiconductor layer described above, the source-gate sheet resistance Rsg, the gate-under sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy equation (d) or equation (e) above. This makes it possible to achieve normally-off operation while keeping the on-resistance low. Furthermore, the number of defect levels can be suppressed compared to the case where the gate electrode 60 is in contact with the nitride semiconductor layer described above via an insulating film. As a result, good high-frequency characteristics and reliability can be obtained. In addition, good characteristics can be obtained by controlling the 2DEG density without removing the cap layer by dry etching.

[0117] In this embodiment, the concentration of the semi-insulating dopant in the cap layer 50, excluding the surface treatment area 51, is 1 × 10⁻⁶. １７ cm －３ The above 4.5 x 10 ２１ cm －３ The following is the explanation. This makes it possible to compensate for the 2DEG directly below the gate electrode 60 even if the cap layer 50 is thin. As a result, good high-frequency characteristics can be obtained.

[0118] In this embodiment, the concentration of the semi-insulating dopant in the cap layer 50, excluding the surface treatment area 51, is 1 × 10⁻⁶. １７ cm －３ The above 4.5 x 10 ２０ cm －３ The following is the explanation. This makes it possible to compensate for the 2DEG directly below the gate electrode 60 even if the cap layer 50 is thin. As a result, good high-frequency characteristics can be obtained.

[0119] In this embodiment, the sheet concentration of the semi-insulating dopant in the cap layer 50, excluding the surface treatment area 51, is 1 × 10⁻⁶. １２ cm －２ This concludes the explanation. As a result, even if the capping layer 50 is thin, the 2DEG directly below the gate electrode 60 can be compensated for. Consequently, good high-frequency characteristics can be obtained.

[0120] In this embodiment, the semi-insulating dopant is C. This allows for compensation of the 2DEG directly beneath the gate electrode 60, even if the cap layer 50 is thin. As a result, good high-frequency characteristics can be obtained.

[0121] In this embodiment, the semi-insulating dopant is Fe or Mn. This allows for compensation of the 2DEG directly beneath the gate electrode 60, even if the cap layer 50 is thin. As a result, good high-frequency characteristics can be obtained.

[0122] In this embodiment, the barrier layer 40 is made of an AlInN-based semiconductor. This allows for a cutoff frequency f of, for example, 20 GHz to 110 GHz. Ｔ This is obtained. As a result, semiconductor device 2 can be used as a power amplifier or the like in next-generation wireless communication devices.

[0123] In this embodiment, the barrier layer 40 is made of AlGaN. The barrier film thickness t ｂａｒ This results in a cutoff frequency f of, for example, 20 GHz to 110 GHz. Ｔ This is obtained. As a result, semiconductor device 2 can be used as a power amplifier or the like in next-generation wireless communication devices.

[0124] In this embodiment, the barrier layer 40 is composed of AlInN or AlGaInN. The barrier film thickness t ｂａｒ This is 25 nm or less, or 15 nm. As a result, the cutoff frequency f is, for example, 20 GHz to 110 GHz. Ｔ This is obtained. As a result, semiconductor device 2 can be used as a power amplifier or the like in next-generation wireless communication devices.

[0125] In this embodiment, the cap layer 50 is made of a GaN-based semiconductor. This suppresses oxidation of the barrier layer 40 and damage during the process, contributing to the stability of the device characteristics. Furthermore, gate leakage can be suppressed.

[0126] In this embodiment, the substrate 10 is a Si substrate, and a buffer layer 20 is provided between the substrate 10 and the channel layer 30. By using the buffer layer 20 in this way, an inexpensive substrate (for example, a Si substrate) that does not lattice match with GaN can be used as the substrate 10. As a result, an inexpensive semiconductor device 2 can be provided.

[0127] In this embodiment, the gate electrode 60 is in contact with the cap layer 50, and the source electrode 70 and drain electrode 80 are in contact with the barrier layer 40. This allows for compensation of the 2DEG directly beneath the gate electrode 60 by thinning the cap layer 50. As a result, good high-frequency characteristics can be obtained.

[0128] In this embodiment, the portion of the cap layer 50 that contacts the source electrode 70 and the drain electrode 80 is a surface-treated region 51. As a result, the semi-insulating effect of the semi-insulating dopant is canceled out in the portion of the cap layer 50 that contacts the source electrode 70 and the drain electrode 80, and 2DEG occurs. As a result, good high-frequency characteristics can be obtained.

[0129] <4. Modifications of the Second Embodiment> Next, a modification of the semiconductor device 2 according to the second embodiment will be described.

[0130] (Modification 4-1) In the second embodiment, for example, as shown in Figure 26, the surface of the region between the gate electrode 60 and the source electrode 70 (access region) of the cap layer 50 is a surface treatment region 51, and the region directly below the gate electrode 60 and the region between the gate electrode 60 and the drain electrode 80 (access region) of the cap layer 50 does not need to have a surface treatment region 51. In this case, the gate electrode 60 and the drain electrode 80 are in contact with the surface of the cap layer 50 that does not have a surface treatment region 51, and the source electrode 70 is in contact with the surface treatment region 51. By making the cap layer 50 thinner, 2DEG in the region directly below the gate electrode 60 and the region between the gate electrode 60 and the drain electrode 80 (access region) can be compensated, and furthermore, in the region between the gate electrode 60 and the source electrode 70 (access region) of the cap layer 50, the semi-insulating effect of the semi-insulating dopant is canceled out, and 2DEG occurs. As a result, normally-off operation and good high-frequency characteristics can be obtained. Furthermore, the compensation of 2DEG in the access region improves high-frequency characteristics through increased breakdown voltage and reduced gate-drain capacitance.

[0131] (Modification 4-2) In the second embodiment, for example, as shown in Figure 27, the surface treatment region 51 is not only on the surface of the region between the gate electrode 60 and the source electrode 70 (access region) of the cap layer 50, but also on the area directly below the gate electrode 60, and the surface treatment region 51 is not provided in the region between the gate electrode 60 and the drain electrode 80 (access region) of the cap layer 50. In this case, the semiconductor device 2 according to this modification functions as a normally-on type HEMT. By making the cap layer 50 thinner, the 2DEG in the region between the gate electrode 60 and the drain electrode 80 (access region) can be compensated for. Furthermore, in this modification, since the surface treatment region 51 exists in the region directly below the gate electrode 60 and the region between the gate electrode 60 and the source electrode 70 (access region) of the cap layer 50, the semi-insulating effect of the semi-insulating dopant is canceled out in the region directly below the gate electrode 60 and the region between the gate electrode 60 and the source electrode 70 (access region) of the cap layer 50, and 2DEG occurs. As a result, normally-on operation and good high-frequency characteristics can be obtained. Furthermore, the compensation of 2DEG in the access region improves high-frequency characteristics through improved breakdown voltage and reduced gate-drain capacitance.

[0132] (Modification 4-3) The threshold voltage Vth is an important parameter in circuit design. In HEMT, Vth is highly dependent on the thickness and composition of the barrier layer. Changing the thickness and composition of the barrier layer simultaneously changes Ns and the resistance of the access region significantly. Therefore, it is basically not possible to independently adjust Vth using the epitaxial structure, and other characteristics will change as a result. In the second embodiment, for example, as shown in Figure 28, by adjusting the concentration of the semi-insulating dopant in the cap layer 50, a 2DEG region 31 thinner than the 2DEG region 31 that occurs in the region between the gate electrode 60 and the source electrode 70 (access region) and the region between the gate electrode 60 and the drain electrode 80 (access region) may be generated directly beneath the gate electrode 60. In this case, the threshold voltage Vth is shifted positively compared to the case where a semi-insulating dopant is not used. On the other hand, the Ns of the access region can be made to the same level as the case where a semi-insulating dopant is not used by surface treatment. In other words, because Vth can be changed independently of the resistance of the access area, the design flexibility is greatly increased.

[0133] (Modification 4-4) In the second embodiment and modifications 4-1, 4-2, and 4-3, the insulating film 52 may be provided between the gate electrode 60 and the cap layer 50. The insulating film 52 may be provided between the gate electrode 60 and the cap layer 50, for example, as shown in Figure 29. In this case, the insulating film 52 and the gate electrode 60 are in contact with each other, and the insulating film 52 and the cap layer 50 are in contact with each other. The insulating film 52 is an oxide film, for example, silicon oxide (SiO ２ ), aluminum oxide (Al ２ O ３ It is composed of a single layer film made of one of the following: ), hafnium oxide (HfO), etc., or a multilayer film made of two or more of these. In other words, in this modified example, the semiconductor device 2 functions as a MIS (Metal Insulator Semiconductor) type HEMT. Even in this case, normally-off operation and good high-frequency characteristics can be obtained.

[0134] <5. Third Embodiment> (Configuration) A semiconductor device 3 according to the third embodiment of the present disclosure will now be described. Figure 30 shows an example of the cross-sectional configuration of the semiconductor device 3. The semiconductor device 3 is a HEMT using a nitride semiconductor. The semiconductor device 3 comprises a substrate 10 and a nitride semiconductor layer formed on the substrate 10 as a crystal growth substrate. For example, MOCVD is used for crystal growth of the nitride semiconductor layer. The nitride semiconductor layer is composed of, for example, a buffer layer 20, a channel layer 30, a barrier layer 40, and an undoped cap layer 53 in this order from the substrate 10 side.

[0135] The semiconductor device 3 further includes a gate electrode 60 provided on an undoped cap layer 53, and a source electrode 70 and a drain electrode 80 provided on the undoped cap layer 53 at locations facing each other with respect to the gate electrode 60. The gate electrode 60, source electrode 70, and drain electrode 80 are in contact with the surface of the nitride semiconductor layer described above. The gate electrode 60, source electrode 70, and drain electrode 80 are in contact with the surface of the cap layer 50.

[0136] The semiconductor device 3 is a high electron mobility transistor (HEMT) with a two-dimensional electron gas (2DEG) region 31 as the channel. The semiconductor device 3 is a HEMT using a nitride semiconductor, and for example, has a Ga polar crystal structure. The 2DEG region 31 arises from the difference between the polarization magnitude of the channel layer 30 and the polarization magnitude of the barrier layer 40. The 2DEG region 31 arises at the heterointerface between the channel layer 30 and the barrier layer 40. The 2DEG region 31 arises in the access region (the region between the source electrode 70 and the gate electrode 60, and the region between the gate electrode 60 and the drain electrode 80).

[0137] In the nitride semiconductor layer described above, the source-gate sheet resistance Rsg, the under-gate sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy either equation (d) or equation (e) below: Rsg < Rg ... (d) Rsg < Rgd ... (e)

[0138] The source-gate sheet resistance Rsg can be calculated, for example, from the resistance when current flows between the source electrode 70 and the gate electrode 60, and the distance between the source electrode 70 and the gate electrode 60. The gate-drain sheet resistance Rgd can be calculated, for example, from the resistance when current flows between the gate electrode 60 and the drain electrode 80, and the distance between the gate electrode 60 and the drain electrode 80. The gate-under sheet resistance Rg when the gate voltage is 0V can be calculated from the resistance when current flows between the source electrode 70 and the drain electrode 80 while 0V is applied to the gate electrode 60, the gate length Lg, the source-gate sheet resistance Rsg, and the gate-drain sheet resistance Rgd. However, it is also necessary to consider the contact resistance between the electrode and the semiconductor in these calculations. When there are multiple structures with different inter-electrode distances and gate lengths, the TLM method can be used to evaluate both the sheet resistance and the contact resistance.

[0139] The undoped cap layer 53 is provided at a position further from the surface S1 of the substrate 10 than the barrier layer 40. The undoped cap layer 53 is made of a nitride semiconductor having a band gap greater than or equal to the band gap of the channel layer 30 and less than or equal to the band gap of the barrier layer 40. The undoped cap layer 53 is a layer for suppressing oxidation of the barrier layer 40. The undoped cap layer 53 is provided on top of the barrier layer 40. The undoped cap layer 53 is made of epitaxially grown gallium nitride (GaN), for example. The undoped cap layer 53 is made of an undoped nitride semiconductor. The undoped cap layer 53 is made of an undoped GaN, for example.

[0140] A cap region 54 is provided in the undoped cap layer 53 at the location in contact with the gate electrode 60. The cap region 54 contains a semi-insulating dopant having a deeper acceptor level than Mg. Examples of semi-insulating dopants include C, Fe, Mn, or other transition metals. The cap region 54 is introduced into the undoped cap layer 53 by means of thermal diffusion or ion implantation, for example, by the semi-insulating dopant having a deeper acceptor level than Mg. Compared to Mg, which is prone to crystal defects, semi-insulating dopants can be introduced at high concentrations.

[0141] (Manufacturing Method) Next, the manufacturing method for the semiconductor device 3 will be described.

[0142] Figures 31A and 31B show an example of the manufacturing procedure for the semiconductor device 3. First, for example, using the MOCVD method, a nitride semiconductor layer is formed on the substrate 10, including a buffer layer 20, a channel layer 30, a barrier layer 40, and an undoped cap layer 53 in that order from the substrate 10 side (Figure 31A). Next, a mask 240 having an opening H2 at a predetermined location on the surface of the nitride semiconductor layer is formed (Figure 31A). Subsequently, using the mask 240 as a mask, a semi-insulating dopant having an acceptor level deeper than Mg is doped into the undoped cap layer 53 in the area not covered by the mask 240 by thermal diffusion or ion implantation. This forms a cap region 54 in the undoped cap layer 53 in the area not covered by the mask 240 (Figure 31B). At this time, 2DEG is compensated in the area opposite the cap region 54. The cap region 54 may extend to the barrier layer 40. Subsequently, the mask 240 is removed, and the gate electrode 60, source electrode 70, and drain electrode 80, which are in contact with the surface of the nitride semiconductor layer described above, are formed. In this way, the semiconductor device 3 is manufactured.

[0143] Incidentally, a method similar to the method of forming a cap region 54 in the undoped cap layer 53 is known, in which F (fluorine) is injected directly beneath the gate electrode 60 in the barrier layer 40 by ion implantation or dry etching to achieve normally-off. However, crystal damage and controllability are challenges with this method. Furthermore, F is not a common dopant for GaN, and much of its behavior is unknown. In contrast, C is a commonly used dopant, so there is much knowledge about it. With C, the thermal diffusion method can be used, which can suppress crystal damage. With F, the thermal diffusion method is extremely difficult from a safety standpoint. When doping Mg by the thermal diffusion method or ion implantation, annealing is necessary for activation. Furthermore, crystal defects are easily introduced due to nitrogen evaporation during annealing, so measures such as annealing under high pressure are necessary. Due to the high cost, this method is difficult to perform with Mg.

[0144] Any impurity atom other than carbon (C) or intrinsic defects (interstitial atoms, antisites, vacancies) with deep acceptor levels can be used. Doping during the growth of new atoms incurs significant costs, such as equipment modifications and control of raw material purity. This embodiment eliminates these costs, resulting in low costs. Furthermore, atoms that are difficult to dope during growth can also be considered as candidates. For example, many metal atoms (such as Ni and Au) have deep levels in semiconductors, and doping during growth is difficult, but this method makes it possible.

[0145] In this embodiment, the cap region 54 includes a semi-insulating dopant having an acceptor level deeper than Mg. In the nitride semiconductor layer described above, the source-gate sheet resistance Rsg, the under-gate sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy equation (d) or equation (e) above. This makes it possible to achieve normally-off operation while keeping the on-resistance low. Furthermore, the number of defect levels can be suppressed compared to the case where the gate electrode 60 is in contact with the nitride semiconductor layer via an insulating film. As a result, good high-frequency characteristics and reliability can be obtained.

[0146] In this embodiment, the concentration of the semi-insulating dopant is 1 × 10⁻⁶. １７ cm －３ The above 4.5 x 10 ２１ cm －３ The following is the explanation. This allows for compensation of the 2DEG directly below the gate electrode 60, even if the cap region 54 is thin. As a result, good high-frequency characteristics can be obtained.

[0147] In this embodiment, the concentration of the semi-insulating dopant is 1 × 10⁻⁶. １７ cm －３ The above 4.5 x 10 ２０ cm －３ The following is the explanation: This allows for compensation of the 2DEG directly below the gate electrode 60, even if the cap region 54 is thin. As a result, good high-frequency characteristics can be obtained.

[0148] In this embodiment, the sheet concentration of the semi-insulating dopant is 1 × 10⁻⁶. １２ cm －２ This concludes the explanation. As a result, even if the cap region 54 is thin, the 2DEG directly below the gate electrode 60 can be compensated for. Consequently, good high-frequency characteristics can be obtained.

[0149] In this embodiment, the semi-insulating dopant is C. This allows for compensation of the 2DEG directly below the gate electrode 60, even if the cap region 54 is thin. As a result, good high-frequency characteristics can be obtained.

[0150] In this embodiment, the semi-insulating dopant is Fe or Mn. This allows for compensation of the 2DEG directly below the gate electrode 60, even if the cap region 54 is thin. As a result, good high-frequency characteristics can be obtained.

[0151] In this embodiment, the barrier layer 40 is made of an AlInN-based semiconductor. This allows for a cutoff frequency f of, for example, 20 GHz to 110 GHz. Ｔ This can be achieved. As a result, semiconductor device 3 can be used as a power amplifier or the like in next-generation wireless communication devices.

[0152] In this embodiment, the barrier layer 40 is made of AlGaN. The barrier film thickness t ｂａｒ This results in a cutoff frequency f of, for example, 20 GHz to 110 GHz. Ｔ This can be achieved. As a result, semiconductor device 3 can be used as a power amplifier or the like in next-generation wireless communication devices.

[0153] In this embodiment, the barrier layer 40 is composed of AlInN or AlGaInN. The barrier film thickness t ｂａｒ This is 25 nm or less, or 15 nm. As a result, the cutoff frequency f is, for example, 20 GHz to 110 GHz. Ｔ This can be achieved. As a result, semiconductor device 3 can be used as a power amplifier or the like in next-generation wireless communication devices.

[0154] In this embodiment, the cap region 54 is made of a GaN-based semiconductor. This suppresses oxidation of the barrier layer 40 and damage during the process, contributing to the stability of the device characteristics. Furthermore, gate leakage can be suppressed.

[0155] In this embodiment, the substrate 10 is a Si substrate, and a buffer layer 20 is provided between the substrate 10 and the channel layer 30. By using the buffer layer 20 in this way, an inexpensive substrate (for example, a Si substrate) that does not lattice match with GaN can be used as the substrate 10. As a result, an inexpensive semiconductor device 3 can be provided.

[0156] In this embodiment, the gate electrode 60 is in contact with the cap region 54, and the source electrode 70 and drain electrode 80 are in contact with the undoped cap layer 53. This allows for compensation of the 2DEG directly beneath the gate electrode 60 by thinning the cap region 54. As a result, good high-frequency characteristics can be obtained.

[0157] <6. Application Examples> Semiconductor devices 1, 2, and 3 are applied to a variety of products. Semiconductor devices 1, 2, and 3 are applied to various electrical circuits and various electronic devices, for example. Examples of electronic devices include power devices and high-frequency devices. Specifically, examples include power supply units and wireless communication devices. Power supply units and wireless communication devices include electrical circuits having power amplifiers, high-frequency switches, etc.

[0158] For example, in fifth-generation mobile communications (5G), which uses radio waves in higher frequency bands, the propagation loss of radio waves becomes greater. Therefore, it is desirable for wireless communication devices compatible with 5G to transmit radio waves at higher power. Wireless communication devices to which any of the semiconductor devices 1, 2, or 3 of this disclosure are applied (for example, wireless communication devices 1000 and 2000) can improve device characteristics as described above, making it possible to perform high-power, low-power, and highly reliable wireless communication. In other words, wireless communication device 1000 is more preferably used for fifth-generation mobile communications (5G) and sixth-generation mobile communications (6G).

[0159] Wireless communication devices may be mounted on any of the following mobile devices: automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, and agricultural machinery (tractors). Wireless communication devices may also be mounted on any surgical system, such as an endoscopic surgical system or a microsurgical system. It should be noted that wireless communication devices are merely one example of electronic equipment.

[0160] Wireless communication devices (for example, wireless communication device 1000 and wireless communication device 2000) to which any of the semiconductor devices 1, 2, or 3 of this disclosure are applied will be described with reference to Figures 32 and 33. Figure 32 is a perspective view showing an example configuration of wireless communication device 1000 in Application Example 1. Figure 33 is a block diagram showing an example configuration of wireless communication device 2000 in Application Example 2.

[0161] As shown in Figure 32, the wireless communication device 1000 comprises, for example, a circuit board 1010, a plurality of edge antennas 1020, and a front-end component group 1030. This wireless communication device 1000 is an antenna-integrated module in which the edge antennas 1020 and the front-end component group 1030 are mounted as a single module. Each edge antenna 1020 is formed in an array on the circuit board 1010. The front-end component group 1030 includes a switch 1031, a low-noise amplifier 1032, a bandpass filter 1033, and a power amplifier 1034, etc. The front-end component group 1030 functions as an electrical circuit.

[0162] Such a wireless communication device 1000 can be used, for example, as a communication transceiver. Any of the semiconductor devices 1, 2, and 3 of this disclosure may be applied to transistors that constitute, for example, a switch 1031, a low-noise amplifier 1032, or a power amplifier 1034. This makes it possible to obtain the same effects in the wireless communication device 1000 as in any of the embodiments and modifications described above.

[0163] As shown in Figure 33, the wireless communication device 2000 includes an antenna (ANT) 2010, an antenna switch circuit 2020, a high-power amplifier (HPA) 2030, a high-frequency integrated circuit (RFIC) 2040, a baseband unit 2050, an audio output unit (MIC) 2060, a data output unit (DT) 2070, and an interface unit (I / F) 2080.

[0164] The wireless communication device 2000 is used, for example, as a multi-functional mobile phone system having voice, data communication, and LAN (Local Area Network) connectivity. Any of the semiconductor devices 1, 2, and 3 of this disclosure may be applied to transistors constituting, for example, an antenna switch circuit 2020, a high-power amplifier 2030, a high-frequency integrated circuit 2040, or a baseband section 2050. This makes it possible to obtain the same effects in the wireless communication device 2000 as in any of the above embodiments and their modifications.

[0165] The present disclosure has been described above with reference to embodiments and their modifications, but the present disclosure is not limited to the above embodiments, and various modifications are possible. The effects described herein are merely illustrative. The effects of the present disclosure are not limited to those described herein. The present disclosure may have effects other than those described herein.

[0166] Furthermore, the present disclosure may also take the following configuration: <1> A semiconductor device comprising a substrate, a nitride semiconductor layer including a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in this order from the first surface side of the substrate, and a gate electrode, a source electrode and a drain electrode in contact with the nitride semiconductor layer, wherein the second semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer, the third semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer and less than or equal to the band gap of the second semiconductor layer, and includes a semi-insulating dopant having an acceptor level deeper than Mg, and in the nitride semiconductor layer, the source-gate sheet resistance Rsg, the gate-under sheet resistance Rg and the gate-drain sheet resistance Rgd satisfy the following equation (1) or equation (2). Rsg < Rg ... (1) Rsg < Rgd ... (2) <2> A semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in this order from the first surface side of the substrate; and a gate electrode, a source electrode and a drain electrode in contact with the nitride semiconductor layer, wherein the second semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer; the third semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer and less than or equal to the band gap of the second semiconductor layer, and contains a dopant having an acceptor level deeper than Mg; the total thickness of the second semiconductor layer and the third semiconductor layer satisfies the following equation (1) or equation (2) in terms of source-gate thickness Tsg, gate-under thickness Tg and gate-drain thickness Tgd. Tsg < Tg ... (1) Tsg < Tgd ... (2) <3> The concentration of the semi-insulating dopant is 1 × 10 １７cm －３ The above 4.5 x 10 ２１ cm －３ The semiconductor device described in <1> or <2> below. <4> The concentration of the semi-insulating dopant is 1 × 10 １７ cm －３ The above 4.5 x 10 ２０ cm －３ The semiconductor device described in <1> or <2> below. <5> The sheet concentration of the semi-insulating dopant is 1 × 10 １２ cm －２The semiconductor device described in <1> or <2> above. <6> The semiconductor device described in any one of <1> to <5>, wherein the semi-insulating dopant is C. <7> The semiconductor device described in any one of <1> to <5>, wherein the semi-insulating dopant is Fe or Mn. <8> The semiconductor device described in any one of <1> to <7>, wherein the second semiconductor layer is made of AlGaN, and the total film thickness of the second semiconductor layer and the third semiconductor layer is 35 nm or less. <9> The semiconductor device described in any one of <1> to <7>, wherein the second semiconductor layer is made of AlInN or AlGaInN, and the total film thickness of the second semiconductor layer and the third semiconductor layer is 25 nm or less. <10> The semiconductor device described in any one of <1> to <7>, wherein the second semiconductor layer is made of AlInN or AlGaInN, and the total film thickness of the second semiconductor layer and the third semiconductor layer is 15 nm or less. <11> The semiconductor device according to any one of <1> to <10>, wherein the third semiconductor layer is provided between the gate electrode and the second semiconductor layer, and is not provided in the region between the source electrode and the gate electrode, and in the region between the gate electrode and the drain electrode. <12> The semiconductor device according to any one of <1> to <10>, wherein the third semiconductor layer is provided between the gate electrode and the second semiconductor layer, and is also provided in the region between the gate electrode and the drain electrode, and is not provided in the region between the source electrode and the gate electrode. <13> The semiconductor device according to any one of <1> to <10>, wherein the third semiconductor layer is provided in the region between the drain electrode and the gate electrode, and is not provided in the region between the gate electrode and the second semiconductor layer, and in the region between the source electrode and the gate electrode.<14> The gate electrode, source electrode, and drain electrode are in contact with the third semiconductor layer, and the portion of the third semiconductor layer in contact with the source electrode and the drain electrode is a surface-treated region in which the semi-insulating effect of the semi-insulating dopant is canceled out. The semiconductor device according to any one of <1> to <10>. <15> The gate electrode, source electrode, and drain electrode are in contact with the third semiconductor layer, and the portion of the third semiconductor layer in contact with the source electrode is a surface-treated region in which the semi-insulating effect of the semi-insulating dopant is canceled out. The semiconductor device according to any one of <1> to <10>. <16> The gate electrode, source electrode, and drain electrode are in contact with the third semiconductor layer, and the portion of the third semiconductor layer in contact with the gate electrode and the source electrode is a surface-treated region in which the semi-insulating effect of the semi-insulating dopant is canceled out. The semiconductor device according to any one of <1> to <10>. <17> The semiconductor device according to any one of <1> to <13>, further comprising an insulating film between the gate electrode and the third semiconductor layer. <18> A semiconductor device comprising: a substrate; a nitride semiconductor layer including a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in this order from the first surface side of the substrate; and a gate electrode, a source electrode and a drain electrode in contact with the nitride semiconductor layer, wherein the second semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer; the third semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer and less than or equal to the band gap of the second semiconductor layer, and includes a semi-insulating dopant having an acceptor level deeper than Mg; and in the nitride semiconductor layer, the source-gate sheet resistance Rsg, the gate-under sheet resistance Rg and the gate-drain sheet resistance Rgd satisfy the following equation (1) or equation (2).Rsg < Rg ... (1) Rsg < Rgd ... (2) <19 A semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in this order from the first surface side of the substrate; a gate electrode, a source electrode and a drain electrode in contact with the nitride semiconductor layer; the second semiconductor layer having a band gap greater than or equal to the band gap of the first semiconductor layer; the third semiconductor layer having a band gap greater than or equal to the band gap of the first semiconductor layer and less than or equal to the band gap of the second semiconductor layer, and containing a dopant having an acceptor level deeper than Mg; the total thickness of the second semiconductor layer and the third semiconductor layer is such that the source-gate thickness Tsg, gate-under thickness Tg and gate-drain thickness Tgd satisfy the following equation (1) or equation (2): Tsg < Tg ... (1) Tsg < Tgd ... (2).

[0167] In the semiconductor device relating to the first aspect of this disclosure and the electrical circuit relating to the second aspect of this disclosure, the third semiconductor layer includes a semi-insulating dopant having an acceptor level deeper than Mg. In the nitride semiconductor layer, the source-gate sheet resistance Rsg, the under-gate sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy equation (1) or equation (2) above. This makes it possible to shorten the distance between the gate electrode and the 2DEG region generated in the nitride semiconductor layer compared to the case where the third semiconductor layer includes Mg as a dopant. Furthermore, it is possible to suppress the number of defect levels compared to the case where the gate electrode is in contact with the nitride semiconductor layer via an insulating film. As a result, good high-frequency characteristics and reliability can be obtained.

[0168] In the semiconductor device relating to the third aspect of this disclosure and the electrical circuit relating to the fourth aspect of this disclosure, the third semiconductor layer includes a semi-insulating dopant having an acceptor level deeper than Mg. In the nitride semiconductor layer, the source-gate sheet resistance Rsg, the under-gate sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy equation (1) or equation (2) above. This makes it possible to shorten the distance between the gate electrode and the 2DEG region generated in the nitride semiconductor layer compared to the case where the third semiconductor layer includes Mg as a dopant. Furthermore, it is possible to suppress the number of defect levels compared to the case where the gate electrode is in contact with the nitride semiconductor layer via an insulating film. As a result, good high-frequency characteristics and reliability can be obtained.

[0169] This application claims priority based on Japanese Patent Application No. 2025-007122, filed with the Japan Patent Office on 17 January 2025, and all contents of that application are incorporated herein by reference.

[0170] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer in this order from the first surface side of the substrate; and a gate electrode, a source electrode, and a drain electrode in contact with the nitride semiconductor layer, wherein the second semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer; the third semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer and less than or equal to the band gap of the second semiconductor layer, and includes a semi-insulating dopant having an acceptor level deeper than Mg; and in the nitride semiconductor layer, the source-gate sheet resistance Rsg, the gate-under sheet resistance Rg when the gate voltage is 0V, and the gate-drain sheet resistance Rgd satisfy the following equation (1) or equation (2): Rsg < Rg ... (1) Rsg < Rgd ... (2) 2. A semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer in this order from the first surface side of the substrate; and a gate electrode, a source electrode, and a drain electrode in contact with the nitride semiconductor layer, wherein the second semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer; the third semiconductor layer has a band gap greater than or equal to the band gap of the first semiconductor layer and less than or equal to the band gap of the second semiconductor layer, and contains a dopant having an acceptor level deeper than Mg; and the total thickness of the second and third semiconductor layers satisfies the following equation (1) or equation (2) in terms of source-gate thickness Tsg, gate-under thickness Tg, and gate-drain thickness Tgd: Tsg < Tg ... (1) Tsg < Tgd ... (2) 3. The concentration of the semi-insulating dopant is 1 × 10⁻⁶ １７ cm －３ The above 4.5 x 10 ２１ cm －３ The semiconductor device according to claim 1, as described below.

4. The concentration of the semi-insulating dopant is 1 × 10⁻⁶ １７ cm －３ The above 4.5 x 10 ２１ cm －３ The semiconductor device according to claim 2, as follows:

5. The semiconductor device according to claim 1, wherein the semi-insulating dopant is C.

6. The semiconductor device according to claim 2, wherein the semi-insulating dopant is C.

7. The semiconductor device according to claim 1, wherein the semi-insulating dopant is Fe or Mn.

8. The semiconductor device according to claim 2, wherein the semi-insulating dopant is Fe or Mn.

9. The semiconductor device according to claim 1, wherein the second semiconductor layer is made of AlInN or AlGaInN, and the total thickness of the second semiconductor layer and the third semiconductor layer is 25 nm or less.

10. The semiconductor device according to claim 2, wherein the second semiconductor layer is made of AlInN or AlGaInN, and the total thickness of the second semiconductor layer and the third semiconductor layer is 25 nm or less.

11. The semiconductor device according to claim 1, wherein the second semiconductor layer is made of AlInN or AlGaInN, and the total thickness of the second semiconductor layer and the third semiconductor layer is 15 nm or less.

12. The semiconductor device according to claim 2, wherein the second semiconductor layer is made of AlInN or AlGaInN, and the total thickness of the second semiconductor layer and the third semiconductor layer is 15 nm or less.

13. The semiconductor device according to claim 2, wherein the third semiconductor layer is provided between the gate electrode and the second semiconductor layer, and is not provided in the region between the source electrode and the gate electrode, and in the region between the gate electrode and the drain electrode.

14. The semiconductor device according to claim 2, wherein the third semiconductor layer is provided between the gate electrode and the second semiconductor layer, and also in the region between the gate electrode and the drain electrode, and further not in the region between the source electrode and the gate electrode.

15. The semiconductor device according to claim 2, wherein the third semiconductor layer is provided in the region between the drain electrode and the gate electrode, and is not provided in the region between the gate electrode and the second semiconductor layer, and between the source electrode and the gate electrode.

16. The semiconductor device according to claim 1, wherein, of the third semiconductor layer, the region between the source electrode and the gate electrode, and the region between the gate electrode and the drain electrode are surface-treated regions in which the semi-insulating effect of the semi-insulating dopant is canceled out, and the region between the gate electrode and the second semiconductor layer of the third semiconductor layer is not provided with the surface-treated region.

17. The semiconductor device according to claim 1, wherein the region of the third semiconductor layer between the source electrode and the gate electrode is a surface-treated region in which the semi-insulating effect of the semi-insulating dopant is canceled out, and the region of the third semiconductor layer between the gate electrode and the drain electrode, and between the gate electrode and the second semiconductor layer, are not provided with the surface-treated region.

18. The semiconductor device according to claim 1, wherein the region of the third semiconductor layer between the source electrode and the gate electrode, and the region between the gate electrode and the second semiconductor layer, are surface-treated regions in which the semi-insulating effect of the semi-insulating dopant is canceled out, and the region of the third semiconductor layer between the gate electrode and the drain electrode is not provided with the surface-treated region.

19. The semiconductor device according to claim 1, further comprising an insulating film between the gate electrode and the third semiconductor layer.

20. The semiconductor device according to claim 2, further comprising an insulating film between the gate electrode and the third semiconductor layer.

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