Power conversion device

Abstract

This power conversion device comprises: a plurality of upper arm semiconductor elements arranged along a first direction; a plurality of lower arm semiconductor elements provided at a predetermined distance from the plurality of upper arm semiconductor elements in a second direction orthogonal to the first direction and arranged along the first direction; and a printed wiring board having positive electrode wiring to which drain electrodes of the plurality of upper arm semiconductor elements are electrically connected, negative electrode wiring to which source electrodes of the plurality of lower arm semiconductor elements are electrically connected, and AC wiring to which source electrodes of the plurality of upper arm semiconductor elements and drain electrodes of the plurality of lower arm semiconductor elements are electrically connected. The AC wiring extends from a first region to which source electrodes of the plurality of upper arm semiconductor elements are connected to a second region to which drain electrodes of the plurality of lower arm semiconductor elements are connected in a state in which the width in the first direction is larger than the width of an arrangement region of the plurality of upper arm semiconductor elements when projected from the normal direction of the printed wiring board, and a laminated wiring part in which the positive electrode wiring and the negative electrode wiring are laminated is arranged so as to overlap the AC wiring extending between the first region and the second region when projected from the normal direction of the printed wiring board.

Description

Power conversion device

[0001] The present invention relates to a power conversion device.

[0002] In Patent Document 1 below, a technique is disclosed in which a plurality of semiconductor chips are cooled on both sides to improve the cooling efficiency, and the parasitic inductance of the wiring is reduced to reduce overvoltage and loss, thereby improving the on-capacitance.

[0003] Japanese Patent Application Laid-Open No. 2002-095267

[0004] In view of the technique described in Patent Document 1, an object of the present invention is to provide a power conversion device that equalizes the source inductance between semiconductor packages mounted in multiple parallel on a printed wiring board, realizes suppression of current imbalance, and reduces switching loss to realize reduction of the main circuit inductance.

[0005] A printed wiring board having a plurality of upper arm semiconductor elements arranged along a first direction, a plurality of lower arm semiconductor elements provided at a predetermined distance from the plurality of upper arm semiconductor elements in a second direction orthogonal to the first direction and arranged along the first direction, a positive electrode wiring to which the drain electrodes of the plurality of upper arm semiconductor elements are electrically connected, a negative electrode wiring to which the source electrodes of the plurality of lower arm semiconductor elements are electrically connected, and an alternating current wiring to which the source electrodes of the plurality of upper arm semiconductor elements and the drain electrodes of the plurality of lower arm semiconductor elements are electrically connected, wherein the alternating current wiring has a width in the first direction larger than the width of the arrangement region of the plurality of upper arm semiconductor elements when projected from the normal direction of the printed wiring board, and extends from a first region to which the source electrodes of the plurality of upper arm semiconductor elements are connected to a second region to which the drain electrodes of the plurality of lower arm semiconductor elements are connected, and the laminated wiring portion formed by laminating the positive electrode wiring and the negative electrode wiring is arranged so as to overlap the alternating current wiring extending between the first region and the second region when projected from the normal direction of the printed wiring board.

[0006] A power conversion device capable of achieving both suppression of current imbalance and reduction of the main circuit inductance can be provided.

[0007] Plan view and cross-sectional view illustrating the overall configuration of a semiconductor package. Plan view illustrating the configuration of a semiconductor package. Plan view of the first layer of a substrate illustrating the mounting of a power converter on a substrate according to one embodiment of the present invention. Plan view of the second to fourth layers of a substrate illustrating the mounting of a power converter on a substrate according to one embodiment of the present invention. Cross-sectional view C-C of the power converter in Figure 3 according to one embodiment of the present invention. Cross-sectional view D-D of the power converter in Figure 3 according to one embodiment of the present invention. Power conversion circuit diagram according to one embodiment of the present invention. Plan view of the first and second layers of a substrate illustrating the mounting of a power converter on a substrate according to a modified example of the present invention. Plan view of the third to sixth layers of a substrate illustrating the mounting of a power converter on a substrate according to a modified example of the present invention. Cross-sectional view E-E of Figure 7 according to a modified example of the present invention. Cross-sectional view F-F of Figure 7 according to a modified example of the present invention.

[0008] Embodiments of the present invention will be described below with reference to the drawings. The following description and drawings are illustrative for illustrating the present invention, and have been omitted and simplified as appropriate for clarity of explanation. The present invention can also be carried out in various other forms. Unless otherwise specified, each component may be singular or plural.

[0009] The positions, sizes, shapes, and ranges of the components shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0010] (An Embodiment and Overall Configuration) (Figure 1) Figure 1(a) is a plan view of a semiconductor package 10 mounted on a power converter 50 according to one embodiment of the present invention, and Figure 1(b) is a cross-sectional view taken along line A-A in Figure 1(a). The semiconductor package 10 has a drain conductor 3, a source conductor 4, a drain terminal 11, a gate signal terminal 12, a source signal terminal 13, and a semiconductor element 20. The semiconductor element 20 is connected to the drain conductor 3 via solder 2 on one side and to the source conductor 4 via solder 2 on the other side. The semiconductor element 20 is electrically connected to the gate signal terminal 12 and the source signal terminal 13 by bonding wires 5. The drain conductor 3 has a drain terminal 11. Each of the aforementioned electrical components constituting the semiconductor package 10 is resin-sealed by a molding resin 6, but the surface of the drain conductor 3 facing the surface that connects to the semiconductor element 20, the surface of the source conductor 4 facing the surface that connects to the semiconductor element 20, and parts of the drain terminal 11, gate signal terminal 12, and source signal terminal 13 are exposed from the molding resin 6.

[0011] (Figure 2) Figure 2(a) is a plan view taken from direction B in Figure 1(b), Figure 2(b) is Figure 2(a) with the mold resin 6 removed, and Figure 2(c) is Figure 2(b) with the source conductor 4 removed. As shown in Figure 2(c), the semiconductor element 20 has a source electrode 21 on the surface connected to the source conductor 4, and a drain electrode (not shown) on the surface connected to the drain conductor 3. The semiconductor element 20 also has a gate signal electrode 23 that is electrically connected to the gate signal terminal 12 by a bonding wire 5, and a source signal electrode 24 that is electrically connected to the source signal terminal 13 by a bonding wire 5.

[0012] (Figure 3) Figure 3(a) is a plan view of the first layer of the substrate of the power converter 50, and Figure 3(b) is a view of Figure 3(a) with the upper arm semiconductor package 10H and lower arm semiconductor package 10L removed. In the following description, the vertical direction of the drawing will be referred to as the first direction, and the left-right direction of the drawing, which is perpendicular to the first direction, will be referred to as the second direction. The power converter 50 has its electrical components mounted on a wiring board 30. Specifically, the first layer of the wiring board 30 has positive electrode wiring 31, AC wiring 32, negative electrode wiring 33, upper arm side gate signal wiring pattern 36H, and lower arm side gate signal wiring pattern 36L mounted on it. Two upper arm semiconductor packages 10H, each having multiple upper arm semiconductor elements, are mounted on the output wiring 32, aligned along the first direction. Two lower arm semiconductor packages 10L, each having multiple lower arm semiconductor elements, are mounted on the negative electrode wiring 33, aligned along the first direction. The upper arm semiconductor package 10H and the lower arm semiconductor package 10L are provided on the printed circuit board 30 at a predetermined distance from each other in the second direction.

[0013] The positive electrode wiring 31 electrically connects the drain electrodes of the upper arm semiconductor elements in multiple upper arm semiconductor packages 10H. The negative electrode wiring 33 electrically connects the source electrodes of the lower arm semiconductor elements in multiple lower arm semiconductor packages 10L. The AC wiring 32 electrically connects the source electrodes of multiple upper arm semiconductor elements and the drain electrodes of multiple lower arm semiconductor elements.

[0014] The wiring board 30 has through-hole vias 42H connected to the source signal of the upper arm gate drive circuit and through-hole vias 42L connected to the source signal of the lower arm gate drive circuit. The wiring board 30 also has high-potential through-hole vias 35 connected to a capacitor (not shown). The positive electrode wiring 31 has low-potential through-hole vias 34 connected to a capacitor. The AC wiring 32 has through-hole vias 38 and through-holes 39 connected to the AC output. The upper arm gate signal wiring pattern 36H has through-hole vias 41H connected to the gate signal of the upper arm gate drive circuit. The lower arm gate signal wiring pattern 36L has through-hole vias 41L connected to the gate signal of the lower arm gate drive circuit.

[0015] Through-hole vias 34, 35, 41H, 42H, 41L, 42L, and 39 penetrate through the first to fourth layers of the wiring board 30, electrically connecting each layer to the others.

[0016] The region to which the source electrodes of multiple upper-arm semiconductor packages 10H, each having multiple upper-arm semiconductor elements, are connected is defined as the first region 30a, and the region to which the drain electrodes of multiple lower-arm semiconductor packages 10L, each having multiple lower-arm semiconductor elements, are connected is defined as the second region 30b. The AC wiring 32 extends from the first region 30a to the second region 30b, such that when projected from the normal direction of the printed circuit board 30 (viewed in a plane), its width in the first direction on the printed circuit board 30 is greater than the width of the arrangement area of ​​the multiple upper-arm semiconductor packages 10H.

[0017] (Figure 4) Figure 4(a) is a plan view of the second layer of the substrate of the power converter 50, Figure 4(b) is a plan view of the third layer of the substrate of the power converter 50, and Figure 4(c) is a plan view of the fourth layer of the substrate of the power converter 50. The second layer of the wiring board 30 has AC wiring 32, negative electrode wiring 33, upper arm side source signal wiring pattern 37H, and lower arm side source signal wiring pattern 37L mounted on it. Through-hole vias 42H are formed in the upper arm side source signal wiring pattern 37H, and through-hole vias 42L are formed in the lower arm side source signal wiring pattern 37L.

[0018] As shown in Figure 4(a), in the second layer of the wiring board 30, a notch 61 is formed in a part of the area where the negative electrode wiring 33 is mounted. AC wiring 32 is formed in the notch 61, and through-hole vias 38 that penetrate in the substrate thickness direction are provided in the AC wiring 32. The notch 61 is formed extending along the arrangement direction of the lower arm semiconductor element between the laminated wiring section (described later) and the second region 30b (see Figure 3(b)). The notch 61 is also formed extending along the second direction to separate the mounting area of ​​the negative electrode wiring 33. As a result, the current flowing from the through-hole vias 38 of the negative electrode wiring 33 in the second and third layers of the printed circuit board 30 towards the capacitor becomes a bypass current path.

[0019] The third layer of the wiring board 30 shown in Figure 4(b) differs from the second layer of the board in that the upper arm side source signal wiring pattern 37H and the lower arm side source signal wiring pattern 37L are not mounted, but the other mounting is the same as the second layer of the board. In the fourth layer of the wiring board 30 shown in Figure 4(b), the notch 61 is not formed in the area where the negative electrode wiring 33 is mounted.

[0020] The wiring board 30 has the configuration shown in Figures 4(a) and 4(b), and the current path of the negative electrode wiring 33 is narrowed by the notch 61, which allows for a more circuitous current path than when the notch 61 is not provided. As a result, the current path of the negative electrode wiring 33 passes between the lower arm semiconductor packages 10L, reducing and equalizing the source inductance difference between the lower arm semiconductor packages 10L, and further equalizing the length of the current path to the capacitor (not shown), thereby suppressing current imbalance. In addition, by providing the through-hole vias 38 formed in the AC wiring 32 together in the notch 61, there is no need to avoid forming the through-hole vias 38 that conduct the AC wiring 32 and the wiring layer that is at a different potential from each other, and the mounting area for the negative electrode wiring 33 can be secured. Furthermore, securing the mounting area for the negative electrode wiring 33 reduces the wiring resistance, which contributes to reducing inductance.

[0021] Regarding the notches 61, they are formed symmetrically on both sides with respect to the negative electrode wiring 33 as the layout. However, for example, the notch 61 formed on the lower side of Figure 4(a) does not affect the bypass of the current in the negative electrode wiring 33 and therefore does not need to be formed.

[0022] (Figures 5 and 6) In the power converter 50, the upper arm semiconductor package 10H and the lower arm semiconductor package 10L are mounted on the printed circuit board 30 by being connected to the printed circuit board 30 via solder 2. In the printed circuit board 30, a laminated wiring section 25 is formed between the first region 30a and the second region 30b, in which positive electrode wiring 31, negative electrode wiring 33, and output wiring 32 are stacked on top of each other. In the first region 30a, the AC wiring 32 is electrically connected in the substrate thickness direction from the first to the fourth layer via through-hole vias 38. In the second region 30b, the negative electrode wiring 33 is electrically connected in the substrate thickness direction from the first to the fourth layer via through-hole vias 38.

[0023] The laminated wiring section 25, formed by stacking the positive electrode wiring 31 and the negative electrode wiring 33, is positioned so as to overlap the AC wiring 32 extending from the first region 30a to the second region 30b when projected from the normal direction of the printed circuit board 30. In this way, the negative electrode wiring 33 on the lower arm side, formed in the second and third layers of the printed circuit board 30, has current flowing in opposite directions to the positive electrode wiring 31. This increases magnetic coupling and cancels out the inductance, thus reducing the inductance. Furthermore, when current flows through the negative electrode wiring 33, the eddy currents generated in the AC wiring 32 flow in a direction that cancels out the current in the negative electrode wiring 33, thus reducing the main circuit inductance.

[0024] (Figure 7) The power conversion circuit of the power converter 50 having the configuration shown in Figures 1 to 6 will be described. The power converter 50 is electrically connected via a smoothing capacitor 80 and through-hole vias 34 and 35. The two upper arm semiconductor packages 10H are electrically connected in series with each other. The two lower arm semiconductor packages 10L are also electrically connected in series with each other. One of the upper arm semiconductor packages 10H is connected to the positive electrode wiring 31 and the other is connected to the AC wiring 32. One of the lower arm semiconductor packages 10L is connected to the AC wiring 32 and the other is connected to the negative electrode wiring 33.

[0025] The upper arm semiconductor package 10H is connected to the upper arm side gate signal wiring pattern 36H and the upper arm side source signal wiring pattern 37H. The upper arm side gate signal wiring pattern 36H and the upper arm side source signal wiring pattern 37H are connected to the gate drive circuit 70 via through-hole vias 41H and 41L.

[0026] The lower arm semiconductor package 10L is connected to the lower arm side gate signal wiring pattern 36L and the lower arm side source signal wiring pattern 37L. The lower arm side gate signal wiring pattern 36L and the lower arm side source signal wiring pattern 37L are connected to the gate drive circuit 70 via through-hole vias 42H and 42L.

[0027] As shown in the figure, the negative electrode wiring 33 has a parasitic inductance 60 on the lower arm source side, but the inductance 60 can be reduced by the configuration of the embodiment of the present invention described above.

[0028] (Modified Version) (Figures 8-11) Figure 8(a) is a plan view of the first layer of the substrate of the modified power converter 50, Figure 8(b) is Figure 3(a) with the upper arm semiconductor package 10H and lower arm semiconductor package 10L removed, and Figure 8(c) is a plan view of the second layer of the substrate of the modified power converter 50. Also, Figure 9(a) is a plan view of the third layer of the substrate of the modified power converter 50, Figure 9(b) is a plan view of the fourth and fifth layers of the substrate of the modified power converter 50, and Figure 9(c) is a plan view of the sixth layer of the substrate of the modified power converter 50. Note that the same configuration as in Figures 3-6 will not be explained below.

[0029] In a modified version of the present invention, an insulating layer 90 is formed between the third layer and the bottom layer of the printed circuit board 30. In other words, the printed circuit board 30 has a six-layer structure, with two layers of insulating layer 90 between the third layer and the bottom layer, making the insulating layer 90 the fourth and fifth layers. In the laminated wiring section 25 of the printed circuit board 30, an insulating layer 90 is provided between the negative electrode wiring 33 and the AC wiring 32, and a floating potential conductor layer 91 that is not electrically connected to the power conversion circuit is provided on the surface of the insulating layer 90. The floating potential conductor layer 91 forms a capacitive circuit that divides the voltage between the wiring layer that becomes AC potential and the wiring layer that becomes negative electrode wiring 33 in the power conversion circuit. Through-hole vias 38 of the AC wiring 32 formed in the notch 61 pass through the floating potential conductor layer 91. This improves partial discharge resistance even when the insulating layer 90 is thin. The insulating layer 90 may be an insulating substrate.

[0030] Furthermore, the number of through-hole vias 38 of the output wiring 32 provided in the notch 61 shown in Figures 8 to 11 is greater than the number of through-hole vias 38 of the output wiring 32 provided in the notch 61 shown in Figures 3 to 6, which further contributes to reducing inductance. However, the number of through-hole vias 38 of the output wiring 32 provided in the notch 61 shown in Figures 8 to 11 may be the same as the number of through-hole vias 38 shown in Figures 3 to 6.

[0031] According to the embodiments of the present invention described above, the following effects and advantages are achieved.

[0032] (1) A printed circuit board 30 having a plurality of upper arm semiconductor elements arranged along a first direction, a plurality of lower arm semiconductor elements arranged along the first direction in a second direction perpendicular to the first direction, provided at a predetermined distance from the plurality of upper arm semiconductor elements, a positive electrode wiring 31 to which the drain electrodes of the plurality of upper arm semiconductor elements are electrically connected, a negative electrode wiring 33 to which the source electrodes of the plurality of lower arm semiconductor elements are electrically connected, and an AC wiring 32 to which the source electrodes of the plurality of upper arm semiconductor elements and the drain electrodes of the plurality of lower arm semiconductor elements are electrically connected. The AC wiring 32 extends from a first region 30a, to which the source electrodes of the multiple upper arm semiconductor elements are connected, to a second region 30b, to which the drain electrodes of the multiple lower arm semiconductor elements are connected, with a width in the first direction greater than the width of the arrangement area of ​​the multiple upper arm semiconductor elements when projected from the normal direction of the printed circuit board 30. The stacked wiring section 25, which stacks the positive electrode wiring 31 and the negative electrode wiring 33, is positioned so as to overlap with the AC wiring 32 extending between the first region 30a and the second region 30b when projected from the normal direction of the printed circuit board 30. This makes it possible to provide a power conversion device 50 that achieves both suppression of current imbalance and reduction of main circuit inductance.

[0033] (2) The negative electrode wiring 33 has a notch 61 that extends along the arrangement direction of the lower arm semiconductor element between the laminated wiring section 25 and the second region 30b. This contributes to suppressing current imbalance.

[0034] (3) The notch 61 is provided with through-hole vias 38 formed in the AC wiring 32 and penetrating in the direction of the substrate thickness. This reduces wiring resistance and contributes to reducing inductance.

[0035] (4) In the laminated wiring section 25, an insulating layer 90 is provided between the negative electrode wiring 33 and the AC wiring 32, and a floating potential conductor layer 91 that is not electrically connected to the power conversion circuit is provided on the surface of the insulating layer 90, and the floating potential conductor layer 91 forms a capacitive circuit that divides the voltage between the wiring layer that becomes AC potential and the wiring layer that becomes the negative electrode wiring 33 in the power conversion circuit. This improves the partial discharge resistance.

[0036] It should be noted that the present invention is not limited to the embodiments described above, and various modifications and combinations of other configurations can be made without departing from the spirit of the invention. Furthermore, the present invention is not limited to having all the configurations described in the embodiments described above, and may also include configurations in which some of those configurations are omitted.

[0037] 2 Solder 3 Drain conductor 4 Source conductor 5 Bonding wire 6 Molding resin 10 Semiconductor package 10H Upper arm semiconductor package 10L Lower arm semiconductor package 11 Drain terminal 12 Gate signal terminal 13 Source signal terminal 20 Semiconductor element 21 Source electrode 23 Gate signal electrode 24 Source signal electrode 25 Stacked wiring section 30 Printed circuit board 30a First region 30b Second region 31 Positive electrode wiring 32 AC wiring 33 Negative electrode wiring 34 Low-potential through-hole via for capacitor connection 35 High-potential through-hole via for capacitor connection 36H Upper arm gate signal wiring pattern 36L Lower arm gate signal wiring pattern 37H Upper arm source signal wiring pattern 37L Lower arm source signal wiring pattern 38 Through-hole via 39 Through-hole for AC output connection 41H Through-hole via 41L Through-hole via 42H Through-hole via 42L Through-hole via 50 Power converter 60 Parasitic inductance on the lower arm source side 61 Notch 70 Gate drive circuit 80 Smoothing capacitor 90 Insulating layer 91 Floating potential conductor layer 91a Capacitive circuit

Claims

1. A printed circuit board comprising: a plurality of upper arm semiconductor elements arranged along a first direction; a plurality of lower arm semiconductor elements arranged along the first direction, provided at a predetermined distance from the plurality of upper arm semiconductor elements in a second direction perpendicular to the first direction; positive electrode wiring to which the drain electrodes of the plurality of upper arm semiconductor elements are electrically connected; negative electrode wiring to which the source electrodes of the plurality of lower arm semiconductor elements are electrically connected; and AC wiring to which the source electrodes of the plurality of upper arm semiconductor elements and the drain electrodes of the plurality of lower arm semiconductor elements are electrically connected, wherein, when projected from the normal direction of the printed circuit board, the width in the first direction is greater than the width of the arrangement area of ​​the plurality of upper arm semiconductor elements, and the AC wiring extends from a first region to which the source electrodes of the plurality of upper arm semiconductor elements are connected to a second region to which the drain electrodes of the plurality of lower arm semiconductor elements are connected. A power conversion device in which the laminated wiring section, formed by stacking the positive electrode wiring and the negative electrode wiring, is arranged to overlap the AC wiring extending between the first region and the second region when projected from the normal direction of the printed circuit board.

2. A power conversion device according to claim 1, wherein the negative electrode wiring has a notch formed between the laminated wiring portion and the second region, extending along the arrangement direction of the lower arm semiconductor element.

3. A power conversion device according to claim 2, wherein the notch portion is provided with through-hole vias formed in the AC wiring and penetrating in the direction of the substrate thickness.

4. A power conversion device according to claim 3, wherein in the laminated wiring section, an insulating layer is provided between the negative electrode wiring and the AC wiring, a floating potential conductor layer that is not electrically connected to the power conversion circuit is provided on the surface of the insulating layer, and the floating potential conductor layer forms a capacitive circuit that divides the voltage between the wiring layer that becomes AC potential and the wiring layer that becomes negative electrode wiring in the power conversion circuit.

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