Power conversion device

Abstract

The present invention addresses the problem of achieving size reduction while reducing ripple current. A power conversion device (100) comprises a positive electrode input terminal (11), a negative electrode input terminal (12), a first capacitor (C1), a plurality of DC-DC converters (9), a plurality of output terminals (13), a plurality of second capacitors (C2), a third capacitor (C3), and a control device (10). The plurality of output terminals (13) are connected to corresponding DC-DC converters (9) from among the plurality of DC-DC converters (9). Each of the plurality of second capacitors (C2) has a first end and a second end. The first end of each of the plurality of second capacitors (C2) is connected to a corresponding output terminal (13) from among the plurality of output terminals (13). The third capacitor (C3) is connected between the second ends of the plurality of second capacitors (C2) and the negative electrode input terminal (12).

Description

Power converter

[0001] This disclosure relates to a power conversion device, and more particularly to a power conversion device comprising a plurality of switching elements.

[0002] Patent Document 1 discloses a three-phase DC / AC converter. The three-phase DC / AC converter disclosed in Patent Document 1 comprises three input-side bridge circuits, three output-side bridge circuits, three inductors, one filter capacitor, and three smoothing capacitors. The one filter capacitor is connected between the positive input voltage rail and the negative input voltage rail and is connected in parallel to the three input-side bridge circuits. Each of the three input-side bridge circuits has a high-side power transistor and a low-side power transistor. Each of the three output-side bridge circuits has a high-side power transistor and a low-side power transistor. The three smoothing capacitors are connected between the three output phase terminals and the reference voltage rail.

[0003] In the three-phase DC / AC converter disclosed in Patent Document 1, the three smoothing capacitors are large, making miniaturization difficult in some cases.

[0004] International Publication No. 2019 / 057771

[0005] The purpose of this disclosure is to provide a power conversion device that can be miniaturized while reducing ripple current.

[0006] A power converter according to one embodiment of the present disclosure comprises a positive input terminal, a negative input terminal, a first capacitor, a plurality of DC-DC converters, a plurality of output terminals, a plurality of second capacitors, a third capacitor, and a control device. The first capacitor is connected between the positive input terminal and the negative input terminal. The plurality of DC-DC converters are connected between the positive input terminal and the negative input terminal. The plurality of output terminals correspond one-to-one with the plurality of DC-DC converters. The plurality of output terminals are connected to the corresponding DC-DC converters among the plurality of DC-DC converters. The plurality of second capacitors correspond one-to-one with the plurality of output terminals. The plurality of second capacitors are connected to the corresponding output terminals among the plurality of output terminals. The third capacitor is connected in series with the plurality of second capacitors. The control device controls the plurality of DC-DC converters. Each of the plurality of DC-DC converters has a first half-bridge circuit, a second half-bridge circuit, and an inductor. The first half-bridge circuit is connected between the positive input terminal and the negative input terminal. The first half-bridge circuit has a first switching element and a second switching element connected in series with each other. The second half-bridge circuit is connected between a corresponding output terminal among the plurality of output terminals and the negative input terminal. The second half-bridge circuit has a third switching element and a fourth switching element connected in series with each other. The inductor is connected between the connection point between the first switching element and the second switching element and the connection point between the third switching element and the fourth switching element. Each of the plurality of second capacitors has a first end and a second end. The first end of each of the plurality of second capacitors is connected to a corresponding output terminal among the plurality of output terminals. The third capacitor is connected between the second end of the plurality of second capacitors and the negative input terminal.

[0007] Figure 1 is a circuit diagram of a power converter according to Embodiment 1. Figure 2 is an explanatory diagram of the operation of the same power converter. Figure 3 is a circuit diagram of a power converter according to a comparative example. Figure 4 is an explanatory diagram of the operation of the same power converter. Figure 5 is a circuit diagram of a power converter according to Embodiment 2. Figure 6 is an explanatory diagram of the operation of the same power converter. Figure 7 is an explanatory diagram of another operation of the same power converter. Figure 8 is an equivalent circuit diagram of the main part of the same power converter. Figure 9 is an explanatory diagram of the response characteristics of the same power converter and the power converter of the comparative example. Figure 10 is an explanatory diagram of the operation of a power converter according to Embodiment 2. Figure 11 is a circuit diagram of a power converter according to Embodiment 3. Figure 12 is a circuit diagram illustrating a voltage detection circuit for the same power converter. Figure 13 is a flowchart for explaining the operation of the control device in the same power converter. Figure 14 is a circuit diagram of a power converter according to Embodiment 4.

[0008] (Embodiment 1) Below, a power conversion device 100 according to Embodiment 1 will be described with reference to Figure 1.

[0009] (1) Configuration of the power converter As shown in Figure 1, the power converter 100 includes a positive input terminal 11, a negative input terminal 12, a first capacitor C1, a plurality of (three in the example of Figure 1) DC-DC converters 9, a plurality of (three in the example of Figure 1) output terminals 13, a plurality of (three in the example of Figure 1) second capacitors C2, a third capacitor C3, and a control device 10. The first capacitor C1 is connected between the positive input terminal 11 and the negative input terminal 12. The plurality of DC-DC converters 9 are connected between the positive input terminal 11 and the negative input terminal 12. The plurality of output terminals 13 correspond one-to-one with the plurality of DC-DC converters 9. The plurality of output terminals 13 are connected to the corresponding DC-DC converter 9 among the plurality of DC-DC converters 9. The plurality of second capacitors C2 correspond one-to-one with the plurality of output terminals 13. The plurality of second capacitors C2 are connected to the corresponding output terminals 13 among the plurality of output terminals 13. The third capacitor C3 is connected in series with multiple second capacitors C2. The control device 10 controls multiple DC-DC converters 9.

[0010] (2) Details of the power converter The power converter 100 according to Embodiment 1 is a three-phase inverter that converts DC to three-phase AC.

[0011] In the power converter 100, a DC power supply E1 is connected between the positive input terminal 11 and the negative input terminal 12, and AC loads 15 are connected to the three output terminals 13. The AC loads 15 are, for example, three-phase servo motors.

[0012] The positive input terminal 11, the negative input terminal 12, and the three output terminals 13 do not necessarily have to be physical components (terminals); for example, they may be part of a conductive portion included in the circuit board of the power converter 100.

[0013] As shown in Figure 1, for example, the power converter 100 has the high-potential output terminal (positive terminal) of the DC power supply E1 connected to the positive input terminal 11, and the low-potential output terminal (negative terminal) of the DC power supply E1 connected to the negative input terminal 12. The output voltage of the DC power supply E1 is, for example, 48V. The output voltage of the DC power supply E1 is not limited to 48V; for example, it may be 12V, 24V, or 141V obtained by inputting an AC voltage of 100V to a diode bridge. Note that the DC power supply E1 and the AC load 15 are not components of the power converter 100, but they may be components of the power converter 100.

[0014] In this embodiment, each of the multiple DC-DC converters 9 is a bidirectional DC-DC converter. A bidirectional DC-DC converter is a buck-boost converter capable of boosting and bucking voltage in both directions.

[0015] In the following, with respect to the multiple DC-DC converters 9, the DC-DC converter 9 corresponding to the U phase will be referred to as DC-DC converter 9u, the DC-DC converter 9 corresponding to the V phase will be referred to as DC-DC converter 9v, and the DC-DC converter 9 corresponding to the W phase will be referred to as DC-DC converter 9w. Also, in the following, with respect to the multiple output terminals 13, the output terminal 13 connected to the U phase terminal of the AC load 15 will be referred to as U phase output terminal 13u, the V phase output terminal 13 connected to the V phase terminal of the AC load 15 will be referred to as output terminal 13v, and the output terminal 13 connected to the W phase terminal of the AC load 15 will be referred to as W phase output terminal 13w.

[0016] Each of the multiple DC-DC converters 9 includes a first half-bridge circuit 21, a second half-bridge circuit 22, and an inductor L1. The first half-bridge circuit 21 is connected between the positive input terminal 11 and the negative input terminal 12. The first half-bridge circuit 21 has a first switching element 1 and a second switching element 2 connected in series with each other. The second half-bridge circuit 22 is connected between a corresponding output terminal 13 from among the multiple output terminals 13 and the negative input terminal 12. The second half-bridge circuit 22 has a third switching element 3 and a fourth switching element 4 connected in series with each other. The inductor L1 is connected between the connection point N1 between the first switching element 1 and the second switching element 2 and the connection point N2 between the third switching element 3 and the fourth switching element 4. The first connection point N1 is not limited to the connection point where the first switching element 1 and the second switching element 2 are directly connected, but may be, for example, a node in the wiring section between the first switching element 1 and the second switching element 2. The second connection point N2 is not limited to a connection point where the third switching element 3 and the fourth switching element 4 are directly connected, but may also be, for example, a node in the wiring section between the third switching element 3 and the fourth switching element 4.

[0017] In this embodiment, the inductances of the multiple (three in Figure 1) inductors L1 are the same. That is, the inductances of the three inductors L1 are the same. "The inductances of the three inductors L1 are the same" means not only that the inductance of two of the three inductors L1 is 100% of the inductance of the remaining inductor L1, but also that the inductance of the two inductors L1 is within the range of 80% to 120% of the inductance of the remaining inductor L1.

[0018] Each of the multiple first switching elements 1, multiple second switching elements 2, multiple third switching elements 3, and multiple fourth switching elements 4 has a control terminal, a first main terminal, and a second main terminal. The multiple first switching elements 1, multiple second switching elements 2, multiple third switching elements 3, and multiple fourth switching elements 4 are controlled by a control device 10. In this embodiment, each of the multiple first switching elements 1, multiple second switching elements 2, multiple third switching elements 3, and multiple fourth switching elements 4 is, for example, a normally-off n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Therefore, the control terminal, first main terminal, and second main terminal of each of the multiple first switching elements 1, multiple second switching elements 2, multiple third switching elements 3, and multiple fourth switching elements 4 are the gate terminal, drain terminal, and source terminal, respectively.

[0019] In each of the multiple first half-bridge circuits 21, the first main terminal of the first switching element 1 is connected to the positive input terminal 11, the second main terminal of the first switching element 1 is connected to the first main terminal of the second switching element 2, and the second main terminal of the second switching element 2 is connected to the negative input terminal 12. In each of the multiple first half-bridge circuits 21, the first switching element 1 is a high-side switching element (P-side switching element), and the second switching element 2 is a low-side switching element (N-side switching element).

[0020] Each of the multiple first half-bridge circuits 21 has a first diode 5 and a second diode 6. In each of the multiple first half-bridge circuits 21, the first diode 5 is connected in antiparallel to the first switching element 1. In each of the multiple first half-bridge circuits 21, the anode of the first diode 5 is connected to the second main terminal (source terminal) of the first switching element 1, and the cathode of the first diode 5 is connected to the first main terminal (drain terminal) of the first switching element 1. In each of the multiple first half-bridge circuits 21, the second diode 6 is connected in antiparallel to the second switching element 2. In each of the multiple first half-bridge circuits 21, the anode of the second diode 6 is connected to the second main terminal of the second switching element 2, and the cathode of the second diode 6 is connected to the first main terminal of the second switching element 2. In each of the multiple first half-bridge circuits 21, the first diode 5 and the second diode 6 are parasitic diodes of the n-channel MOSFETs that constitute the first switching element 1 and the second switching element 2, respectively, but they are not limited to parasitic diodes and may be external diodes.

[0021] In each of the multiple second half-bridge circuits 22, the first main terminal of the third switching element 3 is connected to the output terminal 13, the second main terminal of the third switching element 3 is connected to the first main terminal of the fourth switching element 4, and the second main terminal of the fourth switching element 4 is connected to the negative input terminal 12. In each of the multiple second half-bridge circuits 22, the third switching element 3 is a high-side switching element, and the fourth switching element 4 is a low-side switching element.

[0022] For the sake of explanation, the first switching element 1, second switching element 2, third switching element 3, and fourth switching element 4 of the DC-DC converter 9u may be referred to as the first switching element 1u, second switching element 2u, third switching element 3u, and fourth switching element 4u, respectively. Similarly, the first switching element 1, second switching element 2, third switching element 3, and fourth switching element 4 of the DC-DC converter 9v may be referred to as the first switching element 1v, second switching element 2v, third switching element 3v, and fourth switching element 4v, respectively. Furthermore, the first switching element 1, second switching element 2, third switching element 3, and fourth switching element 4 of the DC-DC converter 9w may be referred to as the first switching element 1w, second switching element 2w, third switching element 3w, and fourth switching element 4w, respectively.

[0023] In the power converter 100, the first main terminal of the third switching element 3u is connected to the U-phase output terminal 13u, the first main terminal of the third switching element 3v is connected to the V-phase output terminal 13v, and the first main terminal of the third switching element 3w is connected to the W-phase output terminal 13w.

[0024] Each of the multiple second half-bridge circuits 22 has a third diode 7 and a fourth diode 8. In each of the multiple second half-bridge circuits 22, the third diode 7 is connected in antiparallel to the third switching element 3. In each of the multiple second half-bridge circuits 22, the anode of the third diode 7 is connected to the second main terminal (source terminal) of the third switching element 3, and the cathode of the third diode 7 is connected to the first main terminal (drain terminal) of the third switching element 3. In each of the multiple second half-bridge circuits 22, the fourth diode 8 is connected in antiparallel to the fourth switching element 4. In each of the multiple second half-bridge circuits 22, the anode of the fourth diode 8 is connected to the second main terminal of the fourth switching element 4, and the cathode of the fourth diode 8 is connected to the first main terminal of the fourth switching element 4. In each of the multiple second half-bridge circuits 22, the third diode 7 and the fourth diode 8 are parasitic diodes of the n-channel MOSFETs that constitute the third switching element 3 and the fourth switching element 4, respectively. However, they are not limited to parasitic diodes and may be external diodes.

[0025] The power converter 100 comprises a plurality (three) first drivers (not shown), a plurality (three) second drivers (not shown), a plurality (three) third drivers (not shown), and a plurality (three) fourth drivers (not shown). The plurality of first drivers correspond one-to-one with the plurality of first switching elements 1. Each of the plurality of first drivers is a high-side gate driver connected to the control terminal (gate terminal) of the corresponding first switching element 1 among the plurality of first switching elements 1. The plurality of second drivers correspond one-to-one with the plurality of second switching elements 2. Each of the plurality of second drivers is a low-side gate driver connected to the control terminal (gate terminal) and second main terminal (source terminal) of the corresponding second switching element 2 among the plurality of second switching elements 2. The plurality of third drivers correspond one-to-one with the plurality of third switching elements 3. Each of the plurality of third drivers is a high-side gate driver connected to the control terminal (gate terminal) of the corresponding third switching element 3 among the plurality of third switching elements 3. The multiple fourth drivers correspond one-to-one with the multiple fourth switching elements 4. Each of the multiple fourth drivers is a low-side gate driver connected to the control terminal (gate terminal) and second main terminal (source terminal) of the corresponding fourth switching element 4. Each of the multiple first drivers, multiple second drivers, multiple third drivers, and multiple fourth drivers includes, for example, a driver IC (Integrated Circuit).

[0026] The first capacitor C1 is connected between the positive input terminal 11 and the negative input terminal 12. The first capacitor C1 has a first terminal and a second terminal. In the first capacitor C1, the first terminal is connected to the positive input terminal 11, and the second terminal is connected to the negative input terminal 12. The first capacitor C1 is also connected in parallel to a plurality of first half-bridge circuits 21.

[0027] Each of the multiple second capacitors C2 has a first terminal and a second terminal. The first terminal of each of the multiple second capacitors C2 is connected to the corresponding output terminal 13 among the multiple output terminals 13. For convenience of explanation, below, the second capacitor C2 connected to the U-phase output terminal 13u will be referred to as the second capacitor C2u, the second capacitor C2 connected to the V-phase output terminal 13v will be referred to as the second capacitor C2v, and the second capacitor C2 connected to the W-phase output terminal 13w will be referred to as the second capacitor C2w.

[0028] Each of the multiple second capacitors C2 is, for example, a high dielectric constant multilayer ceramic capacitor. Therefore, each of the multiple second capacitors C2 has, for example, DC bias characteristics. The dielectric material of the multilayer ceramic capacitor is a ferroelectric material. The ferroelectric material is, for example, barium titanate (BaTiO2). ３ However, this is not limited to barium titanate. The relative permittivity of the dielectric material of a high-dielectric-constant multilayer ceramic capacitor is, for example, 2000 to 12000. A "high-dielectric-constant multilayer ceramic capacitor" is, for example, a multilayer ceramic capacitor classified as "Class 2" in the Japanese Industrial Standards or EIA standards.

[0029] In the power converter 100, the capacitances of the multiple (three in Figure 1) second capacitors C2 are the same. That is, the capacitances of the three second capacitors C2 are the same. "The capacitances of the three second capacitors C2 are the same" means not only that the capacitance of two of the three second capacitors C2 is 100% of the capacitance of the remaining second capacitor C2, but also that the capacitance of the two second capacitors C2 is within the range of 80% to 120% of the capacitance of the remaining second capacitor C2.

[0030] The third capacitor C3 is connected between the second terminals of the multiple second capacitors C2 and the negative input terminal 12. The third capacitor C3 has a third terminal and a fourth terminal. In the third capacitor C3, the third terminal of the third capacitor C3 is connected to the second terminals of the three second capacitors C2, and the fourth terminal of the third capacitor C3 is connected to the negative input terminal 12. The third capacitor C3 is, for example, a high dielectric constant multilayer ceramic capacitor, similar to the multiple second capacitors C2. The third capacitor C3 is not limited to a high dielectric constant multilayer ceramic capacitor, but may be, for example, an electrolytic capacitor.

[0031] In this embodiment, the series circuit of the second capacitor C2u and the third capacitor C3 is connected in parallel to the second half-bridge circuit 22 of the DC-DC converter 9u. Also in this embodiment, the series circuit of the second capacitor C2v and the third capacitor C3 is connected in parallel to the second half-bridge circuit 22 of the DC-DC converter 9v. Also in this embodiment, the series circuit of the second capacitor C2w and the third capacitor C3 is connected in parallel to the second half-bridge circuit 22 of the DC-DC converter 9w.

[0032] The control device 10 controls the plurality of first switching elements 1, plurality of second switching elements 2, plurality of third switching elements 3, and plurality of fourth switching elements 4 via a plurality of first drivers, a plurality of second drivers, a plurality of third drivers, and a plurality of fourth drivers, respectively.

[0033] The control device 10 includes a computer system. The computer system mainly consists of a processor and memory as hardware. The processor executes a program recorded in the computer system's memory, thereby realizing the functions of the control device 10 in this disclosure. The processor of the computer system is composed of one or more electronic circuits, including semiconductor integrated circuits (ICs) or large-scale integrated circuits (LSIs). The integrated circuits referred to here, such as ICs or LSIs, are named differently depending on the degree of integration, and include integrated circuits called system LSIs, VLSIs (Very Large Scale Integrations), or ULSIs (Ultra Large Scale Integrations). Furthermore, FPGAs (Field-Programmable Gate Arrays) that are programmed after the LSI is manufactured, or logic devices that allow for the reconfiguration of junction relationships or circuit compartments within the LSI, can also be used as processors. Multiple electronic circuits may be integrated onto a single chip or distributed across multiple chips. Multiple chips may be integrated onto a single device or distributed across multiple devices. The computer system referred to herein includes a microcontroller having one or more processors and one or more memories. Therefore, the microcontroller also consists of one or more electronic circuits, including semiconductor integrated circuits or large-scale integrated circuits.

[0034] The control device 10 generates a first PWM signal, a second PWM signal, a third PWM signal, and a fourth PWM signal for controlling each of the first switching element 1, the second switching element 2, the third switching element 3, and the fourth switching element 4 of the three DC-DC converters 9. Therefore, the control device 10 can output a plurality of first PWM signals, a plurality of second PWM signals, a plurality of third PWM signals, and a plurality of fourth PWM signals. Each of the plurality of first PWM signals, the plurality of second PWM signals, the plurality of third PWM signals, and the plurality of fourth PWM signals is, for example, a PWM signal that varies between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level. Each of the plurality of switching elements is in an on state when the corresponding PWM signal among the plurality of PWM signals is at a high level, and is in an off state when at a low level.

[0035] The control device 10 uses a triangular first carrier signal to generate a first PWM signal, a second PWM signal, a third PWM signal, and a fourth PWM signal corresponding to the first switching element 1u, the second switching element 2u, the third switching element 3u, and the fourth switching element 4u of the DC-DC converter 9u, respectively. Further, the control device 10 uses a triangular second carrier signal to generate a first PWM signal, a second PWM signal, a third PWM signal, and a fourth PWM signal corresponding to the first switching element 1v, the second switching element 2v, the third switching element 3v, and the fourth switching element 4v of the DC-DC converter 9v, respectively. Further, the control device 10 uses a triangular third carrier signal to generate a first PWM signal, a second PWM signal, a third PWM signal, and a fourth PWM signal corresponding to the first switching element 1w, the second switching element 2w, the third switching element 3w, and the fourth switching element 4w of the DC-DC converter 9w, respectively. In the present embodiment, the first carrier signal, the second carrier signal, and the third carrier signal have the same phase as each other.

[0036] (3) Operation of the power converter Each of the three DC-DC converters 9 is capable of a first conversion operation, which converts the first input voltage from the DC power supply E1 to the first half-bridge circuit 21 into a first output voltage, and a second conversion operation, which converts the second input voltage from the AC load 15 (input voltage to the second half-bridge circuit 22) into a second output voltage. Both the first and second conversion operations are capable of either boost operation (hereinafter also referred to as boost mode operation) or buck operation (hereinafter also referred to as buck mode operation). Furthermore, the power converter 100 is capable of either a power supply operation, which converts the DC power input between the positive input terminal 11 and the negative input terminal 12 into three-phase AC power and outputs it from the three output terminals 13, or a power regeneration operation, which converts the three-phase AC power input from the three output terminals 13 into DC power and outputs it between the positive input terminal 11 and the negative input terminal 12. The power converter 100 performs a power regeneration operation to recover energy from a three-phase servo motor, which is an AC load 15, when the brakes are applied to the three-phase servo motor.

[0037] Multiple DC-DC converters 9 are controlled by a control device 10. The output voltage (phase voltage) of each of the multiple DC-DC converters 9 is, for example, a sinusoidal DC voltage (see Figure 2). Also, the output current (phase current) of each of the multiple DC-DC converters 9 is, for example, a sinusoidal AC current (see Figure 2). The power converter 100 outputs sinusoidal DC voltages from the three DC-DC converters 9u, 9v, and 9w, with phases differing by 120° from each other. The power converter 100 also outputs sinusoidal AC currents from the three DC-DC converters 9u, 9v, and 9w, with phases differing by 120° from each other.

[0038] When the output voltage of each of the plurality of DC-DC converters 9 is less than the output voltage of the DC power supply E1 (for example, 48 V), the control device 10 operates each of the plurality of DC-DC converters 9 in the step-down mode. When the output voltage of each of the plurality of DC-DC converters 9 is greater than or equal to the output voltage of the DC power supply E1, the control device 10 operates each of the plurality of DC-DC converters 9 in the boost mode. In the power conversion device 100, the control device 10 changes the output voltage of each of the plurality of DC-DC converters 9 within a predetermined voltage range (for example, a range of 0 V to 100 V).

[0039] When the control device 10 operates each of the plurality of DC-DC converters 9 in the step-down mode, the control device 10 always controls the third switching element 3 of each of the plurality of second half-bridge circuits 22 to be in the on state, and always controls the fourth switching element 4 to be in the off state.

[0040] When the control device 10 operates each of the plurality of DC-DC converters 9 in the boost mode, the control device 10 always controls the first switching element 1 of each of the plurality of first half-bridge circuits 21 to be in the on state, and always controls the second switching element 2 to be in the off state.

[0041] The control device 10 is not limited to the step-down mode operation in which the third switching element 3 is always controlled to be in the on state and the boost mode operation in which the control device 10 always controls the first switching element 1 to be in the on state, and may perform a buck-boost mode operation in which the first to fourth switching elements 1 to 4 are always switched.

[0042] [[ID=,12]] When the three DC-DC converters 9 are operating in the step-down mode, if the phase voltages of the U phase, V phase, and W phase are Va, Vb, and Vc, respectively, Va, Vb, and Vc are sinusoidal voltages as shown in FIG. 2. However, Va, Vb, and Vc are DC voltages. Also, the line voltage Va-Vb between the U phase and the V phase, the line voltage Vb-Vc between the V phase and the W phase, and the line voltage Vc-Va between the W phase and the U phase are sinusoidal AC voltages with phases different from each other by 120° as shown in FIG. 2. Also, the phase currents isa, isb, and isc of the U phase, V phase, and W phase are sinusoidal AC currents with phases different from each other by 120° as shown in FIG. 2.

[0043] In both the boost mode and buck-boost mode of the first conversion operation of the three DC-DC converters 9, the phase voltages Va, Vb, and Vc are sinusoidal voltages. However, the phase voltages Va, Vb, and Vc are DC voltages. Also, in both the boost mode and buck-boost mode of the three DC-DC converters 9, the line voltages Va-Vb between the U-phase and V-phase, Vb-Vc between the V-phase and W-phase, and Vc-Va between the W-phase and U-phase are sinusoidal AC voltages with a phase difference of 120° from each other. Also, in both the boost mode and buck-boost mode of the first conversion operation of the three DC-DC converters 9, the phase current isa of the U-phase, the phase current isb of the V-phase, and the phase current isc of the W-phase are sinusoidal AC currents with a phase difference of 120° from each other.

[0044] (4) Characteristic Figure 2 shows the operating waveform of the power converter 100 when, as an example, the frequencies of the first carrier signal, the second carrier signal, and the third carrier signal are set to 100 kHz, and the frequencies of the U-phase phase current isa, the V-phase phase current isb, and the W-phase phase current isc are each set to 250 Hz. From Figure 2, it can be seen that no excessive ripple current is generated in the U-phase phase current isa, the V-phase phase current isb, and the W-phase phase current isc. Thus, the power converter 100 according to Embodiment 1 can achieve both a design that does not generate excessive ripple current and miniaturization of the capacitor. However, in the power converter 100 according to Embodiment 1, the ripple of the phase voltages Va, Vb, and Vc is larger compared to the operating waveform (see Figure 4) of the power converter 200 according to the comparative example (see Figure 3). In Figure 2, the voltages across each second capacitor C2 are shown as follows: V2a1 is the voltage across the second capacitor C2u, V2b1 is the voltage across the second capacitor C2v, and V2c1 is the voltage across the second capacitor C2w.

[0045] (5) Advantages The power conversion device 100 according to Embodiment 1 comprises a positive input terminal 11, a negative input terminal 12, a first capacitor C1, a plurality of DC-DC converters 9, a plurality of output terminals 13, a plurality of second capacitors C2, a third capacitor C3, and a control device 10. The first capacitor C1 is connected between the positive input terminal 11 and the negative input terminal 12. The plurality of DC-DC converters 9 are connected between the positive input terminal 11 and the negative input terminal 12. The plurality of output terminals 13 correspond one-to-one with the plurality of DC-DC converters 9. The plurality of output terminals 13 are connected to the corresponding DC-DC converter 9 among the plurality of DC-DC converters 9. The plurality of second capacitors C2 correspond one-to-one with the plurality of output terminals 13. The plurality of second capacitors C2 are connected to the corresponding output terminals 13 among the plurality of output terminals 13. The third capacitor C3 is connected in series with the plurality of second capacitors C2. The control device 10 controls the plurality of DC-DC converters 9. Each of the multiple DC-DC converters 9 has a first half-bridge circuit 21, a second half-bridge circuit 22, and an inductor L1. The first half-bridge circuit 21 is connected between the positive input terminal 11 and the negative input terminal 12. The first half-bridge circuit 21 has a first switching element 1 and a second switching element 2 connected in series with each other. The second half-bridge circuit 22 is connected between a corresponding output terminal 13 from among the multiple output terminals 13 and the negative input terminal 12. The second half-bridge circuit 22 has a third switching element 3 and a fourth switching element 4 connected in series with each other. The inductor L1 is connected between the connection point N1 between the first switching element 1 and the second switching element 2 and the connection point N2 between the third switching element 3 and the fourth switching element 4. Each of the multiple second capacitors C2 has a first end and a second end. The first end of each of the multiple second capacitors C2 is connected to a corresponding output terminal 13 from among the multiple output terminals 13. The third capacitor C3 is connected between the second terminals of the multiple second capacitors C2 and the negative input terminal 12.

[0046] The above configuration makes it possible to reduce ripple current while miniaturizing the device. More specifically, the above configuration includes a third capacitor C3 connected between the second terminals of multiple second capacitors C2 and the negative input terminal 12. Compared to the case where each of the multiple second half-bridge circuits 22 is connected in series with two capacitors and each capacitor is a capacitor with a low voltage rating, the number of capacitors can be reduced (if there are three second half-bridge circuits 22, the number of capacitors for the three second half-bridge circuits 22 can be reduced from six to four), making it possible to reduce ripple current while miniaturizing the device.

[0047] Furthermore, in the power conversion device 100 according to Embodiment 1, the third capacitor C3 is a polarized capacitor.

[0048] With the above configuration, the capacitance density per unit volume can be increased compared to when a multilayer ceramic capacitor is used as the third capacitor C3, making further miniaturization possible. In the power conversion device 100 according to Embodiment 1, as shown in Figure 2, a sinusoidal voltage is applied to the second capacitor C2, so a polarized capacitor is not used as the second capacitor C2 in order to prevent deterioration of the characteristics of the second capacitor C2 when the sinusoidal voltage swings to the negative side. On the other hand, as shown in Figure 2, a substantially constant DC voltage is applied to the third capacitor C3, rather than a sinusoidal voltage, so a polarized capacitor can be used as the third capacitor C3 in the power conversion device 100 according to Embodiment 1.

[0049] (Embodiment 2) The power converter 100A according to Embodiment 2 will be described with reference to Figures 5 to 10. With respect to the power converter 100A according to Embodiment 2, components that are the same as those in the power converter 100 according to Embodiment 1 (see Figure 1) are denoted by the same reference numerals and their description is omitted.

[0050] (1) The power converter 100A according to the second embodiment differs from the power converter 100 according to the first embodiment in that it is equipped with a control device 10A instead of the control device 10 of the power converter 100 according to the first embodiment.

[0051] The control device 10A, like the control device 10, includes a computer system.

[0052] The control device 10A outputs multiple (three) first PWM signals G1, multiple (three) second PWM signals G2, multiple (three) third PWM signals G3, and multiple (three) fourth PWM signals G4, which control the on / off state of multiple (three) first switching elements 1, multiple (three) second switching elements 2, multiple (three) third switching elements 3, and multiple (three) fourth switching elements 4, respectively.

[0053] Multiple first PWM signals G1 correspond one-to-one with multiple first switching elements 1. The multiple first PWM signals G1 include a first PWM signal G1u corresponding to a first switching element 1u, a first PWM signal G1v corresponding to a first switching element 1v, and a first PWM signal G1w corresponding to a first switching element 1w.

[0054] Multiple second PWM signals G2 correspond one-to-one with multiple second switching elements 2. The multiple second PWM signals G2 include a second PWM signal G2u corresponding to a second switching element 2u, a second PWM signal G2v corresponding to a second switching element 2v, and a second PWM signal G2w corresponding to a second switching element 2w.

[0055] Multiple third PWM signals G3 correspond one-to-one with multiple third switching elements 3. The multiple third PWM signals G3 include a third PWM signal G3u corresponding to a third switching element 3u, a third PWM signal G3v corresponding to a third switching element 3v, and a third PWM signal G3w corresponding to a third switching element 3w.

[0056] The multiple fourth PWM signals G4 correspond one-to-one with the multiple fourth switching elements 4. The multiple fourth PWM signals G4 include a fourth PWM signal G4u corresponding to a fourth switching element 4u, a fourth PWM signal G4v corresponding to a fourth switching element 4v, and a fourth PWM signal G4w corresponding to a fourth switching element 4w.

[0057] Each of the multiple first PWM signals G1, multiple second PWM signals G2, multiple third PWM signals G3, and multiple fourth PWM signals G4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) which is higher than the first potential level. Each of the multiple first switching elements 1 is turned on when the corresponding first PWM signal G1 among the multiple first PWM signals G1 is at a high level, and turned off when it is at a low level. Similarly, each of the multiple second switching elements 2 is turned on when the corresponding second PWM signal G2 among the multiple second PWM signals G2 is at a high level, and turned off when it is at a low level. Similarly, each of the multiple third switching elements 3 is turned on when the corresponding third PWM signal G3 among the multiple third PWM signals G3 is at a high level, and turned off when it is at a low level. Furthermore, each of the multiple fourth switching elements 4 is turned on when the corresponding fourth PWM signal G4 among the multiple fourth PWM signals G4 is at a high level, and turned off when it is at a low level.

[0058] When the control device 10A generates the first PWM signal G1, the second PWM signal G2, the third PWM signal G3, and the fourth PWM signal G4 for each of the three DC-DC converters 9, it uses three triangular wave carrier signals CA1, CA2, and CA3 (see Figure 6) that correspond one-to-one with the three DC-DC converters 9 and have different phases from each other. In other words, the control device 10A uses three triangular wave carrier signals CA1, CA2, and CA3 that have different phases from each other to generate a plurality of first PWM signals G1, a plurality of second PWM signals G2, a plurality of third PWM signals G3, and a plurality of fourth PWM signals G4. The control device 10A has a signal generation unit 124 that generates a plurality of first PWM signals G1, a plurality of second PWM signals G2, a plurality of third PWM signals G3, and a plurality of fourth PWM signals G4 based on carrier signals CA1, CA2, CA3 and duty command values ​​da, db, dc (see Figure 7). Figure 6 is an explanatory diagram of the operation when the control device 10A operates each of the three DC-DC converters 9u, 9v, and 9w in step-down mode.

[0059] In this embodiment, carrier signals CA1, CA2, and CA3 are, for example, triangular waveform signals with a phase difference of 120° from each other.

[0060] The signal generation unit 124 generates, for example, a first PWM signal G1u, a second PWM signal G2u, a third PWM signal G3u, and a fourth PWM signal G4u to be supplied to the first switching element 1u, the second switching element 2u, the third switching element 3u, and the fourth switching element 4u, respectively, based on the carrier signal CA1 and the duty cycle command value da of the U phase (see Figure 7).

[0061] The duty cycles of the first PWM signal G1u and the second PWM signal G2u, generated by the signal generation unit 124, change based on the duty cycle command value da. The signal generation unit 124 generates the first PWM signal G1u by comparing the duty cycle command value da with the carrier signal CA1. More specifically, the signal generation unit 124 generates the first PWM signal G1u which is high level ("1") during periods when the duty cycle command value da is greater than the value of the carrier signal CA1, and low level ("0") during periods when the duty cycle command value da is less than or equal to the value of the carrier signal CA1. The signal generation unit 124 also generates the second PWM signal G2u by inverting the first PWM signal G1u. The signal generation unit 124 sets a dead time period between the high-level period of the first PWM signal G1u and the high-level period of the second PWM signal G2u so that the ON period of the first switching element 1u and the ON period of the second switching element 2u do not overlap.

[0062] The duty cycles of the third PWM signal G3u and the fourth PWM signal G4u, both generated by the signal generation unit 124, change based on the duty cycle command value da. The signal generation unit 124 generates the third PWM signal G3u by comparing the duty cycle command value da with the carrier signal CA1. More specifically, the signal generation unit 124 generates a third PWM signal G3u that is high level ("1") during periods when the duty cycle command value da is greater than the value of the carrier signal CA1, and low level ("0") during periods when the duty cycle command value da is less than or equal to the value of the carrier signal CA1. The signal generation unit 124 also generates the fourth PWM signal G4u by inverting the third PWM signal G3u. The signal generation unit 124 sets a dead time period between the high-level period of the third PWM signal G3u and the high-level period of the fourth PWM signal G4u so that the ON period of the third switching element 3u and the ON period of the fourth switching element 4u do not overlap.

[0063] The signal generation unit 124 generates, for example, a first PWM signal G1v, a second PWM signal G2v, a third PWM signal G3v, and a fourth PWM signal G4v to be supplied to the first switching element 1v, the second switching element 2v, the third switching element 3v, and the fourth switching element 4v, respectively, based on the carrier signal CA2 and the duty cycle command value db of the V phase (see Figure 7).

[0064] The duty cycles of the first PWM signal G1v and the second PWM signal G2v, both generated by the signal generation unit 124, change based on the duty cycle command value db. The signal generation unit 124 generates the first PWM signal G1v by comparing the duty cycle command value db with the carrier signal CA2. More specifically, the signal generation unit 124 generates the first PWM signal G1v which is high level ("1") during periods when the duty cycle command value db is greater than the value of the carrier signal CA2, and low level ("0") during periods when the duty cycle command value db is less than or equal to the value of the carrier signal CA1. The signal generation unit 124 also generates the second PWM signal G2v by inverting the first PWM signal G1v. The signal generation unit 124 sets a dead time period between the high-level period of the first PWM signal G1v and the high-level period of the second PWM signal G2v so that the ON period of the first switching element 1v and the ON period of the second switching element 2v do not overlap.

[0065] The duty cycles of the third PWM signal G3v and the fourth PWM signal G4v, both generated by the signal generation unit 124, change based on the duty cycle command value db. The signal generation unit 124 generates the third PWM signal G3v by comparing the duty cycle command value db with the carrier signal CA2. More specifically, the signal generation unit 124 generates a third PWM signal G3v that is high level ("1") during periods when the duty cycle command value db is greater than the value of the carrier signal CA2, and low level ("0") during periods when the duty cycle command value db is less than or equal to the value of the carrier signal CA2. The signal generation unit 124 also generates the fourth PWM signal G4v by inverting the third PWM signal G3v. The signal generation unit 124 sets a dead time period between the high-level period of the third PWM signal G3v and the high-level period of the fourth PWM signal G4v so that the ON period of the third switching element 3v and the ON period of the fourth switching element 4v do not overlap.

[0066] The signal generation unit 124 generates, for example, a first PWM signal G1w, a second PWM signal G2w, a third PWM signal G3w, and a fourth PWM signal G4w to be supplied to the first switching element 1w, the second switching element 2w, the third switching element 3w, and the fourth switching element 4w, respectively, based on the carrier signal CA3 and the W-phase duty command value dc (see Figure 7).

[0067] The duty cycles of the first PWM signal G1w and the second PWM signal G2w, generated by the signal generation unit 124, change based on the duty cycle command value dc. The signal generation unit 124 generates the first PWM signal G1w by comparing the duty cycle command value dc with the carrier signal CA3. More specifically, the signal generation unit 124 generates the first PWM signal G1w which is high level ("1") during periods when the duty cycle command value dc is greater than the value of the carrier signal CA3, and low level ("0") during periods when the duty cycle command value dc is less than or equal to the value of the carrier signal CA3. The signal generation unit 124 also generates the second PWM signal G2w by inverting the first PWM signal G1w. The signal generation unit 124 sets a dead time period between the high-level period of the first PWM signal G1w and the high-level period of the second PWM signal G2w so that the ON period of the first switching element 1w and the ON period of the second switching element 2w do not overlap.

[0068] The duty cycles of the third PWM signal G3w and the fourth PWM signal G4w, both generated by the signal generation unit 124, change based on the duty cycle command value dc. The signal generation unit 124 generates the third PWM signal G3w by comparing the duty cycle command value dc with the carrier signal CA3. More specifically, the signal generation unit 124 generates a third PWM signal G3w that is high level ("1") during periods when the duty cycle command value dc is greater than the value of the carrier signal CA3, and low level ("0") during periods when the duty cycle command value dc is less than or equal to the value of the carrier signal CA3. The signal generation unit 124 also generates the fourth PWM signal G4w by inverting the third PWM signal G3w. Furthermore, the signal generation unit 124 sets a dead time period between the high-level period of the third PWM signal G3w and the high-level period of the fourth PWM signal G4w so that the ON period of the third switching element 3w and the ON period of the fourth switching element 4w do not overlap.

[0069] In this embodiment, as shown in Figure 7, the control device 10A includes, in addition to the signal generation unit 124 described above, a subtraction unit 122 that performs subtraction and a PI (Proportional Integral) control unit 123 that performs PI control.

[0070] The subtraction unit 122 calculates the U-phase voltage difference value by subtracting the detected value of the U-phase voltage Va from the U-phase command voltage value Va0. The subtraction unit 122 also calculates the V-phase voltage difference value by subtracting the detected value of the V-phase voltage Vb from the V-phase command voltage value Vb0. The subtraction unit 122 also calculates the W-phase voltage difference value by subtracting the detected value of the W-phase voltage Vc from the W-phase command voltage value Vc0.

[0071] The PI control unit 123 generates a duty cycle command value da for performing feedback control to bring the U-phase voltage difference value output from the subtraction unit 122 closer to zero. The PI control unit 123 also generates a duty cycle command value db for performing feedback control to bring the V-phase voltage difference value output from the subtraction unit 122 closer to zero. The PI control unit 123 also generates a duty cycle command value dc for performing feedback control to bring the W-phase voltage difference value output from the subtraction unit 122 closer to zero. The duty cycle command values ​​da, db, and dc generated by the PI control unit 123 are used by the signal generation unit 124 as described above.

[0072] Figure 8 shows the equivalent circuit used to determine the voltage V3 across the third capacitor C3. In the equivalent circuit of Figure 8, the voltage source Ea connected in series with the second capacitor C2u outputs the phase voltage Va, the voltage source Eb connected in series with the second capacitor C2v outputs the phase voltage Vb, and the voltage source Ec connected in series with the second capacitor C2w outputs the phase voltage Vc.

[0073] The capacitance of each of the multiple second capacitors C2 is C Ｈ And the capacitance of the third capacitor C3 is C Ｌ Let Va be the phase voltage of the U phase, Vb be the phase voltage of the V phase, Vc be the phase voltage of the W phase, and V3 be the voltage across the third capacitor C3. Then V3 can be calculated using the following equation (1). In deriving equation (1), first, the voltage across the third capacitor C3 is calculated for each of the three voltage sources Ea, Eb, and Ec, and finally, these voltages are superimposed. In other words, equation (1) is derived based on the superposition principle.

[0074]

[0075] Furthermore, Va, Vb, and Vc can be expressed as the sum of the amplitude component and the bias voltage (DC voltage), and are represented by equations (2), (3), and (4), respectively.

[0076]

[0077]

[0078]

[0079] Therefore, substituting Va, Vb, and Vc in Equation (1) with Va, Vb, and Vc in Equation (2), Equation (3), and Equation (4) respectively, and then simplifying, V3 can be expressed by the following Equation (5).

[0080]

[0081] Moreover, Va, Vb, and Vc are respectively expressed by Equation (6), Equation (7), and Equation (8).

[0082]

[0083]

[0084]

[0085] The voltage across both ends of the second capacitor C2u, V2a1, the voltage across both ends of the second capacitor C2v, V2b1, and the voltage across both ends of the second capacitor C2w, V2c1, can be expressed as the sum of the amplitude component and the bias voltage (Vbias - V3).

[0086] Also, let the inductance of each of the three inductors L1 be L, and let the cut-off frequency of the circuit including the three inductors L1, the three second capacitors C2u, C2v, C2w, and the third capacitor C3 be f Ｖ３ Then, f Ｖ３ is expressed by Equation (9).

[0087]

[0088] Also, let the inductance of each of the three inductors L1 be L, let the cut-off frequency of the circuit including the inductor L1 and the second capacitor C2u be f Ｖａ Let the cut-off frequency of the circuit including the inductor L1 and the second capacitor C2v be f Ｖｂ Let the cut-off frequency of the circuit including the inductor L1 and the second capacitor C2w be f Ｖｃ Then, f Ｖａ f Ｖｂ f Ｖｃ are expressed by Equation (10).

[0089]

[0090] In the power converter 100A according to Embodiment 2, f Ｖａ , f Ｖｂ , f Ｖｃ However, in the PI control unit 123, the gain related to the amplitude component is determined, f Ｖ３ However, this relates to the determination of the gain for the bias component in the PI control unit 123.

[0091] Table 1 shows a comparison between the power converter 100A according to Embodiment 2 and the power converter 200 (see Figure 3) according to the comparative example, with respect to the cutoff frequency and time constant of the bias component. Here, L = 15 μH, C Ｈ = 6μF, C Ｌ Assuming = 6μF, the cutoff frequency in Embodiment 2 is calculated using equation (9). Regarding the comparative example, capacitor C20 is configured as a series circuit of two capacitors, and the capacitance of one of the two capacitors is set to the capacitance C of the second capacitor C2. Ｈ The capacitance of the remaining capacitor is set to the same 6μF as the third capacitor C3, and the capacitance of the remaining capacitor is set to the capacitance C3. Ｌ Assuming the same 6μF capacitance as before, and denoting the capacitance of the series circuit of the two capacitors as C, the cutoff frequency in the comparative example can be calculated in the same way as in equation (10).

[0092]

[0093] Table 1 shows that Embodiment 2 can reduce the time constant by approximately 30% compared to the comparative example.

[0094] (2) Characteristics In the power converter 100A according to Embodiment 2, the proportional gain Kp and period Ti used in the PI control unit 123 are set in advance. In setting the proportional gain Kp and period Ti, the Ziegler-Nichols limit sensitivity method in PI control is used to calculate the proportional gain at the stability limit as Ku and the period at the stability limit as Tu. The proportional gain Kp is determined by the calculation Kp = 0.45 × Ku, and the period Ti is determined by the calculation Ti = 0.83 × Tu. Table 2 is a table showing a comparison between the power converter 100A according to Embodiment 2 and the power converter 200 of the comparative example.

[0095]

[0096] Table 2 shows that the power converter 100A of Embodiment 2 can shorten the period Ti compared to the comparative example, and the time constant of the control device 10A can be made smaller than the time constant of the control device 10 of the power converter 200 of the comparative example, thereby enabling faster response speed.

[0097] Figure 9 shows the phase voltage response characteristics A1 of Embodiment 2 and the phase voltage response characteristics B1 of the comparative example when the input voltage is 48V, the carrier frequency is 100kHz, and the command voltage value is changed in a step manner from 10V to 30V with respect to the command voltage waveform D1. In the example in Figure 9, the command voltage value changes from 10V to 30V at 30ms. Also, in Figure 9, the command voltage value is the command voltage value of the U phase, and the phase voltage is the phase voltage Va of the U phase.

[0098] When the command voltage value changes from 10V to 30V, the settling time is 5.1 ms in the comparative example, while in embodiment 2, the settling time is shortened to 3.3 ms, making it possible to improve responsiveness compared to the comparative example. Here, "settling time" refers to the time it takes from the point of change to when the phase voltage is changed in a step-like manner until it falls within ±2% of the target value of the phase voltage (30V in the example of Figure 9).

[0099] When the first conversion operation of the three DC-DC converters 9 is in step-down mode, if the phase voltages of the U-phase, V-phase, and W-phase are Va, Vb, and Vc, respectively, then Va, Vb, and Vc are sinusoidal voltages as shown in Figure 10. However, Va, Vb, and Vc are DC voltages. Furthermore, the line voltages between the U-phase and V-phase (Va-Vb), between the V-phase and W-phase (Vb-Vc), and between the W-phase and U-phase (Vc-Va) are sinusoidal AC voltages with a phase difference of 120° from each other, as shown in Figure 10. Also, the phase currents isa of the U-phase, isb of the V-phase, and isc of the W-phase are sinusoidal AC currents with a phase difference of 120° from each other, as shown in Figure 10.

[0100] Figure 10 shows the operating waveform of the power converter 100A, as an example, when the frequencies of the carrier signals CA1, CA2, and CA3 are set to 100 kHz, and the frequencies of the U-phase phase current isa, V-phase phase current isb, and W-phase phase current isc are each set to 250 Hz. From Figure 10, it can be seen that no ripple current is generated in the U-phase phase current isa, V-phase phase current isb, and W-phase phase current isc. Furthermore, from Figures 10 and 2, it can be seen that the power converter 100A according to Embodiment 2 can reduce voltage ripple compared to the power converter 100 according to Embodiment 1.

[0101] In both the boost mode and buck-boost mode of the first conversion operation of the three DC-DC converters 9, Va, Vb, and Vc are sinusoidal voltages. However, Va, Vb, and Vc are DC voltages. Also, in both the boost mode and buck-boost mode of the first conversion operation of the three DC-DC converters 9, the line voltages between the U-phase and V-phase (Va-Vb), the line voltages between the V-phase and W-phase (Vb-Vc), and the line voltages between the W-phase and U-phase (Vc-Va) are sinusoidal AC voltages with a phase difference of 120° from each other. Also, in both the boost mode and buck-boost mode of the first conversion operation of the three DC-DC converters 9, the phase currents isa of the U-phase, isb of the V-phase, and isc of the W-phase are sinusoidal AC currents with a phase difference of 120° from each other.

[0102] (3) Advantages The power converter 100A according to Embodiment 2, like the power converter 100 according to Embodiment 1, includes a third capacitor C3 connected between the second end of a plurality of second capacitors C2 and the negative input terminal 12, making it possible to reduce the size while suppressing current ripple.

[0103] Furthermore, in the power converter 100A of Embodiment 2, the plurality of DC-DC converters 9 include three DC-DC converters 9. The control device 10A has a signal generation unit 124. The signal generation unit 124 generates a first PWM signal G1, a second PWM signal G2, a third PWM signal G3, and a fourth PWM signal G4 to control the first switching element 1, second switching element 2, third switching element 3, and fourth switching element 4 of each of the three DC-DC converters 9. When the signal generation unit 124 generates the first PWM signal G1, second PWM signal G2, third PWM signal G3, and fourth PWM signal G4 for each of the three DC-DC converters 9, it uses triangular wave carrier signals CA1, CA2, and CA3, which have different phases from each other, for each of the three DC-DC converters 9.

[0104] The above configuration makes it possible to improve responsiveness. Furthermore, the above configuration makes it possible to reduce the voltage ripple of the U-phase voltage Va, the V-phase voltage Vb, and the W-phase voltage Vc. Carrier signals CA1, CA2, and CA3 are, for example, triangular waveform signals with a phase difference of 120° from each other. If the capacitance of the second capacitor C2 and the capacitance of the third capacitor C3 are the same, then if the phase difference between carrier signals CA1, CA2, and CA3 is 120° ± 30°, it is possible to reduce voltage ripple.

[0105] (Embodiment 3) The power converter 100B according to Embodiment 3 will be described with reference to Figures 11 to 13. With respect to the power converter 100B according to Embodiment 3, components that are the same as those in the power converter 100A according to Embodiment 2 (see Figure 5) are denoted by the same reference numerals and their description is omitted.

[0106] (1) The power converter 100B according to Embodiment 3 differs from the power converter 100A according to Embodiment 2 in that it further includes a voltage detection circuit 17 for detecting the voltage V3 across the third capacitor C3, as shown in Figure 12. Also, the power converter 100B according to Embodiment 3 differs from the power converter 100A according to Embodiment 2 in that it includes a control device 10B instead of the control device 10A of the power converter 100A according to Embodiment 2.

[0107] The voltage detection circuit 17 is a resistive voltage divider circuit having two resistors 171 and 172 connected in series with each other. The number of resistors in the resistive voltage divider circuit is not limited to two; it may be three or more.

[0108] The control device 10B, like the control device 10A, includes a computer system. Based on the values ​​detected by the voltage detection circuit 17, the control device 10B controls the gains for the amplitudes of the phase voltages Va, Vb, and Vc, and the gains for the bias voltages of the phase voltages Va, Vb, and Vc.

[0109] The control device 10B will be described in more detail below.

[0110] As shown in Figure 11, the control device 10B includes a first conversion unit 101, a first subtraction unit 102, a second subtraction unit 103, a first PI control unit 104, a second PI control unit 105, a second conversion unit 106, an addition unit 107, a voltage calculation unit 108, a third subtraction unit 109, a fourth subtraction unit 110, a third PI control unit 111, a fourth PI control unit 112, a duty cycle command value generation unit 113, and a signal generation unit 114.

[0111] The first conversion unit 101 acquires a detected value ia from a current sensor 14a (hereinafter also referred to as the U-phase current sensor 14a) that detects the phase current isa. The first conversion unit 101 also acquires a detected value ib from a current sensor 14b (hereinafter also referred to as the V-phase current sensor 14b) that detects the phase current isb. The first conversion unit 101 also acquires a detected value ic from a current sensor 14c (hereinafter also referred to as the W-phase current sensor 14c) that detects the phase current isc. Note that the U-phase current sensor 14a, the V-phase current sensor 14b, and the W-phase current sensor 14c are not components of the power conversion device 100B, but they may be components of the power conversion device 100B. Each of the three current sensors 14a, 14b, and 14c is a current detection resistor, but they are not limited to current detection resistors and may be current transformers.

[0112] The first conversion unit 101 includes, for example, a three-phase to two-phase conversion unit and a dq conversion unit, and converts the detected values ​​ia, ib, and ic of the three-phase phase currents isa, isb, and isc of the abc reference coordinate system, where the U phase is the a phase, the V phase is the b phase, and the W phase is the c phase, into the d-axis current value id and the q-axis current value iq of the dq rotating coordinate system.

[0113] The first subtraction unit 102 calculates the difference between the reference value id1 and the d-axis current value id (hereinafter also referred to as the d-axis current difference) by performing an operation to subtract the d-axis current value id from the reference value id1 of the d-axis current.

[0114] The second subtraction unit 103 calculates the difference between the reference value iq1 and the q-axis current value iq (hereinafter also referred to as the q-axis current difference) by performing an operation to subtract the q-axis current value iq from the reference value iq1 of the q-axis current.

[0115] The reference values ​​id1 for the d-axis current and iq1 for the q-axis current described above are determined in the control device 10B by external commands from a higher-level controller (not shown) to the control device 10B. In other words, the control device 10B has the function of generating the reference values ​​id1 for the d-axis current and iq1 for the q-axis current based on external commands from the higher-level controller. Alternatively, the reference values ​​id1 for the d-axis current and iq1 for the q-axis current are stored in the control device 10B in advance by a program. Alternatively, the reference values ​​id1 for the d-axis current and iq1 for the q-axis current may be calculated in the control device 10B based on the angle (position) information of the AC load 15, etc.

[0116] The first PI control unit 104 generates a reference value Vd0 for the d-axis voltage to perform feedback control that brings the d-axis current difference value output from the first subtraction unit 102 closer to zero.

[0117] The second PI control unit 105 generates a reference value Vq0 for the q-axis voltage to perform feedback control that brings the q-axis current difference value output from the second subtraction unit 103 closer to zero.

[0118] The second conversion unit 106 includes, for example, an inverse dq conversion unit and a two-phase three-phase conversion unit, and converts the reference value Vd0 of the d-axis voltage and the reference value Vq0 of the q-axis voltage into the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0.

[0119] The adder 107 obtains the U-phase reference voltage value Va1, V-phase reference voltage value Vb1, and W-phase reference voltage value Vc1 by adding the bias voltage value Vbias to each of the U-phase command voltage value Va0, V-phase command voltage value Vb0, and W-phase command voltage value Vc0. That is, the adder 107 performs the calculations shown in equations (11), (12), and (13) below. Note that the U-phase reference voltage value Va1, V-phase reference voltage value Vb1, and W-phase reference voltage value Vc1 correspond to the target values ​​of the output voltages (phase voltages) of the three DC-DC converters 9u, 9v, and 9w. The value of the bias voltage value Vbias is, for example, an arbitrarily determined value. In the control device 10B, the value of the bias voltage value Vbias is determined to be, for example, a value larger than the amplitude of the U-phase command voltage value Va0.

[0120]

[0121]

[0122]

[0123] The voltage calculation unit 108 calculates the reference voltage value V2a of the second capacitor C2u, the reference voltage value V2b of the second capacitor C2v, and the reference voltage value V2c of the second capacitor C2w by performing calculations using the following equations (14), (15), and (16).

[0124]

[0125]

[0126]

[0127] In equations (14), (15), and (16), V3 can be expressed by equation (17).

[0128]

[0129] Furthermore, the third subtraction unit 109 calculates the difference between the reference voltage value V2a and the voltage V2a1 (hereinafter also referred to as the U-phase voltage difference) by subtracting the voltage V2a1 across the second capacitor C2u from the reference voltage value V2a of the second capacitor C2u. Furthermore, the third subtraction unit 109 calculates the difference between the reference voltage value V2b and the voltage V2b1 (hereinafter also referred to as the V-phase voltage difference) by subtracting the voltage V2b1 across the second capacitor C2v from the reference voltage value V2b of the second capacitor C2v. Furthermore, the third subtraction unit 109 calculates the difference between the reference voltage value V2c and the voltage V2c1 (hereinafter also referred to as the W-phase voltage difference) by subtracting the voltage V2c1 across the second capacitor C2w from the reference voltage value V2c of the second capacitor C2w. As described above, the reference voltage values ​​V2a, V2b, and V2c are obtained by calculation in the voltage calculation unit 108. The voltages V2a1, V2b1, and V2c1 across the second capacitors C2u, C2v, and C2w are, for example, voltages detected by three resistor voltage divider circuits (not shown) connected in parallel to each of the second capacitors C2u, C2v, and C2w.

[0130] The fourth subtraction unit 110 calculates the voltage difference between the reference voltage value V30 and the voltage across the third capacitor C3 by subtracting the voltage across the third capacitor C3 V3 from the reference voltage value V30 of the third capacitor C3.

[0131] The third PI control unit 111 generates a duty cycle command value da2 for performing feedback control to bring the U-phase voltage difference value output from the third subtraction unit 109 closer to zero. The third PI control unit 111 also generates a duty cycle command value db2 for performing feedback control to bring the V-phase voltage difference value output from the third subtraction unit 109 closer to zero. The third PI control unit 111 also generates a duty cycle command value dc2 for performing feedback control to bring the W-phase voltage difference value output from the third subtraction unit 109 closer to zero.

[0132] The fourth PI control unit 112 generates a duty cycle command value d3 for performing feedback control to bring the voltage difference value output from the fourth subtraction unit 110 closer to zero.

[0133] The duty cycle command value generation unit 113 assigns weights to the duty cycle command values ​​da2, db2, dc2, and d3, respectively, and calculates the duty cycle command values ​​da, db, and dc by the calculations of equations (18), (19), and (20), respectively. Here, the weights for the duty cycle command values ​​da2, db2, dc2, and d3 are ka, kb, kc, and k3. Here, the duty cycle command value generation unit 113 sets ka + k3 = 1, kb + k3 = 1, and kc + k3 = 1, and in a steady state where neither the target voltage nor the bias voltage (voltage V3 across the third capacitor C3) changes, ka = kb = kc and k3 = 0.

[0134]

[0135]

[0136]

[0137] An example of the operation of the duty cycle command value generation unit 113 will be explained based on the flowchart shown in Figure 13.

[0138] The duty cycle command value generation unit 113 confirms the command voltage value (step S1). The command voltage value includes an oscillation component and a bias component.

[0139] The duty cycle command value generation unit 113 compares the rate of change ΔV3 (bias component) of the voltage V3 across the third capacitor C3 and the rate of change ΔV2 (oscillating component) of the voltage V2 across the second capacitor C2 based on the command value voltage. If ΔV3 ≥ ΔV2 (step S2: Yes), it weights the duty cycle command value da2, db2, or dc2 (step S3) to obtain the duty cycle command values ​​da, db, and dc (step S4). On the other hand, if ΔV3 < ΔV2 (step S2: No), the duty cycle command value generation unit 113 weights the duty cycle command value d3 (step S3) to obtain the duty cycle command values ​​da, db, and dc (step S4).

[0140] For example, with respect to the command voltage value of the U phase, if the rate of change of the bias voltage is greater than the rate of change of the oscillation component, and the voltage V3 across the third capacitor C3 changes from, for example, 10V to 50V, then k3 = |50 - 10| / 50 = 0.8, and ka = 1 - 0.8 = 0.2. Also, with respect to the command voltage value of the V phase, if the rate of change of the bias voltage is greater than the rate of change of the oscillation component, and the voltage V3 across the third capacitor C3 changes from, for example, 10V to 50V, then k3 = |50 - 10| / 50 = 0.8, and kb = 1 - 0.8 = 0.2. Also, with respect to the command voltage value of the W phase, if the rate of change of the bias voltage is greater than the rate of change of the oscillation component, and the voltage V3 across the third capacitor C3 changes from 10V to 50V, then k3 = |50 - 10| / 50 = 0.8, and kc = 1 - 0.8 = 0.2.

[0141] If the duty cycle command value generation unit 113 does not satisfy the condition ΔV3 ≥ ΔV2 in step S2 (step S2: No), it weights the duty cycle command value d3 (step S5) to obtain duty cycle command values ​​da, db, and dc (step S4).

[0142] The duty cycle command values ​​da, db, and dc generated by the duty cycle command value generation unit 113 are used by the signal generation unit 114.

[0143] The signal generation unit 114 generates a plurality of first PWM signals G1, a plurality of second PWM signals G2, a plurality of third PWM signals G3, and a plurality of fourth PWM signals G4 using carrier signals CA1, CA2, CA3 and duty cycle command values ​​da, db, dc. More specifically, the signal generation unit 114 generates a first PWM signal G1u, a second PWM signal G2u, a third PWM signal G3u, and a fourth PWM signal G4u using carrier signal CA1 and duty cycle command value da. The signal generation unit 114 also generates a first PWM signal G1v, a second PWM signal G2v, a third PWM signal G3v, and a fourth PWM signal G4v using carrier signal CA2 and duty cycle command value db. Furthermore, the signal generation unit 114 generates the first PWM signal G1w, the second PWM signal G2w, the third PWM signal G3w, and the fourth PWM signal G4w using the carrier signal CA3 and the duty cycle command value dc. In this embodiment, the control device 10B sets the maximum value of each of the three carrier signals CA1, CA2, and CA3 to 1 and the minimum value to 0. The control device 10B also sets the maximum value of each of the duty cycle command values ​​da, db, and dc to 1 and the minimum value to 0.

[0144] (2) Advantages The power converter 100B according to Embodiment 3, like the power converter 100 according to Embodiment 1, includes a third capacitor C3 connected between the second terminals of a plurality of second capacitors C2 and the negative input terminal 12, making it possible to reduce the size while suppressing current ripple.

[0145] Furthermore, in the power converter 100B of Embodiment 3, the plurality of DC-DC converters 9 include three DC-DC converters 9. The control device 10B has a signal generation unit 114. The signal generation unit 114 generates a first PWM signal G1, a second PWM signal G2, a third PWM signal G3, and a fourth PWM signal G4 to control the first switching element 1, second switching element 2, third switching element 3, and fourth switching element 4 of each of the three DC-DC converters 9. When the signal generation unit 114 generates the first PWM signal G1, second PWM signal G2, third PWM signal G3, and fourth PWM signal G4 for each of the three DC-DC converters 9, it uses triangular wave carrier signals CA1, CA2, and CA3, which have different phases from each other, for each of the three DC-DC converters 9.

[0146] The above configuration makes it possible to improve responsiveness. Furthermore, the above configuration makes it possible to reduce the voltage ripple of the U-phase phase voltage Va, the V-phase phase voltage Vb, and the W-phase phase voltage Vc.

[0147] (Embodiment 4) The power converter 100C according to Embodiment 4 will be described with reference to Figure 14. With respect to the power converter 100C according to Embodiment 4, components that are the same as those in the power converter 100 according to Embodiment 1 (see Figure 1) are denoted by the same reference numerals and their description is omitted.

[0148] (1) In the power converter 100C according to the configuration embodiment 4, the first half-bridge circuit 21 of the three DC-DC converters 9 is common. That is, in the power converter 100C of this embodiment, the first half-bridge circuit 21 of the DC-DC converter 9u, the first half-bridge circuit 21 of the DC-DC converter 9v, and the first half-bridge circuit 21 of the DC-DC converter 9w are common. The power converter 100C of this embodiment has three second half-bridge circuits 22, while having only one first half-bridge circuit 21, and three inductors L1 are connected one by one between the connection point N1 of the first half-bridge circuit 21 and the connection point N2 of the three second half-bridge circuits 22.

[0149] Furthermore, the power converter 100C according to Embodiment 4 includes a control device 10C instead of the control device 10 of the power converter 100 according to Embodiment 1.

[0150] The control device 10C, like the control device 10, includes a computer system.

[0151] The control device 10C outputs one first PWM signal G1, one second PWM signal G2, multiple (three) third PWM signals G3, and multiple (three) fourth PWM signals G4, which control the on / off state of one first switching element 1, one second switching element 2, multiple (three) third switching elements 3, and multiple (three) fourth switching elements 4, respectively.

[0152] One first PWM signal G1 corresponds one-to-one with one first switching element 1.

[0153] One second PWM signal G2 corresponds one-to-one with one second switching element 2.

[0154] Multiple third PWM signals correspond one-to-one with multiple third switching elements 3. The multiple third PWM signals G3 include a third PWM signal G3u corresponding to a third switching element 3u, a third PWM signal G3v corresponding to a third switching element 3v, and a third PWM signal G3w corresponding to a third switching element 3w.

[0155] Multiple fourth PWM signals correspond one-to-one with multiple fourth switching elements 4. The multiple fourth PWM signals G4 include a fourth PWM signal G4u corresponding to a fourth switching element 4u, a fourth PWM signal G4v corresponding to a fourth switching element 4v, and a fourth PWM signal G4w corresponding to a fourth switching element 4w.

[0156] Each of the one first PWM signal G1, one second PWM signal G2, multiple third PWM signals G3, and multiple fourth PWM signals G4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level. The first switching element 1 is turned on when the first PWM signal G1 is at a high level and turned off when it is at a low level. The second switching element 2 is turned on when the second PWM signal G2 is at a high level and turned off when it is at a low level. Each of the multiple third switching elements 3 is turned on when the corresponding third PWM signal G3 among the multiple third PWM signals G3 is at a high level and turned off when it is at a low level. Each of the multiple fourth switching elements 4 is turned on when the corresponding fourth PWM signal G4 among the multiple fourth PWM signals G4 is at a high level and turned off when it is at a low level.

[0157] (2) Advantages The power converter 100C according to Embodiment 4, like the power converter 100 according to Embodiment 1, includes a third capacitor C3 connected between the second end of a plurality of second capacitors C2 and the negative input terminal 12, making it possible to reduce the size while suppressing current ripple.

[0158] In the power conversion device 100C according to Embodiment 4, the three DC-DC converters 9 share a common first half-bridge circuit 21.

[0159] With the above configuration, compared to the power conversion device 100 according to Embodiment 1, the number of first switching elements 1 and two second switching elements 2 can be reduced, making further miniaturization possible.

[0160] (Other Modifications) Embodiments 1 to 4 described above are merely one of many embodiments of this disclosure. Embodiments 1 to 4 described above can be modified in various ways depending on the design, etc., as long as the objectives of this disclosure are achieved.

[0161] For example, each of the multiple first switching elements 1, multiple second switching elements 2, multiple third switching elements 3, and multiple fourth switching elements 4 is not limited to n-channel MOSFETs, but may also be p-channel MOSFETs. Also, each of the multiple first switching elements 1, multiple second switching elements 2, multiple third switching elements 3, and multiple fourth switching elements 4 is a Si-based MOSFET, but is not limited to Si-based MOSFETs, but may also be, for example, a SiC-based MOSFET. Furthermore, each of the multiple first switching elements 1, multiple second switching elements 2, multiple third switching elements 3, and multiple fourth switching elements 4 is not limited to MOSFETs, but may also be, for example, an IGBT (Insulated Gate Bipolar Transistor) or a GaN-based GIT (Gate Injection Transistor).

[0162] Furthermore, in Embodiment 3, the control device 10B (see Figure 11) may, instead of the first PI control unit 104 that performs PI (Proportional Integral) control as the first feedback control unit that performs feedback control, include, for example, a P control unit that performs P (Proportional) control or a PID control unit that performs PID (Proportional Integral Differential) control.

[0163] Furthermore, in Embodiment 3, the control device 10B may, instead of the second PI control unit 105 that performs PI control, be equipped with, for example, a P control unit that performs P control or a PID control unit that performs PID control as a second feedback control unit that performs feedback control.

[0164] In Embodiment 3, the control device 10B may use the detected values ​​of phase voltage Va, phase voltage Vb, and phase voltage Vc for feedback control, in addition to the detected values ​​of phase current isa ia, phase current isb ib, and phase current isc ic.

[0165] (Aspects) The following aspects are disclosed in this specification.

[0166] The power converter (100; 100A; 100B; 100C) according to the first embodiment comprises a positive input terminal (11), a negative input terminal (12), a first capacitor (C1), a plurality of DC-DC converters (9), a plurality of output terminals (13), a plurality of second capacitors (C2), a third capacitor (C3), and a control device (10; 10A; 10B; 10C). The first capacitor (C1) is connected between the positive input terminal (11) and the negative input terminal (12). The plurality of DC-DC converters (9) are connected between the positive input terminal (11) and the negative input terminal (12). The plurality of output terminals (13) correspond one-to-one to the plurality of DC-DC converters (9). The plurality of output terminals (13) are connected to the corresponding DC-DC converter (9) among the plurality of DC-DC converters (9). Multiple second capacitors (C2) correspond one-to-one with multiple output terminals (13). Multiple second capacitors (C2) are connected to the corresponding output terminals (13) among the multiple output terminals (13). A third capacitor (C3) is connected in series with multiple second capacitors (C2). Control devices (10; 10A; 10B; 10C) control multiple DC-DC converters (9). Each of the multiple DC-DC converters (9) has a first half-bridge circuit (21), a second half-bridge circuit (22), and an inductor (L1). The first half-bridge circuit (21) is connected between the positive input terminal (11) and the negative input terminal (12). The first half-bridge circuit (21) has a first switching element (1) and a second switching element (2) connected in series with each other. The second half-bridge circuit (22) is connected between the corresponding output terminal (13) and the negative input terminal (12) among the plurality of output terminals (13). The second half-bridge circuit (22) has a third switching element (3) and a fourth switching element (4) connected in series with each other. The inductor (L1) is connected between the connection point (N1) between the first switching element (1) and the second switching element (2) and the connection point (N2) between the third switching element (3) and the fourth switching element (4). Each of the plurality of second capacitors (C2) has a first end and a second end.Each of the multiple second capacitors (C2) has its first end connected to the corresponding output terminal (13) among the multiple output terminals (13). The third capacitor (C3) is connected between the second ends of the multiple second capacitors (C2) and the negative input terminal (12).

[0167] This embodiment makes it possible to reduce ripple current while miniaturizing the device.

[0168] In the power converter (100A; 100B) according to the second embodiment, the plurality of DC-DC converters (9) in the first embodiment include three DC-DC converters (9). The control device (10A; 10B) has a signal generation unit (114; 124). The signal generation unit (114; 124) generates a first PWM signal (G1), a second PWM signal (G2), a third PWM signal (G3), and a fourth PWM signal (G4) to control the first switching element (1), second switching element (2), third switching element (3), and fourth switching element (4) of each of the three DC-DC converters (9). The signal generation unit (114; 124) generates a first PWM signal (G1), a second PWM signal (G2), a third PWM signal (G3), and a fourth PWM signal (G4) for each of the three DC-DC converters (9), using three triangular wave carrier signals (CA1, CA2, CA3) that correspond one-to-one with the three DC-DC converters (9) and have different phases from each other.

[0169] According to this embodiment, it is possible to improve responsiveness. Furthermore, according to this embodiment, it is possible to reduce the voltage ripple in the phase voltage of the U phase (Va), the phase voltage of the V phase (Vb), and the phase voltage of the W phase (Vc).

[0170] In the power converter (100A; 100B) according to the third embodiment, as in the second embodiment, the three triangular wave carrier signals (CA1, CA2, CA3) have a phase difference of 120 ± 30° from each other.

[0171] According to this embodiment, when the capacitance of each of the three second capacitors (C2) and the capacitance of the third capacitor (C3) are the same, it is possible to reduce the voltage ripple of the U-phase phase voltage (Va), the V-phase phase voltage (Vb), and the W-phase phase voltage (Vc). Furthermore, according to this embodiment, with respect to the voltage ripple of the U-phase phase voltage (Va), the V-phase phase voltage (Vb), and the W-phase phase voltage (Vc), it is possible to reduce it compared to the comparative example in which a smoothing capacitor (capacitor C20) having the same capacitance as the series circuit of the second capacitor (C2) and the third capacitor (C3) is connected to each of the three second half-bridge circuits (22).

[0172] In the power converter (100C) according to the fourth embodiment, the first half-bridge circuit (21) of the three DC-DC converters (9) is common to any one of the first to third embodiments.

[0173] According to this embodiment, further miniaturization becomes possible.

[0174] The power converter (100B) according to the fifth embodiment further includes a voltage detection circuit (17) for detecting the voltage of the third capacitor (C3) in any one of the first to fourth embodiments. The control device (10B) controls the gain with respect to the amplitude of the phase voltages (Va, Vb, Vc) and the gain with respect to the bias voltage of the phase voltages (Va, Vb, Vc) based on the values ​​detected by the voltage detection circuit (17).

[0175] According to this embodiment, it becomes possible to individually control the gain with respect to the amplitude of the phase voltage (Va, Vb, Vc) and the gain with respect to the bias voltage of the phase voltage (Va, Vb, Vc), thereby further improving responsiveness.

[0176] In the power converter according to the sixth embodiment (100; 100A; 100B; 100C), in any one of the first to fifth embodiments, the third capacitor (C3) is a polarized capacitor.

[0177] According to this embodiment, further miniaturization becomes possible.

[0178] 1 First switching element 2 Second switching element 3 Third switching element 4 Fourth switching element 11 Positive input terminal 12 Negative input terminal 13 Output terminal 17 Voltage detection circuit 21 First half-bridge circuit 22 Second half-bridge circuit 10, 10A, 10B, 10C Control device C1 First capacitor C2 Second capacitor C3 Third capacitor 100, 100A, 100B, 100C Power converter L1 Inductor N1 First connection point N2 Second connection point G1 First PWM signal G2 Second PWM signal G3 Third PWM signal G4 Fourth PWM signal

Claims

Positive input terminal and Negative input terminal and A first capacitor connected between the positive input terminal and the negative input terminal, A plurality of DC-DC converters connected between the positive input terminal and the negative input terminal, Multiple output terminals that correspond one-to-one with the aforementioned multiple DC-DC converters and are connected to the corresponding DC-DC converters, Multiple second capacitors, each corresponding to one of the aforementioned multiple output terminals and connected to the corresponding output terminals, A third capacitor connected in series with the plurality of second capacitors, The system comprises a control device for controlling the plurality of DC-DC converters, Each of the aforementioned plurality of DC-DC converters is A first half-bridge circuit having a first switching element and a second switching element connected in series with each other, is connected between the positive input terminal and the negative input terminal. A second half-bridge circuit having a third switching element and a fourth switching element connected in series with each other, which are connected between a corresponding output terminal among the plurality of output terminals and the negative input terminal. The system includes an inductor connected between the connection point of the first switching element and the second switching element and the connection point of the third switching element and the fourth switching element, Each of the plurality of second capacitors has a first end and a second end, Each of the plurality of second capacitors has its first end connected to a corresponding output terminal among the plurality of output terminals. The third capacitor is connected between the second terminal of the plurality of second capacitors and the negative input terminal. Power converter. 　 The aforementioned plurality of DC-DC converters include three DC-DC converters, The control device has a signal generation unit that generates a first PWM signal, a second PWM signal, a third PWM signal, and a fourth PWM signal to control the first switching element, the second switching element, the third switching element, and the fourth switching element of each of the three DC-DC converters, respectively. The signal generation unit, when generating the first PWM signal, the second PWM signal, the third PWM signal, and the fourth PWM signal for each of the three DC-DC converters, uses three triangular wave carrier signals that correspond one-to-one to the three DC-DC converters and have different phases from each other. The power conversion device according to claim 1. 　 The three triangular wave carrier signals have phases that differ from each other by 120 ± 30°. The power conversion device according to claim 2. 　 The first half-bridge circuit of the plurality of DC-DC converters is common to all of them. A power conversion device according to any one of claims 1 to 3. 　 The circuit further comprises a voltage detection circuit for detecting the voltage of the third capacitor, The control device controls the gain for the amplitude of the phase voltage and the gain for the bias voltage of the phase voltage based on the value detected by the voltage detection circuit. A power conversion device according to any one of claims 1 to 4. 　 The third capacitor is a polarized capacitor. A power conversion device according to any one of claims 1 to 5.

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