Imaging device and electronic apparatus

Abstract

[Problem] To provide an imaging device capable of further suppressing noise. [Solution] This imaging device comprises: a plurality of pixels arranged in columns in a first layer and having a charge-voltage conversion unit for converting charge corresponding to the amount of incident light into voltage, the plurality of pixels being configured from a plurality of pixel groups; a reference signal supply unit configured in a layer different from the first layer, and supplies a prescribed reference signal to the charge-voltage conversion unit; and a comparator configured in a second layer stacked on the first layer, the comparator comparing a prescribed reference voltage and the voltage of a signal line for transmitting an analog pixel signal output from a pixel to which the reference signal has been supplied. The signal line is configured from a plurality of first signal lines for each of the plurality of pixel groups.

Description

Imaging device and electronic equipment

[0001] This disclosure relates to imaging devices and electronic equipment.

[0002] The imaging device is equipped with an analog-to-digital conversion unit that digitizes the analog pixel signals read from the pixels. The analog-to-digital conversion unit installed in the imaging device consists of multiple analog-to-digital converters arranged in accordance with the pixel rows.

[0003] As an analog-to-digital converter that constitutes a column-parallel type analog-to-digital conversion unit, for example, a so-called single-slope type analog-to-digital converter is known, which digitizes an analog pixel signal by comparing the analog pixel signal read from the pixel with a predetermined reference signal.

[0004] Japanese Patent Publication No. 2022-87529

[0005] In an imaging device, pixel signals are supplied to an Analog-to-Digital (AD) conversion circuit via vertical signal lines that, at most, extend from one end of the pixel array in the column direction to the other end of the same column. Pixel signals transmitted via vertical signal lines are analog signals with a wide signal bandwidth, making them susceptible to noise.

[0006] This disclosure provides an imaging device capable of further suppressing noise.

[0007] To solve the above problems, the present disclosure provides an imaging device comprising: a plurality of pixels arranged in a row on a first layer, each having a charge-voltage conversion unit that converts charge to voltage according to the amount of incident light, and composed of a plurality of pixel groups; a reference signal supply unit configured on a layer different from the first layer and supplying a predetermined reference signal to the charge-voltage conversion unit; and a comparator configured on a second layer stacked on the first layer and comparing the voltage of a signal line that transmits an analog pixel signal output from the pixel to which the reference signal has been supplied with a predetermined reference voltage, wherein the signal line is composed of a plurality of first signal lines for each of the plurality of pixel groups.

[0008] The reference signal supply unit may supply the reference signal to the charge-voltage conversion unit via an input capacitive element.

[0009] The array further includes a second signal line that supplies the reference signal to the plurality of pixels arranged in a row, and the second signal line may be configured in the second layer.

[0010] The input capacitance element is configured in the first layer, and the input capacitance element and the second signal line may be electrically connected by a metal and a metal junction.

[0011] The system may further include a switch for switching the supply of the reference signal to the plurality of pixels arranged in a row.

[0012] The switch unit may be synchronized with the reading of the analog pixel signals from the plurality of pixels arranged in a row.

[0013] The second layer is further composed of multiple layers, and the comparator has a first-stage comparator and a second-stage comparator, the first-stage comparator is configured in any of the multiple layers, and the second-stage comparator may be configured in a layer among the multiple layers that is different from the layer in which the first-stage comparator is configured.

[0014] A single subsequent comparator may be connected to multiple initial comparators.

[0015] One of the first-stage comparators may be connected to the aforementioned pixel group.

[0016] The reference signal may be a voltage with a sloped waveform that changes linearly with a predetermined slope.

[0017] The comparator may compare the reference voltage with a signal voltage superimposed with a sloped waveform voltage supplied through the first signal line.

[0018] The plurality of pixels may be arranged in a matrix.

[0019] The reference signal generation unit may be commonly arranged for the plurality of pixels configured in the matrix.

[0020] The system may further include a clipping circuit that clips the voltage of the first signal line to a predetermined lower voltage level using the power supply voltage line of the pixel connected to the first signal line.

[0021] The system includes a selector that selects at least one of the multiple first-stage comparators, and the first-stage comparator selected by the selector may be connected to the subsequent comparator.

[0022] The system may further include a pre-charge circuit for pre-charging the output node of the first-stage comparator that was not selected by the selector.

[0023] The first-stage comparator may further include a voltage setting circuit that sets the corresponding first signal line to a predetermined voltage level when it is not connected to the subsequent-stage comparator.

[0024] According to this disclosure, an electronic imaging device is provided, comprising: a plurality of pixels arranged in a row on a first layer, each having a charge-voltage conversion unit that converts a charge corresponding to the amount of incident light into a voltage, and composed of a plurality of pixel groups; a reference signal supply unit configured on a layer different from the first layer and supplying a predetermined reference signal to the charge-voltage conversion unit; and a comparator configured on a second layer stacked on the first layer and comparing the potential of a signal line that transmits an analog pixel signal output from the pixel to which the reference signal has been supplied with a predetermined reference potential, wherein the signal line is composed of a plurality of first signal lines for each of the plurality of pixel groups.

[0025] A block diagram showing the configuration of an example of electronic equipment applicable to all embodiments. A block diagram showing the configuration of an example of an imaging device in each embodiment of this disclosure. A schematic diagram illustrating signal processing for pixel signals. A diagram showing an example of a stacked configuration of pixels and comparators. A circuit diagram showing an example of a pixel circuit configuration. A diagram showing a more detailed configuration example of pixels and comparators. A diagram showing the current path of the comparator when it is auto-zeroing. A diagram showing the current path of the comparator when it is AD-shifting. A timing chart for explaining the operation of the imaging device. A diagram conceptually illustrating the pulse signal of the comparator. A circuit diagram of the area around the comparator of the imaging device. A circuit diagram of the area around the first-stage comparator of the imaging device according to the first embodiment. A diagram explaining the operation of the clipping circuit. A circuit diagram of the area around the comparator of the imaging device according to the third embodiment. A diagram showing the voltage waveform of the signal line and the current waveform flowing through the power supply voltage line of the pixel. A circuit diagram of the area around the comparator of the imaging device according to the fourth embodiment. A diagram showing the current path during D-phase AD-shifting. A diagram showing the current path during P-phase AD-shifting. A diagram showing the voltage of the vertical signal line with and without a clipping circuit. Circuit diagram of the area around the comparator of the imaging device according to the fifth embodiment. Diagram showing an example of the stacked structure of the imaging device.

[0026] The following description will focus on the main components of the imaging device, but there may be other components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0027] (First Embodiment) Figure 1 is a block diagram showing the configuration of an example of an electronic device that can be applied to all embodiments. In Figure 1, the electronic device 1000 includes an optical system 1002, a control unit 1003, an imaging device 1004, an image processing unit 1005, a memory 1006, a storage unit 1007, a display unit 1008, an interface (I / F) unit 1009, and an input device 1012. Here, the electronic device 1000 can be a digital still camera, a digital video camera, a mobile phone or smartphone with imaging capabilities, etc. It is also possible to use a surveillance camera, an in-vehicle camera, a medical camera, etc., as the electronic device 1000.

[0028] The imaging device 1004 includes, for example, a plurality of photoelectric conversion elements arranged in a matrix. The photoelectric conversion elements convert received light into electric charge through photoelectric conversion. The imaging device 1004 includes a drive circuit for driving the plurality of photoelectric conversion elements, a signal processing circuit for reading the charge from each of the plurality of photoelectric conversion elements and generating image data based on the read charge, and a power supply circuit for supplying power to the drive circuit.

[0029] The optical system 1002 includes a main lens formed by a combination of one or more lenses, and a mechanism for driving the main lens, and forms an image of the image light (incident light) from the subject on the light-receiving surface of the imaging device 1004 via the main lens. The optical system 1002 also includes an autofocus mechanism that adjusts the focus according to a control signal, and a zoom mechanism that changes the zoom ratio according to a control signal. Furthermore, the electronic device 1000 may make the optical system 1002 detachable so that it can be replaced with other optical systems 1002.

[0030] The image processing unit 1005 performs predetermined image processing on the pixel data output from the imaging device 1004. For example, the image processing unit 1005 is connected to a memory 1006, such as a frame memory, and writes the image data output from the imaging device 1004 to the memory 1006. The image processing unit 1005 performs predetermined image processing on the pixel data written to the memory 1006 and writes the processed pixel data back to the memory 1006. The memory 1006 can store pixel data for one frame as image data.

[0031] The storage unit 1007 is a non-volatile memory such as flash memory or a hard disk drive, and stores the image data output from the image processing unit 1005 in a non-volatile manner. The display unit 1008 includes a display device such as an LCD (Liquid Crystal Display) and a drive circuit for driving the display device, and can display an image based on the image data output by the image processing unit 1005. The I / F unit 1009 is an interface for transmitting the image data output from the image processing unit 1005 to the outside. For example, a USB (Universal Serial Bus) can be used as the I / F unit 1009. However, it is not limited to this, and the I / F unit 1009 may be an interface that can connect to a network by wired communication or wireless communication.

[0032] The input device 1012 includes controls for receiving user input. If the electronic device 1000 is, for example, a digital still camera, a digital video camera, a mobile phone with an imaging function, or a smartphone, the input device 1012 may include a shutter button for instructing the imaging device 1004 to take an image, or controls for realizing the function of a shutter button.

[0033] The control unit 1003 includes a processor such as a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory), and controls the overall operation of the electronic device 1000 using the RAM as work memory according to a program pre-stored in the ROM. For example, the control unit 1003 can control the operation of the electronic device 1000 in response to user input received by the input device 1012. The control unit 1003 can also control the autofocus mechanism in the optical system 1002 based on the image processing results of the image processing unit 1005.

[0034] Figure 2 is a block diagram showing an example configuration of an imaging device 1004 in each embodiment of the present disclosure. In Figure 2, the imaging device 1004 includes a vertical scanning circuit 12, a timing control unit 13, a DAC (Digital to Analog Converter) 14, a pixel array unit 11, a column signal processing unit 15, and a horizontal scanning circuit 16. The imaging device 1004 can be configured as a CMOS image sensor (CIS) in which each of these parts is integrally formed using a CMOS (Complementary Metal Oxide Semiconductor).

[0035] Multiple pixels 10 are arranged in a matrix-like arrangement in the pixel array section 11. Hereafter, in the pixel array section 11, the horizontal direction in Figure 2 will be referred to as rows and the vertical direction as columns.

[0036] In the pixel array section 11, each pixel 10 includes a photoelectric conversion element that generates an electric charge in response to received light, and a pixel circuit that outputs a pixel signal based on the charge generated by the photoelectric conversion element. The vertical scanning circuit 12 drives each pixel 10 in the pixel array section 11 row by row and causes each pixel 10 to output a pixel signal. At this time, the vertical scanning circuit 12 drives each pixel 10 sequentially according to the row order and causes it to output a pixel signal. In other words, the vertical scanning circuit 12 functions as a readout control circuit that controls the reading of the charge from the photoelectric conversion element and the output of the pixel signal.

[0037] The timing control unit 13 controls the operating timing of the vertical scanning circuit 12, DAC 14, column signal processing unit 15, and horizontal scanning circuit 16 in synchronization with the vertical synchronization signal VSYNC. The vertical synchronization signal VSYNC is a periodic signal with a predetermined frequency (for example, 60 Hz) that indicates the imaging timing.

[0038] The DAC 14 generates a predetermined reference signal by DA (Digital to Analog) conversion. For example, a sawtooth-shaped ramp (RAMP) signal is used as the reference signal. The DAC 14 supplies the reference signal to each pixel 10 of the pixel array 11. The RAMP signal is a signal whose level (voltage value) increases (or decreases) in steps along a time series according to a predetermined clock pulse. In this embodiment, the DAC 14 corresponds to the reference signal supply unit.

[0039] The column signal processing unit 15 receives analog pixel signals from pixels 10 to which a reference signal has been applied, via vertical signal lines VSL provided for each column in the pixel array unit 11. The column signal processing unit 15 performs signal processing on the pixel signals for each column, such as AD (Analog to Digital) conversion and CDS (Correlated Double Sampling) processing. The column signal processing unit 15 outputs the processed digital pixel signals (pixel data). The pixel data output from the column signal processing unit 15 is supplied to the image processing unit 1005.

[0040] The horizontal scanning circuit 16 controls the column signal processing unit 15 to output pixel data from the column signal processing unit 15, for example, row by row in column order.

[0041] Figure 3 is a schematic diagram illustrating signal processing for pixel signals. In each embodiment of this disclosure, the comparator is divided into multiple circuits. In the example in Figure 3, the comparator 20 is divided into two circuits: a first-stage comparator 20a and a second-stage comparator 20b. The first-stage comparator 20a and the second-stage comparator 20b may be configured as a single unit, or they may be divided into three or more units.

[0042] The first-stage comparator 20a, the second-stage comparator 20b, the counter 30, and the logic circuit 40 are configured in the column signal processing unit 15. The column signal processing unit 15 is configured in a two-stage layered structure, with the first-stage comparator 20a in the first stage and the second-stage comparator 20b, the counter 30, and the logic circuit 40 in the second stage. Details of the first-stage comparator 20a and the second-stage comparator 20b will be described later.

[0043] The analog pixel signal, to which the RAMP signal output from pixel 10 is added, is supplied to comparator 20. Comparator 20 compares the pixel signal with a reference signal (REF signal) and supplies the comparison result to counter 30. For example, if the level of the pixel signal is lower than the level of the reference signal, comparator 20 outputs a Low difference signal to counter 30. On the other hand, if the level of the pixel signal is the same as or higher than the level of the reference signal, comparator 20 inverts its output and outputs a High difference signal to counter 30. The polarity of the output of comparator 20 is just an example, and the relationship between High and Low may be reversed depending on the comparator configuration.

[0044] The counter 30 counts the time from when the pixel signal starts to voltage drop until it reaches the same level as or higher than the reference signal, in accordance with the difference signal input from the comparator 20 during the P-phase (Preset Phase) period and the D-phase (Data Phase) period, and outputs the respective count results to the logic circuit 40. The P-phase period is the period during which the reset level of the pixel signal is detected in the CDS processing, and the D-phase period is the detection period during which the signal level of the pixel signal is detected in the CDS processing.

[0045] The logic circuit 40 performs CDS processing and AD conversion processing based on the count result of the P-phase period and the count result of the D-phase period input from the counter 30 to generate and output a digital pixel signal (pixel data).

[0046] Figure 4 shows an example of a stacked configuration of pixels and comparators. As shown in Figure 4, in the imaging device 1004 according to this embodiment, pixels 10, a first-stage comparator 20a, and a second-stage comparator 20b can be configured as a stacked semiconductor chip structure. For example, it is a structure in which three or more semiconductor chips are stacked. For example, pixels 10 are formed on the first layer semiconductor chip 2010, the first-stage comparator 20a is formed on the second layer semiconductor chip 2011, and the second-stage comparator 20b is formed on the third layer semiconductor chip 2012.

[0047] The DAC 14 is formed on the third layer semiconductor chip 2012. The reference signal generated by the DAC 14 is supplied to each pixel 10 via the vertical scanning circuit (RAMP) 18 and the ramp (RAMP) signal line Lr.

[0048] The first layer semiconductor chip 2010 and the second layer semiconductor chip 2011 are joined, for example, by CCCs (Copper-Copper Connections) 21a and 21b to transmit signals. The first layer semiconductor chip 2010 and the second layer semiconductor chip 2011 have two CCCs (metal-metal junctions) for each pixel 10. One CCC 21a is connected to the ramp signal line and is supplied with a reference signal from the vertical scanning circuit (RAMP) 18. The other CCC 21b is used to supply the pixel signal, to which the reference signal output from the pixel 10 has been added, to the first-stage comparator 20a of the second layer semiconductor chip 2011.

[0049] The second-layer semiconductor chip 2011 and the third-layer semiconductor chip 2012 each have two CCCs 21c for each first-stage comparator 20a. The CCCs 21c are used to supply the output signal of the first-stage comparator 20a to the subsequent comparator 20b.

[0050] Furthermore, the second layer semiconductor chip 2011 and the third layer semiconductor chip 2012 have a CCC 21d. The CCC 21d is used to supply the reference signal of the DAC 14 to the vertical scanning circuit (RAMP) 18. A process suitable for fabricating the pixel array section 11 can be applied to the first layer semiconductor chip 2010, a process suitable for fabricating the circuit portion of the first stage comparator 20a can be applied to the second layer semiconductor chip 2011, and a process suitable for fabricating the circuit portion of the subsequent stage comparator 20b can be applied to the third layer semiconductor chip 2012. This allows for process optimization in the manufacturing of the imaging device 1004. Note that in the following description, CCCs 21a to 21d may be omitted for the sake of simplifying the drawings.

[0051] Figure 5 is a circuit diagram showing an example of the circuit configuration of pixel 10. Pixel 10 has, for example, a photodiode 300 as a photoelectric conversion element. In addition to the photodiode 300, pixel 10 has a transfer transistor 301, a reset transistor 303, an amplification transistor 305, a selection transistor 306, and an input capacitance element 307. Note that in the following description, symbols within pixel 10 may be omitted for the sake of simplifying the diagram.

[0052] The four transistors, transfer transistor 301, reset transistor 303, amplification transistor 305, and selection transistor 306, are, for example, N-channel MOS field-effect transistors. However, the combination of conductivity types of the four transistors 301 to 306 exemplified here is merely an example and is not limited to these combinations.

[0053] Multiple pixel control lines are wired in common to each pixel 10 in the same pixel row from the vertical scanning circuit 12 (see Figure 2) to this pixel 10. These multiple pixel control lines are connected to the output terminals corresponding to each pixel row of the vertical scanning circuit 12, on a pixel row basis. The vertical scanning circuit 12 outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the multiple pixel control lines as appropriate.

[0054] The photodiode 300 has its anode electrode connected to a low-potential power supply (for example, ground), and it photoelectrically converts the received light into photocharges (in this case, photoelectrons) of an amount corresponding to the amount of light, and stores these photocharges. The cathode electrode of the photodiode 300 is electrically connected to the gate electrode of the amplification transistor 305 via a transfer transistor 301. Here, the region electrically connected to the gate electrode of the amplification transistor 305 is the floating diffusion region (impurity diffusion region) FD. The floating diffusion region FD is a charge-voltage conversion unit that converts charge into voltage.

[0055] One end of the input capacitance element 307 is connected to the floating diffusion FD, and the other end is connected to the CCC 21a. As a result, the reference signal generated by the DAC 14 is applied to the floating diffusion FD of each pixel 10 via the vertical scanning circuit (RAMP) 18 and the RAMP signal line.

[0056] A transfer signal TRG, which activates at a high level (e.g., VDD level), is supplied to the gate electrode of the transfer transistor 301 from the vertical scanning circuit 12. In response to the transfer signal TRG, the transfer transistor 301 becomes conductive, which is then photoelectrically converted by the photodiode 300, and the photocharge accumulated in the photodiode 300 is transferred to the floating diffusion FD.

[0057] The reset transistor 303 is connected between the node of the high-potential side power supply voltage VDD and the floating diffusion FD. A reset signal RST, which becomes active at a high level, is supplied to the gate electrode of the reset transistor 303 from the vertical scanning circuit 12. In response to the reset signal RST, the reset transistor 303 becomes conductive and resets the floating diffusion FD by discarding its charge to the node of voltage VDD.

[0058] The amplification transistor 305 has its gate electrode connected to the floating diffusion FD and its drain electrode connected to the node of the high-potential-side power supply voltage VDD, respectively. The amplification transistor 305 serves as the input part of a source follower that reads out the signal obtained by the photoelectric conversion in the photodiode 300. That is, the source electrode of the amplification transistor 305 is connected to the vertical signal line VSL via the selection transistor 306.

[0059] The selection transistor 306 has its drain electrode connected to the source electrode of the amplification transistor 305 and its source electrode connected to the vertical signal line VSL. A selection signal SEL at a high level to become active is supplied from the vertical scanning circuit 12 to the gate electrode of the selection transistor 306. The selection transistor 306 becomes conductive in response to the selection signal SEL, thereby putting the pixel 10 in a selected state and transmitting the signal output from the amplification transistor 305 to the vertical signal line VSL.

[0060] FIG. 6A is a diagram showing a more detailed configuration example of the pixel 10 and the comparator 20. The imaging device 1004 of the present disclosure includes, for example, a comparator (comparator) 20 composed of a P-channel MOS transistor and having an input transistor PT connected between one end of the vertical signal line VSL and the input-side load current source I11. １１ The comparator 20 has a first-stage comparator 20a configured between CCC21b and CCC21c and a second-stage comparator 20b configured after the CCC21c.

[0061] The comparator 20 includes an input transistor PT １１ , a capacitive element C ０１ , an auto-zero switch SW ＡＺ１ , SW ＡＺ２ , SW ＡＺ３ , a switching switch SW ＸＡＺ１ , SW ＸＡＺ２ , an input-side load current source I １１ , an input-side clamp transistor NT １２ , a comparator selection switch NT １３ , an output transistor PT １２ , a capacitive element C ０３ａ ·C ０３ｂOutput side load current source I １２ , and output amplifier transistor NT １４ The configuration includes the following: Capacitive element C ０１ The input transistor PT １１ It is connected between the gate electrode and a node with a predetermined reference voltage. Capacitive element C ０３ａ The output amplifier transistor NT １４ The gate electrode and the timing control unit 13 (see Figure 1) are connected to the input terminal T. １４ The drive signal V is input via ＳＨＩＦＴ It is connected between and . Capacitive element C ０３ｂ is a capacitive element C ０３ａ In parallel with this, the output amplifier transistor NT １４ It is connected between the gate electrode and a node with a predetermined reference voltage.

[0062] Input transistor PT １１ The source electrode is connected to one end of the vertical signal line VSL, and the changeover switch SW ＸＡＺ１ One end is connected in parallel, and the drain electrode is connected to the auto zero switch SW ＡＺ１ One aspect of it is the auto zero switch SW ＡＺ２ One part of it, and the changeover switch SW ＸＡＺ２ It is connected in parallel to one end of the auto zero switch SW. ＡＺ１ The other end is the input transistor PT １１ It is connected to the gate electrode of the toggle switch SW. ＸＡＺ２ The other end is a comparator selection switch NT １３ The source electrode and the input side clamp transistor NT １２ It is connected in parallel with the drain electrode. Also, the input side clamp transistor NT １２ The source electrode is the auto zero switch SW ＡＺ２ The other end and the changeover switch SW ＸＡＺ１ It is connected in parallel to the other end. Comparator selection switch NT １３ The drain electrode is connected to the input-side load current source I １１ It is connected to one end.

[0063] Auto Zero Switch SW ＡＺ１ SW ＡＺ２SW ＡＺ３ The on / off control is performed by a drive signal AZ input from the timing control unit 13 (see Figure 1) via the input terminal T12a. Also, the changeover switch SW ＸＡＺ１ SW ＸＡＺ２ The on / off control is performed by the drive signal XAZ input from the timing control unit 13 (see Figure 1) via the input terminal T12b. Furthermore, the comparator selection switch NT １３ The gate electrode is connected to the input terminal T from the timing control unit 13 (see Figure 1). １３ On / off control is performed by the drive signal CMSEL input via the comparator. When the comparator is in the active state, the comparator selection switch NT １３ When it turns on, the input transistor PT １１ The source electrode receives the analog pixel signal V through the vertical signal line VSL. ＶＳＬ The following is input. Auto Zero Switch SW ＡＺ１ SW ＡＺ２ SW ＡＺ３ , and changeover switch SW ＡＺ１ SW ＡＺ２ This can be constructed using P-channel or N-channel MOS transistors.

[0064] Input-side load current source I １１ One end is an input transistor PT １１ It is connected to the drain electrode, and the other end is connected to a low-potential power source, such as ground GND. Input-side load current source I １１ The input transistor PT １１ A constant current is supplied to the series connection circuit between the vertical signal line VSL and the vertical signal line VSL.

[0065] Figure 6B shows the current path during auto-zero when the comparator is operating. Auto-zero switch SW ＡＺ１ SW ＡＺ２ SW ＡＺ３ The toggle switch SW is turned ON. ＸＡＺ１ SW ＸＡＺ２ It is in the off state. Here, the input transistor PT １１ Capacitive element C in the thermal electrode ０１A fixed voltage (e.g., ground GND) is input as a predetermined reference voltage via the auto zero switch SW. ＡＺ１ When it turns on, it performs an auto-zero (initialization operation) that shorts the gate electrode and drain electrode of the input transistor PT11.

[0066] Input clamp transistor NT １２ This consists of, for example, an N-channel MOS transistor, with a voltage of bias 1 applied to the gate electrode. When auto-zero, the input transistor PT １１ From the input side clamp transistor NT １２ Current flows through it, and the initial value of the first-stage comparator output node V1STOUT is determined according to the voltage set by bias1. In other words, the initial value of V1STOUT at auto-zero can be determined independently of the VSL voltage, without using the VSL voltage as a reference. If this input-side clamp transistor NT １２ If not provided, the initial voltage of V1STOUT when auto-zero is set to the input transistor PT. １１ SW that shorts the gate and drain ＡＺ１ Auto-zero connection is performed, and the VSL voltage is used as the reference. In this case, the subsequent comparator 20b also needs to operate based on the VSL voltage, so the number of CCCs 21c is increased and the VSL wiring is extended to the layer of the subsequent comparator 20b, i.e., to the third layer semiconductor chip 2012, and then the output transistor PT １２ It becomes necessary to connect to the source electrode, increasing the VSL wiring load, which increases the time required for VSL settling and reduces the comparator's response speed. Input clamp transistor NT １２ This allows the initial voltage of the downstream comparator 20b at auto-zero to be determined independently of the VSL voltage, thereby preventing the VSL wiring from becoming redundant.

[0067] Figure 6C shows the current path during AD conversion (P phase and D phase). At this time, the auto zero switch SW ＡＺ１ SW ＡＺ２ SW ＡＺ３ The switch SW will be turned off. ＸＡＺ１ SWＸＡＺ２ is in the ON state. In this state, SW ＸＡＺ１ , SW ＸＡＺ２ , through which the drain electrode of the input-side clamp transistor NT １２ is connected to the source electrode of the input transistor PT １１ , and the source electrode is connected to the drain electrode of the input transistor PT １１ . Thus, during AD conversion, the input-side clamp transistor NT １２ [[ID=IS]]acts as a transistor that limits the lower limit of the drain voltage Vd of the input transistor PT11 regardless of the voltage of the vertical signal line VSL due to the voltage bias1 applied to the gate electrode, and can directly prevent the supply stop of the drain current.

[0068] As described above, the input transistor PT １１ outputs, as the V1STOUT voltage from the drain electrode, a first-stage comparator output signal indicating whether the voltage difference between the analog pixel signal V ＶＳＬ input to the source electrode through the vertical signal line VSL and the constant voltage input to the gate electrode exceeds a predetermined threshold voltage.

[0069] The parasitic capacitance C ０２ is the parasitic capacitance associated with the V1STOUT wiring, which is the output node of the first-stage comparator. The V1STOUT wiring corresponds to the first-stage output wiring 440 in FIG. 9 described later. As shown in FIG. 9, the V1STOUT wiring is a relatively long wiring shared among a plurality of comparators arranged in the vertical direction. By using the parasitic capacitance C ０２ associated with this wiring as a bandwidth limiting capacitance, the output noise of the comparator 20 can be reduced.

[0070] The output transistor PT １２ is composed of, for example, a P-channel MOS transistor. The source side is connected to the low-potential side power supply, for example, GND, and the drain side is connected between the source of the output-side amplifier transistor NT １４ . The gate electrode of the output transistor PT １２ is connected to the first-stage comparator output V1STOUT, and the source electrode is connected to the output-side load current source I through the output-side amplifier transistor NT １４ ​１２ is connected to one end thereof.

[0071] Output-side load current source I １２ has one end connected to the drain electrode of the output-side amplifier transistor NT １４ and the other end connected to a high-potential-side power source, for example, VDD. The output-side load current source I １２ supplies a constant current to the output transistor PT １２ and the output-side amplifier transistor NT １４

[0072] Output transistor PT １２ The gate electrode of is connected to the drain electrode of the input transistor PT ＸＡＺ２ by the switches SW １３ and NT １１ that are on during AD conversion. Thereby, the drain voltage of the input transistor PT １２ [[ID=2...]]is input to the gate electrode of the output transistor PT １１ Output transistor PT １２ and the load current source I １２ constitute a source follower. Therefore, the source voltage of PT １２ varies according to the voltage V1STOUT of the output of the first-stage comparator. The source voltage of the output transistor PT １２ is equal to the source voltage of the output-side amplifier transistor NT １４ [[ID=...]]Therefore, the source voltage of the output-side amplifier transistor NT １４ varies according to the voltage V1STOUT of the output of the first-stage comparator. Also, the output-side amplifier transistor NT １４ and the load current source I １２ constitute a gate-grounded amplifier with the source voltage of NT １４ as an input signal.

[0073] Auto-zero switch SW ＡＺ３ is connected to the gate electrode and the drain electrode of the output-side amplifier transistor NT １４ Here, a capacitive element C １４ is connected to the gate electrode of the output-side amplifier transistor NT ０３ｂ ​A fixed voltage (e.g., ground GND) is input as a predetermined reference voltage via the auto zero switch SW. ＡＺ３ When it turns on, the output amplifier transistor NT １４ The gate electrode and drain electrode of the transistor are short-circuited to perform an auto-zero (initialization operation). Meanwhile, the output offset transistor NT １４ The terminal electrode has a capacitive element C ０３ｂ Capacitive element C in parallel with ０３ａ The capacitive element C is connected. ０３ａ Through this, the timing control unit 13 (see Figure 1) transmits to the input terminal T １３ The drive signal V is input via ＳＨＩＦＴ A pulse signal is provided by this. This pulse signal changes from Low to High immediately after the auto-zero is completed, resulting in C ０３ａ and C ０３ｂ The offset voltage corresponding to the voltage division ratio is applied to the output amplifier transistor NT. １４ This is applied to the gate voltage. This allows you to adjust the threshold voltage at which the subsequent comparator inverts.

[0074] As described above, the output transistor PT １２ and output amplifier transistor NT １４ In the subsequent comparator 20b, an OUT signal indicating whether the output signal V1STOUT of the first stage comparator has exceeded a predetermined threshold voltage is transmitted to the output amplifier transistor NT. １４ From the drain electrode to the output terminal T １５ Output through this.

[0075] Figure 7 is a timing chart for explaining the operation of the imaging device. As described above, the DAC 14 has an input capacitive element 307 that is applied to the floating diffusion FD of the pixel 10 via a vertical scanning circuit (RAMP) 18 and a RAMP signal line.

[0076] The timing relationships between the selection signal SEL that drives the selection transistor 306 of pixel 10, the reset signal RST that drives the reset transistor 303, the transfer signal TRG that drives the transfer transistor 301, and the analog pixel signal VVSL are shown. The timing chart in Figure 7 further shows the reference signal V of the ramp wave applied to the floating diffusion FD. ＲＡＭＰ Auto Zero Switch SW ＡＺ The drive signal AZ and the pixel signal V after ramp wave superimposition. ＶＳＬ This shows the timing relationship.

[0077] By applying the ramp wave reference signal VRAMP generated by the DAC14 to the floating diffusion FD via the input capacitance element 307, the vertical signal line VSL is subjected to a pixel signal V, in which the ramp wave reference signal VRAMP is superimposed on the potential of the floating diffusion FD. ＶＳＬ The following is read out. Then, the comparator 20 reads out the reference signal V of the ramp wave, which is supplied through the vertical signal line VSL. ＲＡＭＰ The superimposed pixel signal V ＶＳＬ The voltage and the input transistor PT １１ A process is performed to compare the gate electrode with a predetermined reference voltage (for example, ground GND).

[0078] Figure 8 is a conceptual diagram showing the pulse signal of the comparator 20. As shown in Figure 8, the comparator 20 outputs a ramp wave reference signal V ＲＡＭＰ Based on the timing at which it crosses a predetermined reference voltage, the pixel signal V ＶＳＬ A pulse signal with a pulse width corresponding to the signal level, specifically a pulse width corresponding to the magnitude of the signal level, is compared to terminal T. １５ (See Figure 6) The output is generated from here.

[0079] As described above, according to this embodiment, by applying to the floating diffusion FD via the input capacitance element 307, the pixel signal V at the time of inversion of the comparator 20 ＶＳＬThe potential can be kept constant regardless of the light intensity. By keeping the inversion potential constant, the required operating range is narrowed, making it possible to reduce current consumption. Therefore, the power supply voltage can be lowered while maintaining the high frame rate of the three-layer stacked design, enabling further power reduction.

[0080] (Second Embodiment) The imaging device 1004 according to the second embodiment differs from the imaging device 1004 according to the first embodiment in that it is configured by dividing the vertical signal line VSL into multiple parts. The differences from the imaging device 1004 according to the first embodiment will be explained below.

[0081] Figure 9 is a circuit diagram of the area around the comparator 20 of the imaging device 1004 according to the second embodiment. The imaging device 1004 shown in Figure 9 shows an example of a three-layer structure. Pixels 10 are arranged on the first layer 2010. The first stage comparator 20a of the comparator 20 is arranged on the second layer 2011, which is stacked below the first layer 2010. The second stage comparator 20b of the comparator 20 is arranged on the third layer 2012, which is stacked below the second layer 2011.

[0082] In the example shown in Figure 9, the vertical signal line VSL differs from the imaging device 1004 according to the first embodiment in that it is divided into multiple sections along the vertical direction. Each of the divided vertical signal lines VSL is sometimes referred to as a divided VSL.

[0083] Each segmented VSL is connected to two or more pixels 10 arranged in the vertical direction (second direction). In addition, each segmented VSL is connected to the first-stage comparator 20a within a single comparator 20.

[0084] In the first-stage comparator 20a shown in Figure 9, the readout operation of the photoelectric conversion element 300 in the pixel 10 is controlled by the signals TRG1, RST1, and SEL1 supplied row by row from the vertical scanning circuit 12. The readout operation of the photoelectric conversion element 300 in the adjacent first-stage comparator 20a is controlled by the signals TRG2, RST2, and SEL2 supplied row by row from the vertical scanning circuit 12.

[0085] The first-stage comparator 20a is controlled by the inverted signals AZ (subscript omitted) and XAZ (subscript omitted), and the signal NCLP, which are supplied row by row from the vertical scanning circuit 12 by the first-stage comparator 20a. The connection between the first-stage comparator 20a and the middle-stage comparator input line 440 is controlled by the signal CMSEL (subscript omitted), which is supplied row by row from the vertical scanning circuit 12 by the first-stage comparator 20a.

[0086] The signals TRG, RST, SEL, CMSEL, and AZ (subscripts omitted) are supplied to the pixel 10, the first-stage comparator 20a, and the subsequent-stage comparator 20b via the vertical scanning circuit 12.

[0087] The downstream comparator 20b shown in Figure 9 includes PMOS transistors 380, 381, and 383, NMOS transistors 382 and 384, capacitors 385 and 386, and a NAND circuit 387.

[0088] The input line to the subsequent comparator 20b is connected to the gate of the PMOS transistor 383. The drain of the PMOS transistor 383 is connected to a first fixed potential, and its source is connected to the source of the NMOS transistor 382. The drain of the NMOS transistor 384 is connected to the drain of the NMOS transistor 382, ​​and the source of the NMOS transistor 384 is connected to the gate of the NMOS transistor 382. The signal AZ is input to the gate of the NMOS transistor 384. In addition, the signal V2ndshift is input via capacitor 386 to the connection point where the gate of the NMOS transistor 382 and the source of the NMOS transistor 384 are connected. In this way, the NMOS transistors 382 and 384 and the capacitor 386 constitute a comparator that performs a comparison operation with respect to the signal supplied from the input line to the subsequent comparator 20b.

[0089] Meanwhile, a bias voltage BaisP is input to the source of PMOS transistor 380, and its drain is connected to the gate of PMOS transistor 381. The other end of capacitor 385, one end of which is connected to a second fixed voltage, is connected to the connection point where the drain of PMOS transistor 380 and the gate of PMOS transistor 381 are connected. The source of PMOS transistor 381 is connected to the second fixed voltage, and its drain is connected to the drain of NMOS transistor 382.

[0090] An output signal is taken from the connection point where the drains of the PMOS transistor 381 and the NMOS transistor 382 are connected, and input to one input terminal of the NAND circuit 387. The signal STB is input to the other input terminal of the NAND circuit 387. Signal STB functions as a mask signal to mask signals that are unnecessary for comparator operation. Signal STB is generated, for example, in the logic circuit 40 of the memory + logic unit 2012. The output of the NAND circuit 387 becomes the output signal of the subsequent comparator 20b.

[0091] The output of the NAND circuit 387 is input to the counter. Alternatively, the circuit after the NAND circuit 387 may be designated as a third circuit.

[0092] In this embodiment, the ratio of the number of first-stage comparators 20a to the number of subsequent-stage comparators 20b is, for example, 2:1. Note that this ratio is not limited to 2:1; it may also be N:1, where N is a natural number greater than or equal to 1.

[0093] The reference (Ramp) signal output from the DAC 14 is supplied to the active (Active) pixel 10 via the vertical scanning circuit 18. It is also possible to supply reference (Ramp) signals for multiple rows, including the disabled (Disable) state.

[0094] Figure 10 shows an example configuration of the vertical scanning circuit 18 in Figure 9. As shown in Figure 10, the vertical scanning circuit 18 has a plurality of switches SW1 to SWN. Switches SW1 to SWN connect the pixels 10 of each row to the DAC 14. Switches SW1 to SWN synchronize with the vertical scanning circuit 12 according to the timing control of the timing control unit 13 (see Figure 2).

[0095] Figure 11 is a time chart showing an example of control for switches SW1 to SWN. The horizontal axis represents time, and the vertical axis shows the row-order signals for the selection transistor 306 of the vertical scanning circuit 12, indicated by SEL1 to SEL4, and the row-order signals for switches SW1 to SW4 of the timing control unit 13, indicated by SW1 to SW4. A high level indicates an ON signal, and a low level indicates an OFF signal.

[0096] At time t0, the selection transistor 306 of the first row of pixels 10 and the switch SW1 are connected, and the pixel signal VSL is read out via the vertical signal line VSL1. Next, at time t1, the selection transistor 306 of the second row of pixels 10 and the switch SW1 are connected, and the pixel signal VSL is read out via the vertical signal line VSL1. Next, at time t2, the selection transistor 306 of the third row of pixels 10 and the switch SW1 are connected, and the pixel signal VSL is read out via the vertical signal line VSL2. Next, at time t3, the selection transistor 306 of the fourth row of pixels 10 and the switch SW1 are connected, and the pixel signal VSL is read out via the vertical signal line VSL2.

[0097] Furthermore, the first-stage comparator 20a corresponding to the selected pixel 10 is activated by setting the gate voltage of the NMOS comparator selection switch 328 shown in Figure 9 to High. On the other hand, the first-stage comparator 20a corresponding to the unselected pixel 10 is disabled by setting the gate voltage of the comparator selection switch 328 to Low. The comparator outputs in the active state and the comparator outputs in the disabled state are connected via the comparator selection switch 328 to the intermediate input line 440, which is connected to a common current source 388. The current source 388 always drives the first-stage comparator 20a in the active state. In this way, by sharing one current source 388 among multiple first-stage comparators 20a arranged vertically and driving only the first-stage comparators 20a in the active state, power consumption is suppressed. Furthermore, since the DAC 14 is electrically connected to the pixel 10 that is in the operating (Active) state, it becomes possible to reduce the resistance and noise of the RAMP line.

[0098] (Third Embodiment) The imaging device 1004 according to the third embodiment differs from the imaging device 1004 according to the second embodiment in that it further includes a voltage setting circuit 28. The differences from the imaging device 1004 according to the second embodiment will be described below.

[0099] Figure 12 is a circuit diagram of the area around the comparator 20 of the imaging device 1004 according to the third embodiment. The imaging device 1004 shown in Figure 12 further includes a voltage setting circuit 28.

[0100] As shown in Figure 12, the voltage setting circuit 28 has a PMOS transistor 393 and an NMOS transistor 394 connected between the power line and the ground line. The power supply voltage of the power line is the same as the power supply voltage of the power line of the pixel 10. The DMYSF_SW1 signal is input to the gate of the PMOS transistor 393.

[0101] The VANA signal is input to the gate of the NMOS transistor 394. The NMOS transistor 394 is a source follower circuit. Therefore, when the DMYSF_SW1 signal goes low, the PMOS transistor 393 turns on, and the divided VSL becomes a voltage level corresponding to the voltage level of the VANA signal. The DMYSF_SW1 signal becomes high only in the first-stage comparator 20a in the active state among the multiple first-stage comparators 20a connected to the divided VSL. In other words, each of the multiple first-stage comparators 20a connected to the divided VSL is input to a different DMYSF_SW signal. The voltage level of the VSL of the first-stage comparator 20a can be adjusted according to the voltage level of the VANA signal.

[0102] Transistors 393 and 394 are source follower circuits having the same electrical characteristics as the amplification transistor 305 and selection transistor 306 within the pixel 10.

[0103] Figure 13 shows the voltage waveform of the divided VSL shown in Figure 12 and the current waveform flowing through the power supply voltage line VDDH of the pixel 10. The horizontal axis represents time, and the vertical axis represents the voltage of the vertical signal line VSL2 and the power supply current of the pixel 10 connected to the vertical signal line VSL2. Between times t4 and t5, the pixel 10 connected to the vertical signal line VSL2 is in an unselected state. In this case, the voltage of the vertical signal line VSL2 and the power supply current of the pixel 10 are maintained at constant values.

[0104] On the other hand, between times t5 and t6, one of the pixels 10 connected to the vertical signal line VSL2 is selected. In this case, a fluctuation occurs immediately after time t5 depending on the amount of light received, but then it becomes a constant value. Because it transitions from an inactive state to an active state at time t5, the voltage level of the divided VSL fluctuates slightly, but the amount of fluctuation is not very large.

[0105] By configuring the voltage setting circuit 28 in this way, it becomes possible to adjust the voltage level of the vertical signal line VSL of the non-selected first-stage comparator 20a.

[0106] (Fourth Embodiment) The imaging device 1004 according to the fourth embodiment differs from the imaging device 1004 according to the second embodiment in that it further includes a clipping circuit 2. The differences from the imaging device 1004 according to the second embodiment will be described below.

[0107] Figure 14 is a circuit diagram of the area around the comparator 20 of the imaging device 1004 according to the fourth embodiment. The imaging device 1004 shown in Figure 14 further includes a clipping circuit 2. The clipping circuit 2 is configured within the first-stage comparator 20a.

[0108] The clipping circuit 2 uses one of the power supply voltage lines VDDH of two or more pixels 10 connected to the divided VSL to clip the voltage of the divided VSL to a predetermined lower voltage level. By providing the clipping circuit 2, the voltage level of the divided VSL will not drop too low below the predetermined lower voltage level, and the settling time of the divided VSL can be shortened.

[0109] The clipping circuit 2 has two NMOS transistors 111 and 112 connected between the power supply voltage line VDD of the pixel 10 connected to the divided VSL and the power supply line of the first-stage comparator 20a. The VCCP signal is input to the gate of NMOS transistor 111, and the CLPSEL signal is input to the gate of NMOS transistor 112. In Figure 14, subscripts are added after VCCP and CLPSEL, but in this specification, the subscripts are omitted. The VCCP signal is a signal that indicates the clipping voltage of the divided VSL. When indicating the clipping voltage of the divided VSL, a voltage corresponding to the lower limit voltage of the VSL is set. The CLPSEL signal becomes high when selecting a specific divided VSL to set to the lower limit voltage level. The CLPSEL signal is provided separately for each individual clipping circuit 2.

[0110] When the VCCP signal voltage is set and the CLPSEL signal reaches a high level, the NMOS transistor 112 turns on, and current flows from the power supply voltage line VDDH of the pixel 10 connected to the divided VSL to the clipping circuit 2.

[0111] As shown in Figure 14, the output node of the clipping circuit 2 is connected to the input node of the first-stage comparator 20a and the current source 388. When the NMOS transistor 112 in the clipping circuit 2 is turned on, current flows from the power supply voltage line VDDH of the pixel 10 connected to the divided VSL through the clipping circuit 2 to the current source 388, and the divided VSL is clipped to a predetermined lower limit voltage level corresponding to the gate voltage VCCP voltage of the NMOS transistor 111. Also, when at least one transistor in the clipping circuit 2 is off, no current flows from the power supply voltage line VDDH to the clipping circuit 2, and therefore the divided VSL is not clipped. The voltage level of the VSL of the first-stage comparator 20a in the active state can be adjusted by the voltage level of the VCCP signal.

[0112] Figure 15 shows the current path during D-phase AD conversion. Figure 16 shows the current path during P-phase AD conversion. Figure 17 shows the voltage of the vertical signal line with and without the clipping circuit 2. The horizontal axis is time, and the vertical axis is voltage. At time t7, the phase changes from P-phase to D-phase. By configuring the clipping circuit 2, the voltage of the vertical signal line V ＳＬ By limiting the lower voltage, it becomes possible to suppress the occurrence of current source failure in the event of an excessive signal input.

[0113] (Fifth Embodiment) The imaging device 1004 according to the fifth embodiment differs from the imaging device 1004 according to the second embodiment in that it further includes a first selector 23 and a pre-charge circuit 25. The differences from the imaging device 1004 according to the second embodiment will be described below.

[0114] Figure 18 is a circuit diagram of the area around the comparator 20 of the imaging device 1004 according to the fifth embodiment. The imaging device 1004 shown in Figure 18 further includes a first selector 23 and a precharge circuit 25.

[0115] As shown in Figure 18, the output wiring of multiple first-stage comparators 20a connected to multiple divided VSLs is divided into multiple sets, and a first selector 23 is provided to select one of the multiple sets. In addition, each set contains the output wiring of two or more first-stage comparators 20a, and a second selector 24 is provided to select one of the two or more output wirings of first-stage comparators 20a in each set.

[0116] As shown in Figure 18, by providing a first selector 23 and a second selector 24 between the multiple first-stage comparators 20a and one subsequent-stage comparator 20b of the comparator 20, the output signals of the first-stage comparators 20a selected by the first selector 23 and the second selector 24 are input to the subsequent-stage comparator 20b. Since the first selector 23 divides the output nodes of the multiple first-stage comparators 20a into multiple sets, the load on the input wiring of the subsequent-stage comparator 20b can be reduced.

[0117] (Sixth Embodiment) The imaging device according to the sixth embodiment is an example of the stacked structure of the imaging device 1004. Figure 19 is a diagram showing an example of the stacked structure of the imaging device 1004. As shown in Figure 19, the imaging device 1004 has a stacked structure in which a light-collecting layer 3090, a first semiconductor layer 3020, a first wiring layer 3030, a second wiring layer 3040, a second semiconductor layer 3050, a third wiring layer 3060, a fourth wiring layer 3070, and a third semiconductor layer 3080 are stacked in this order.

[0118] The light-gathering layer 3090 has a stacked structure in which, for example, a color filter 3091 and an on-chip lens 3092 are stacked in that order, starting from the second surface S2 side of the first semiconductor layer 3020. The first semiconductor layer 3020 has a photoelectric conversion region, which will be described later, and one surface is the first surface S1 and the other surface is the second surface S2 which is the light incident surface. The first wiring layer 3030 is superimposed on the first surface S1 of the first semiconductor layer 3020. The second wiring layer 3040 is superimposed on the surface of the first wiring layer 3030 opposite to the surface on the first semiconductor layer 3020 side. The second semiconductor layer 3050 has multiple transistors, one surface is the third surface S3 and the other surface is the fourth surface S4, and the third surface S3 is superimposed on the surface of the second wiring layer 3040 opposite to the surface on the first wiring layer 3030 side. The third wiring layer 3060 is superimposed on the fourth surface S4 of the second semiconductor layer 3050. The fourth wiring layer 3070 is superimposed on the surface of the third wiring layer 3060 opposite to the surface facing the second semiconductor layer 3050. The fifth surface S5 of the third semiconductor layer 3080 is superimposed on the surface of the fourth wiring layer 3070 opposite to the surface facing the third wiring layer 3060.

[0119] Here, the first surface S1 of the first semiconductor layer 3020 is sometimes called the device formation surface or main surface, and the second surface S2 of the first semiconductor layer 3020 is sometimes called the light incident surface or back surface. Also, the third surface S3 of the second semiconductor layer 3050 is sometimes called the device formation surface or main surface, and the fourth surface S4 of the second semiconductor layer 3050 is sometimes called the back surface. Furthermore, the fifth surface S5 of the third semiconductor layer 3080 is sometimes called the device formation surface or main surface, and the surface opposite to the fifth surface S5 is sometimes called the back surface.

[0120] Furthermore, the first semiconductor layer 3020 and the second semiconductor layer 3050 are joined via the first wiring layer 3030 and the second wiring layer 3040 using the F2F (Face to Face) method, that is, so that the device formation surfaces face each other. In addition, the second semiconductor layer 3050 and the third semiconductor layer 3080 are joined via the third wiring layer 3060 and the fourth wiring layer 3070 using the B2F (Back to Face) method, that is, so that the back surface and the device formation surface face each other.

[0121] (First Semiconductor Layer) The first semiconductor layer 3020 is made of a semiconductor substrate. The first semiconductor layer 3020 is made of a single-crystal silicon substrate of a first conductivity type, for example, p-type. In addition, a bonding pad 3014 is provided in the region of the first semiconductor layer 3020 that overlaps with the peripheral region 3002B in a plan view. In the region of the first semiconductor layer 3020 that overlaps with the pixel region, a photoelectric conversion region 3020a is provided for each pixel 3003. For example, an island-shaped photoelectric conversion region 3020a partitioned by a separation region 3020b is provided for each pixel 3003. Note that the number of pixels 3003 is not limited to that shown in Figure 32A.

[0122] The photoelectric conversion region 3020a, although not shown in the figure, has a well region of a first conductivity type, for example, p-type, and a semiconductor region (photoelectric conversion section) of a second conductivity type, for example, n-type, embedded inside the well region. The photoelectric conversion element 300 shown in Figure 5 is configured as a photoelectric conversion region 3020a including the well region of the first semiconductor layer 3020 and the photoelectric conversion section. The photoelectric conversion region 3020a may also be provided with a charge storage region (not shown), which is a semiconductor region of a second conductivity type, for example, n-type, and a transistor T1, although this is not limited to the above.

[0123] The isolation region 3020b, while not limited to this, may have a trench structure in which an isolation groove is formed in the first semiconductor layer 3020 and an insulating film is embedded within this isolation groove. In the example shown in Figure 32A, an insulating film and a metal are embedded within the isolation groove.

[0124] (First Wiring Layer) The first wiring layer 3030 includes an insulating film 3031, wiring 3032, a first connection pad 3033, and vias (contacts) 3034. The wiring 3032 and the first connection pad 3033 are laminated via the insulating film 3031 as shown in the figure. The first connection pad 3033 faces the side of the first wiring layer 3030 opposite to the first semiconductor layer 3020. The vias 3034 connect the first semiconductor layer 3020 to the wiring 3032, to each other, and to the wiring 3032 to the first connection pad 3033, etc. The wiring 3032 and the first connection pad 3033 are not limited to these, but for example they may be made of copper and formed by the damascene process.

[0125] (Second Wiring Layer) The second wiring layer 3040 includes an insulating film 3041, wiring 3042, a second connection pad 3043, and vias (contacts) 3044. The wiring 3042 and the second connection pad 3043 are laminated via the insulating film 3041 as shown in the figure. The second connection pad 3043 faces the side of the second wiring layer 3040 opposite to the second semiconductor layer 3050 and is joined to the first connection pad 3033. The vias 3044 connect the second semiconductor layer 3050 to the wiring 3042, to each other, and to the wiring 3042 and the second connection pad 3043, etc. The wiring 3042 and the second connection pad 3043 are not limited to these, but for example they may be made of copper and formed by the damascene process.

[0126] (Second Semiconductor Layer) The second semiconductor layer 3050 is made of a semiconductor substrate. The second semiconductor layer 3050 is made of a single-crystal silicon substrate, although it is not limited to this. The second semiconductor layer 3050 exhibits a first conductivity type, for example, p-type. Multiple transistors T2 are provided in the second semiconductor layer 3050. More specifically, the transistors T2 are provided in the region of the second semiconductor layer 3050 that overlaps with the pixel region. In order to distinguish between the region of the second semiconductor layer 3050 that overlaps with the pixel region in a plan view and the region that overlaps with the peripheral region of the pixel region in a plan view, the region that overlaps with the peripheral region 3002B is called the first region 3050a, and the region that overlaps with the pixel region 3002A is called the second region 3050b.

[0127] (First and Second Conductors) The second semiconductor layer 3050 is provided with a first conductor 3051 and a second conductor 3052. More specifically, the first region 3050a is provided with a first conductor 3051 having a first width, made of a first material, and penetrating the second semiconductor layer 3050 along the thickness direction. The second region 3050b is provided with a second conductor 3052 having a second width smaller than the first width, made of a second material different from the first material, and penetrating the second semiconductor layer 3050 along the thickness direction. The first conductor 3051 and the second conductor 3052 are conductors (electrodes) that penetrate the semiconductor layer. In this embodiment, since the semiconductor layer is made of silicon, the first conductor 3051 and the second conductor 3052 are through-silicon vias (TSVs).

[0128] The first conductor 3051 is not limited to this, but can be used, for example, as a power line. For this reason, it is preferable that the first conductor 3051 has low electrical resistance. Therefore, it is preferable to use a conductive material with low electrical resistivity as the first material constituting the first conductor 3051. Here, copper, which is an example of such a conductive material, is used as the first material. In addition, the resistance of the first conductor 3051 can be reduced by increasing the first width. The first region 3050a on which the first conductor 3051 is provided has a low density of elements and wiring, so the first width can be increased.

[0129] Since the second conductor 3052 is provided in the second region 3050b where multiple transistors T2 are provided, it may be necessary to provide the second conductor 3052 in a narrow region between the transistors T2. For this reason, it is necessary to reduce the second width. Reducing the second width increases the aspect ratio of the second conductor 3052. The aspect ratio of the second conductor 3052 is not limited to this, but may be 5 or more, for example. With such an aspect ratio, it may be difficult to embed it using the same material as the first material (here, for example, copper). Therefore, it is preferable to use a conductive material with good embedding properties for holes with a high aspect ratio as the second material constituting the second conductor 3052. Examples of such conductive materials include high-melting-point metals. Examples of high-melting-point metals include tungsten (W), cobalt (Co), ruthenium (Ru), or metallic materials containing at least one of these. Here, tungsten is used as the second material.

[0130] Furthermore, this technology can take the following configuration: (1) An imaging device comprising: a plurality of pixels arranged in a row on a first layer, each having a charge-voltage conversion unit that converts charge to voltage according to the amount of incident light, and composed of a plurality of pixel groups; a reference signal supply unit configured on a layer different from the first layer and supplying a predetermined reference signal to the charge-voltage conversion unit; and a comparator configured on a second layer stacked on the first layer, which compares the voltage of a signal line that transmits an analog pixel signal output from the pixel to which the reference signal has been supplied with a predetermined reference voltage, wherein the signal line is composed of a plurality of first signal lines for each of the plurality of pixel groups.

[0131] (2) The imaging apparatus according to (1), wherein the reference signal supply unit supplies the reference signal to the charge-voltage conversion unit via an input capacitive element.

[0132] (3) The imaging apparatus according to (2), further comprising a second signal line that supplies the reference signal to the plurality of pixels arranged in a row, wherein the second signal line is configured in the second layer.

[0133] (4) The imaging apparatus according to (3), wherein the input capacitance element is configured in the first layer, and the input capacitance element and the second signal line are electrically connected by a metal and a metal junction.

[0134] (5) The imaging apparatus according to (4), further comprising a switch unit for switching the supply of the reference signal to the plurality of pixels arranged in a row.

[0135] (6) The imaging apparatus according to (5), wherein the switch unit is synchronized with the reading of the analog pixel signals from the plurality of pixels arranged in a row.

[0136] (7) The imaging apparatus according to (6), wherein the second layer is further composed of a plurality of layers, the comparator comprises a first-stage comparator and a second-stage comparator, the first-stage comparator is configured in any of the plurality of layers, and the second-stage comparator is configured in a layer among the plurality of layers that is different from the layer in which the first-stage comparator is configured.

[0137] (8) The imaging apparatus according to (7), wherein one of the subsequent comparators is connected to a plurality of the initial comparators.

[0138] (9) The imaging apparatus according to (8), wherein one of the first-stage comparators is connected to the pixel group.

[0139] (10) The imaging apparatus according to (9), wherein the reference signal is a voltage of a sloped waveform that changes linearly with a predetermined slope.

[0140] (11) The imaging apparatus according to (10), wherein the comparator compares a signal voltage having a sloped waveform superimposed on it, supplied through the first signal line, with the reference voltage.

[0141] (12) The imaging device according to (11), wherein the plurality of pixels are arranged in a matrix.

[0142] (13) The imaging apparatus according to (12), wherein the reference signal generation unit is arranged in common for the plurality of pixels arranged in the matrix.

[0143] (14) The imaging apparatus according to (13), further comprising a clipping circuit that clips the voltage of the first signal line to a predetermined lower limit voltage level using the power supply voltage line of the pixel connected to the first signal line.

[0144] (15) The imaging apparatus according to (13), having a selector that selects at least one of a plurality of first-stage comparators, wherein the first-stage comparator selected by the selector is connected to the subsequent comparator.

[0145] (16) The imaging apparatus according to (15), further comprising a pre-charge circuit for pre-charging the output node of the first-stage comparator that was not selected by the selector.

[0146] (17) The imaging apparatus according to (16), further comprising a voltage setting circuit that sets the corresponding first signal line to a predetermined voltage level when the first stage comparator is not connected to the subsequent stage comparator.

[0147] (18) An electronic imaging device comprising: a plurality of pixels arranged in a row on a first layer, each having a charge-voltage conversion unit that converts a charge corresponding to the amount of incident light into a voltage, and composed of a plurality of pixel groups; a reference signal supply unit configured on a layer different from the first layer and supplying a predetermined reference signal to the charge-voltage conversion unit; and a comparator configured on a second layer stacked on the first layer and comparing the potential of a signal line that transmits an analog pixel signal output from the pixel to which the reference signal has been supplied with a predetermined reference potential, wherein the signal line is composed of a plurality of first signal lines for each of the plurality of pixel groups.

[0148] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0149] 2: Clipping circuit, 10: Pixel, 14: DAC (Reference Signal Supply Unit), 20: Comparator, 20a: First-stage comparator, 20b: Second-stage comparator, 1000: Electronic equipment, 1004: Imaging device, 2010: First-layer semiconductor chip, 2011: Second-layer semiconductor chip, 2012: Third-layer semiconductor chip, 21a-21d: CCC (Metal and Metal Junction), FD: Floating Diffusion (Charge-Voltage Conversion Unit), VSL: Vertical signal line (First signal line)

Claims

1. An imaging device comprising: a plurality of pixels arranged in a row on a first layer, each having a charge-voltage conversion unit that converts charge to voltage according to the amount of incident light, and composed of a plurality of pixel groups; a reference signal supply unit configured on a layer different from the first layer and supplying a predetermined reference signal to the charge-voltage conversion unit; and a comparator configured on a second layer stacked on the first layer and comparing the voltage of a signal line that transmits an analog pixel signal output from the pixel to which the reference signal has been supplied with a predetermined reference voltage, wherein the signal line is composed of a plurality of first signal lines for each of the plurality of pixel groups.

2. The imaging apparatus according to claim 1, wherein the reference signal supply unit supplies the reference signal to the charge-voltage conversion unit via an input capacitive element.

3. The imaging apparatus according to claim 2, further comprising a second signal line that supplies the reference signal to the plurality of pixels arranged in a row, wherein the second signal line is configured in the second layer.

4. The imaging apparatus according to claim 3, wherein the input capacitance element is configured in the first layer, and the input capacitance element and the second signal line are electrically connected by a metal and a metal junction.

5. The imaging apparatus according to claim 4, further comprising a switch unit for switching the supply of the reference signal to the plurality of pixels arranged in a row.

6. The imaging apparatus according to claim 5, wherein the switch unit is synchronized with the reading of the analog pixel signals from the plurality of pixels arranged in a row.

7. The imaging apparatus according to claim 6, wherein the second layer is further composed of a plurality of layers, the comparator comprises a first-stage comparator and a second-stage comparator, the first-stage comparator is configured in any of the plurality of layers, and the second-stage comparator is configured in a layer among the plurality of layers that is different from the layer in which the first-stage comparator is configured.

8. The imaging apparatus according to claim 7, wherein one of the subsequent comparators is connected to a plurality of the initial comparators.

9. The imaging apparatus according to claim 8, wherein one of the first-stage comparators is connected to the pixel group.

10. The imaging apparatus according to claim 9, wherein the reference signal is a voltage of a sloped waveform that changes linearly with a predetermined slope.

11. The imaging apparatus according to claim 10, wherein the comparator compares a signal voltage superimposed with a sloped waveform voltage supplied through the first signal line with the reference voltage.

12. The imaging apparatus according to claim 11, wherein the plurality of pixels are arranged in a matrix.

13. The imaging apparatus according to claim 12, wherein the reference signal generation unit is commonly arranged for the plurality of pixels configured in a matrix.

14. The imaging apparatus according to claim 13, further comprising a clipping circuit that clips the voltage of the first signal line to a predetermined lower limit voltage level using the power supply voltage line of the pixel connected to the first signal line.

15. The imaging apparatus according to claim 13, comprising a selector that selects at least one of a plurality of first-stage comparators, wherein the first-stage comparator selected by the selector is connected to the subsequent comparator.

16. The imaging apparatus according to claim 15, further comprising a pre-charge circuit for pre-charging the output node of the first-stage comparator that was not selected by the selector.

17. The imaging apparatus according to claim 16, further comprising a voltage setting circuit that sets the corresponding first signal line to a predetermined voltage level when the first stage comparator is not connected to the subsequent stage comparator.

18. An electronic imaging device comprising: a plurality of pixels arranged in a row on a first layer, each having a charge-voltage conversion unit that converts charge to voltage according to the amount of incident light, and composed of a plurality of pixel groups; a reference signal supply unit configured on a layer different from the first layer and supplying a predetermined reference signal to the charge-voltage conversion unit; and a comparator configured on a second layer stacked on the first layer and comparing the potential of a signal line that transmits an analog pixel signal output from the pixel to which the reference signal has been supplied with a predetermined reference potential, wherein the signal line is composed of a plurality of first signal lines for each of the plurality of pixel groups.

Images