Semiconductor module

Abstract

A semiconductor module (1) comprises a semiconductor element (10) that has a surface electrode (12), a wiring board (20), a main current wiring (W1) that is joined to the surface electrode (12) and the wiring board (20), and an auxiliary conductor (W2) that is joined only to the surface electrode (12).

Description

Semiconductor module

[0001] The present invention relates to a semiconductor module including a main current wiring joined to a surface electrode of a semiconductor element and a wiring board.

[0002] Conventionally, in a semiconductor module used in a power conversion device or the like, a plurality of circuit layers separated from each other are provided on an insulating layer on a wiring board (see, for example, Patent Documents 1 and 2). Semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are mounted on the circuit layers and connected to other circuit layers by main current wirings such as aluminum wires.

[0003] Japanese Patent Application Laid-Open No. 2008-186957 Japanese Patent Application Laid-Open No. 2003-218155

[0004] By the way, the inrush current flowing from the main current wiring into the semiconductor element is divided into a current flowing from a joint portion such as an ultrasonic joint portion of the main current wiring into the element body and a current flowing along the surface electrode from the joint portion. The surface electrode is thinner than the entire semiconductor element and has a relatively small current capacity. Therefore, the semiconductor element is likely to be damaged at the surface electrode by the inrush current.

[0005] On one side, an object of the present invention is to provide a semiconductor module capable of suppressing the destruction of a semiconductor element due to an inrush current.

[0006] In one aspect, the semiconductor module includes a semiconductor element having a surface electrode, a wiring board, a main current wiring joined to the surface electrode and the wiring board, and an auxiliary conductor joined only to the surface electrode.

[0007] According to the above aspect, in the semiconductor module, the destruction of the semiconductor element due to the inrush current can be suppressed.

[0008] This is a plan view showing the internal structure of a semiconductor module according to one embodiment. This is a cross-sectional view taken along line II-II in Figure 1. This is a circuit diagram showing an example of the circuit configuration of a semiconductor module according to one embodiment. This is a plan view showing an example of the arrangement of main current wiring and auxiliary wiring (part 1) in one embodiment. This is a side view showing an example of the arrangement of main current wiring and auxiliary wiring (part 1) in one embodiment. This is an enlarged view of section V in Figure 4B. This is a side view showing an example of the arrangement of main current wiring and auxiliary wiring (part 2) in one embodiment. This is a side view showing an example of the arrangement of main current wiring and auxiliary wiring (part 3) in one embodiment. This is a side view showing an example of the arrangement of main current wiring and auxiliary wiring (part 4) in one embodiment. This is a side view showing an example of the arrangement of main current wiring and auxiliary wiring (part 5) in one embodiment. This is a plan view showing the internal structure of a semiconductor module according to a modified example of one embodiment. This is a side view showing an example of the arrangement of main current wiring and auxiliary wiring (part 6) in one embodiment. This is a side view showing an example of the arrangement of main current wiring and auxiliary blocks in one embodiment. This is an explanatory diagram for explaining the destruction of a semiconductor element in a comparative example (corresponding to an enlarged view of section V in Figure 4B). This is an explanatory diagram showing the results of a comparison of surge power withstand capability between one embodiment and a comparative example.

[0009] Hereinafter, a semiconductor module 1 according to one embodiment of the present invention will be described in detail with reference to the drawings. The X, Y, and Z axes in the referenced figures are shown for the purpose of defining the directions and surfaces of the example semiconductor module 1, etc. The X, Y, and Z axes are orthogonal to each other and form a right-handed system. In the following description, the Z direction may be referred to as the up and down direction. Also, the surface containing the X and Y axes may be referred to as the top surface or bottom surface. These directions and surfaces are terms used for convenience of explanation, and the correspondence with the X, Y, and Z directions may change depending on the mounting orientation of the semiconductor module 1, etc. For example, in this specification, the surface facing the positive Z direction (+Z direction) of the components constituting the semiconductor module 1 is referred to as the top surface, and the surface facing the negative Z direction (-Z direction) is referred to as the bottom surface. However, the surface facing the negative Z direction may be referred to as the top surface, and the surface facing the positive Z direction may be referred to as the bottom surface. Also, in this specification, a plan view means the view of the top surface (XY plane) of the semiconductor module 1, etc., from the positive Z direction towards the negative Z direction.

[0010] The aspect ratios and relative sizes of components in each diagram are purely schematic representations and do not necessarily correspond to the actual relationships in manufactured semiconductor modules. For explanatory purposes, the relative sizes of components may be exaggerated in some cases. Furthermore, the shape of the same component may differ between different diagrams.

[0011] In the following description, as an example of a semiconductor module 1 according to one embodiment, a device applied to a power conversion device such as an inverter device for industrial or automotive motors is given. For this reason, detailed descriptions of configurations, functions, operations, assembly methods, etc., that are the same as or similar to known semiconductor modules are omitted in the following description.

[0012] Figure 1 is a plan view showing the internal structure of semiconductor module 1. Figure 2 is a cross-sectional view taken along line II-II of Figure 1.

[0013] The semiconductor module 1 shown in Figure 1 comprises a plurality of semiconductor elements 10, two wiring boards 20, a case 30, terminals 40, 50, and 60, main current wiring W1, W4, and W5, and control wiring W3. Furthermore, as shown in Figure 2, the semiconductor module 1 also comprises a sealing resin 70 and a heat sink 80. Additionally, as shown in Figure 4B, the semiconductor module 1 includes auxiliary wiring W2.

[0014] As the semiconductor element 10, for example, an RC (Reverse Conducting)-IGBT element that integrates the functions of an IGBT element and an FWD (Free Wheeling Diode) element, an IGBT element, a power MOSFET, or a diode can be used. The semiconductor element 10 is formed in a planar rectangular shape using a semiconductor substrate made of a wide bandgap (WBG) semiconductor such as a Si (silicon) substrate, SiC (silicon carbide), or gallium nitride (GaN). If necessary, when using an IGBT element or a SiC MOSFET, a diode may be added to enhance the function of conducting freewheeling current.

[0015] Four semiconductor elements 10 are mounted on each of the two wiring boards 20. Each semiconductor element 10 has an element body 11, a main electrode 12 provided on most of the upper surface of the element body 11, and a control electrode 13 provided on a part of the upper surface of the element body 11. The main electrode 12 is an example of a surface electrode to which the main current wiring W1 is joined.

[0016] The main electrode 12 is a thin film made of aluminum, an aluminum alloy, or the like. For example, if the semiconductor element 10 is an IGBT, it is the emitter electrode; if the semiconductor element 10 is a MOSFET, it is the source electrode. The control electrode 13 is also a thin film made of aluminum, an aluminum alloy, or the like, and is, for example, the gate electrode. A back electrode (not shown) is provided on the lower surface of the semiconductor element 10 and is joined to the upper surface of the circuit layer 23, for example, via solder. The main electrode 12 and the control electrode 13 may be plated after being made of aluminum, an aluminum alloy, or the like.

[0017] As shown in Figure 2, each of the two wiring boards 20 is joined to a common single heat sink 80 at its lower surface (heat dissipation layer 22) by a bonding material such as solder. Of the two wiring boards 20, the wiring board 20 on the positive X-direction side forms the upper arm, and the wiring board 20 on the negative X-direction side forms the lower arm. The wiring boards 20 may be, for example, DCB (Direct Copper Bonding) boards or AMB (Active Metal Brazing) boards. The wiring boards 20 may also be called laminated boards, insulated circuit boards, insulated heat dissipation circuit boards, etc.

[0018] As shown in Figure 3, the four semiconductor elements 10 mounted on the wiring board 20 constituting the upper arm are connected in parallel. Similarly, the four semiconductor elements 10 mounted on the wiring board 20 constituting the lower arm are connected in parallel. The upper arm and the lower arm are connected in series. A single module configured in this way can be used to form a three-phase inverter circuit by arranging the U-phase, V-phase, and W-phase modules side by side. The collectors of the four semiconductor elements 10 in the upper arm are connected to terminal 50 (P terminal), and their emitters are connected to terminal 40 (M terminal). The collectors of the four semiconductor elements 10 in the lower arm are connected to terminal 40 (M terminal), and their emitters are connected to terminal 60 (N terminal). In the case of MOSFETs with WBG application, the emitter becomes the source and the collector becomes the drain.

[0019] As shown in Figures 1 and 2, the wiring board 20 has an insulating layer 21, a heat dissipation layer 22 formed on the lower surface of the insulating layer 21, and circuit layers 23 to 26 (only circuit layers 23 to 25 in the wiring board 20 that constitutes the lower arm) formed on the upper surface of the insulating layer 21.

[0020] The insulating layer 21 is formed in a rectangular shape in plan view using an insulating material such as ceramic or resin. The insulating layer 21 may also be called an insulating plate or insulating film. The insulating material of the insulating layer 21 may be, for example, alumina (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ Ceramic materials such as ), resin materials such as epoxy, or resin materials using ceramic materials as fillers are used.

[0021] The heat dissipation layer 22 shown in Figure 2 functions as a heat conduction member that conducts heat generated in the inverter circuit to the heat sink 80, and is composed of a metal layer of a predetermined thickness formed from copper foil or the like on the lower surface of the insulating layer 21. The heat dissipation layer 22 may also be called a heat sink, metal plate, or metal layer. The heat dissipation layer 22 has a rectangular shape in plan view that covers most of the lower surface of the insulating layer 21.

[0022] Circuit layers 23 to 26, like the heat dissipation layer 22, are composed of metal layers of a predetermined thickness formed from copper foil or the like, and function, for example, as wiring members in an inverter circuit. Circuit layers 23 to 26 may also be called conductive layers, circuit boards, circuit patterns, etc. Circuit layers 23 to 26 are arranged separately from each other. Circuit layers 23, 25, and 26 are main current wiring layers, and circuit layer 24 is a control wiring layer.

[0023] Case 30 is formed using a thermoplastic resin material such as PPS (Polyphenylene Sulfide) or PA (Polyamide), and is insulating. As shown in Figures 1 and 2, Case 30 has an annular wall portion 31, a stepped portion 32, and four protruding pieces 33, and has a rectangular annular (rectangular frame) shape.

[0024] As shown in Figure 2, the case 30 is fixed, for example, to the periphery of the upper surface of the heat sink 80 by adhesive. The four corners of the case 30 may be provided with fastening holes (not shown) for fixing the case 30 together with the heat sink 80 to the cooler.

[0025] The stepped portion 32 is formed on the inner circumference side of the upper surface of the annular wall portion 31, at a height lower than the upper surface of the annular wall portion 31. The stepped portion 32 can be considered as a rectangular annular recess.

[0026] The four protruding pieces 33 include two protruding pieces 33 that project in the negative X direction from the X-side end of the annular wall portion 31, and two protruding pieces 33 that project in the positive X direction from the X-side end of the annular wall portion 31. The outer exposed portions 41 and 42 of the terminal 40 are embedded in the two protruding pieces 33 that project in the negative X direction from the annular wall portion 31. The outer exposed portions 51 of the terminal 50 and the outer exposed portion 61 of the terminal 60 are embedded in the two protruding pieces 33 that project in the positive X direction from the annular wall portion 31.

[0027] Terminals 40, 50, and 60 are formed by insert molding into the case 30, for example, by bending a metal plate-like body. Terminal 40 (M terminal) is integrally formed such that two outer exposed portions 41 and 42 exposed on the upper surface of the protruding piece 33 and one inner exposed portion 43 exposed on the upper surface of the stepped portion 32 of the case 30 are electrically connected within the annular wall portion 31. Similarly, terminals 50 (P terminal) and 60 (N terminal) are integrally formed such that one outer exposed portion 51 and 61 exposed on the upper surface of the protruding piece 33 and one inner exposed portion 52 and 62 exposed on the upper surface of the stepped portion 32 of the case 30 are electrically connected within the annular wall portion 31.

[0028] As shown in Figure 1, the main current wiring W1 is connected to the main electrode 12 of the semiconductor element 10 and the circuit layer 25. The control wiring W3 is connected to the control electrode 13 of the semiconductor element 10 and the circuit layer 24. The main current wiring W4 is connected to the inner exposed portions 43, 52, 62 of terminals 40, 50, 60 and the circuit layers 23, 26. Some of the main current wiring W5 is connected to the circuit layer 25 of the wiring board 20 that constitutes the upper arm and the circuit layer 23 of the wiring board 20 that constitutes the lower arm. Other parts of the main current wiring W5 are connected to the circuit layer 26 of the wiring board 20 that constitutes the upper arm and the circuit layer 25 of the wiring board 20 that constitutes the lower arm.

[0029] The auxiliary wiring W2 shown in Figures 4A and 4B is joined at both ends to the main electrode 12 of the semiconductor element 10. The auxiliary wiring W2 should have the same diameter as or less than the main current wiring W1, and preferably be thinner than the main current wiring W1 (smaller cross-sectional area perpendicular to the current path). For example, if the diameter of the main current wiring W1 is 400 μm, the diameter of the auxiliary wiring W2 should be about half, around 200 μm. The auxiliary wiring W2 is an example of an auxiliary conductor joined only to the main electrode 12. The auxiliary wiring W2 is not in contact with any external conductors other than the main electrode 12.

[0030] Each wiring W1 to W5 is a wire made of, for example, aluminum or an aluminum alloy. However, the main current wirings W4 and W5 that are not joined to the semiconductor element 10 may be formed from a metal wiring board (lead frame) or the like.

[0031] As shown in Figure 2, the sealing resin 70 (not shown in Figure 1) seals the semiconductor element 10, the wiring board 20, and the wirings W1 to W5, etc., within the internal space of the case 30 defined by the annular wall portion 31. Epoxy resin or silicone gel can be used as the sealing resin 70. The space above the case 30 after the sealing resin 70 has been filled is preferably sealed with a plate-shaped lid member.

[0032] The heat sink 80 has a rectangular shape in plan view, and the wiring board 20 (heat dissipation layer 22) is joined to it as described above. The heat sink 80 functions as a heat conductive member that conducts the heat generated by the semiconductor element 10 to the cooler, and is formed from a metal plate such as a copper plate or an aluminum plate.

[0033] The shape, number, and placement of each part of the semiconductor module 1, such as the semiconductor element 10 and the wiring board 20, can be changed as appropriate. In other words, the configuration of the semiconductor module 1 described above is merely one preferred example.

[0034] Next, we will describe an example of the arrangement of the main current wiring W1 and auxiliary wiring W2 with reference to Figures 4A and 4B. As shown in Figure 4A, four main current wirings W1 and four auxiliary wirings W2 are arranged in parallel, but we will explain using one of each as an example. Furthermore, ultrasonic bonding will be used as the wire bonding method for joining the main current wirings W1 and auxiliary wirings W2. Also, in Figure 4A, the control wiring W3 that is joined to the control electrode 13 is not shown.

[0035] As shown in Figures 4A and 4B, the main current wiring W1 is joined to the circuit layer 25 at a circuit junction J10 at one end (the negative end in the Y direction). The main current wiring W1 is also joined to the main electrode 12 of the semiconductor element 10 at two separate junctions in the Y direction: a first junction J11 (negative side in the Y direction) and a second junction J12 (positive side in the Y direction). Here, the first junction J11 is joined to the main electrode 12 in the middle portion of the main current wiring W1, while the second junction J12 is joined to the main electrode 12 at the other end of the main current wiring W1 (the positive end in the Y direction) opposite to the circuit layer 25. Therefore, the current path from the circuit layer 25 to the second junction J12 is longer than that to the first junction J11.

[0036] The auxiliary wiring W2 is joined to the main electrode 12 of the semiconductor element 10 at its third junction J21 (negative side in the Y direction) and fourth junction J22 (positive side in the Y direction) at both ends, which are separated in the Y direction. As described above, the auxiliary wiring W2 is joined only to the main electrode 12. It is preferable that the auxiliary wiring W2 is not in contact with any external conductors other than the main electrode 12. However, the auxiliary wiring W2 may, for example, partially contact the main current wiring W1 after ultrasonic bonding to the main electrode 12. In this case, the auxiliary wiring W2 is not in contact with anything other than the main electrode 12 and the main current wiring W1. Furthermore, even if the first junction J11 of the main current wiring W1 and the third junction J21 of the auxiliary wiring W2 are not separated but are integrated, it can still be said that the auxiliary wiring W2 is joined only to the main electrode 12.

[0037] As shown in Figure 4B, the main current wiring W1 has a first loop LP1 that protrudes in the direction away from the main electrode 12 (positive Z direction) between the first junction J11 and the second junction J12.

[0038] Furthermore, the auxiliary wiring W2 has a second loop LP2 that protrudes in the direction away from the main electrode 12 (positive Z direction) between the third joint J21 and the fourth joint J22. The auxiliary wiring W2 is preferably located in the region enclosed by the first loop LP1 of the main current wiring W1 and the main electrode 12. That is, the auxiliary wiring W2 (second loop LP2) is preferably located below the first loop LP1 of the main current wiring W1. In this way, when the main current wiring W1 has a first loop LP1 and the auxiliary wiring W2 has a second loop LP2, it is preferable that the main current wiring W1 is connected to the main electrode 12 after the auxiliary wiring W2 is connected.

[0039] Here, the distance (length L3) between the third joint J21 of the auxiliary wiring W2 and the first joint J11 of the main current wiring W1 is shorter than the distance (length L1) between the second joint J12 of the main current wiring W1 and the first joint J11 of the main current wiring W1, and more preferably less than or equal to half the length L1. In this embodiment, the relationship between the distances (lengths L1 to L3) is shown as the distance between the centers of each joint J11, J12, J21, and J22, but it may also be the distance of the gap between each joint J11, J12, J21, and J22.

[0040] Further, the distance (length L3) between the third joint J21 of the auxiliary wiring W2 and the first joint J11 of the main current wiring W1 may be shorter than the distance (length L2) between the third joint J21 of the auxiliary wiring W2 and the fourth joint J22 of the auxiliary wiring W2.

[0041] Thus, it is desirable that the third joint J21 of the auxiliary wiring W2 is provided near the first joint J11 of the main current wiring W1. As shown in FIG. 5, the inrush current C flowing from the circuit layer 25 into the main current wiring W1 is divided into the current flowing from the first joint J11 into the element body 11, the current flowing in the first loop LP1 of the main current wiring W1, and the current flowing along the main electrode 12 (illustrated by thicker arrows as the current value is larger). The current flowing along the main electrode 12 is divided into the second loop LP2 of the auxiliary wiring W2 from the third joint J21 while flowing into the element body 11. The inrush current C flows into, for example, the body diode if the semiconductor element 10 is an RC-IGBT, the semiconductor element 10 which is a FWD element if the semiconductor element 10 which is an IGBT element and the semiconductor element 10 which is a FWD element are connected in parallel, and the body diode if the semiconductor element 10 is a MOSFET, respectively. However, even in the semiconductor element 10 which is an IGBT element, etc., the auxiliary wiring W2 may be used to prevent breakdown due to the inrush current C flowing through the main electrode 12.

[0042] Next, in the example shown in FIG. 6, the main current wiring W11 does not have the first loop LP1 shown in FIG. 4B and is joined only to the circuit joint J10 of the circuit layer 25 and the first joint J11 of the main electrode 12. Even in this case, the current flowing along the main electrode 12 is divided into the current flowing into the second loop LP2 of the auxiliary wiring W2 from the third joint J21 while flowing into the element body 11. The main current wiring W11 is joined to the main electrode 12 only at one first joint J11, but it is desirable that it is joined to the main electrode 12 at two first joints J11 and second joints J12 as in the main current wiring W1 shown in FIG. 4B. Further, the main current wiring W1 may have a plurality of first loops LP1 by being joined (stitch wiring) to the main electrode 12 at three or more locations.

[0043] The example shown in Figure 7 has a similar structure to the example shown in Figure 4B, but the auxiliary wiring W21 has the same diameter as the main current wiring W1. Thus, the auxiliary wiring W21 is not limited to being thinner than the main current wiring W1. Alternatively, the diameter of the main current wiring W1 may be 400 μm, and the diameter of the auxiliary wiring W21 may be close to that of the main current wiring W1, such as 300 μm. The example shown in Figure 7 is also applicable when a main current wiring W11 without a first loop LP1 is used, as shown in Figure 6.

[0044] In the example shown in Figure 8, the auxiliary wiring W22 is connected to the main electrode 12 not only at the third and fourth joints J21 and J22, but also at the fifth joint J23. That is, the auxiliary wiring W22 has its negative Y-side end connected to the main electrode 12 at the third joint J21, its intermediate fourth joint J22 connected to the main electrode 12, and its positive Y-side end connected to the main electrode 12 at the fifth joint J23. The auxiliary wiring W22 has a second loop LP2 that protrudes in the direction away from the main electrode 12 (positive Z-side) between the third joint J21 and the fourth joint J22, and a third loop LP3 that protrudes in the direction away from the main electrode 12 (positive Z-side) between the fourth joint J22 and the fifth joint J23. The example shown in Figure 8 is applicable when a main current wiring W11 without a first loop LP1 is used, as shown in Figure 6, or when the auxiliary wiring W21 has the same diameter as the main current wiring W1, as shown in Figure 7.

[0045] In the example shown in Figure 9, the auxiliary wiring W23 does not have a second loop LP2 and extends in the Y direction along the main electrode 12 between the third junction J21 and the fourth junction J22. The example shown in Figure 9 is also applicable when a main current wiring W11 without a first loop LP1 is used, as shown in Figure 6, or when the auxiliary wiring W21 has the same diameter as the main current wiring W1, as shown in Figure 7.

[0046] The semiconductor module 2 according to the modification shown in FIG. 10 is the same as the semiconductor module 1 shown in FIG. 1, except that eight semiconductor elements 10 are mounted on each of the two wiring boards 20. In the semiconductor module 2 shown in FIG. 10, as shown in FIG. 11, two semiconductor elements 10 arranged in the Y direction are connected in series by a single main current wiring W1. The main current wiring W1 is joined to the circuit layer 25 at a circuit joint J10 at one end (the end on the negative side in the Y direction). Further, the main current wiring W1 is joined to the main electrode 12 of the semiconductor element 10 on the negative side in the Y direction at two first joints J11 (on the negative side in the Y direction) and a second joint J12 (on the positive side in the Y direction), and is joined to the main electrode 12 of the semiconductor element 10 on the positive and negative sides in the Y direction at two first joints J11 (on the negative side in the Y direction) and a second joint J12 (on the positive side in the Y direction). Here, the semiconductor element 10 on the negative side in the Y direction is directly connected to the circuit layer 25 by the main current wiring W1, whereas the semiconductor element 10 on the positive side in the Y direction is indirectly connected to the circuit layer 25 via the semiconductor element 10 on the negative side in the Y direction by the main current wiring W1. Therefore, the inrush current C (see FIG. 5) of the semiconductor element 10 on the negative side in the Y direction into which the main current directly flows from the circuit layer 25 is larger than that of the semiconductor element 10 on the positive side in the Y direction. Therefore, it is preferable that the auxiliary wiring W2 is arranged only in the former of the semiconductor element 10 into which the main current directly flows from the circuit layer 25 and the semiconductor element 10 into which the main current indirectly flows from the circuit layer 25 via another semiconductor element 10.

[0047] In the example shown in FIG. 12, as an example of an auxiliary conductor joined only to the main electrode 12, instead of the auxiliary wiring W2, an auxiliary block B joined to the main electrode 12 is used. This auxiliary block B may have a shape other than linear, for example, a rectangular parallelepiped shape or a spherical shape, and may be made of aluminum, an aluminum alloy, or the like. Even when the auxiliary block B is used, the auxiliary block B is preferably located in the region surrounded by the first loop LP1 of the main current wiring W1 and the main electrode 12. Even when only a part of the auxiliary block B is located in the region surrounded by the first loop LP1 of the main current wiring W1 and the main electrode 12, it can be said that the auxiliary block B is located in the region surrounded by the first loop LP1 of the main current wiring W1 and the main electrode 12.

[0048] The distance (length L3) between the junction (third junction) of the main electrode 12 of the auxiliary block B and the first junction J11 of the main current wiring W1 is shorter than the distance (length L1) between the second junction J12 of the main current wiring W1 and the first junction J11 of the main current wiring W1, and more preferably less than half the length L1. Note that four auxiliary blocks B may be arranged, the same number as the four main current wirings W1, or fewer auxiliary blocks B (for example, one) may extend below the four main current wirings W1. The example shown in Figure 12 is also applicable when the main current wiring W11 does not have a first loop LP1, as shown in Figure 6. Furthermore, the auxiliary blocks B shown in Figure 12 may be arranged only in semiconductor elements 10 into which the main current flows directly from the circuit layer 25, similar to the example shown in Figure 11.

[0049] In the comparative example shown in Figure 13, auxiliary conductors such as auxiliary wirings W2, W21, W22, W23 and auxiliary block B are not arranged. Therefore, the inrush current C flowing from the circuit layer 25 to the main current wiring W1 is not diverted to the auxiliary conductors. Consequently, the semiconductor element 10 is easily damaged at the main electrode 12 due to the current flowing from the first junction J11 along the main electrode 12 (for example, the damaged portion D near the first junction J11). When auxiliary wiring W2 is arranged as in the example of this embodiment shown in Figures 4A and 4B, as shown in Figure 14, the surge power withstand capability [W] (surge voltage withstand capability VFSM × surge current withstand capability IFSM) is set to 1 compared to the case where auxiliary wiring W2 is not arranged as in the comparative example in Figure 13, and the surge power withstand capability [W] becomes approximately 1.05, an improvement of approximately 5%. Note that the surge voltage withstand capability VFSM can be said to be the voltage at the time of measurement of the surge current withstand capability IFSM.

[0050] In the embodiment described above, the semiconductor module 1 comprises a semiconductor element 10 having a main electrode 12 (an example of a surface electrode), a wiring board 20, main current wirings W1 and W11 joined to the main electrode 12 and the wiring board 20, and an auxiliary conductor (for example, auxiliary wirings W2, W21, W22, W23 or auxiliary block B) joined only to the main electrode 12.

[0051] However, since the thickness of the main electrode 12 is thin (for example, 1 to 10 μm) compared to the overall thickness of the semiconductor element 10 (for example, 100 μm), its current capacity is relatively small, and the inrush current C is divided along the main electrode 12, making the semiconductor element 10 more susceptible to damage at the main electrode 12. In this embodiment, the inrush current C (see Figure 5) flowing from the circuit layer 25 through the main current wirings W1 and W11 is divided along the main electrode 12 and can be routed to auxiliary wirings W2, W21, W22, and W23, or the current capacity can be increased by using auxiliary block B. Therefore, according to this embodiment, the damage to the semiconductor element 10 due to the inrush current C can be suppressed.

[0052] In this embodiment, semiconductor elements 10 are mounted on the wiring board 20, and the main current wiring W1 is joined to the main electrode 12 by a first junction J11 and a second junction J12, the current path from the circuit layer 25 (wiring board 20) is longer than that of the first junction J11, and has a first loop LP1 that protrudes in a direction away from the main electrode 12 between the first junction J11 and the second junction J12.

[0053] This allows the inrush current C (see Figure 5) flowing from the circuit layer 25 through the main current wiring W1 to be diverted to the first loop LP1 of the main current wiring W1. Therefore, the destruction of the semiconductor element 10 due to the inrush current C can be further suppressed. Furthermore, in an embodiment in which the main current wiring W1 extends along the main electrode 12 without having the first loop LP1, thermal stress is generated because the amount of thermal expansion due to temperature changes in the semiconductor element 10 differs between the main current wiring W1 and the main electrode 12, reducing the power cycle withstand capability (power cycle life). However, in this embodiment, the power cycle withstand capability can be increased by having the main current wiring W1 have the first loop LP1.

[0054] Furthermore, in this embodiment, the distance (length L3) between the third junction on the main electrode 12 of the auxiliary conductor (the third junction J21 of the auxiliary wirings W2, W21, W22, W23 or the junction on the main electrode 12 of the auxiliary block B) and the first junction J11 of the main current wiring W1 is shorter than the distance (length L1) between the second junction J12 of the main current wiring W1 and the first junction J11 of the main current wiring W1, and more preferably half the length L1 or less.

[0055] This allows the current flowing along the main electrode 12 to be routed to auxiliary wirings W2, W21, W22, and W23 near the first junction J11 of the main current wiring W1, or the current capacity to be increased near the first junction J11 of the main current wiring W1 by using auxiliary block B. Therefore, the destruction of the semiconductor element 10 due to inrush current C can be further suppressed.

[0056] Furthermore, in this embodiment, an auxiliary wiring W2, W21, W22, W23 or auxiliary block B, which is an example of an auxiliary conductor, is located in the region surrounded by the first loop LP1 of the main current wiring W1 and the main electrode 12.

[0057] This avoids the limitation of space on the main electrode 12 caused by using auxiliary wiring W2, W21, W22, W23 and auxiliary block B, and allows for an increase in the number of main current wiring W1 and auxiliary wiring W2, W21, W22, W23 on the main electrode 12, or an increase in the number of connections between a single main current wiring W1 or a single auxiliary wiring W2, W21, W22, W23.

[0058] Furthermore, in this embodiment, auxiliary wirings W2, W21, W22, and W23, which are joined to the main electrode 12 at the third joint J21 and the fourth joint J22, are used as auxiliary conductors joined only to the main electrode 12.

[0059] This allows the current flowing along the main electrode 12 to be diverted to the auxiliary wirings W2, W21, W22, and W23, unlike when auxiliary block B is used as an auxiliary conductor. Therefore, the destruction of the semiconductor element 10 due to the inrush current C can be further suppressed.

[0060] Furthermore, in this embodiment, the auxiliary wirings W2, W21, and W22 have a second loop LP2 that protrudes in a direction away from the main electrode 12 between the third joint J21 and the fourth joint J22.

[0061] As a result, unlike the case where auxiliary wiring W23 extending along the main electrode 12 is used between the third junction J21 and the fourth junction J22 as shown in Figure 9, the inrush current C can be diverted to auxiliary wirings W2, W21, and W22 separated from the main electrode 12. Therefore, the destruction of the semiconductor element 10 due to the inrush current C can be further suppressed.

[0062] Furthermore, in this embodiment, the distance (length L3) between the third joint J21 of the auxiliary wirings W2, W21, and W22 and the first joint J11 of the main current wiring W1 is shorter than the distance (length L2) between the third joint J21 of the auxiliary wirings W2, W21, and W22 and the fourth joint J22 of the auxiliary wirings W2, W21, and W22.

[0063] This allows the current flowing along the main electrode 12 to flow through the auxiliary wirings W2, W21, and W22 near the first junction J11 of the main current wiring W1. Therefore, the destruction of the semiconductor element 10 due to the inrush current C can be further suppressed.

[0064] Furthermore, in this embodiment, the auxiliary wirings W2, W22, and W23 are thinner than the main current wirings W1 and W11.

[0065] This makes it easier to arrange the auxiliary wirings W2, W22, and W23 on the main electrode 12. In addition, it is possible to increase the number of main current wirings W1, W11 and auxiliary wirings W2, W22, and W23 on the main electrode 12, or to increase the number of connections between a single main current wiring W1 or a single auxiliary wiring W2, W22, and W23.

[0066] Furthermore, in this embodiment, an auxiliary block B joined to the main electrode 12 is used as an auxiliary conductor joined only to the main electrode 12.

[0067] As a result, compared to the case where auxiliary wirings W2, W21, W22, and W23 are used on the main electrode 12 as auxiliary conductors, space is secured on the main electrode 12, and the number of main current wirings W1 and W11 on the main electrode 12 can be increased, or the number of junctions of a single main current wiring W1 or W11 can be increased.

[0068] In the above description, aluminum and aluminum alloys were given as materials for the main electrode 12, main current wiring W1, W11, auxiliary wiring W2, W21, W22, W23, and auxiliary block B. However, other materials such as copper and copper alloys may be used, especially when the main electrode 12 is made of other materials such as copper or copper alloy. Thus, the materials for each part of the semiconductor module 1 are not limited to the above examples. Also, the number of main current wiring W1, W11 and auxiliary wiring W2, W21, W22, W23 does not have to be four for each semiconductor element 10, but can be any number of one or more (preferably multiple).

[0069] Furthermore, in the above description, auxiliary conductors, such as auxiliary wirings W2, W21, W22 and auxiliary block B, are located in the region surrounded by the first loop LP1 of the main current wiring W1 and the main electrode 12. However, auxiliary conductors can be placed at any position as long as space on the main electrode 12 allows.

[0070] Furthermore, while it is preferable for semiconductor module 1 to be used as a power semiconductor, semiconductor module 1 can be used as a semiconductor in any electronic device, such as discrete semiconductors.

[0071] The semiconductor module according to the present invention is not limited to the embodiments described above, and may be modified, substituted, or transformed in various ways without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way by technological advancements or other derived technologies, it may be implemented by that method. Accordingly, the claims cover all embodiments that may fall within the scope of the technical idea.

[0072] The following are some of the inventions described in the specification and drawings of this application.

[0073] <Note 1> A semiconductor module characterized by comprising: a semiconductor element having a surface electrode; a wiring board; a main current wiring connected to the surface electrode and the wiring board; and an auxiliary conductor connected only to the surface electrode.

[0074] <Note 2> The semiconductor module according to Note 1, wherein the semiconductor element is mounted on the wiring board, the main current wiring is joined to the surface electrode by a first junction and a second junction having a longer current path from the wiring board than the first junction, and has a first loop protruding in a direction away from the surface electrode between the first junction and the second junction.

[0075] <Note 3> The semiconductor module according to Note 2, characterized in that the distance between the third junction of the surface electrode of the auxiliary conductor and the first junction of the main current wiring is shorter than the distance between the second junction of the main current wiring and the first junction of the main current wiring.

[0076] <Note 4> The semiconductor module according to Note 3, characterized in that the distance between the third junction on the surface electrode of the auxiliary conductor and the first junction of the main current wiring is half or less the distance between the second junction of the main current wiring and the first junction of the main current wiring.

[0077] <Note 5> The semiconductor module according to Note 2, characterized in that the auxiliary conductor is located in the region surrounded by the first loop and the surface electrode.

[0078] <Note 6> The semiconductor module according to Note 1, characterized in that the auxiliary conductor is an auxiliary wiring joined to the surface electrode at a third joint and a fourth joint.

[0079] <Note 7> The semiconductor module according to Note 6, characterized in that the auxiliary wiring has a second loop that protrudes in a direction away from the surface electrode between the third joint and the fourth joint.

[0080] <Note 8> The semiconductor module according to Note 7, wherein the main current wiring is joined to the surface electrode by a first joint and a second joint having a longer current path from the wiring board than the first joint, and has a first loop protruding in a direction away from the surface electrode between the first joint and the second joint, and the distance between the third joint of the auxiliary wiring and the first joint of the main current wiring is shorter than the distance between the third joint of the auxiliary wiring and the fourth joint of the auxiliary wiring.

[0081] <Note 9> The semiconductor module according to Note 6, characterized in that the auxiliary wiring is thinner than the main current wiring.

[0082] <Note 10> The semiconductor module according to Note 1, characterized in that the auxiliary conductor is an auxiliary block bonded to the surface electrode.

[0083] As described above, the present invention has the effect of suppressing the destruction of semiconductor elements due to inrush current, and is particularly useful for inverter devices for industrial or electrical applications.

[0084] This application is based on Japanese Patent Application No. 2025-005341, filed on January 15, 2025. All of its contents are included herein.

[0085] 1,2 Semiconductor module 10 Semiconductor element 11 Element body 12 Main electrode (surface electrode) 13 Control electrode 20 Wiring board 21 Insulating layer 22 Heat dissipation layer 23-26 Circuit layer 30 Case 31 Annular wall 32 Stepped section 33 Protruding piece 40, 50, 60 Terminals 41, 42, 51, 61 Outer exposed part 43, 52, 62 Inner exposed part 70 Sealing resin 80 Heat sink B Auxiliary block (auxiliary conductor) C Inrush current D Damaged part J10 Circuit junction J11 First junction J12 Second junction J21 Third junction J22 Fourth junction J23 Fifth junction LP1 First loop LP2 Second loop LP3 Third loop W1, W4, W5, W11 Main current wiring: W2, W21, W22, W23; Auxiliary wiring (auxiliary conductor): W3; Control wiring:

Claims

1. A semiconductor module comprising: a semiconductor element having a surface electrode; a wiring board; a main current wiring connected to the surface electrode and the wiring board; and an auxiliary conductor connected only to the surface electrode.

2. The semiconductor module according to claim 1, wherein the semiconductor element is mounted on the wiring board, and the main current wiring is joined to the surface electrode by a first junction and a second junction having a longer current path from the wiring board than the first junction, and has a first loop protruding in a direction away from the surface electrode between the first junction and the second junction.

3. The semiconductor module according to claim 2, characterized in that the distance between the third junction of the surface electrode of the auxiliary conductor and the first junction of the main current wiring is shorter than the distance between the second junction of the main current wiring and the first junction of the main current wiring.

4. The semiconductor module according to claim 3, characterized in that the distance between the third junction on the surface electrode of the auxiliary conductor and the first junction of the main current wiring is half or less the distance between the second junction of the main current wiring and the first junction of the main current wiring.

5. The semiconductor module according to claim 2, characterized in that the auxiliary conductor is located in a region surrounded by the first loop and the surface electrode.

6. The semiconductor module according to claim 1, characterized in that the auxiliary conductor is an auxiliary wiring joined to the surface electrode at a third joint and a fourth joint.

7. The semiconductor module according to claim 6, characterized in that the auxiliary wiring has a second loop that protrudes in a direction away from the surface electrode between the third joint and the fourth joint.

8. The semiconductor module according to claim 7, wherein the main current wiring is joined to the surface electrode by a first joint and a second joint having a longer current path from the wiring board than the first joint, and has a first loop protruding in a direction away from the surface electrode between the first joint and the second joint, and the distance between the third joint of the auxiliary wiring and the first joint of the main current wiring is shorter than the distance between the third joint of the auxiliary wiring and the fourth joint of the auxiliary wiring.

9. The semiconductor module according to claim 6, characterized in that the auxiliary wiring is thinner than the main current wiring.

10. The semiconductor module according to claim 1, characterized in that the auxiliary conductor is an auxiliary block bonded to the surface electrode.

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