Monitoring device and monitoring method
The monitoring device addresses the challenge of unknown data transfer amounts by comparing read and write data transfers to detect DMA control device abnormalities, maintaining system stability.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2025-12-12
- Publication Date
- 2026-07-23
AI Technical Summary
Conventional methods for monitoring DMA control device abnormalities require presetting upper and lower limits of data transfer amounts, which is challenging when the transfer amount is unknown, potentially leading to system abnormalities.
A monitoring device that compares the difference between the read and write data transfer amounts during DMA operations to detect abnormalities, using counters and comparators to determine if the difference exceeds the DMAC's buffer capacity.
Enables effective monitoring of DMA control device abnormalities without relying on predefined transfer amount limits, ensuring system stability by detecting anomalies in DMA transfers.
Smart Images
Figure JP2025043565_23072026_PF_FP_ABST
Abstract
Description
Monitoring Device and Monitoring Method
[0001] The present disclosure relates to a monitoring device and a monitoring method.
[0002] As a method of data transfer to a memory provided in a microcomputer or the like, there are a method performed via a CPU (Central Processing Unit) and a DMA (Direct Memory Access) transfer method that directly performs data transfer without going through the CPU. The DMA transfer is controlled by a DMA control device as described in, for example, Japanese Patent Application Laid-Open No. 2007-310735.
[0003] [Summary] By the way, when the DMA control device malfunctions and an unintended DMA transfer occurs, it is assumed that the entire microcomputer malfunctions by destroying the contents of the memory. Therefore, for the memory area, an area accessible from the DMA control device and an area accessible from the CPU are set respectively. By setting the accessible areas in this way, even when the DMA control device malfunctions, the memory area used by the CPU is not destroyed, thereby preventing the CPU from malfunctioning.
[0004] In this case, although it is possible to prevent the CPU from malfunctioning, if the DMA control device malfunctions, an abnormality may occur in the DMA transfer, and as a result, an abnormality may occur in the system. Therefore, monitoring of the abnormality of the DMA control device is being performed. As a method for monitoring the abnormality of the DMA control device, there is known a monitoring method in which the DMA transfer amount is monitored, and when the transfer amount does not fall within a preset range, it is determined as abnormal.
[0005] However, in this conventional method, in order to monitor an abnormality in the transfer amount in the DMA transfer, it is necessary to preset the upper and lower limits of the data transfer amount, and it is necessary to know the transfer amount of data generated within a certain time measured by a timer or within a certain processing period controlled by the CPU.
[0006] The technology of the present disclosure has been made in view of the above points, and it is possible to monitor the abnormality of the DMA control device even when the transfer amount of data is not known.
[0007] The monitoring device of this disclosure monitors the comparison result between a first transfer amount, which is the amount of data transferred when data is read from the source area of the memory, under the control of a DMA (Direct Memory Access) control device, and a second transfer amount, which is the amount of data transferred when the data read from the source area is written to the destination area of the memory, under the control of the DMA control device.
[0008] Figure 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. Figure 2 is a block diagram showing an example of the configuration of a monitoring device according to Example 1 of the first embodiment. Figure 3 is a flowchart showing an example of the abnormality monitoring flow by the monitoring device of Example 1. Figure 4 is a block diagram showing an example of the configuration of a monitoring device according to Example 2 of the first embodiment. Figure 5 is a block diagram showing an example of the configuration of a monitoring device according to the second embodiment. [Detailed Description]
[0009] An example of an embodiment of the disclosed technology will be described below with reference to the drawings. Note that the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from actual ratios.
[0010] [First Embodiment] Figure 1 shows a block diagram illustrating an example of the configuration of a memory system 10 using the monitoring device 16 of this embodiment. The memory system 10 of this embodiment comprises a DMAC (Direct Memory Access Controller) 12, a CPU (Central Processing Unit) 14, a monitoring device 16, and a memory 18.
[0011] The CPU 14 is connected to the memory 18 via a bus such as a system bus. As shown in Figure 1, the CPU 14 in this embodiment is capable of using the entire memory 18 area. That is, the CPU 14 is capable of reading and writing data to all areas of the memory 18.
[0012] The DMAC 12 is connected to the memory 18 by a bus such as a system bus, and controls the DMA (Direct Memory Access) transfer of data to the memory 18. In this embodiment, the DMAC 12 is capable of using a predetermined area of the memory 18. That is, the DMAC 12 is capable of reading and writing data to a predetermined area of the memory 18. In this embodiment, as shown in Figure 1, in DMA transfer by the DMAC 12, the DMAC 12 writes the data read from the transfer source 18A to the transfer destination 18B.
[0013] As shown in Figure 1, the DMAC 12 and CPU 14 can be used for data transfer to the destination 18B and source 18A, which are areas within the memory 18.
[0014] In the case of DMA transfer, since the data read from the source 18A is written to the destination 18B, the amount of data read from the source 18A (hereinafter referred to as the read transfer amount) and the amount of data written to the destination 18B (hereinafter referred to as the write transfer amount) are equal at the time of completion of the DMA transfer. The data read from the source 18A is buffered in the DMAC 12 before being written to the destination 18B. Therefore, the difference between the read transfer amount and the write transfer amount (hereinafter referred to as the difference in transfer amount) will not exceed the maximum buffer amount of the DMAC 12 (hereinafter referred to as the maximum buffer amount). Accordingly, the monitoring device 16 of this embodiment determines that an abnormality has occurred in the transfer if the difference between the read transfer amount and the write transfer amount exceeds the maximum buffer amount of the DMAC 12. The read transfer amount in this embodiment is an example of the first transfer amount of this disclosure, and the write transfer amount in this embodiment is an example of the second transfer amount of this disclosure.
[0015] The monitoring device 16 is a device that monitors the DMAC 12 by monitoring the amount of DMA transfer. A specific example of the monitoring device 16 will be described below.
[0016] (Example 1) Figure 2 shows a block diagram illustrating an example of the configuration of the monitoring device 16 in this embodiment.
[0017] As shown in Figure 2, the monitoring device 16 of this embodiment includes a source area setting register 20, a destination area setting register 22, a read transfer amount counter 24, a write transfer amount counter 26, a DMAC maximum buffer amount setting register 28, and a comparison circuit 30.
[0018] The source area setting register 20 is a register that sets the area of the source memory 18A. Examples of the source area setting register 20 include a combination of a register that specifies the starting address of the source memory 18A and a register that specifies the size, or a combination of a register that specifies the starting address and a register that specifies the ending address.
[0019] The destination area setting register 22 is a register that sets the area of the destination 18B in memory 18. Examples of the destination area setting register 22 include a combination of a register that specifies the starting address of the destination 18B and a register that specifies the size, or a combination of a register that specifies the starting address and a register that specifies the ending address.
[0020] The DMAC maximum buffer size setting register 28 is a register that sets the maximum buffer size of the DMAC 12.
[0021] The read transfer amount counter 24 is a counter that measures the amount of read transfer that occurs at the source 18A during DMA transfer controlled by the DMAC 12. The read transfer amount counter 24 in this embodiment is an example of the first counter of this disclosure. The write transfer amount counter 26 is a counter that measures the amount of write transfer that occurs at the destination 18B during DMA transfer controlled by the DMAC 12. The write transfer amount counter 26 in this embodiment is an example of the location of the second counter of this disclosure.
[0022] In this embodiment, the comparison circuit 30 determines that an abnormality exists if the difference between the read transfer amount and the write transfer amount exceeds the maximum buffer amount of the DMAC 12. As shown in Figure 2, the comparison circuit 30 in this embodiment includes a subtractor 31 and a comparator 33. The subtractor 31 outputs the result of subtracting the count value of the write transfer amount counter 26 from the count value of the read transfer amount counter 24 to the comparator 33. In other words, the subtractor 31 outputs the difference between the read transfer amount and the write transfer amount to the comparator 33.
[0023] The comparator 33 receives the subtraction result from the subtractor 31 and the setting value of the DMAC maximum buffer amount setting register 28 as input. In other words, the comparator 33 receives the difference between the read transfer amount and the write transfer amount and the maximum buffer amount of the DMAC 12 as input. The comparator 33 outputs a comparison result by comparing the difference between the read transfer amount and the write transfer amount with the maximum buffer amount of the DMAC 12. The comparison result corresponds to the judgment result for abnormality. For example, if the difference between the read transfer amount and the write transfer amount is less than or equal to the maximum buffer amount of the DMAC 12, the comparator 33 outputs "1", which indicates a judgment result of normal. On the other hand, if the difference between the read transfer amount and the write transfer amount is less than or equal to the maximum buffer amount of the DMAC 12, it outputs "0", which indicates a judgment result of abnormality. The destination to which the comparator 33 (comparison circuit 30) outputs the judgment result is not limited, but it may be the CPU 14, for example.
[0024] Figure 3 shows an example of the flow of monitoring for abnormalities by the monitoring device 16 during DMA transfer by the DMAC 12.
[0025] First, when the monitoring device 16 detects a DMA transfer, it determines whether or not data has been read from the transfer source 18A (step S100). If data has been read from the transfer destination 18A (affirmative determination: Y), the read transfer amount counter 24 counts the read transfer amount according to the data read (step S102).
[0026] On the other hand, if data has not been read from the source 18A (negative determination in step S100: N), the monitoring device 16 determines whether or not to write the data to the destination 18 (step S104). If the data is not to be written to the destination 18B (negative determination: N), the monitoring device 16 terminates monitoring. On the other hand, if data is written to the destination 18B (positive determination in step S104: Y), the write transfer amount counter 26 counts the write transfer amount in accordance with the data writing (step S106).
[0027] The subtractor 31 of the comparison circuit 30 refers to the read transfer amount counter 24 and the write transfer amount counter 26 and derives the difference between the read transfer amount and the write transfer amount (step S108).
[0028] The comparator 33 of the comparison circuit 30 compares the difference in transfer amounts with the maximum buffer amount set in the DMAC maximum buffer amount setting register 28. If the difference in transfer amounts is less than or equal to the maximum buffer amount (positive determination in step S110: Y), the comparator 33 outputs a result indicating that it is normal (step S112). On the other hand, if the difference in transfer amounts exceeds the maximum buffer amount (negative determination in step S110: N), the comparator 33 outputs a result indicating that it is abnormal (step S114).
[0029] Thus, according to the monitoring device 16 of Example 1, abnormalities in the DMAC 12 can be monitored by monitoring the amount of DMA transfer during DMA transfer.
[0030] (Example 2) In Example 1, a configuration was described in which the monitoring device 16 is equipped with two counters, a read transfer counter 24 and a write transfer counter 26, in order to derive the difference between the read transfer amount and the write transfer amount. However, the configuration for deriving the difference between the read transfer amount and the write transfer amount is not limited to the above configuration. In this example, an example of a configuration for deriving the difference between the read transfer amount and the write transfer amount will be described.
[0031] Figure 4 shows a block diagram illustrating an example of the configuration of the monitoring device 16 in this embodiment. As shown in Figure 4, the monitoring device 16 in this embodiment differs from the monitoring device 16 shown in Figure 2 in that it includes a transfer amount counter 27 instead of a read transfer amount counter 24 and a write transfer amount counter 26, and the comparison circuit 30 does not include a subtractor 31.
[0032] The transfer volume counter 27 is a counter that, in DMA transfers controlled by the DMAC 12, adds (counts up) the counter value according to the amount of read transfer when a read transfer occurs at the source 18A, and subtracts (counts down) the counter value according to the amount of write transfer when a write transfer occurs at the destination 18B. If the counter value becomes "0" while subtracting the counter value according to the amount of write transfer, it should be counted up again.
[0033] Therefore, the count value of the transfer amount counter 27 when reading from the transfer source 18A and writing to the transfer destination 18B have been completed is the difference between the read transfer amount and the write transfer amount. The transfer amount counter 27 outputs the difference between the read transfer amount and the write transfer amount to the comparator 33 of the comparison circuit 30.
[0034] The comparator 33 receives the count value of the transfer amount counter 27, which is the difference between the read transfer amount and the write transfer amount, and the setting value of the DMAC maximum buffer amount setting register 28 as input. Therefore, the comparator 33 of the comparison circuit 30 shown in Figure 4 functions in the same way as the comparator 33 of the comparison circuit 30 shown in Figure 2, and outputs a judgment result regarding abnormalities in DMAC transfer.
[0035] Thus, in the monitoring device 16 of Example 2, abnormalities in the DMAC 12 can be monitored by monitoring the amount of DMA transfer.
[0036] As described above, the monitoring device 16 of the first embodiment monitors the comparison result between the read transfer amount, which is the amount of data transferred when data is read from the source 18A of the memory 18 by the control of the DMAC 12, and the write transfer amount, which is the amount of data transferred when the data read from the source 18A is written to the destination 18B of the memory 18 by the control of the DMAC 12.Therefore, the monitoring device 16 can monitor the DMA transfer amount even if the amount of data transferred is unknown, and thus can monitor abnormalities in the DMAC 12.
[0037] [Second Embodiment] Figure 5 shows a block diagram illustrating an example of the configuration of the monitoring device 16 in this embodiment.
[0038] As shown in Figure 5, the monitoring device 16 of this embodiment includes a source area setting register 20, a destination area setting register 22, a comparison circuit 30, a CPU write transfer amount counter 40, a CPU read transfer amount counter 42, a DMAC write transfer amount counter 44, and a DMAC read transfer amount counter 46.
[0039] The source area setting register 20 and the destination area setting register 22 are the same as in the first embodiment, so their description is omitted.
[0040] The CPU write transfer amount counter 40 is a counter that measures the amount of write transfers that occur at the source 18A under the control of the CPU 14. The amount of write transfers by the CPU 14 in this embodiment is an example of the third transfer amount in this disclosure. The CPU read transfer amount counter 42 is a counter that measures the amount of read transfers that occur at the destination 18B under the control of the CPU 14. The amount of read transfers by the CPU 14 in this embodiment is an example of the fourth transfer amount in this disclosure.
[0041] The DMAC write transfer amount counter 44 is the same as the read transfer amount counter 24 in the first embodiment. The read transfer amount of the DMAC 12 in this embodiment is an example of the first transfer amount in this disclosure. The DMAC read transfer amount counter 46 is the same as the write transfer amount counter 26 in the first embodiment. The write transfer amount of the DMAC 12 in this embodiment is an example of the second transfer amount in this disclosure.
[0042] When the CPU 14 pre-writes data to the source 18A and the DMAC 12 reads that data, it is presumed that the amount of data written by the CPU 14 to the source 18A and the amount of data read by the DMAC 12 will match. Similarly, when the CPU 14 reads data written to the destination 18B by the DMAC 12, it is presumed that the amount of data written by the DMAC 12 to the destination 18B and the amount of data read by the CPU 14 will match. However, due to differences in the transfer methods, there may be a difference between the amount of data transferred by the DMAC 12 and the amount of data transferred by the CPU 14. Therefore, in this embodiment, the maximum difference between the amount of data transferred by the DMAC 12 and the amount of data transferred by the CPU 14 is set as a set value in the maximum difference setting register 48. This set value may be set to a desired value depending on the DMAC 12, CPU 14, etc.
[0043] The comparison circuit 30 includes subtractors 31A and 31B, and comparators 33A and 33B. Subtractor 31A outputs the difference between the write transfer amount of CPU 14 and the read transfer amount of DMAC 12 to comparator 33A. Comparator 33A compares the difference between the write transfer amount of CPU 14 and the read transfer amount of DMAC 12 with the setting value of the maximum difference setting register 48 and outputs the comparison result. The storage unit 31B also outputs the difference between the write transfer amount of DMAC 12 to the transfer destination 18B and the read transfer amount of CPU 14 to comparator 33B. Comparator 33B compares the difference between the write transfer amount of DMAC 12 to the transfer destination 18B and the read transfer amount of CPU 14 and outputs the comparison result. The comparison results output from comparators 33A and 33B may be the same as those of comparator 33 in the comparison circuit 30 of the first embodiment.
[0044] The comparison circuit 30 determines whether the DMAC 12 is abnormal based on the comparison result of at least one of the comparators 33A and 33B. Specifically, the comparison circuit 30 determines that the DMAC is abnormal if the difference between the write transfer amount of the CPU 14 and the read transfer amount of the DMAC 12 exceeds the setting value of the maximum difference setting register 48, or if the difference between the write transfer amount of the DMAC 12 to the transfer destination 18B and the read transfer amount of the CPU 14 exceeds the setting value of the maximum difference setting register 48.
[0045] Incidentally, it is assumed that a further difference may occur between the transfer amount of the CPU 14 and the transfer amount of the DMAC 12 according to a specific rule. For example, when reading data only from the data area of a communication frame, a difference occurs in the amount of data corresponding to information not read by the CPU 14 (for example, check bits such as a checksum). Also, in the case of transfer according to the data amount, for example, transfer when an encryption process for data is performed within the same area, it is considered that in this case, two transfers of reading and rewriting always occur. Therefore, after performing a predetermined operation on at least one of the transfer amount of the DMAC 12 and the transfer amount of the CPU 14, the comparison circuit 30 may perform a comparison. For example, the transfer amount of the DMAC 12 may be multiplied by a coefficient set in a register in advance, a preset offset may be added (subtracted if the offset amount is a negative number), and then compared with the transfer amount of the CPU 14. Also, for example, conversely, the transfer amount of the CPU 14 may be multiplied by a coefficient set in a register in advance, a preset offset may be added (subtracted if the offset amount is a negative number), and then compared with the transfer amount of the DMAC 12.
[0046] Incidentally, different from this embodiment, the monitoring device 16 may be configured to determine that an abnormality has occurred when the difference between the write transfer amount of the CPU 14 and the read transfer amount of the DMAC 12 exceeds the set value of the maximum difference setting register 48. In this case, the DMAC write transfer amount counter 44, the DMAC read transfer amount counter 46, the subtracter 31B, and the comparator 33B may not be provided. Also, the monitoring device 16 may be configured to determine that an abnormality has occurred when the difference between the write transfer amount of the DMAC 12 to the transfer destination 18B and the read transfer amount of the CPU 14 exceeds the set value of the maximum difference setting register 48. In this case, the CPU write transfer amount counter 40, the CPU read transfer amount counter 42, the subtracter 31A, and the comparator 33A may not be provided.
[0047] As described above, the monitoring device 16 of the present embodiment monitors the comparison result between the data transfer amount by the control of the DMAC 12 and the data transfer amount by the control of the CPU 14 for the same area of the memory 18 (at least one of the transfer destination 18B and the transfer source 18A). Therefore, according to the monitoring device 16, even if the data transfer amount is unknown, the abnormality of the DMAC 12 can be monitored.
[0048] As described above, according to the monitoring device 16 of the first and second embodiments, even if the data transfer amount is unknown, the abnormality of the DMAC 12 can be monitored.
[0049] In the monitoring device 16 of the first and second embodiments, although one channel (a combination of the transfer destination and the transfer source to be monitored, or an area where transfer is performed by the DMAC 12 and the CPU 14) has been described, the above aspect may also be applied to a plurality of channels.
[0050] Further, in combination with the prior art, it may be combined with monitoring the transfer amount generated within a certain time or within a certain processing time, and setting a transfer prohibition area where the expected transfer amount is at most 0.
[0051] Further, the monitoring device 16 may further determine that the DMAC 12 is abnormal when the DMAC 12 writes to the transfer source 18A and when the DMAC 12 reads from the transfer destination 18B.
[0052] Moreover, each of the above embodiments is merely an example, and any change or improvement can be applied.
[0053] One or more elements included in one of the above plurality of embodiments can be combined with one or more elements included in other embodiments of the above plurality of embodiments.
[0054] (Notes) (Note 1) A monitoring device that monitors the comparison result between a first data transfer amount, which is the amount of data transferred when data is read from the source area of the memory under the control of a DMA (Direct Memory Access) control device, and a second data transfer amount, which is the amount of data transferred when the data read from the source area is written to the destination area of the memory under the control of the DMA control device.
[0055] (Appendix 2) The monitoring device described in Appendix 1 that determines an abnormality based on the difference between the first transfer amount and the second transfer amount.
[0056] (Note 3) The monitoring device described in Note 2, which determines an abnormality when the difference between the first transfer amount and the second transfer amount exceeds the maximum amount of the buffer of the DMA control device.
[0057] (Appendix 4) A monitoring device according to any one of Appendix 1 to 3, comprising: a first counter for counting the first transfer amount; a second counter for counting the second transfer amount; a subtractor for subtracting the second transfer amount from the first transfer amount; and a comparison circuit including a comparator for comparing the output of the subtractor with the maximum amount of the buffer of the DMA control device.
[0058] (Appendix 5) A monitoring device according to any one of Appendix 1 to 3, comprising: a counter whose count value is added according to the first transfer amount and whose count value is subtracted according to the second transfer amount; and a comparison circuit including a comparator that compares the count value of the counter after subtraction with the maximum amount of the buffer of the DMA control device.
[0059] (Note 6) A monitoring device that monitors the comparison result between the amount of data transferred to the same memory area under the control of the DMA control device and the amount of data transferred under the control of the CPU.
[0060] (Note 7) A monitoring device according to Note 6 that determines an abnormality based on: a first transfer amount, which is the amount of data transferred when data is read from the source area of the memory by the control of the DMA control device; a second transfer amount, which is the amount of data transferred when data read from the source area of the memory is written to the destination area of the memory by the control of the DMA control device; a third transfer amount, which is the amount of data transferred when data is written to the source area by the control of the CPU; and a fourth transfer amount, which is the amount of data transferred when data is read from the destination area by the control of the CPU.
[0061] (Appendix 8) The monitoring device according to Appendix 7, which determines an abnormality when the difference between the third transfer amount and the first transfer amount exceeds a set value, and when the difference between the fourth transfer amount and the second transfer amount exceeds the set value, in at least one of these cases.
[0062] (Note 9) The monitoring device described in Note 8, which allows the setting of the aforementioned set value.
[0063] (Note 10) A monitoring device according to any one of Note 6 to Note 9, which determines an abnormality if the result of a predetermined calculation performed on the difference between the amount of data transferred under the control of the CPU and the amount of data transferred under the control of the DMA control device exceeds a set value.
[0064] (Note 11) A monitoring method that uses a comparison circuit to monitor the comparison result between a first transfer amount, which is the amount of data transferred when data is read from the source area of the memory under the control of the DMA control device, and a second transfer amount, which is the amount of data transferred when the data read from the source area is written to the destination area of the memory under the control of the DMA control device.
[0065] (Appendix 12) A monitoring method that uses a comparison circuit to monitor the comparison result between the amount of data transferred under the control of the DMA control device and the amount of data transferred under the control of the CPU for the same area of memory.
[0066] The disclosure of Japanese Patent Application No. 2025-006450, filed on 16 January 2025, is incorporated herein by reference in its entirety. All documents, patent applications, and technical standards described herein are incorporated herein by reference to the same extent as if each individual document, patent application, and technical standard were specifically and individually noted to be incorporated by reference.
Claims
1. A monitoring device that monitors the comparison result between a first data transfer amount, which is the amount of data transferred when data is read from the source area of the memory under the control of a DMA control device, and a second data transfer amount, which is the amount of data transferred when the data read from the source area is written to the destination area of the memory under the control of the DMA control device.
2. The monitoring device according to claim 1, which determines an abnormality based on the difference between the first transfer amount and the second transfer amount.
3. The monitoring device according to claim 2, which determines an abnormality when the difference between the first transfer amount and the second transfer amount exceeds the maximum amount of the buffer of the DMA control device.
4. A monitoring device according to any one of claims 1 to 3, comprising: a first counter for counting the first transfer amount; a second counter for counting the second transfer amount; a subtractor for subtracting the second transfer amount from the first transfer amount; and a comparison circuit including a comparator for comparing the output of the subtractor with the maximum amount of the buffer of the DMA control device.
5. A monitoring device according to any one of claims 1 to 3, comprising: a counter whose count value is added according to the first transfer amount and whose count value is subtracted according to the second transfer amount; and a comparison circuit including a comparator that compares the count value of the counter after subtraction with the maximum amount of the buffer of the DMA control device.
6. A monitoring device that monitors the comparison between the amount of data transferred to the same memory region under the control of the DMA control device and the amount of data transferred under the control of the CPU.
7. The monitoring device according to claim 6, which determines an abnormality based on: a first transfer amount, which is the amount of data transferred when data is read from the source area of the memory by the control of the DMA control device; a second transfer amount, which is the amount of data transferred when data read from the source area of the memory is written to the destination area of the memory by the control of the DMA control device; a third transfer amount, which is the amount of data transferred when data is written to the source area by the control of the CPU; and a fourth transfer amount, which is the amount of data transferred when data is read from the destination area by the control of the CPU.
8. The monitoring device according to claim 7, which determines an abnormality when the difference between the third transfer amount and the first transfer amount exceeds a set value, and when the difference between the fourth transfer amount and the second transfer amount exceeds the set value, in at least one of these cases.
9. The monitoring device according to claim 8, wherein the setting value can be set.
10. A monitoring device according to any one of claims 6 to 9, wherein if the result of a predetermined calculation performed on the difference between the amount of data transferred under the control of the CPU and the amount of data transferred under the control of the DMA control device exceeds a set value, an abnormality is determined.
11. A monitoring method that uses a comparison circuit to monitor the comparison result between a first transfer amount, which is the amount of data transferred when data is read from the source area of the memory under the control of the DMA control device, and a second transfer amount, which is the amount of data transferred when the data read from the source area is written to the destination area of the memory under the control of the DMA control device.
12. A monitoring method that uses a comparison circuit to monitor the comparison result between the amount of data transferred to the same memory region under the control of a DMA control device and the amount of data transferred under the control of a CPU.