Imaging device and method for manufacturing same

Abstract

This imaging device comprises: a semiconductor substrate; a first through-via that penetrates the semiconductor substrate; a second through-via that is adjacent to the first through-via in a plan view of the semiconductor substrate and penetrates the semiconductor substrate; an insulating layer that covers the first through-via and the second through-via from above and overlaps the first through-via and the second through-via in the plan view; a first metal film that is disposed above the insulating layer and overlaps the first through-via in the plan view; and a second metal film that is disposed above the insulating layer and overlaps the second through-via in the plan view. The first metal film is separated from the second metal film.

Description

Imaging Device and Method for Manufacturing the Same

[0001] The present disclosure relates to an imaging device and a method for manufacturing the same.

[0002] In digital cameras and the like, imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used. As such an imaging device, an imaging device is known that includes a pixel portion and a peripheral circuit portion provided around the pixel portion, and the pixel portion includes a photoelectric conversion film, an upper electrode positioned above the photoelectric conversion film, and a lower electrode facing the upper electrode with the photoelectric conversion film interposed therebetween (see, for example, Patent Document 1). Further, this imaging device includes a semiconductor substrate and an interlayer insulating layer disposed between the semiconductor substrate and the photoelectric conversion film.

[0003] International Publication No. 2021 / 084971

[0004] By the way, in the imaging device as described in Patent Document 1, when a through-via penetrating the semiconductor substrate is provided, image quality deteriorates due to an increase in parasitic capacitance.

[0005] The present disclosure provides an imaging device and a method for manufacturing the same that can suppress an increase in parasitic capacitance even when a through-via penetrating the semiconductor substrate is provided.

[0006] An imaging device according to an aspect of the present disclosure includes a semiconductor substrate, a first through-via penetrating the semiconductor substrate, a second through-via that is adjacent to the first through-via in a plan view with respect to the semiconductor substrate and penetrates the semiconductor substrate, an insulating layer that covers above the first through-via and the second through-via and overlaps the first through-via and the second through-via in the plan view, a first metal film disposed above the insulating layer and overlapping the first through-via in the plan view, and a second metal film disposed above the insulating layer and overlapping the second through-via in the plan view. The first metal film is separated from the second metal film.

[0007] An imaging device according to another aspect of the present disclosure comprises a semiconductor substrate, a first through-via penetrating the semiconductor substrate, a plurality of pixels including optical black pixels, an insulating layer covering the top of the first through-via and overlapping the first through-via in a plan view with respect to the semiconductor substrate, a first metal film disposed above the insulating layer and overlapping the first through-via in a plan view, and a cover metal film disposed above the optical black pixels. The first metal film is separated from the cover metal film.

[0008] A method for manufacturing an imaging device according to one aspect of the present disclosure includes: forming a first through-via penetrating a semiconductor substrate; forming an insulating layer above the first through-via so as to overlap with the first through-via in a plan view of the semiconductor substrate; forming a metal layer above the insulating layer; and etching the metal layer to form a first metal film overlapping with the first through-via in a plan view and a separate metal film separated from the first metal film.

[0009] According to this disclosure, it is possible to provide an imaging apparatus and a method for manufacturing the same that can suppress an increase in parasitic capacitance even when through-vias are provided that penetrate a semiconductor substrate.

[0010] Figure 1 is a block diagram showing an example of the configuration of an imaging device according to one embodiment of the present disclosure. Figure 2 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device according to one embodiment of the present disclosure. Figure 3 is a cross-sectional view showing an example of the device structure of an imaging device according to one embodiment of the present disclosure. Figure 4 is a plan view showing an example of the structure of a through electrode and a metal film. Figure 5 is a plan view showing another example of the structure of a through electrode and a metal film. Figure 6 is a flowchart showing a method for manufacturing an imaging device. Figure 7 is a cross-sectional view illustrating a method for manufacturing an imaging device. Figure 8 is a cross-sectional view illustrating a method for manufacturing an imaging device. Figure 9 is a cross-sectional view illustrating a method for manufacturing an imaging device. Figure 10 is a cross-sectional view illustrating a method for manufacturing an imaging device. Figure 11 is a cross-sectional view illustrating a method for manufacturing an imaging device. Figure 12 is a cross-sectional view illustrating a method for manufacturing an imaging device. Figure 13 is a cross-sectional view illustrating a method for manufacturing an imaging device. Figure 14 is a cross-sectional view showing the device structure of an imaging device of a first modified example. Figure 15 is a plan view showing an example of the connection wiring and metal film structure of an imaging device of a first modified example. Figure 16 is a plan view showing another example of the connection wiring and metal film structure of an imaging device of a first modified example. Figure 17 is a cross-sectional view illustrating the manufacturing method of the first modified imaging device. Figure 18 is a cross-sectional view illustrating the manufacturing method of the first modified imaging device. Figure 19 is a cross-sectional view illustrating the manufacturing method of the first modified imaging device. Figure 20 is a cross-sectional view showing the device structure of the second modified imaging device. Figure 21 is a flowchart illustrating the manufacturing method of the second modified imaging device. Figure 22 is a cross-sectional view illustrating the manufacturing method of the second modified imaging device. Figure 23 is a cross-sectional view illustrating the manufacturing method of the second modified imaging device. Figure 24 is a cross-sectional view illustrating the manufacturing method of the second modified imaging device. Figure 25 is a cross-sectional view illustrating the manufacturing method of the second modified imaging device. Figure 26 is a cross-sectional view showing the device structure of the third modified imaging device. Figure 27 is a plan view showing an example of the structure of the through electrode and metal film of the fourth modified imaging device. Figure 28 is a plan view showing an example of the structure of the connection wiring and metal film of the fifth modified imaging device.

[0011] (Summary of this disclosure) An example of an imaging device and its manufacturing method related to this disclosure is shown below as an overview of this disclosure.

[0012] (First Embodiment) For example, an imaging device according to the first embodiment of the present disclosure comprises a semiconductor substrate, a first through-via penetrating the semiconductor substrate, a second through-via adjacent to the first through-via in a plan view with respect to the semiconductor substrate and penetrating the semiconductor substrate, an insulating layer covering the top of the first and second through-vias and overlapping the first and second through-vias in a plan view, a first metal film disposed above the insulating layer and overlapping the first through-via in a plan view, and a second metal film disposed above the insulating layer and overlapping the second through-via in a plan view. The first metal film is separated from the second metal film.

[0013] This makes it possible to suppress the increase in parasitic capacitance between the first and second through-vias, even if, for example, a short circuit occurs between the first through-via and the first metal film, or between the second through-via and the second metal film.

[0014] (Second Embodiment) For example, in the imaging device according to the first embodiment, the first metal film and the second metal film may have light-shielding properties.

[0015] This makes it possible to suppress the incidence of light on transistors and diodes, etc., included in sample-and-hold circuits and / or other circuits, around the first and second through-vias, by the first and second metal films.

[0016] (Third Embodiment) For example, an imaging device according to the third embodiment of the present disclosure is an imaging device according to the first or second embodiment, further comprising: a first connecting wire disposed between the first through via and the first metal film and connected to the first through via; and a second connecting wire disposed between the second through via and the second metal film and connected to the second through via. The first connecting wire may overlap with the first metal film in the plan view, and the second connecting wire may overlap with the second metal film in the plan view.

[0017] As a result, even if a short circuit occurs between the first connecting wire connected to the first through-via and the first metal film, or between the second connecting wire connected to the second through-via and the second metal film, it is possible to suppress the increase in parasitic capacitance between the first connecting wire connected to the first through-via and the second connecting wire connected to the second through-via.

[0018] (Fourth embodiment) For example, in the imaging device according to the third embodiment, the entirety of the first connecting wiring may overlap with the first metal film in the plan view, and the entirety of the second connecting wiring may overlap with the second metal film in the plan view.

[0019] This prevents the first and second connecting wires from being exposed.

[0020] (Fifth aspect) For example, an imaging device according to the fifth aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, which may further include a pixel array containing a plurality of pixels arranged in a matrix in a plan view. The first through via and the second through via may be located outside the pixel array in a plan view.

[0021] This allows the first and second through-vias to be placed outside the pixel array, making it easier to suppress the increase in parasitic capacitance compared to, for example, forming the first and second through-vias within the pixel array.

[0022] (Sixth Embodiment) For example, an imaging device according to the sixth embodiment of the present disclosure is an imaging device according to the second embodiment, further comprising a plurality of pixels including optical black pixels, and a cover metal film disposed above the optical black pixels. The upper surface of the cover metal film may be located above the upper surface of the first metal film and the upper surface of the second metal film.

[0023] This allows the first and second metal films to be positioned below the cover metal film, thus enabling them to be placed closer to the light-shielding object, such as a sample-hold circuit. This improves the light-shielding performance.

[0024] (Seventh aspect) For example, in an imaging device according to any one of the first to sixth aspects, the entirety of the first through via may overlap with the first metal film in the plan view.

[0025] This prevents the first through via from being exposed.

[0026] (Eighth aspect) For example, in an imaging device according to any one of the first to seventh aspects, the entirety of the second through via may overlap with the second metal film in the plan view.

[0027] This prevents the second through via from being exposed.

[0028] (9th aspect) For example, an imaging device according to the 9th aspect of the present disclosure is an imaging device according to any one of the 1st to 8th aspects, which may further include a photoelectric conversion layer disposed above the insulating layer.

[0029] Thus, in a configuration in which the photoelectric conversion layer is positioned above the insulating layer, adverse effects such as those caused by copper exposure (described later) and / or light reflected by the first through-via, etc., are more likely to occur compared to a configuration in which the photoelectric conversion layer is formed on the semiconductor substrate. For this reason, applying this disclosure to a configuration in which the photoelectric conversion layer is positioned above the insulating layer is particularly effective.

[0030] (Tenth Embodiment) For example, in an imaging device according to any one of the first to ninth embodiments, at least one selected from the group consisting of the first metal film and the second metal film may be in an electrically floating state.

[0031] As a result, even if a short circuit occurs between the first through-via and the first metal film, or between the second through-via and the second metal film, the potential of the first and second through-vias is maintained, thus preventing the imaging device from failing. However, if the first and second metal films have an potential, i.e., are not in a floating state, a potential difference will occur between the first through-via and the first metal film, and between the second through-via and the second metal film, making short circuits more likely. If a short circuit occurs between the first through-via and the first metal film, and / or between the second through-via and the second metal film, where parts have different potentials, the imaging device will fail.

[0032] (11th embodiment) For example, in an imaging device according to any one of the first to tenth embodiments, the potential of the first through via may be different from the potential of the second through via.

[0033] Thus, when the potential of the first through-via and the potential of the second through-via are different, it is preferable to separate the first metal film from the second metal film.

[0034] (Twelfth Embodiment) For example, an imaging device according to the twelfth embodiment of the present disclosure is an imaging device according to any one of the first to eleventh embodiments, further comprising a pixel region including a plurality of pixels and a peripheral region provided around the pixel region. The imaging device may be provided with a plurality of through vias, the plurality of through vias arranged in the peripheral region and including a first through via and a second through via, the imaging device may be provided with a plurality of metal films, the plurality of metal films arranged above the insulating layer and including a first metal film and a second metal film, in plan view each of the plurality of metal films may overlap with a corresponding through via among the plurality of through vias, the insulating layer may overlap all of the plurality of through vias in plan view, and the plurality of metal films may be spaced apart from each other.

[0035] This makes it possible to suppress the increase in parasitic capacity for all through vias located in the surrounding area, for example.

[0036] (Third Embodiment) For example, an imaging device according to the thirteenth embodiment of the present disclosure comprises a semiconductor substrate, a first through-via penetrating the semiconductor substrate, a plurality of pixels including optical black pixels, an insulating layer covering the upper part of the first through-via and overlapping the first through-via in a plan view with respect to the semiconductor substrate, a first metal film disposed above the insulating layer and overlapping the first through-via in a plan view, and a cover metal film disposed above the optical black pixels. The first metal film is separated from the cover metal film.

[0037] This suppresses the increase in parasitic capacitance that occurs in the first through-via. Specifically, for example, if the first metal film and the cover metal film are connected and not separated, a short circuit occurs between the first through-via and the first metal film, and the parasitic capacitance that the cover metal film has between itself and the surrounding wiring is added as the parasitic capacitance of the first through-via. As a result, the parasitic capacitance of the first through-via increases. However, by separating the first metal film and the cover metal film, even if a short circuit occurs between the first through-via and the first metal film, the parasitic capacitance that the cover metal film has between itself and the surrounding wiring is suppressed from being added as the parasitic capacitance of the first through-via. As a result, the increase in parasitic capacitance that occurs in the first through-via can be suppressed.

[0038] Furthermore, even if a short circuit occurs between the first through-via and the first metal film when the cover metal film has an electrical potential, the separation between the first metal film and the cover metal film prevents a short circuit from occurring between areas with different electrical potentials. This helps to prevent the imaging device from malfunctioning.

[0039] (14th embodiment) For example, in the imaging device according to the 13th embodiment, the first metal film may have light-shielding properties.

[0040] This allows the first metal film to suppress the incidence of light on transistors and diodes, etc., included in sample-and-hold circuits and / or other circuits, around the first through-via.

[0041] (15th Aspect) For example, the imaging device according to the 15th aspect of the present disclosure is the imaging device according to the 13th aspect or the 14th aspect, and may further include a first connection wiring disposed between the first through via and the first metal film and connected to the first through via. The first connection wiring may overlap the first metal film in the plan view.

[0042] Thereby, it is possible to suppress an increase in the parasitic capacitance generated in the first through via. Specifically, for example, when the first metal film and the cover metal film are not separated but connected, if a short occurs between the first connection wiring connected to the first through via and the first metal film, the parasitic capacitance that the cover metal film has with the surrounding wirings etc. is added as the parasitic capacitance of the first through via. For this reason, the parasitic capacitance of the first through via increases. However, by separating the first metal film and the cover metal film, even when a short occurs between the first connection wiring connected to the first through via and the first metal film, it is possible to suppress the parasitic capacitance that the cover metal film has with the surrounding wirings etc. from being added as the parasitic capacitance of the first through via. For this reason, it is possible to suppress an increase in the parasitic capacitance generated in the first through via.

[0043] Further, when the cover metal film has a potential, even if a short occurs between the first connection wiring connected to the first through via and the first metal film, since the first metal film and the cover metal film are separated, it is possible to suppress a short between parts having different potentials. For this reason, it is possible to suppress the imaging device from malfunctioning.

[0044] (16th Aspect) For example, in the imaging device according to the 第15態様, the entire first connection wiring may overlap the first metal film in the plan view.

[0045] Thereby, it is possible to suppress the first connection wiring from being exposed.

[0046] (17th Aspect) For example, in the imaging device according to any one of the 13th aspect to the 16th aspect, the entire first through via may overlap the first metal film in the plan view.

[0047] This can suppress the exposure of the first through via.

[0048] (18th Aspect) For example, in the imaging device according to any one of the 13th to 17th aspects, the first metal film may be in an electrically floating state.

[0049] This can suppress the failure of the imaging device even when a short circuit occurs between the first through via and the first metal film.

[0050] (19th Aspect) Further, for example, the method of manufacturing an imaging device according to the 19th aspect of the present disclosure includes forming a first through via penetrating a semiconductor substrate, forming an insulating layer above the first through via so as to overlap the first through via in a plan view with respect to the semiconductor substrate, forming a metal layer above the insulating layer, and etching the metal layer to form a first metal film overlapping the first through via in the plan view and a separation metal film separated from the first metal film.

[0051] This can suppress an increase in the parasitic capacitance generated in the first through via. Specifically, for example, when the first metal film and the separation metal film are not separated but connected, if a short circuit occurs between the first through via and the first metal film, the parasitic capacitance that the separation metal film has with surrounding wirings and the like is added as the parasitic capacitance of the first through via. Therefore, the parasitic capacitance of the first through via increases. However, by separating the first metal film and the separation metal film, even when a short circuit occurs between the first through via and the first metal film, it is possible to suppress the parasitic capacitance that the separation metal film has with surrounding wirings and the like from being added as the parasitic capacitance of the first through via. Therefore, an increase in the parasitic capacitance generated in the first through via can be suppressed.

[0052] (20th aspect) For example, in the manufacturing method of an imaging device according to the 19th aspect, forming the metal layer may include forming the metal layer above the insulating layer and above a plurality of pixels including optical black pixels, and forming the first metal film and the separating metal film may include forming the separating metal film such that the separating metal film and the optical black pixels overlap in the plan view.

[0053] This allows for the simultaneous formation of the first metal film and the separation metal film positioned above the optical black pixel. Therefore, the manufacturing method of the imaging device can be simplified.

[0054] Embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components. In each figure, components having substantially the same function are indicated by a common reference numeral, and redundant descriptions may be omitted or simplified.

[0055] Furthermore, the various elements shown in the drawings are for illustrative purposes only, and their dimensional ratios and appearance may differ from those of the actual object. In other words, each drawing is a schematic representation and not necessarily a strictly accurate depiction. Therefore, for example, the scale in each drawing may not necessarily match.

[0056] Furthermore, in this specification, terms indicating relationships between elements, such as vertical or parallel, terms indicating the shape of elements, such as circular or rectangular, and numerical ranges are not expressions that represent only strict meanings, but also expressions that include substantially equivalent ranges, such as differences of a few percent.

[0057] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Specifically, the light-receiving side of the imaging device is defined as "upper," and the side opposite the light-receiving side is defined as "lower." Similarly, for the "upper surface" and "lower surface" of each component, the light-receiving side of the imaging device is defined as the "upper surface," and the side opposite the light-receiving side is defined as the "lower surface." It should be noted that terms such as "upper," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device when in use. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other. Furthermore, in this specification, "plan view" refers to a view taken from a direction perpendicular to the semiconductor substrate (in other words, in the thickness direction of the semiconductor substrate).

[0058] (Embodiment) An imaging device according to one embodiment of the present disclosure will be described.

[0059] [Configuration] First, an overview of the configuration of an imaging device according to one embodiment of this disclosure will be described. Figure 1 is a block diagram showing an example of the configuration of an imaging device 100 according to one embodiment of this disclosure.

[0060] As shown in Figure 1, the imaging device 100 comprises a first substrate 10 and a second substrate 20. In this embodiment, the first substrate 10 is provided with a pixel array 30 composed of a plurality of pixels 31 and a plurality of through electrodes 41. The second substrate 20 is provided with peripheral circuits 51. The plurality of through electrodes 41 connect the plurality of pixels 31 and the peripheral circuits 51. The peripheral circuits 51 include circuits for driving the plurality of pixels 31 and circuits for processing signals output by the plurality of pixels 31. In the example shown in Figure 1, it includes a vertical scanning circuit 52, a column signal processing circuit 53, a memory (not shown), and a control circuit (not shown). The through electrodes 41 are an example of "through vias" in this disclosure. Note that some of the peripheral circuits 51 may be arranged on the first substrate 10. The through electrodes 41 may also connect peripheral circuits arranged on the first substrate 10 and peripheral circuits arranged on the second substrate 20.

[0061] As will be described in more detail later, the first substrate 10 and the second substrate 20 are stacked on top of each other. The electrical connection between the first substrate 10 and the second substrate 20 is made via a plurality of through electrodes 41.

[0062] The pixel array 30 includes a plurality of pixels 31 arranged in two dimensions. In this embodiment, the pixel array 30 includes a plurality of pixels 31 arranged in a matrix (matrix) in a planar view. Each of the plurality of pixels 31 includes a photoelectric conversion unit that converts light into electric charge and outputs a signal corresponding to the incidence of light on the photoelectric conversion unit.

[0063] Multiple pixels 31 are connected to an external power supply that provides voltage via through electrodes 41. At least a portion of the power supply may be provided in the imaging device 100.

[0064] The vertical scanning circuit 52 is connected to the multiple pixels 31 via control signal lines L1 provided for each row of pixels 31, and performs signal reading and resetting of the pixels 31 for each row of pixels 31. Figure 1 shows a diagram in which one control signal line L1 is provided for each row of pixels 31, but multiple control signal lines L1 may be provided for each row of pixels 31. The control signal line L1 is connected to the vertical scanning circuit 52 via through electrodes 41.

[0065] The column signal processing circuit 53 is connected to the multiple pixels 31 via vertical signal lines L2 provided for each column of the multiple pixels 31, and converts the analog signal output for each column of the multiple pixels 31 into a digital signal. The vertical signal lines L2 are connected to the column signal processing circuit 53 via through electrodes 41.

[0066] The memory (not shown) temporarily stores, for example, the digital signals converted by the column signal processing circuit 53.

[0067] A control circuit (not shown) controls the operation of the imaging device 100. The control circuit controls the operation of at least one of the memory, the vertical scanning circuit 52, and the column signal processing circuit 53. The control circuit may be implemented, for example, by a microcontroller or one or more processors. The functions of the control circuit may be implemented by a combination of general-purpose processing circuits and software, or by hardware specialized for such processing.

[0068] Figure 2 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device 100 according to one embodiment of the present disclosure. In Figure 2, four pixels 31 arranged in two rows and two columns are shown as representative examples to avoid complexity in the drawing. Each of these pixels 31 is an example of the pixel 31 shown in Figure 1. Each of the pixels 31 has a photoelectric conversion unit 70 and includes a signal detection circuit 314 electrically connected to the photoelectric conversion unit 70.

[0069] The photoelectric conversion unit 70 generates positive and negative charges, typically hole-electron pairs, upon the incidence of light. The photoelectric conversion unit 70 may be a photoelectric conversion structure including a photoelectric conversion layer disposed above the semiconductor substrate 11, or a photodiode formed on the semiconductor substrate 11. The photoelectric conversion units 70 of each pixel 31 are arranged continuously on the semiconductor substrate 11 without spacing between them. Alternatively, the photoelectric conversion units 70 of each pixel 31 may be spatially separated from each other.

[0070] Each pixel 31's photoelectric conversion unit 70 has a connection to a storage control line 331. When the imaging device 100 is operating, a predetermined voltage is applied to the storage control line 331. For example, if the positive charge among the positive and negative charges generated by photoelectric conversion is used as the signal charge, a positive voltage of, for example, about 10V may be applied to the storage control line 331 when the imaging device 100 is operating. The following example illustrates the case where a hole is used as the signal charge.

[0071] In the configuration illustrated in Figure 2, the signal detection circuit 314 includes a signal detection transistor 322, an address transistor 324, a reset transistor 326, and a protection transistor 327. The signal detection transistor 322, the address transistor 324, the reset transistor 326, and the protection transistor 327 are typically field-effect transistors (FETs) formed on the semiconductor substrate 11 supporting the photoelectric conversion unit 70. In the following, unless otherwise specified, examples using N-channel MOSFETs as transistors will be described.

[0072] As schematically shown in Figure 2, the gate of the signal detection transistor 322 is electrically connected to the photoelectric conversion unit 70. In the illustrated example, the charge storage node FD, which connects the gate of the signal detection transistor 322 to the photoelectric conversion unit 70, has the function of temporarily holding the charge generated by the photoelectric conversion unit 70. By applying a predetermined voltage to the storage control line 331 during operation, for example, holes can be stored in the charge storage node FD as signal charge. The charge storage node FD includes an impurity region formed on the semiconductor substrate 11 as part of its structure.

[0073] One of the drains and sources of the signal detection transistor 322 is connected to the power supply wiring 332. The power supply wiring 332 supplies a power supply voltage VDD1 to each pixel 31 when the imaging device 100 is operating. The power supply voltage VDD1 is, for example, 3.3V. The other of the drains and sources of the signal detection transistor 322 is connected to the vertical signal line L2 via the address transistor 324. By receiving the power supply voltage VDD1 on the other of the drains and sources, the signal detection transistor 322 outputs a signal voltage corresponding to the amount of signal charge stored in the charge storage node FD.

[0074] The gate of the address transistor 324, which is connected between the signal detection transistor 322 and the vertical signal line L2, is connected to the control signal line L1. The vertical scanning circuit 52 applies a row selection signal to the control signal line L1 to control the on and off states of the address transistor 324. This allows the output of the signal detection transistor 322 of the selected pixel 31 to be read out to the corresponding vertical signal line L2. Note that the arrangement of the address transistor 324 is not limited to the example shown in Figure 2, and may be between the drain of the signal detection transistor 322 and the power supply wiring 332.

[0075] The gate and drain of the protection transistor 327, and one of its sources, are connected to the charge storage node FD. The other of the drain and source of the protection transistor 327 is connected to the power supply wiring 337. The power supply wiring 337 supplies a power supply voltage VDD2 to each pixel 31 when the imaging device 100 is in operation. The power supply voltage VDD2 is, for example, 2.0V. When high-brightness light is incident on the photoelectric conversion unit 70, the amount of holes accumulated in the charge storage node FD increases. In that case, a bias exceeding, for example, 5V may occur in the charge storage node FD, potentially destroying the gate oxide film of the signal detection transistor 322 connected to the charge storage node FD. Therefore, when a high bias exceeding 5V occurs in the charge storage node FD, for example, the protection transistor 327 is made to conduct. This allows the holes accumulated in the charge storage node FD to be discharged, thereby lowering the potential of the charge storage node FD.

[0076] A load circuit 345 and a column signal processing circuit 347 are connected to each of the vertical signal lines L2. The load circuit 345, together with the signal detection transistor 322, forms a source follower circuit. The column signal processing circuit 347, also called a row signal storage circuit, performs noise suppression signal processing and analog-to-digital conversion, such as correlated double sampling. The column signal processing circuit 53 sequentially reads signals from the multiple column signal processing circuits 347 to the horizontal common signal line 349. The load circuit 345 and the column signal processing circuits 347 may be part of the peripheral circuit 51 described above.

[0077] A reset signal line 336, which has a connection to the vertical scanning circuit 52, is connected to the gate of the reset transistor 326. The reset signal line 336 is provided for each row of pixels 31, similar to the control signal line L1. The vertical scanning circuit 52 can select the pixels 31 to be reset on a row-by-row basis by applying a row selection signal to the control signal line L1. The vertical scanning circuit 52 can also switch the reset transistor 326 of the selected row on and off by applying a reset signal to the gate of the reset transistor 326 via the reset signal line 336. When the reset transistor 326 is turned on, the potential of the charge storage node FD is reset.

[0078] In this example, one of the drains and sources of the reset transistor 326 is connected to the charge storage node FD, and the other drain and source is connected to the corresponding feedback line 353 provided for each row of pixels 31. That is, in this example, the voltage of the feedback line 353 is supplied to the charge storage node FD as a reset voltage to initialize the charge of the photoelectric conversion unit 70.

[0079] In the configuration illustrated in Figure 2, the imaging device 100 has a feedback circuit 316 that includes an inverting amplifier 350 as part of the feedback path. As shown in Figure 2, an inverting amplifier 350 is provided for each row of pixels 31, and the above-mentioned feedback line 353 is connected to the corresponding output terminal of one of the multiple inverting amplifiers 350. The inverting amplifier 350 may be part of the peripheral circuit 51 described above.

[0080] As shown in Figure 2, the inverting input terminal of the inverting amplifier 350 is connected to the corresponding vertical signal line L2, and a reference voltage Vref is supplied to the non-inverting input terminal of the inverting amplifier 350 when the imaging device 100 is operating. By turning on the address transistor 324 and the reset transistor 326, a feedback path can be formed that negatively feeds back the output of the pixel 31. With the formation of the feedback path, the voltage of the vertical signal line L2 converges to the reference voltage Vref, which is the input voltage to the non-inverting input terminal of the inverting amplifier 350. In other words, with the formation of the feedback path, the voltage of the charge storage node FD is reset to a voltage such that the voltage of the vertical signal line L2 becomes the reference voltage Vref. The reference voltage Vref can be any voltage within the range of the power supply voltage and ground. The reference voltage Vref is, for example, a positive voltage of 1V or near 1V. With the formation of the feedback path, the reset noise that is generated when the reset transistor 326 is turned off can be reduced.

[0081] Next, the detailed device configuration of the imaging device 100 according to this embodiment will be described with reference to Figure 3. Figure 3 is a cross-sectional view showing an example of the device structure of the imaging device 100 according to one embodiment of this disclosure. Note that in Figure 3, for ease of viewing, hatching indicating the cross-section of the insulating layers 12 and 22 has been omitted. This is also the case in subsequent cross-sectional views.

[0082] As shown in Figure 3, the imaging device 100 comprises a first substrate 10, a second substrate 20, a photoelectric conversion unit 70, a connecting electrode 75, an insulating layer 81, a cover metal film 82, a color filter (not shown), and a microlens (not shown). The photoelectric conversion unit 70, the insulating layer 81, the color filter (not shown), and the microlens (not shown) are included in each pixel 31 (see Figure 1). The cover metal film 82 is an example of the "separation metal film" of this disclosure.

[0083] The first substrate 10 and the second substrate 20 are stacked on top of each other. For example, in a plan view, the first substrate 10 and the second substrate 20 have the same shape and size, and their outer edges coincide. The first substrate 10 and the second substrate 20 are joined at the interface between them. The first substrate 10 and the second substrate 20 can be manufactured, for example, using a semiconductor manufacturing process.

[0084] The first substrate 10 has, in a plan view, a pixel region R1 in which a plurality of pixels 31 (see Figure 1) are arranged, and a peripheral region R2 provided around the pixel region R1. The pixel region R1 is the region in which the pixel array 30 (see Figure 1) is formed. The pixel region R1 is, for example, a rectangular region. The peripheral region R2 is, for example, arranged to surround the pixel region R1 in a plan view.

[0085] The first substrate 10 includes a semiconductor substrate 11 located in the pixel region R1 and the peripheral region R2, and an insulating layer 12 located above the semiconductor substrate 11 in the pixel region R1 and the peripheral region R2. In the example shown in Figure 3, the insulating layer 12 is located on the upper surface of the semiconductor substrate 11.

[0086] The second substrate 20 includes a semiconductor substrate 21 and an insulating layer 22 located above the semiconductor substrate 21. In the example shown in Figure 3, the insulating layer 22 is located on the upper surface of the semiconductor substrate 21. The orientation of the second substrate 20 may be reversed compared to the example shown in Figure 3.

[0087] The semiconductor substrates 11 and 21 are, for example, p-type or n-type semiconductor substrates in which various impurity regions are formed. Wells may be formed in each of the semiconductor substrates 11 and 21. In this embodiment, the semiconductor substrates 11 and 21 are, for example, silicon substrates.

[0088] A detection circuit 32 for each pixel 31 is formed on the upper surface of the semiconductor substrate 11. A detection circuit 32 is provided for each pixel 31. Figure 3 shows a portion of the transistors in the detection circuit 32.

[0089] The insulating layer 12 is a layer formed of an insulating material such as silicon dioxide or tetraethyl orthosilicate (TEOS).

[0090] A wiring layer is arranged within the insulating layer 12. In the example shown in Figure 3, the imaging device 100 has wiring layers 15A and 15B provided within the insulating layer 12 in the pixel region R1. Each wiring within the insulating layer 12, such as wiring 15A and 15B, is connected to wiring arranged in another wiring layer via vias 18. The vias 18 are columnar conductors extending in the thickness direction of the semiconductor substrate 11. In the example shown in Figure 3, the imaging device 100 also includes a pixel electrode 71, vias 18, and a contact plug 19. The contact plug 19 is a columnar conductor extending in the thickness direction of the semiconductor substrate 11. In the pixel region R1, it includes vias 18 arranged within the insulating layer 12 and connected to wiring 15B and the pixel electrode 71. The pixel electrode 71 is connected to the detection circuit 32 via vias 18, wiring 15B, 15A, and the contact plug 19. The detection circuit 32 is connected to the pixel electrode 71 of the photoelectric conversion unit 70 and detects a signal based on the charge generated by the photoelectric conversion unit 70.

[0091] Peripheral circuits 51 (see Figure 1) are formed on the upper surface of the semiconductor substrate 21. Note that in Figure 3, peripheral circuits 51 are omitted for the sake of simplifying the drawing.

[0092] The insulating layer 22 is made of an insulating material such as silicon dioxide. A wiring layer is arranged within the insulating layer 22. In the example shown in Figure 3, wiring 25 is provided as a wiring layer within the insulating layer 22 in the peripheral region R2. Here, wiring 25 includes wirings 25A and 25B formed from the same wiring layer. Each wiring within the insulating layer 22, such as wiring 25, is connected to the peripheral circuit 51 via vias and contact plugs (not shown). Furthermore, wirings 25A and 25B are connected to wiring 15A or 15B (here, wiring 15A) of the first substrate 10 via through electrodes 41.

[0093] Specifically, the through electrode 41 includes a first through electrode 41A and a second through electrode 41B positioned adjacent to the first through electrode 41A in a plan view. The first through electrode 41A connects wiring 25A and wiring 15A. The second through electrode 41B connects wiring 25B and wiring 15A. Hereinafter, wiring 15A connected to the first through electrode 41A may be referred to as wiring 151. Similarly, wiring 15A connected to the second through electrode 41B may be referred to as wiring 152. The first through electrode 41A is an example of the "first through via" in this disclosure. The second through electrode 41B is an example of the "second through via" in this disclosure.

[0094] The wiring 15A, 15B, 25, vias, and contact plugs, which are arranged within the insulating layer 12 and the insulating layer 22, are formed of, for example, metal. The wiring 15A, 15B, 25, vias, and contact plugs are formed using, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum.

[0095] The photoelectric conversion unit 70 generates positive and negative charges upon the incidence of light. In other words, the photoelectric conversion unit 70 converts light into electric charge. The photoelectric conversion unit 70 includes a pixel electrode 71, a counter electrode 72, and a photoelectric conversion layer 73. The photoelectric conversion unit 70 may further include other layers, such as a charge blocking layer, a buffer layer, or a charge transport layer, at least one of the spaces between the pixel electrode 71 and the photoelectric conversion layer 73, and between the photoelectric conversion layer 73 and the counter electrode 72.

[0096] The pixel electrode 71 is located on the upper surface of the insulating layer 12 in the pixel region R1. The pixel electrode 71 is a film-like electrode. The pixel electrode 71 may contain at least one selected from metals, metal compounds, and polysilicon doped with impurities to impart conductivity. Examples of metals include copper, titanium, tantalum, and aluminum. Examples of metal compounds include metal nitrides. Examples of metal nitrides include titanium nitride and tantalum nitride. The pixel electrode 71 may contain metal nitride as its main component. In this embodiment, the pixel electrode 71 does not contain copper.

[0097] The photoelectric conversion layer 73 is located above the pixel electrode 71 and covers the pixel electrode 71. The photoelectric conversion layer 73 is also positioned above the insulating layer 12. The photoelectric conversion layer 73 contains an organic semiconductor material and, upon receiving light incident via the counter electrode 72, generates positive and negative charges through photoelectric conversion. In other words, the photoelectric conversion layer 73 converts light into electric charge. The photoelectric conversion layer 73 may also contain an inorganic semiconductor material such as amorphous silicon. The positive and negative charges are, for example, hole-electron pairs. The photoelectric conversion layer 73 is formed continuously across multiple pixels 31, for example. The photoelectric conversion layer 73 is shared by multiple pixels 31. The photoelectric conversion layer 73 may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0098] The counter electrode 72 is located above the photoelectric conversion layer 73 and covers the photoelectric conversion layer 73. The counter electrode 72 is a film-like electrode. In the example shown in Figure 3, the counter electrode 72 and the photoelectric conversion layer 73 are aligned in terms of their side surfaces when viewed from above. The counter electrode 72 is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is positioned on the light-receiving surface side of the photoelectric conversion layer 73. The counter electrode 72 is formed continuously across multiple pixels 31, similar to the photoelectric conversion layer 73. That is, the counter electrodes 72 of multiple pixels 31 are electrically connected to each other. The counter electrodes 72 may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0099] The potential of the counter electrode 72 is controlled via the connecting electrode 75. When the imaging device 100 is in operation, the potential of the counter electrode 72 is controlled to make it different from the potential of the pixel electrode 71, so that the signal charge generated by photoelectric conversion can be collected by the pixel electrode 71. The signal charge collected by the pixel electrode 71 is stored in a charge storage region connected to the pixel electrode 71 and detected by the detection circuit 32.

[0100] The insulating layer 81 is formed above the counter electrode 72. The insulating layer 81 is made of an insulating material such as silicon dioxide, silicon oxynitride, and aluminum oxide. A color filter (not shown) is located above the counter electrode 72 and faces the counter electrode 72 via the insulating layer 81. The color filter (not shown) is formed, for example, as an on-chip color filter by patterning, and a photosensitive resin in which dyes or pigments are dispersed is used. A microlens (not shown) is located above the color filter (not shown) and faces the color filter (not shown). The microlens (not shown) is formed, for example, as an on-chip microlens, and an ultraviolet photosensitive material is used.

[0101] The connecting electrode 75 is positioned in the peripheral region R2. The connecting electrode 75 is located on the upper surface of the insulating layer 12 in the peripheral region R2. The connecting electrode 75 is a film-like electrode. In the example shown in Figure 3, the connecting electrode 75 is located in the same layer as the pixel electrode 71. This allows the connecting electrode 75 to be formed simultaneously using the same process as the pixel electrode 71, thereby simplifying the manufacturing process of the imaging device 100. In this specification, "located in the same layer" means that the distance from the semiconductor substrate 11 is the same.

[0102] The material used for the connecting electrode 75 can be the same material used for the pixel electrode 71. The connecting electrode 75 may contain the same material as the material used for the pixel electrode 71. In this embodiment, the material of the connecting electrode 75 and the material of the pixel electrode 71 are the same. This allows for the common use of materials for the pixel electrode 71 and the connecting electrode 75, thereby reducing the number of materials used in the manufacture of the imaging device 100.

[0103] In the example shown in Figure 3, the connecting electrode 75 is electrically connected to the counter electrode 72 via a conductive cover metal film 82. Specifically, the connecting electrode 75 is electrically connected to the cover metal film 82 on its upper surface, and the counter electrode 72 is electrically connected to the cover metal film 82 on its side surface near the connecting electrode 75. The cover metal film 82 is in contact with the upper surface of the connecting electrode 75 and the side surface of the counter electrode 72. Note that the connecting electrode 75 may also be connected to the counter electrode 72 via a conductor other than the cover metal film 82, as long as it is electrically connected to the counter electrode 72.

[0104] The cover metal film 82 covers at least a portion of the counter electrode 72 from above. In this embodiment, the cover metal film 82 covers the connecting electrode 75 and a portion of the counter electrode 72 from above. In the pixel region R1, the cover metal film 82 is located above the insulating layer 81 and faces the counter electrode 72. Here, the cover metal film 82 has light-shielding properties. In this specification, having light-shielding properties means, for example, that the light-shielding rate is 99% or more. The cover metal film 82 shields the light directed toward the photoelectric conversion unit 70 of some of the pixels 31, specifically the pixels 31 located at the ends of the pixel array 30. Therefore, the pixels 31 whose photoelectric conversion unit 70 is covered by the cover metal film 82 become optical black pixels. In the peripheral region R2, the cover metal film 82 is located above the connecting electrode 75. The provision of optical black pixels has the following advantages. Specifically, the multiple pixels 31 include pixels 31 in the effective pixel region that are not covered by the cover metal film 82, and optical black pixels 31 that are covered by the cover metal film 82. Even when these pixels 31 are not receiving light, noise signals are generated due to temperature and other factors. Therefore, it is possible to reduce the noise by correcting the signals generated by the pixels 31 in the effective pixel region using the signals generated by the optical black pixels.

[0105] Furthermore, the cover metal film 82 covers the sides of the insulating layer 81, the counter electrode 72, and the photoelectric conversion layer 73. In other words, the cover metal film 82 is formed from the connecting electrode 75, through the sides of the insulating layer 81, the counter electrode 72, and the photoelectric conversion layer 73, up to the upper surface of the insulating layer 81. The cover metal film 82 electrically connects the connecting electrode 75 and the counter electrode 72.

[0106] Furthermore, a plurality of metal films 83 are provided on the insulating layer 12. The plurality of metal films 83 are formed from the same metal layer as the cover metal film 82. This allows the plurality of metal films 83 to be formed using the same process as the cover metal film 82, thereby simplifying the manufacturing process of the imaging device 100. In this embodiment, the plurality of metal films 83 include at least a first metal film 83A and a second metal film 83B. That is, the first metal film 83A and the second metal film 83B are provided on the insulating layer 12. The first metal film 83A and the second metal film 83B are formed from the same metal layer as the cover metal film 82. This allows the first metal film 83A and the second metal film 83B to be formed using the same process as the cover metal film 82, thereby simplifying the manufacturing process of the imaging device 100. The second metal film 83B is an example of the "separation metal film" of this disclosure.

[0107] The distance between the first metal film 83A and the second metal film 83B is several to tens of times greater than the distance between the through electrode 41 and the metal film 83. Similarly, the distance between the first metal film 83A and the cover metal film 82 is several to tens of times greater than the distance between the through electrode 41 and the metal film 83.

[0108] Furthermore, in this embodiment, the upper surface 82a of the cover metal film 82 is located above the upper surface 831 of the first metal film 83A and the upper surface 831 of the second metal film 83B. Specifically, the upper surface 82a of the portion 82b of the cover metal film 82 above the optical black pixels is located above the upper surface 831 of the first metal film 83A and the upper surface 831 of the second metal film 83B.

[0109] The cover metal film 82, the first metal film 83A, and the second metal film 83B each include at least one selected from the group consisting of metals and metal compounds. The cover metal film 82, the first metal film 83A, and the second metal film 83B are formed of metal. The cover metal film 82, the first metal film 83A, and the second metal film 83B each include at least one selected from the group consisting of, for example, titanium, titanium nitride, tantalum, and tungsten. By forming the cover metal film 82, the first metal film 83A, and the second metal film 83B from the above materials, it is possible to make the light reflectivity relatively small. In this embodiment, the cover metal film 82, the first metal film 83A, and the second metal film 83B are formed of at least one of titanium and titanium nitride. Specifically, the cover metal film 82, the first metal film 83A, and the second metal film 83B are formed by a laminated film of titanium and titanium nitride (TiN). Furthermore, the film thicknesses of the cover metal film 82, the first metal film 83A, and the second metal film 83B are, for example, 100 nm to 1000 nm. In this embodiment, the film thicknesses of the cover metal film 82, the first metal film 83A, and the second metal film 83B are, for example, 200 nm to 600 nm. The film thicknesses of the cover metal film 82, the first metal film 83A, and the second metal film 83B may be, for example, 300 nm or more, 400 nm or more, 450 nm or more, or 500 nm or more. Also, the film thicknesses of the cover metal film 82, the first metal film 83A, and the second metal film 83B may be 550 nm or less, 500 nm or less, 450 nm or less, 400 nm or less, or 350 nm or less. Also, the cover metal film 82, the first metal film 83A, and the second metal film 83B may be, for example, films in which an insulating layer and a metal layer are laminated. In this case, for example, a metal layer may be placed on the lower side, and an insulating layer serving as a metal protective layer of several tens of nanometers may be placed on the upper side. The insulating layer may also be formed of an insulating material such as silicon dioxide or silicon oxynitride. The metal layer may also be formed of a metal or metal compound containing at least one selected from the group consisting of titanium, titanium nitride, tantalum, and tungsten.

[0110] The through-electrode 41 is positioned, for example, in the peripheral region R2. The number of through-electrodes 41 is not limited to the example shown in Figure 3, but may be one or three or more.

[0111] The through-electrode 41 is a via that penetrates the semiconductor substrate 11. The through-electrode 41 is, for example, a TSV (Through Silicon Via). An insulating layer (not shown) is placed between the through-electrode 41 and the semiconductor substrate 11, and the through-electrode 41 and the semiconductor substrate 11 are separated by the insulating layer.

[0112] The through electrode 41 is formed of a metal. The through electrode 41 includes, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum. In this embodiment, the through electrode 41 mainly contains copper.

[0113] The structure of the imaging device 100 of this embodiment will be described in more detail with reference to Figures 3 to 5. Figure 4 is a plan view showing an example of the structure of the through electrode 41 and the metal film 83. Figure 5 is a plan view showing another example of the structure of the through electrode 41 and the metal film 83.

[0114] As shown in Figure 3, the imaging device 100 comprises a semiconductor substrate 11, a first through electrode 41A, a second through electrode 41B, an insulating layer 12, a first metal film 83A, and a second metal film 83B, as described above.

[0115] The insulating layer 12 covers the upper parts of the first through electrode 41A and the second through electrode 41B. Specifically, the upper ends of the first through electrode 41A and the second through electrode 41B are embedded in the insulating layer 12. The upper portion of the insulating layer 12 is positioned above the first through electrode 41A and the second through electrode 41B.

[0116] In this embodiment, the first metal film 83A is positioned above the insulating layer 12 so as to overlap with the first through electrode 41A in a plan view. The second metal film 83B is also positioned above the insulating layer 12 so as to overlap with the second through electrode 41B in a plan view. Furthermore, the first metal film 83A is separated from the second metal film 83B. In addition, the first metal film 83A is electrically insulated and isolated from the second metal film 83B.

[0117] Furthermore, in this embodiment, the insulating layer 12 is arranged to overlap all of the through electrodes 41 in a plan view. The multiple metal films 83 are arranged above the insulating layer 12, corresponding to each of the multiple through electrodes 41. The multiple metal films 83 are spaced apart from each other. The multiple metal films 83 are also electrically insulated and isolated from each other.

[0118] Furthermore, in this embodiment, the first metal film 83A is separated from the cover metal film 82. Also, the first metal film 83A is electrically insulated and isolated from the cover metal film 82. In addition, all of the multiple metal films 83 are separated from the cover metal film 82 and are electrically insulated and isolated from the cover metal film 82.

[0119] Furthermore, in this embodiment, the first metal film 83A and the second metal film 83B have light-shielding properties. The first metal film 83A and the second metal film 83B are formed from the same material. However, the first metal film 83A and the second metal film 83B may be formed from different materials.

[0120] Furthermore, the first through electrode 41A and the second through electrode 41B are positioned outside the pixel array 30, i.e., outside the pixel region R1, in a plan view. Alternatively, the first through electrode 41A and the second through electrode 41B may be positioned inside the pixel array 30 in a plan view.

[0121] As shown in Figure 4, in this embodiment, the first through electrode 41A is housed inside the first metal film 83A in a plan view. In other words, the first through electrode 41A is located inside the outer edge 832 of the first metal film 83A in a plan view. Also, as shown in Figure 5, the first through electrode 41A does not have to be housed inside the first metal film 83A in a plan view. That is, the first through electrode 41A may protrude outside the outer edge 832 of the first metal film 83A in a plan view. However, it is preferable that the first through electrode 41A is housed inside the first metal film 83A in a plan view, as shown in Figure 4.

[0122] Furthermore, the second through electrode 41B is housed inside the second metal film 83B in a plan view. In other words, the second through electrode 41B is located inside the outer edge 832 of the second metal film 83B in a plan view. However, the second through electrode 41B does not necessarily have to be housed inside the second metal film 83B in a plan view. That is, the second through electrode 41B may protrude outside the outer edge 832 of the second metal film 83B in a plan view. However, it is preferable that the second through electrode 41B is housed inside the second metal film 83B in a plan view. Note that since the second through electrode 41B has the same structure as the first through electrode 41A, its illustration in Figures 4 and 5 is omitted.

[0123] Furthermore, in this embodiment, at least one of the first metal film 83A and the second metal film 83B is electrically floating. In this embodiment, both the first metal film 83A and the second metal film 83B are electrically floating. Floating means being electrically independent and not electrically connected to other wiring, etc.

[0124] Furthermore, the potential of the first through electrode 41A is different from the potential of the second through electrode 41B. The first through electrode 41A and the second through electrode 41B are not electrically connected. In this specification, "different potentials" means that the potentials are different regardless of timing. Also, even if the potentials become the same or different depending on the timing, such as a through electrode 41 fixed at 1V and a through electrode 41 that fluctuates between 1V and 2V, the potentials are considered to be different. On the other hand, "same potential" means that the potentials are the same regardless of timing. For example, if two through electrodes 41 are fixed at 1V, and if two through electrodes 41 fluctuate between 1V and 2V at the same timing, they are considered to be at the same potential.

[0125] [Manufacturing Method] The manufacturing method of the imaging device 100 of this embodiment will be described with reference to Figures 6 to 13. Figure 6 is a flowchart illustrating the manufacturing method of the imaging device 100. Figures 7 to 13 are cross-sectional views illustrating the manufacturing method of the imaging device 100. In the manufacturing of the imaging device 100, conventionally known methods such as semiconductor integrated circuit formation processes can be used for forming impurity regions in the semiconductor substrate, as well as for forming insulating layers, wiring, vias, electrodes, etc.

[0126] As shown in Figure 6, in step S1, the first substrate 10 and the second substrate 20 are stacked. Specifically, as shown in Figure 7, the first substrate 10 is prepared with an insulating layer 12a which will become an insulating layer 12, wiring 15A, 15B and contact plugs 19 etc. provided on top of the semiconductor substrate 11. The second substrate 20 is prepared with an insulating layer 22 and wiring 25 etc. provided on top of the semiconductor substrate 21. Then, the first substrate 10 and the second substrate 20 are stacked and connected to each other. The connection between the first substrate 10 and the second substrate 20 can be performed using known techniques such as those disclosed in Japanese Patent Application Publication No. 2020-31074 (Patent Document) and Japanese Patent No. 6907944 (Patent Document).

[0127] Next, in step S2, a through-electrode 41 is formed that penetrates the semiconductor substrate 11. Specifically, as shown in Figure 8, a recess is formed from the top surface of the first substrate 10 to a depth midway through the second substrate 20 so as to penetrate the semiconductor substrate 11. More specifically, the recess is formed from the top surface of the first substrate 10 to the top surface of the wiring 25. Then, the through-electrode 41 is formed by filling the recess with metal. As a result, the wiring 25A and the wiring 151 are connected by the first through-electrode 41A. Also, the wiring 25B and the wiring 152 are connected by the second through-electrode 41B. Note that step S2 is an example of the "step of forming the first through-via" in this disclosure.

[0128] Next, in step S3, an insulating layer 12 is formed so as to cover the upper part of the through electrode 41. Specifically, as shown in Figure 9, an insulating layer 12b, which will become the insulating layer 12, is formed so as to cover the semiconductor substrate 11 and the upper part of the through electrode 41. Thus, the insulating layer 12 is formed by the insulating layer 12a and the insulating layer 12b. In this embodiment, the insulating layer 12b is formed using, for example, TEOS. Step S3 is an example of the "step of forming an insulating layer" in this disclosure.

[0129] Next, in step S4, pixel electrodes 71 and the like are formed on the first substrate 10. Specifically, as shown in Figure 10, vias 18 are formed in a predetermined region of the insulating layer 12a (Figure 9), and pixel electrodes 71 and connecting electrodes 75 are formed in a predetermined region of the insulating layer 12b (Figure 9). At this time, recesses may be formed in the predetermined regions of the insulating layers 12a and 12b, and then filled with metal or a metal compound to fill the recesses. Alternatively, pixel electrodes 71 and connecting electrodes 75 may be formed by doping impurities in a predetermined region of the insulating layer 12b. After the pixel electrodes 71 are formed, the thickness T12 of the insulating layer 12 on the through-electrode 41 is, for example, 250 nm or less, 200 nm or less, 150 nm or less, or 100 nm or less. The thinner the thickness T12 of the insulating layer 12 on the through-electrode 41, the easier it is for the through-electrode 41 to be exposed, thus increasing the effect of providing the metal film 83. Furthermore, as the thickness T12 becomes thinner, a short circuit is more likely to occur between the through electrode 41 and the metal film 83, thus increasing the effect of separating the first metal film 83A and the second metal film 83B.

[0130] Next, in step S5, the photoelectric conversion layer 73 and the like are laminated onto the first substrate 10. Specifically, as shown in Figure 11, the photoelectric conversion layer 73, the counter electrode 72, and the insulating layer 81 are laminated in this order so as to cover the insulating layer 12 and the pixel electrode 71 and the like.

[0131] Next, in step S6, a portion of the photoelectric conversion layer 73 and the like is removed. Specifically, as shown in Figure 12, the photoelectric conversion layer 73, the counter electrode 72, and the area of ​​the insulating layer 81 other than the pixel area R1, which is a predetermined area, are removed. At this time, in this embodiment, a portion of the photoelectric conversion layer 73 is etched using an oxygen-based gas. As a result, a portion of the photoelectric conversion layer 73 is removed, while the insulating layer 12 is not removed.

[0132] Next, in step S7, a metal layer 84 is formed above the insulating layer 12. Specifically, as shown in Figure 13, a metal layer 84 is formed above the insulating layer 12 and above the multiple pixels 31, including the optical black pixels. More specifically, a metal layer 84 is formed to cover the insulating layer 12, the connecting electrode 75, and the insulating layer 81, forming a cover metal film 82 and a metal film 83. At this time, the sides of the photoelectric conversion layer 73, the counter electrode 72, and the insulating layer 81 are also covered by the metal layer 84. Note that step S7 is an example of the "step of forming a metal layer" in this disclosure.

[0133] Next, in step S8, the first metal film 83A, the second metal film 83B which is a separation metal film, and the cover metal film 82 are formed. Specifically, as shown in Figure 3, the metal film 83 including the first metal film 83A and the second metal film 83B, and the cover metal film 82 are formed by removing a predetermined area of ​​the metal layer 84 (see Figure 13). At this time, in this embodiment, a mask is used to etch a predetermined area of ​​the metal layer 84 with a chlorine-based gas. As a result, the portion of the insulating layer 12 covered by the first metal film 83A, the second metal film 83B, and the cover metal film 82 is not removed. Therefore, the exposure of the first through electrode 41A and the second through electrode 41B can be suppressed. Note that step S8 is an example of the "step of forming the first metal film and the separation metal film" in this disclosure.

[0134] In this way, the imaging device 100 shown in Figure 3 is manufactured.

[0135] As described above, the imaging device 100 according to this embodiment includes a first through electrode 41A, a second through electrode 41B, an insulating layer 12 covering the tops of the first through electrode 41A and the second through electrode 41B, a first metal film 83A positioned above the insulating layer 12 so as to overlap with the first through electrode 41A, and a second metal film 83B positioned above the insulating layer 12 so as to overlap with the second through electrode 41B, wherein the first metal film 83A is separated from the second metal film 83B.

[0136] As a result, even if a short circuit occurs between the first through electrode 41A and the first metal film 83A, or between the second through electrode 41B and the second metal film 83B, it is possible to suppress an increase in parasitic capacitance between the first through electrode 41A and the second through electrode 41B. As a result, a decrease in the operating speed of the imaging device 100 can be suppressed, and thus a decrease in the image quality captured by the imaging device 100 can be suppressed. Furthermore, even if a short circuit occurs between the first through electrode 41A and the first metal film 83A, and also between the second through electrode 41B and the second metal film 83B, it is possible to suppress a short circuit between the first through electrode 41A and the second through electrode 41B.

[0137] Furthermore, in the imaging device 100, the first metal film 83A and the second metal film 83B have light-shielding properties. As a result, the first metal film 83A and the second metal film 83B can suppress light from entering transistors and diodes, etc., included in the sample-and-hold circuit and / or other circuits, around the first through-electrode 41A and the second through-electrode 41B. Therefore, it is possible to suppress the deterioration of image quality caused by charges generated when light enters the pn junctions of these components.

[0138] Furthermore, the first metal film 83A and the second metal film 83B can suppress light from reaching the first through electrode 41A and the second through electrode 41B. This prevents light reflected by the first through electrode 41A and the second through electrode 41B from leaking outside the imaging device 100, for example, and causing noise or other problems.

[0139] Furthermore, in the imaging device 100, the first through-electrode 41A and the second through-electrode 41B are positioned outside the pixel array 30 in a plan view. This suppresses the increase in parasitic capacitance compared to, for example, the case where the first through-electrode 41A and the second through-electrode 41B are formed inside the pixel array 30. Since the pixel array 30 is protected by the photoelectric conversion layer 73, etc., there is no need to separately provide a metal film or the like to prevent the first through-electrode 41A and the second through-electrode 41B from being exposed. In the peripheral region R2, there is no protective film such as the photoelectric conversion layer 73 and / or a semiconductor layer, so a metal film 83 is provided. Also, if the first through-electrode 41A and the second through-electrode 41B are formed inside the pixel array 30, extraneous parasitic capacitance tends to increase, and irregularities tend to form on the surface of the insulating layer 12, etc. inside the pixel array 30, so it is preferable to form the first through-electrode 41A and the second through-electrode 41B outside the pixel array 30.

[0140] Furthermore, the imaging device 100 includes a plurality of pixels 31, including optical black pixels, and a cover metal film 82 positioned above the optical black pixels. The upper surface 82a of the cover metal film 82 is positioned above the upper surface 831 of the first metal film 83A and the upper surface 831 of the second metal film 83B. This allows the first metal film 83A and the second metal film 83B to be positioned below the cover metal film 82, so that the first metal film 83A and the second metal film 83B can be positioned closer to light-shielding objects such as transistors and diodes included in a sample-and-hold circuit. This improves the light-shielding performance. Also, because the first metal film 83A and the second metal film 83B can be positioned below the cover metal film 82, the first metal film 83A and the second metal film 83B can shield light reaching the first through electrode 41A and the second through electrode 41B. This effectively suppresses light reflection from the upper surfaces of the first through electrode 41A and the second through electrode 41B. Note that light reflection from the upper surfaces of the first through electrode 41A and the second through electrode 41B can easily cause noise and other problems.

[0141] Furthermore, in the imaging device 100, the entire first through electrode 41A overlaps with the first metal film 83A in a plan view. In other words, the first through electrode 41A is contained within the first metal film 83A in a plan view. This prevents the first through electrode 41A from being exposed. Specifically, in step S8, when etching the metal layer 84, a portion of the insulating layer 12 is also removed by over-etching, but the insulating layer 12 beneath the first metal film 83A is not removed. Therefore, it is possible to prevent the insulating layer 12 on the first through electrode 41A from becoming thin or being completely removed, thus preventing the exposure of the first through electrode 41A by the first metal film 83A. Consequently, for example, the deposition of metals such as copper can be suppressed. Also, for example, it is possible to prevent copper from scattering and contaminating the wafer and / or manufacturing equipment due to dry etching. Furthermore, since the entire first through electrode 41A overlaps with the first metal film 83A in a plan view, the light-shielding performance of the first through electrode 41A can be improved.

[0142] Furthermore, in the imaging device 100, the entire second through electrode 41B overlaps with the second metal film 83B in a plan view. In other words, the second through electrode 41B is contained within the second metal film 83B in a plan view. This prevents the exposure of the second through electrode 41B from being suppressed. Specifically, in step S8, when etching the metal layer 84, a portion of the insulating layer 12 is also removed by over-etching, but the insulating layer 12 beneath the second metal film 83B is not removed. Therefore, it is possible to prevent the insulating layer 12 on the second through electrode 41B from becoming thin or being completely removed, thus preventing the exposure of the second through electrode 41B by the second metal film 83B. Consequently, for example, the deposition of metals such as copper can be suppressed. Also, for example, it is possible to prevent copper from scattering and contaminating the wafer and / or manufacturing equipment due to dry etching. Furthermore, since the entire second through electrode 41B overlaps with the second metal film 83B in a plan view, the light-shielding performance of the second through electrode 41B can be improved.

[0143] Furthermore, the imaging device 100 includes a photoelectric conversion layer 73 positioned above the insulating layer 12. In this configuration, where the photoelectric conversion layer 73 is positioned above the insulating layer 12, adverse effects such as copper exposure and / or light reflected by the first through-electrode 41A are more likely to occur compared to a configuration where the photoelectric conversion layer is formed on the semiconductor substrate 11. For this reason, applying the present disclosure to a configuration in which the photoelectric conversion layer 73 is positioned above the insulating layer 12 is particularly effective.

[0144] Furthermore, in a configuration where the photoelectric conversion layer 73 is positioned above the insulating layer 12, parasitic capacitance can occur between vias 18 connected to adjacent pixel electrodes 71, potentially causing crosstalk between pixels 31. One method to reduce parasitic capacitance is to shorten the vias 18 by making them lower, but this reduces the thickness of the insulating layer 12 on the through-electrode 41, making the through-electrode 41 more susceptible to exposure. For this reason, in a configuration where the photoelectric conversion layer 73 is positioned above the insulating layer 12, the metal film 83 is particularly effective in suppressing the exposure of the through-electrode 41.

[0145] Furthermore, in the imaging device 100, at least one of the first metal film 83A and the second metal film 83B is electrically floating. As a result, even if a short circuit occurs between the first through electrode 41A and the first metal film 83A, or between the second through electrode 41B and the second metal film 83B, the potential of the first through electrode 41A and the second through electrode 41B is maintained, thereby preventing the imaging device 100 from failing. If the first metal film 83A and the second metal film 83B are not floating, a potential difference will occur between the first through electrode 41A and the first metal film 83A, and between the second through electrode 41B and the second metal film 83B, making short circuits more likely. If a short circuit occurs between the first through electrode 41A and the first metal film 83A, and / or between the second through electrode 41B and the second metal film 83B, the imaging device 100 will fail.

[0146] Furthermore, in the imaging device 100, an insulating layer 12b (see Figure 9) is provided between the first through electrode 41A and the first metal film 83A, so the first through electrode 41A and the first metal film 83A are not connected and are electrically isolated, allowing the first metal film 83A to be electrically floating. Similarly, since an insulating layer 12b is provided between the second through electrode 41B and the second metal film 83B, the second metal film 83B can be electrically floating. However, if the insulating layer 12b is not provided, and the first through electrode 41A and the first metal film 83A are connected, and the second through electrode 41B and the second metal film 83B are connected, then the first metal film 83A has the same potential as the first through electrode 41A, and the second metal film 83B has the same potential as the second through electrode 41B. Here, the area of ​​contact between the first metal film 83A and the second metal film 83B is larger than the area of ​​contact between the first through electrode 41A and the second through electrode 41B. Also, the distance between the first metal film 83A and the second metal film 83B is shorter than the distance between the first through electrode 41A and the second through electrode 41B. As a result, the parasitic capacitance of the first metal film 83A and the second metal film 83B becomes larger than the parasitic capacitance of the first through electrode 41A and the second through electrode 41B. Therefore, by providing an insulating layer 12b, the area between the first through electrode 41A and the first metal film 83A, and the area between the second through electrode 41B and the second metal film 83B are electrically isolated.

[0147] Furthermore, in the imaging device 100, the potential of the first through electrode 41A is different from the potential of the second through electrode 41B. In this case, where the potential of the first through electrode 41A and the potential of the second through electrode 41B are different, it is preferable to separate the first metal film 83A from the second metal film 83B.

[0148] Furthermore, the imaging device 100 includes a plurality of through electrodes 41 and a plurality of metal films 83, each of the plurality of metal films 83 being arranged to overlap with a corresponding through electrode 41, and the plurality of metal films 83 being spaced apart from each other. This makes it possible to suppress an increase in parasitic capacitance for all through electrodes 41 arranged in the peripheral region R2, for example.

[0149] Furthermore, the imaging device 100 includes a first through-electrode 41A, an insulating layer 12 covering the upper part of the first through-electrode 41A, a first metal film 83A positioned above the insulating layer 12 so as to overlap with the first through-electrode 41A, and a cover metal film 82 positioned above the optical black pixels, wherein the first metal film 83A is separated from the cover metal film 82. This suppresses an increase in parasitic capacitance occurring in the first through-electrode 41A. Specifically, for example, if the first metal film 83A and the cover metal film 82 are not separated but connected, a short circuit occurs between the first through-electrode 41A and the first metal film 83A, and the parasitic capacitance that the cover metal film 82 has between itself and the surrounding wiring etc. is added as the parasitic capacitance of the first through-electrode 41A. As a result, the parasitic capacitance of the first through-electrode 41A increases. However, by separating the first metal film 83A and the cover metal film 82, even if a short circuit occurs between the first through electrode 41A and the first metal film 83A, the parasitic capacitance that the cover metal film 82 has with surrounding wiring etc. can be suppressed from being added as parasitic capacitance to the first through electrode 41A. Therefore, it is possible to suppress the increase in parasitic capacitance generated in the first through electrode 41A.

[0150] Furthermore, even if a short circuit occurs between the first through electrode 41A and the first metal film 83A when the cover metal film 82 has an electrical potential, the first metal film 83A and the cover metal film 82 are separated, so a short circuit between parts with different electrical potentials can be suppressed. This prevents the imaging device 100 from malfunctioning.

[0151] Furthermore, the manufacturing method of the imaging device 100 according to this embodiment includes the steps of: forming a first through-electrode 41A that penetrates the semiconductor substrate 11 (S2); forming an insulating layer 12 above the first through-electrode 41A so as to overlap with the first through-electrode 41A in a plan view (S3); forming a metal layer 84 above the insulating layer 12 (S7); and etching the metal layer 84 to form a first metal film 83A that overlaps with the first through-electrode 41A in a plan view, a second metal film 83B which is a separating metal film and a cover metal film 82 which are separated from the first metal film 83A (S8).

[0152] This makes it possible to suppress an increase in parasitic capacitance occurring in the first through-electrode 41A. Specifically, for example, if the first metal film 83A and the separating metal film, the second metal film 83B and the cover metal film 82, are not separated but connected, a short circuit occurs between the first through-electrode 41A and the first metal film 83A, and the parasitic capacitance that the separating metal film, the second metal film 83B and the cover metal film 82, have with the surrounding wiring, etc., is added as the parasitic capacitance of the first through-electrode 41A. As a result, the parasitic capacitance of the first through-electrode 41A increases. However, by separating the first metal film 83A and the separating metal film, the second metal film 83B and the cover metal film 82, even if a short circuit occurs between the first through-electrode 41A and the first metal film 83A, it is possible to suppress the addition of the parasitic capacitance that the separating metal film, the second metal film 83B and the cover metal film 82, have with the surrounding wiring, etc., as the parasitic capacitance of the first through-electrode 41A. Therefore, it is possible to suppress the increase in parasitic capacitance that occurs in the first through electrode 41A.

[0153] Furthermore, in the manufacturing method of the imaging device 100, the step of forming the metal layer 84 (S7) includes forming the metal layer 84 above the insulating layer 12 and above a plurality of pixels 31 including optical black pixels, and the step of forming the first metal film 83A, the second metal film 83B which is a separating metal film, and the cover metal film 82 (S8) includes forming the second metal film 83B which is a separating metal film and the cover metal film 82 such that, in a plan view, the second metal film 83B which is a separating metal film and the cover metal film 82 overlap with the optical black pixels.

[0154] This allows for the simultaneous formation of the first metal film 83A and the cover metal film 82, which is a separate metal film positioned above the optical black pixel. Therefore, the manufacturing method of the imaging device 100 can be simplified.

[0155] [First Modified Example] Next, a first modified example of the imaging device 100 according to the above embodiment will be described with reference to Figures 14 to 19. Figure 14 is a cross-sectional view showing the device structure of the imaging device 100 of the first modified example. Figure 15 is a plan view showing an example of the structure of the connection wiring 16 and metal film 83 of the imaging device 100 of the first modified example. Figure 16 is a plan view showing another example of the structure of the connection wiring 16 and metal film 83 of the imaging device 100 of the first modified example.

[0156] As shown in Figure 14, in the first modified example, unlike the above embodiment, the imaging device 100 is provided with connecting wiring 16. Specifically, connecting wiring 16 is provided as a wiring layer within the insulating layer 12. In the first modified example, the connecting wiring 16 is formed by a different wiring layer than wiring 15A and 15B. Also, the connecting wiring 16 is provided in the peripheral region R2.

[0157] In the first modified example, the connecting wiring 16 includes at least a first connecting wiring 16A and a second connecting wiring 16B. The first connecting wiring 16A is positioned between the first through electrode 41A and the first metal film 83A. The first connecting wiring 16A is connected to the first through electrode 41A. In a plan view, the first connecting wiring 16A overlaps with the first metal film 83A. The second connecting wiring 16B is positioned between the second through electrode 41B and the second metal film 83B. The second connecting wiring 16B is connected to the second through electrode 41B. In a plan view, the second connecting wiring 16B overlaps with the second metal film 83B.

[0158] The connecting wire 16 is made of metal. The connecting wire 16 is made using, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum. In the first modified example, the connecting wire 16 contains copper as its main component.

[0159] In this first modified example, the first through-electrode 41A is connected to the wiring 25A of the second substrate 20, but is not directly connected to the wirings 15A and 15B of the first substrate 10. Specifically, in a plan view, the first through-electrode 41A overlaps with the wiring 25A, but does not overlap with the wirings 15A and 15B. Similarly, the second through-electrode 41B is connected to the wiring 25B of the second substrate 20, but is not directly connected to the wirings 15A and 15B of the first substrate 10. Specifically, in a plan view, the second through-electrode 41B overlaps with the wiring 25B, but does not overlap with the wirings 15A and 15B.

[0160] Furthermore, vias 17 are provided within the insulating layer 12. Vias 17 include a first via 17A and a second via 17B. The first via 17A is connected to wiring 15A or 15B (here, wiring 15B) on the first substrate 10, but is not directly connected to wiring 25A on the second substrate 20. Similarly, the second via 17B is connected to wiring 15A or 15B (here, wiring 15B) on the first substrate 10, but is not directly connected to wiring 25B on the second substrate 20. Hereinafter, the wiring 15B connected to the first via 17A may be referred to as wiring 153. Also, the wiring 15B connected to the second via 17B may be referred to as wiring 154.

[0161] In the first modified example, the wiring 153 of the first substrate 10 and the wiring 25A of the second substrate 20 are connected via the first via 17A, the first connecting wiring 16A, and the first through electrode 41A. In addition, the wiring 154 of the first substrate 10 and the wiring 25B of the second substrate 20 are connected via the second via 17B, the second connecting wiring 16B, and the second through electrode 41B.

[0162] The via 17 is formed using, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum.

[0163] Furthermore, in the first modified example, as shown in Figure 15, the first connecting wire 16A is housed inside the first metal film 83A in a plan view. In other words, the first connecting wire 16A is located inside the outer edge 832 of the first metal film 83A in a plan view. Also, as shown in Figure 16, the first connecting wire 16A does not have to be housed inside the first metal film 83A in a plan view. That is, the first connecting wire 16A may protrude outside the outer edge 832 of the first metal film 83A in a plan view. However, it is preferable that the first connecting wire 16A is housed inside the first metal film 83A in a plan view, as shown in Figure 15.

[0164] Furthermore, the second connecting wire 16B is housed inside the second metal film 83B in a plan view. In other words, the second connecting wire 16B is located inside the outer edge 832 of the second metal film 83B in a plan view. However, the second connecting wire 16B does not necessarily have to be housed inside the second metal film 83B in a plan view. That is, the second connecting wire 16B may protrude outside the outer edge 832 of the second metal film 83B in a plan view. However, it is preferable that the second connecting wire 16B is housed inside the second metal film 83B in a plan view. Note that since the second connecting wire 16B has the same structure as the first connecting wire 16A, its illustration in Figures 15 and 16 is omitted.

[0165] The other structures of the first modified example are the same as those of the embodiment described above.

[0166] [Manufacturing Method of the First Modified Example] A manufacturing method of the imaging device 100 of the first modified example will be described with reference to Figures 6 and 17 to 19. Figures 17 to 19 are cross-sectional views illustrating the manufacturing method of the imaging device 100 of the first modified example.

[0167] As shown in Figure 6, in step S1, the first substrate 10 and the second substrate 20 are stacked. In the first modified example, as shown in Figure 17, the first substrate 10 is prepared with an insulating layer 12a which will become an insulating layer 12, wiring 15A, 15B and contact plugs 19 etc. provided on top of the semiconductor substrate 11. The second substrate 20 is prepared with an insulating layer 22 and wiring 25 etc. provided on top of the semiconductor substrate 21. Then, the first substrate 10 and the second substrate 20 are stacked and connected to each other.

[0168] Next, in step S2, a through electrode 41 is formed that penetrates the semiconductor substrate 11. In the first modified example, as shown in Figure 18, a recess is formed from the top surface of the first substrate 10 to a depth midway through the second substrate 20 so as to penetrate the semiconductor substrate 11. More specifically, a recess is formed from the top surface of the first substrate 10 to the top surface of the wiring 25. Also, a recess is formed from the top surface of the first substrate 10 to a depth midway through the insulating layer 12. Specifically, a recess is formed from the top surface of the first substrate 10 to the top surfaces of the wirings 153 and 154. Furthermore, a recess is formed in the region of the insulating layer 12 that will become the first connecting wiring 16A and the second connecting wiring 16B.

[0169] Then, by filling the recess with metal, the through electrode 41, via 17, and connecting wire 16 are formed. As a result, the first through electrode 41A, the first connecting wire 16A, and the first via 17A connect the wire 25A and the wire 153. In addition, the second through electrode 41B, the second connecting wire 16B, and the second via 17B connect the wire 25B and the wire 154.

[0170] Next, in step S3, an insulating layer 12 is formed so as to cover the upper part of the through electrode 41. In the first modified example, as shown in Figure 19, an insulating layer 12b, which will become the insulating layer 12, is formed so as to cover the upper part of the semiconductor substrate 11 and the connecting wiring 16. Thus, the insulating layer 12 is formed by the insulating layer 12a and the insulating layer 12b.

[0171] Next, vias 18, pixel electrodes 71, connecting electrodes 75, photoelectric conversion layer 73, counter electrodes 72, insulating layer 81, cover metal film 82, first metal film 83A, and second metal film 83B are formed in the same manner as described using Figures 10 to 13. In this way, the imaging device 100 shown in Figure 14 is manufactured.

[0172] As described above, the imaging device 100 of the first modified example includes a first connecting wire 16A positioned between the first through electrode 41A and the first metal film 83A and connected to the first through electrode 41A, and a second connecting wire 16B positioned between the second through electrode 41B and the second metal film 83B and connected to the second through electrode 41B, wherein the first connecting wire 16A overlaps with the first metal film 83A in a plan view, and the second connecting wire 16B overlaps with the second metal film 83B in a plan view.

[0173] As a result, even if a short circuit occurs between the first connecting wire 16A connected to the first through electrode 41A and the first metal film 83A, or between the second connecting wire 16B connected to the second through electrode 41B and the second metal film 83B, it is possible to suppress an increase in parasitic capacitance between the first connecting wire 16A connected to the first through electrode 41A and the second connecting wire 16B connected to the second through electrode 41B. As a result, a decrease in the operating speed of the imaging device 100 can be suppressed, and therefore a decrease in the image quality of the images captured by the imaging device 100 can be suppressed.

[0174] Furthermore, the first connecting wire 16A and the second connecting wire 16B have a larger area in plan view compared to the first through electrode 41A and the second through electrode 41B. Therefore, when light reaches the first connecting wire 16A and the second connecting wire 16B, a large amount of light is reflected by the first connecting wire 16A and the second connecting wire 16B, which can easily cause noise and other problems. For this reason, in a configuration in which the first connecting wire 16A and the second connecting wire 16B are provided, it is particularly effective to block the light with the first metal film 83A and the second metal film 83B.

[0175] Furthermore, in the imaging device 100 of the first modified example, the entirety of the first connection wiring 16A overlaps with the first metal film 83A in a plan view, and the entirety of the second connection wiring 16B overlaps with the second metal film 83B in a plan view. In other words, the first connection wiring 16A is contained inside the first metal film 83A in a plan view, and the second connection wiring 16B is contained inside the second metal film 83B in a plan view. This makes it possible to suppress the exposure of the first connection wiring 16A and the second connection wiring 16B. Specifically, when etching the metal layer 84 in step S8, it is possible to suppress the exposure of the first connection wiring 16A and the second connection wiring 16B. Therefore, for example, the deposition of metals such as copper can be suppressed. Also, for example, it is possible to suppress the scattering of copper due to dry etching and contamination of the wafer and / or manufacturing equipment. Furthermore, since the entirety of the first connecting wiring 16A overlaps with the first metal film 83A in a plan view, and the entirety of the second connecting wiring 16B overlaps with the second metal film 83B in a plan view, the light-shielding performance of the first connecting wiring 16A and the second connecting wiring 16B can be improved.

[0176] Other manufacturing methods and effects of the first modified example are the same as those of the embodiments described above.

[0177] [Second Modification] Next, a second modification of the imaging device 100 according to the above embodiment will be described with reference to Figures 20 to 25. Figure 20 is a cross-sectional view showing the device structure of the imaging device 100 of the second modification. In the second modification, a part of the embodiment shown in Figure 3 is modified for explanation, but for example, a part of the first modification shown in Figure 14 may also be modified.

[0178] As shown in Figure 20, in the second modified example, unlike the above embodiment, the photoelectric conversion unit 70 is not provided on the insulating layer 12. In the second modified example, the photoelectric conversion unit may be provided on the semiconductor substrate 11.

[0179] The other structures of the second modified example are the same as those of the embodiments described above.

[0180] [Manufacturing Method of the Second Modified Example] The manufacturing method of the second modified image device 100 will be described with reference to Figures 21 to 25. Figure 21 is a flowchart showing the manufacturing method of the second modified image device 100. Figures 22 to 25 are diagrams illustrating the manufacturing method of the second modified image device 100.

[0181] As shown in Figure 21, in step S1, the first substrate 10 and the second substrate 20 are stacked. In the second modified example, as shown in Figure 22, the first substrate 10 is prepared with an insulating layer 12a, wiring 15A, 15B, vias 18, etc., which will become an insulating layer 12, on top of the semiconductor substrate 11. The second substrate 20 is prepared with an insulating layer 22 and wiring 25, etc., on top of the semiconductor substrate 21. Then, the first substrate 10 and the second substrate 20 are stacked and connected to each other.

[0182] Next, in step S2, a through-electrode 41 is formed that penetrates the semiconductor substrate 11. In the second modified example, as shown in Figure 23, a recess is formed from the top surface of the first substrate 10 to a certain depth in the second substrate 20 so as to penetrate the semiconductor substrate 11. Then, a through-electrode 41 is formed by filling the recess with metal. As a result, the wiring 25A and the wiring 151 are connected by the first through-electrode 41A. Also, the wiring 25B and the wiring 152 are connected by the second through-electrode 41B.

[0183] Next, in step S3, an insulating layer 12 is formed so as to cover the upper part of the through electrode 41. In the second modified example, as shown in Figure 24, an insulating layer 12b, which will become the insulating layer 12, is formed so as to cover the upper part of the semiconductor substrate 11 and the through electrode 41. As a result, the insulating layer 12 is formed by the insulating layer 12a and the insulating layer 12b.

[0184] Next, in step S7, a metal layer 84 is formed above the insulating layer 12. In the second modified example, as shown in Figure 25, a metal layer 84 that will become a metal film 83 is formed so as to cover the top of the insulating layer 12.

[0185] Next, in step S8, a first metal film 83A and a second metal film 83B, which is a separating metal film, are formed. In the second modified example, as shown in Figure 20, a metal film 83 including the first metal film 83A and the second metal film 83B is formed by removing a predetermined area of ​​the metal layer 84 (see Figure 25). In this way, the imaging device 100 shown in Figure 20 is manufactured.

[0186] Other manufacturing methods and effects of the second modified example are the same as those of the embodiments described above.

[0187] [Third Modification] Next, a third modification of the imaging device 100 according to the above embodiment will be described with reference to Figure 26. Figure 26 is a cross-sectional view showing the device structure of the imaging device 100 of the third modification.

[0188] As shown in Figure 26, in the third modified example, unlike the embodiments described above, the plurality of through electrodes 41 further include one or more (two in Figure 26) through electrodes 41 in addition to the first through electrode 41A and the second through electrode 41B. Specifically, the plurality of through electrodes 41 include the first through electrode 41A, the second through electrode 41B, the third through electrode 41C, and the fourth through electrode 41D.

[0189] Furthermore, in the third modified example, the multiple metal films 83 include one or more (two in Figure 26) metal films 83 in addition to the first metal film 83A and the second metal film 83B. Specifically, the multiple metal films 83 include the first metal film 83A, the second metal film 83B, the third metal film 83C, and the fourth metal film 83D.

[0190] In the third modified example, in a plan view, each of the multiple metal films 83 is arranged to overlap with the corresponding through electrode 41 among the multiple through electrodes 41. Specifically, each of the through electrodes 41 is covered from above by the corresponding metal film 83 among the multiple metal films 83.

[0191] Furthermore, similar to the embodiments described above, the insulating layer 12 is arranged to overlap all of the multiple through electrodes 41 in a plan view.

[0192] The multiple metal films 83 are separated from each other. Furthermore, the multiple metal films 83 are electrically insulated from each other.

[0193] In the third modified example, the number of through electrodes 41 and the number of metal films 83 are the same, and each of the through electrodes 41 is covered from above by the corresponding metal film 83. With this configuration, for example, even if through electrodes 41 that were at the same potential become at different potentials due to a subsequent change in conditions, only one metal film 83 corresponds to one through electrode 41, so it is possible to suppress short circuits between through electrodes 41 that are at different potentials.

[0194] The other structures, manufacturing methods, and effects of the third modified example are the same as those of the embodiments described above.

[0195] [Fourth Modification] Next, a fourth modification of the imaging device 100 according to the above embodiment will be described with reference to Figure 27. Figure 27 is a plan view showing an example of the structure of the through electrode 41 and metal film 83 of the imaging device 100 of the fourth modification.

[0196] As shown in Figure 27, in the fourth modified example, unlike the embodiments described above, one metal film 83 (here, the first metal film 83A) covers the top of multiple (here, two) through electrodes 41. However, the multiple through electrodes 41 whose tops are covered by one metal film 83 are at the same potential as each other. In other words, multiple through electrodes 41 with the same potential may be covered from above by one metal film 83.

[0197] On the other hand, the through electrode 41 whose upper surface is covered by the second metal film 83B adjacent to the first metal film 83A has a different potential from the multiple through electrodes 41 whose upper surfaces are covered by the first metal film 83A.

[0198] The other structures, manufacturing methods, and effects of the fourth modified example are the same as those of the embodiments described above.

[0199] [Fifth Modification] Next, a fifth modification of the imaging device 100 according to the above embodiment will be described with reference to Figure 28. Figure 28 is a plan view showing an example of the structure of the connection wiring 16 and metal film 83 of the imaging device 100 of the fifth modification.

[0200] As shown in Figure 28, in the fifth modified example, unlike the first modified example, one metal film 83 (here, the first metal film 83A) covers the top of multiple (here, two) connecting wires 16. However, the multiple connecting wires 16 whose tops are covered by one metal film 83 are at the same potential as each other. In other words, multiple connecting wires 16 that are at the same potential may be covered from above by one metal film 83.

[0201] On the other hand, the connecting wire 16 whose upper surface is covered by the second metal film 83B adjacent to the first metal film 83A has a different potential than the multiple connecting wires 16 whose upper surface is covered by the first metal film 83A.

[0202] The other structures, manufacturing methods, and effects of the fifth modified example are the same as those of the embodiments described above.

[0203] (Other Embodiments) The imaging apparatus and its manufacturing method according to the present disclosure have been described above based on embodiments and modifications, but the present disclosure is not limited to these embodiments. Without departing from the spirit of the present disclosure, various modifications to the embodiments that a person skilled in the art can conceive of, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of the present disclosure.

[0204] For example, in the above embodiments, the imaging device 100 includes a first substrate 10 and a second substrate 20, but is not limited thereto. The imaging device according to this disclosure may include only the first substrate 10 as a substrate, and the pixels 31 may be connected to a device or element other than the imaging device according to this disclosure via a through electrode 41.

[0205] Furthermore, although the above embodiments describe an example in which the through-electrode 41 is provided outside the pixel array 30, this disclosure is not limited to this. For example, the through-electrode 41 may be provided on the pixel array 30. In other words, the through-electrode 41 may be provided in the pixel region R1.

[0206] Furthermore, although the above embodiment shows an example where the semiconductor substrate 11 is a silicon substrate, this disclosure is not limited to this, and the semiconductor substrate 11 may be a substrate other than a silicon substrate.

[0207] Furthermore, although the above embodiments show examples in which all through electrodes 41 overlap with the metal film 83 in a plan view, this disclosure is not limited to this. For example, due to layout constraints, there may be through electrodes 41 that do not overlap with the metal film 83.

[0208] Furthermore, the imaging device 100 may be used in camera systems such as smartphones, digital cameras, video cameras, and in-vehicle cameras. Such a camera system may include, for example, an imaging device, a lens optical system that focuses light onto the imaging device, a system controller consisting of a CPU (Central Processing Unit) and the like, and a camera signal processing circuit that processes the output signal from the imaging device.

[0209] Furthermore, each of the above embodiments may be modified, replaced, added, omitted, etc., within the scope of the claims or their equivalents.

[0210] The imaging device and its manufacturing method described herein are useful, for example, in image sensors, digital cameras, and the like. The imaging device and its manufacturing method described herein can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like.

[0211] 10 First substrate 20 Second substrate 11, 21 Semiconductor substrate 12, 12a, 12b, 22, 81 Insulating layer 15A, 5B, 25, 25A, 25B, 151, 152, 153, 154 Wiring 16 Connection wiring 16A First connection wiring 16B Second connection wiring 17, 18 Via 17A First via 17B Second via 19 Contact plug 30 Pixel array 31 Pixel 32 Detection circuit 41 Through electrode (through via) 41A First through electrode (first through via) 41B Second through electrode (second through via) 41C Third through electrode 41D Fourth through electrode 51 Peripheral circuit 52 Vertical scanning circuit 53 Column signal processing circuit 70 Photoelectric conversion unit 71 Pixel electrode 72 Opposing electrode 73 Photoelectric conversion layer 75 Connecting electrode 82 Cover metal film (separation metal film) 82a Top surface 82b Part 83 Metal film 83A First metal film 83B Second metal film (separation metal film) 83C Third metal film 83D Fourth metal film 84 Metal layer 100 Imaging device 314 Signal detection circuit 316 Feedback circuit 322 Signal detection transistor 324 Address transistor 326 Reset transistor 327 Protection transistor 331 Accumulation control line 332, 337 Power supply wiring 336 Reset signal line 345 Load circuit 347 Column signal processing circuit 349 Horizontal common signal line 350 Inverting amplifier 353 Feedback line 831 Top surface 832 Outer edge FD Charge accumulation node L1 Control signal line L2 Vertical signal line R1 Pixel area R2 Peripheral area S2 Step (Process to form the first through via) S3 Step (Process to form the insulating layer) S7 Step (Process to form the metal layer) S8 Step (Process to form the first metal film and the separating metal film)

Claims

1. An imaging device comprising: a semiconductor substrate; a first through-via penetrating the semiconductor substrate; a second through-via adjacent to the first through-via in a plan view of the semiconductor substrate and penetrating the semiconductor substrate; an insulating layer covering the top of the first and second through-vias and overlapping the first and second through-vias in a plan view; a first metal film positioned above the insulating layer and overlapping the first through-via in a plan view; and a second metal film positioned above the insulating layer and overlapping the second through-via in a plan view, wherein the first metal film is separated from the second metal film.

2. The imaging apparatus according to claim 1, wherein the first metal film and the second metal film have light-shielding properties.

3. The imaging apparatus according to claim 1, further comprising: a first connecting wire disposed between the first through via and the first metal film and connected to the first through via; and a second connecting wire disposed between the second through via and the second metal film and connected to the second through via, wherein the first connecting wire overlaps with the first metal film in the plan view, and the second connecting wire overlaps with the second metal film in the plan view.

4. The imaging apparatus according to claim 3, wherein the entirety of the first connecting wiring overlaps with the first metal film in the plan view, and the entirety of the second connecting wiring overlaps with the second metal film in the plan view.

5. The imaging apparatus according to claim 1, further comprising a pixel array including a plurality of pixels arranged in a matrix in a plan view, wherein the first through via and the second through via are located outside the pixel array in a plan view.

6. The imaging apparatus according to claim 2, further comprising: a plurality of pixels including optical black pixels; and a cover metal film disposed above the optical black pixels, wherein the upper surface of the cover metal film is located above the upper surface of the first metal film and the upper surface of the second metal film.

7. The imaging apparatus according to claim 1, wherein the entirety of the first through via overlaps with the first metal film in the plan view.

8. The imaging apparatus according to claim 7, wherein the entirety of the second through via overlaps with the second metal film in the plan view.

9. The imaging apparatus according to claim 1, further comprising a photoelectric conversion layer disposed above the insulating layer.

10. The imaging apparatus according to any one of claims 1 to 9, wherein at least one selected from the group consisting of the first metal film and the second metal film is in an electrically floating state.

11. The imaging apparatus according to any one of claims 1 to 9, wherein the potential of the first through via is different from the potential of the second through via.

12. The imaging device further comprises: a pixel region including a plurality of pixels; and a peripheral region provided around the pixel region, wherein the imaging device is provided with a plurality of through vias, the plurality of through vias are arranged in the peripheral region and include a first through via and a second through via; the imaging device is provided with a plurality of metal films, the plurality of metal films are arranged above the insulating layer and include a first metal film and a second metal film; in a plan view, each of the plurality of metal films overlaps with a corresponding through via among the plurality of through vias; the insulating layer overlaps all of the plurality of through vias in a plan view; and the plurality of metal films are spaced apart from each other, as described in any one of claims 1 to 9.

13. An imaging device comprising: a semiconductor substrate; a first through-via penetrating the semiconductor substrate; a plurality of pixels including optical black pixels; an insulating layer covering the upper part of the first through-via and overlapping the first through-via in a plan view relative to the semiconductor substrate; a first metal film disposed above the insulating layer and overlapping the first through-via in a plan view; and a cover metal film disposed above the optical black pixels, wherein the first metal film is separated from the cover metal film.

14. The imaging apparatus according to claim 13, wherein the first metal film has light-shielding properties.

15. The imaging apparatus according to claim 13, further comprising a first connecting wire positioned between the first through via and the first metal film and connected to the first through via, wherein the first connecting wire overlaps with the first metal film in a plan view.

16. The imaging apparatus according to claim 15, wherein the entirety of the first connecting wiring overlaps with the first metal film in the plan view.

17. The imaging apparatus according to claim 13, wherein the entirety of the first through via overlaps with the first metal film in the plan view.

18. The imaging apparatus according to any one of claims 13 to 17, wherein the first metal film is in an electrically floating state.

19. A method for manufacturing an imaging apparatus, comprising: forming a first through-via penetrating a semiconductor substrate; forming an insulating layer above the first through-via so as to overlap with the first through-via in a plan view of the semiconductor substrate; forming a metal layer above the insulating layer; and etching the metal layer to form a first metal film overlapping with the first through-via in a plan view, and a separating metal film separated from the first metal film.

20. The method for manufacturing an imaging apparatus according to claim 19, wherein forming the metal layer includes forming the metal layer above the insulating layer and above a plurality of pixels including optical black pixels, and forming the first metal film and the separating metal film includes forming the separating metal film such that the separating metal film and the optical black pixels overlap in a plan view.

Images