Semiconductor device and light detection device

Abstract

[Problem] To provide a semiconductor device capable of transmitting a signal to be transmitted, which is transmitted via a plurality of transmission circuits, to a far end at a desired timing. [Solution] This semiconductor device comprises: a plurality of transmission circuits that are connected in series and sequentially transmit signals to be transmitted; and an adjustment control circuit that individually adjusts the transmission capability of each of the plurality of transmission circuits.

Description

Semiconductor device and photodetection device

[0001] The present disclosure relates to a semiconductor device and a photodetection device.

[0002] With the increasing functionality of image sensors, a photodetection device having a stacked structure in which a substrate on which a sensor for performing photoelectric conversion is mounted and a substrate on which a circuit for processing a signal photoelectrically converted by the sensor are stacked has been proposed (see Patent Document 1).

[0003] Also, a solid-state imaging device including an ADC that counts the result of comparing a pixel signal with a ramp wave signal for each pixel column has been proposed (see Patent Document 2).

[0004] Japanese Patent Application Laid-Open No. 2023-59522, Japanese Patent Application Laid-Open No. 2011-182095

[0005] In Patent Document 1, a pulse signal indicating that incident light has been detected is generated in synchronization with two control signals input to each pixel. These two control signals are supplied to a plurality of pixels in the pixel column direction via two control lines. When the number of pixels increases and the size of the pixel array becomes large, the two control lines become long, and the parasitic capacitance and parasitic resistance of these control lines increase, and due to the variation thereof, there is a possibility that the timings of the two control signals deviate for each pixel. For example, at the far ends of the two control lines, the deviation of the timing of each control signal becomes large, and in extreme cases, each control signal may disappear.

[0006] In Patent Document 2, in order to transmit a clock signal input to a plurality of counters in a plurality of ADCs arranged in the row direction, a repeater in which a plurality of inverters are connected in series is provided. In Patent Document 2, by connecting a buffer or an inverter to the output node of the inverter of each stage of the repeater, the variation in the high width and low width of the clock signal of each stage is suppressed.

[0007] However, Patent Document 2 only considers the timing adjustment of a single clock signal and does not anticipate the timing adjustment of multiple control signals. When repeaters are provided for each of the multiple control lines that transmit multiple control signals, the parasitic capacitance and parasitic resistance of each control line will vary depending on the transistor size of each inverter constituting the repeater and the placement of each transistor. Although it is possible to extract the parasitic capacitance after the layout of each transistor and adjust the inverter size to some extent, even if the characteristics of the central part are matched, the characteristics of the transistors, the thickness of the interlayer film that affects parasitic capacitance, and the thickness of the wiring layer that affects parasitic resistance will vary between manufacturing lots and between substrates, making it extremely difficult to design in a way that accommodates all timings.

[0008] Furthermore, when multiple circuit boards are stacked and each circuit is mounted on multiple boards, the characteristics of each board vary uncorrelatedly, making adjustment even more difficult.

[0009] Therefore, this disclosure provides a semiconductor device and an optical detection device capable of transmitting a signal to be transmitted via multiple transmission circuits to a distant end at a desired timing.

[0010] To solve the above problems, the present disclosure provides a semiconductor device comprising: a plurality of transmission circuits connected in series to sequentially transmit a signal to be transmitted; and an adjustment control circuit for individually adjusting the transmission capability of each of the plurality of transmission circuits.

[0011] The plurality of transmission circuits are arranged in a first direction, and the plurality of transmission circuit groups are arranged in a second direction intersecting the first direction, each having the plurality of transmission circuits, and the adjustment control circuit may individually adjust the transmission capability of each of the plurality of transmission circuits in each of the plurality of transmission circuit groups.

[0012] The adjustment control circuit may individually adjust the current flowing through the plurality of transmission circuits.

[0013] The adjustment control circuit outputs a plurality of adjustment signals for individually adjusting the transmission capabilities of the plurality of transmission circuits, and the plurality of transmission circuits may include at least one inverter connected in series to sequentially transfer the signal to be transmitted, and a plurality of current adjustment circuits that adjust the current flowing through the at least one inverter based on the plurality of adjustment signals output from the adjustment control circuit.

[0014] The current adjustment circuit may include a normally-current circuit.

[0015] The current adjustment circuit has a first transistor that adjusts the current flowing through the corresponding inverter, and the adjustment control circuit may have a second transistor that can adjust the source-drain current and forms a current mirror circuit with the first transistor.

[0016] Each of the plurality of transmission circuits may have a stop switching circuit that switches whether the corresponding current adjustment circuit performs or stops the operation of adjusting the current flowing to the corresponding inverter.

[0017] Each of the multiple stop switching circuits corresponding to the multiple transmission circuits may stop the operation of the corresponding current adjustment circuit to adjust the current flowing to the corresponding inverter when the stop switching instruction signal is of a predetermined logic.

[0018] The plurality of transmission circuits are arranged in a first direction, and the plurality of transmission circuit groups are arranged in a second direction intersecting the first direction, each having the plurality of transmission circuits, and the stop switching instruction signal is provided for each of the plurality of transmission circuit groups, and each of the plurality of transmission circuit groups may switch whether or not to perform an operation to adjust the current flowing to the inverter based on the corresponding stop switching instruction signal.

[0019] A plurality of inverters are provided arranged in a first direction, and each of the plurality of transmission circuits is arranged in a second direction intersecting the first direction, and each has a plurality of inverter groups including the plurality of inverters, and each of the plurality of current adjustment circuits may adjust the current flowing to the plurality of inverters of the corresponding stage in the plurality of inverter groups.

[0020] Each of the plurality of transmission circuits may have a capacitance adjustment circuit that adjusts at least one of the wiring capacitance or parasitic capacitance of the output wiring of each of the plurality of transmission circuits based on the plurality of adjustment signals output from the adjustment control circuit.

[0021] The capacitance adjustment circuit includes a capacitor and a transistor connected in series between the output wiring and the reference voltage node, and the adjustment control circuit may output the adjustment signal that switches the transistor in each of the plurality of transmission circuits on or off.

[0022] The plurality of transmission circuits may be classified into two or more sets, the adjustment control circuit may generate an adjustment signal supplied to each of the two or more sets, and the transmission circuits belonging to each of the two or more sets may have their transmission capability adjusted based on the corresponding adjustment signal.

[0023] The device comprises a first substrate and a second substrate that are stacked on top of each other, and the plurality of transmission circuits may be arranged separately on the first substrate and the second substrate.

[0024] A first portion of at least one of the plurality of transmission circuits may be placed on the first substrate, and a second portion different from the first portion may be placed on the second substrate.

[0025] At least some of the transmission circuits may be arranged so as to overlap the first substrate and the second substrate in the stacking direction.

[0026] The system may also include: a plurality of monitor circuits having the same circuit configuration as the plurality of transmission circuits; a plurality of amplifiers connected to the plurality of output wires in the plurality of monitor circuits; and an output unit that outputs the voltage levels of the plurality of output wires amplified by the plurality of amplifiers.

[0027] The output unit may output the voltage level of an output wire that is selectively selected from among the plurality of output wires.

[0028] The present disclosure provides an optical detection device comprising: a plurality of pixels arranged in a first and second direction that intersect each other; a plurality of transmission circuits arranged between groups of pixels including two or more pixels arranged in the first direction and connected in series to sequentially transmit a signal to be transmitted; and an adjustment control circuit for individually adjusting the transmission capability of each of the plurality of transmission circuits, wherein the signal to be transmitted output from each of the plurality of transmission circuits is supplied to the corresponding pixel.

[0029] The system comprises a plurality of transmission circuit groups arranged in the second direction, each containing the plurality of transmission circuits, and the signals to be transmitted output from two adjacent transmission circuits in the second direction may be supplied to pixels shifted in the first direction.

[0030] A block diagram of a semiconductor device according to the first embodiment. A block diagram showing one configuration of a pixel having SPAD. A circuit diagram showing a specific configuration of the light receiving unit in Figure 2. A circuit diagram of a transmission circuit according to the first embodiment. A diagram showing the transmission capability of a group of transmission circuits consisting of multiple transmission circuits. A circuit diagram of a first current adjustment circuit according to a first modification of the first embodiment. A circuit diagram of a second current adjustment circuit according to a first modification of the first embodiment. A circuit diagram of a transmission circuit according to a second modification of the first embodiment. A block diagram of a semiconductor device according to the second embodiment. A circuit diagram of the first transmission circuit in Figure 8. A circuit diagram of the second transmission circuit in Figure 8. A circuit diagram of a first transmission circuit according to a modification of the second embodiment. A circuit diagram of a second transmission circuit according to a modification of the second embodiment. A block diagram of a semiconductor device according to the third embodiment. A circuit diagram of a transmission circuit according to a third embodiment. A circuit diagram of a transmission circuit according to a modification of the third embodiment. A block diagram of a semiconductor device according to the fourth embodiment. A circuit diagram of a transmission circuit according to the fourth embodiment. A circuit diagram of a transmission circuit according to a modification of the fourth embodiment. A circuit diagram of a transmission circuit according to a fifth embodiment. A diagram showing the arrangement of capacitance adjustment circuits connected to the output wiring of each transmission circuit. A diagram showing the first example of an adjustment signal. A diagram showing the second example of an adjustment signal. A diagram showing the third example of an adjustment signal. A layout diagram of the photodetector according to the seventh embodiment. A diagram showing the first to fourth transmission circuit groups arranged on both the first and second substrates. A layout diagram of the photodetector according to the eighth embodiment. A circuit diagram showing the internal configuration of the first amplifier. A circuit diagram showing the internal configuration of the second amplifier. A block diagram showing an example of the general configuration of the vehicle control system. An explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit.

[0031] Embodiments of the semiconductor device and photodetector will be described below with reference to the drawings. While the main components of the semiconductor device and photodetector will be described below, there may be components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0032] The semiconductor device described herein can be applied, for example, to a photodetector that generates an image based on a photoelectrically converted pixel signal, but it can also be applied to various devices with signal transmission functions other than photodetectors. This specification mainly describes typical embodiments of a semiconductor device applied to a photodetector.

[0033] (First Embodiment) Figure 1 is a block diagram of a semiconductor device 1 according to the first embodiment. Since the semiconductor device 1 in Figure 1 has a light detection function, the semiconductor device 1 in Figure 1 may be referred to as the light detection device 2 below. As shown in Figure 1, the light detection device 2 according to the first embodiment comprises a plurality of transmission circuits 3 and an adjustment control circuit 4.

[0034] Multiple transmission circuits 3 are connected in series, and each transmission circuit 3 sequentially transmits the signal to be transmitted. The adjustment control circuit 4 individually adjusts the transmission capacity of each of the multiple transmission circuits 3. More specifically, the adjustment control circuit 4 individually adjusts the current flowing through each of the multiple transmission circuits 3.

[0035] The higher the transmission capacity, the smaller at least one of the parasitic resistance or parasitic capacitance of the output line of each transmission circuit 3. The adjustment control circuit 4 adjusts the delay time through the parasitic resistance or parasitic capacitance of the output line by individually adjusting the current amount of each transmission circuit 3. Note that the parasitic resistance includes the wiring resistance of the output line, and the parasitic capacitance includes the wiring capacitance of the output line.

[0036] Here, "individually" does not necessarily mean for each individual transmission circuit 3. As will be described later, multiple transmission circuits 3 may be classified into two or more groups, and at least one of the current amount or load capacity of the transmission circuit may be adjusted individually for each group.

[0037] The signals to be transmitted by the multiple transmission circuits 3 are output from the transmission control circuit 5. The transmission control circuit 5 may be included in the photodetector 2 as shown in Figure 1, or it may be provided separately from the photodetector 2.

[0038] Multiple transmission circuits 3 do not necessarily transmit only one signal. While Figure 1 shows an example where multiple transmission circuits 3 transmit two signals, InA and InB, they may transmit three or more signals.

[0039] The light detection device 2 according to the first embodiment includes a pixel array section 6. The pixel array section 6 has a plurality of pixels px arranged in a first direction (e.g., column direction) Y and a second direction (e.g., row direction) X that intersect with each other.

[0040] The plurality of transmission circuits 3 according to the first embodiment are arranged between pixel rows consisting of two or more pixels px arranged in a first direction Y. A transmission circuit 3 may be arranged for each pixel px in the pixel row, or a transmission circuit 3 may be arranged for every two or more pixels px in the pixel row.

[0041] As described later, the output line of each transmission circuit 3 is connected to the corresponding pixel px and the next transmission circuit 3. Therefore, the signal to be transmitted output from each transmission circuit 3 is input to the corresponding pixel px and the next transmission circuit 3.

[0042] As shown in Figure 1, multiple transmission circuits 3 are arranged in a first direction Y (e.g., column direction) along corresponding pixel rows. In this specification, multiple transmission circuits 3 arranged in the first direction Y are referred to as a transmission circuit group 7 or repeater. Multiple transmission circuit groups 7 are arranged in a second direction X (e.g., row direction) of the pixel array section 6. Thus, each of the multiple transmission circuit groups 7 is provided corresponding to a plurality of pixel rows that extend in the first direction Y and are arranged in the second direction X. Each transmission circuit 3 in each transmission circuit group 7 is positioned between corresponding pixel rows. The adjustment control circuit 4 individually adjusts the transmission capability of each transmission circuit 3 in each of the multiple transmission circuit groups 7.

[0043] In the example shown in Figure 1, each transmission circuit 3 in two adjacent transmission circuit groups 7 in the second direction X (e.g., row direction) inputs the signal to be transmitted to pixels px at different row positions in the first direction Y (e.g., column direction). This allows the connection positions between the transmission circuits 3 and pixels px to be evenly distributed across the entire pixel array 6.

[0044] The configuration of each pixel px in the pixel array unit 6 is arbitrary. Hereinafter, an example in which each pixel px has a SPAD (Single Photon Avalanche Diode) will be described.

[0045] FIG. 2 is a block diagram showing a configuration of a pixel px having a SPAD. The pixel px in FIG. 2 includes a light receiving unit 11, a counter 12, and a selection switch 13.

[0046] The light receiving unit 11 outputs a pulse signal when the SPAD detects photons of incident light. In this specification, the detection of photons by the SPAD may be referred to as firing. The counter 12 counts the number of pulse signals output from the light receiving unit 11. The count value of the counter 12 is sent to the vertical signal line VSL when the selection switch 13 is on. The selection switch 13 turns on when the SEL signal is of a predetermined logic. The SEL signal is supplied, for example, from the transmission control circuit 5 in FIG. 1.

[0047] FIG. 3 is a circuit diagram showing a specific configuration of the light receiving unit 11 in FIG. 2. The light receiving unit 11 in FIG. 3 includes a SPAD 14, a clip transistor Q1, an inverter IV1, a recharge transistor Q2, and a detection circuit 15. The CLIP signal and the XRST signal output from the transmission control circuit 5 in FIG. 1 are input to the light receiving unit 11.

[0048] The anode of the SPAD 14 is connected to a predetermined reference voltage node lower than the power supply voltage VDD. Since the SPAD 14 needs to be fired, the anode may be set to a voltage level even lower than the GND level. The cathode of the SPAD 14 is connected to the drain of the clip transistor Q1.

[0049] In FIG. 3, both the clip transistor Q1 and the recharge transistor Q2 are shown as examples of PMOS transistors, but the conductivity types of these transistors are arbitrary.

[0050] A CLIP signal is input to the gate of clip transistor Q1 to suppress the signal level input to detection circuit 15, and an XRST signal is input to the gate of recharge transistor Q2. The source of recharge transistor Q2 is connected to the power supply voltage VDD node, and the drain of recharge transistor Q2 is connected to the source of clip transistor Q1. An XRST signal is input to the gate of recharge transistor Q2 and the input node of the inverter.

[0051] The detection circuit 15 includes a PMOS transistor Q3, an NMOS transistor Q4, and two inverters IV2 and IV3 connected in series.

[0052] The source of PMOS transistor Q3 is connected to the power supply voltage VDD node. The drains of PMOS transistor Q3 and NMOS transistor Q4 are connected to the input node of inverter IV2. The source of NMOS transistor Q4 is connected to the ground voltage node. When SPAD14 is ignited, a pulse signal PLS is output from the downstream inverter IV3.

[0053] The adjustment control circuit 4 in Figure 1 outputs a CLIP signal and an XRST signal that synchronize with each other. The CLIP signal and the XRST signal are pulse signals that remain low for a predetermined period of time. After the CLIP signal transitions from high to low, the XRST signal transitions from high to low while the CLIP signal is low. After the CLIP signal transitions from low to high, the XRST signal transitions from low to high.

[0054] By making the CLIP signal and XRST signal negative pulse signals that synchronize with each other, the cathode voltage of SPAD14 can be quickly restored to the initialization voltage when SPAD14 is fired, reducing the parasitic capacitance of the SPAD14 cathode and thus reducing power consumption. On the other hand, if the transition order of each signal cannot be ensured, malfunctions may occur, and if a margin is required in the transition timing of each signal to ensure this, the reduction in power consumption will be limited, and this becomes more pronounced as the size of the pixel array 6 increases.

[0055] Thus, when each pixel px of the pixel array 6 has the configuration shown in Figures 2 and 3, the multiple transmission circuits 3 in Figure 1 use the CLIP signal and the XRST signal as the transmission targets signals InA and InB. If the configuration of the pixel px changes, the type of transmission target signal transmitted by the multiple transmission circuits 3 also changes.

[0056] Figure 4 is a circuit diagram of the transmission circuit 3 according to the first embodiment. The transmission circuit 3 in Figure 4 includes two inverters IV4 and IV5 connected in series, a current adjustment circuit 16 that adjusts the current flowing to the downstream inverter IV5, and an inverter IV6 that inverts the output signal of the upstream inverter IV4 and inputs it to the corresponding pixel px. Inverters IV5 and IV6 are provided to match the signal logic with the signal to be transmitted that is input to the transmission circuit 3. The signal to be transmitted that is input to the transmission circuit 3 in Figure 4 is, for example, the CLIP signal or XRST signal in Figure 3.

[0057] Inverter IV4 has a PMOS transistor Q5 and an NMOS transistor Q6 that are cascode-connected between the power supply voltage node and the ground voltage node.

[0058] The current adjustment circuit 16 includes a first current adjustment circuit 16a and a second current adjustment circuit 16b. The inverter IV5 includes a PMOS transistor Q7 and an NMOS transistor Q8 that are cascode-connected between the output node of the first current adjustment circuit 16a and the output node of the second current adjustment circuit 16b.

[0059] Furthermore, inverter IV6 has a PMOS transistor Q9 and an NMOS transistor Q10 that are cascode-connected between the power supply voltage node and the ground voltage node.

[0060] The first current adjustment circuit 16a adjusts the current flowing from the first current adjustment circuit 16a to the inverter IV5 based on the adjustment signals Pgm0 and Pgm1 output from the adjustment control circuit 4. The second current adjustment circuit 16b adjusts the current flowing from the inverter IV5 to the second current adjustment circuit 16b based on the adjustment signals Ngm0 and Ngm1 output from the adjustment control circuit 4.

[0061] The current flowing through inverter IV5 refers to the current flowing from the source of PMOS transistor Q7 to the source of NMOS transistor Q8 in inverter IV5. The first current adjustment circuit 16a adjusts the transconductance Gm of PMOS transistor Q7 in inverter IV5 based on adjustment signals Pgm0 and Pgm1. The second current adjustment circuit 16b adjusts the transconductance Gm of NMOS transistor Q8 in inverter IV5 based on adjustment signals Ngm0 and Ngm1.

[0062] The first current adjustment circuit 16a includes three PMOS transistors Q11 to Q13 cascode-connected between the power supply voltage node and the source of the PMOS transistor 9 of the inverter IV5, two PMOS transistors Q14 and Q15 cascode-connected between the power supply voltage node and the source of the PMOS transistor Q7, and one PMOS transistor Q16 connected between the power supply voltage node and the source of the PMOS transistor Q7.

[0063] The gates of PMOS transistors Q11 to Q13 are connected to the ground voltage node. Therefore, PMOS transistors Q11 to Q13 are always ON, the first current adjustment circuit 16a operates normally-on, and the output node of the first current adjustment circuit 16a (the source of PMOS transistor Q7) is always at the power supply voltage level. The gates of PMOS transistors Q14 and Q15 are input to the adjustment signal Pgm0 supplied from the adjustment control circuit 4. The gate of PMOS transistor Q16 is input to the adjustment signal Pgm1 supplied from the adjustment control circuit 4.

[0064] The second current adjustment circuit 16b includes three NMOS transistors Q17 to Q19 cascode-connected between the source of the NMOS transistor Q8 of the inverter IV5 and the ground voltage node, two NMOS transistors Q20 and Q21 cascode-connected between the source of the NMOS transistor Q8 of the inverter IV5 and the ground voltage node, and one NMOS transistor Q22 connected between the source of the NMOS transistor Q8 of the inverter IV5 and the ground voltage node.

[0065] The gates of NMOS transistors Q17 to Q19 are connected to the power supply voltage node. Therefore, NMOS transistors Q17 to Q19 are always ON, the second current adjustment circuit 16b operates normally-on, and the output node of the second current adjustment circuit 16b (the source of NMOS transistor Q8) is always at ground voltage level. The gates of NMOS transistors Q20 and Q21 are input to the adjustment signal Ngm0 supplied from the adjustment control circuit 4. The gate of NMOS transistor Q22 is input to the adjustment signal Ngm1 supplied from the adjustment control circuit 4.

[0066] The adjustment signals Pgm0 and Pgm1 are individually controlled to high or low. When both adjustment signals Pgm0 and Pgm1 are low, more current can flow from the first current adjustment circuit 16a to the source of the PMOS transistor Q7 of the inverter IV5, thereby improving the transmission capability of the inverter IV5.

[0067] When adjustment signal Pgm0 is high and adjustment signal Pgm1 is low, PMOS transistors Q14 and Q15 are turned off and PMOS transistor Q16 is turned on. Therefore, the current that can flow from the first current adjustment circuit 16a to PMOS transistor Q7 of inverter IV5 is smaller than when both adjustment signals Pgm0 and Pgm1 are low, but more current can flow than when control signal Pgm0 is low and adjustment signal Pgm1 is high.

[0068] Similarly, adjustment signals Ngm0 and Ngm1 are individually controlled to high or low. When both adjustment signals Ngm0 and Ngm1 are high, more current can flow from the source of the NMOS transistor Q8 of inverter IV5 to the second current adjustment circuit 16b, thereby improving the transmission capability of inverter IV5.

[0069] When adjustment signal Ngm0 is low and adjustment signal Ngm1 is high, NMOS transistors Q20 and Q21 are turned off and PMOS transistor Q22 is turned on. As a result, the current that can flow from the source of NMOS transistor Q8 of inverter IV5 to the second current adjustment circuit 16b is smaller than when both adjustment signals Ngm0 and Ngm1 are high, but more current can flow than when control signal Ngm0 is high and adjustment signal Ngm1 is low.

[0070] In this way, the transmission capability of inverter IV5 can be adjusted in steps by individually controlling the adjustment signals Pgm0, Pgm1, Ngm0, and Ngm1 to high or low. More specifically, when adjustment signals Pgm0 and Pgm1 are both high and adjustment signals Ngm0 and Ngm1 are both low, the transmission capability of inverter IV5 is minimized. When adjustment signal Pgm0 is low, adjustment signal Pgm1 is high, adjustment signal Ngm0 is high, and adjustment signal Ngm1 is low, the transmission capability of inverter IV5 is small. When adjustment signal Pgm1 is low, adjustment signal Pgm0 is high, adjustment signal Ngm0 is low, and adjustment signal Ngm1 is high, inverter IV5 has a medium transmission capability. When adjustment signals Pgm0 and Pgm1 are both low and adjustment signals Ngm0 and Ngm1 are both high, inverter IV5 has a maximum transmission capability. The adjustment control circuit 4 supplies adjustment signals Pgm0, Pgm1, Ngm0, and Ngm1, which are digital signals that allow the code to be adjusted, to each transmission circuit 3.

[0071] The reason for setting the PMOS transistors Q11 to Q13 in the first current adjustment circuit 16a to a normally-on state is to ensure that the inverter IV5 can be correctly controlled even when the logic of the adjustment signals Pgm0 and Pgm1 is uncertain, such as when the power is turned on. However, if it is possible to control the output potential of the first current adjustment circuit 16a so that it is not uncertain, for example by specifying the power-on order, the PMOS transistors Q11 to Q13 may be switched on or off in the same way as the adjustment signals Pgm0 and Pgm1, rather than being fixed on. The same applies to the NMOS transistors Q17 to Q19 in the second current adjustment circuit 16b. This allows for more precise control of the transmission capability of the inverter IV5.

[0072] Figure 5 shows the transmission capability of a transmission circuit group 7 (repeater) consisting of multiple transmission circuits 3. The horizontal axis of Figure 5 represents the number of connection stages of the transmission circuit 3, and the vertical axis represents the normalized delay amount. Figure 5 shows waveforms w1 to w8 that indicate the transmission capability of the transmission circuit 3 adjusted with different adjustment signals. The solid waveform w1 is the waveform with the minimum transmission capability, which turns off the PMOS transistors Q14 to Q16 in the first current adjustment circuit 16a and the NMOS transistors Q20 to Q22 in the second current adjustment circuit 16b in Figure 4. The solid waveform w2 is the waveform with low transmission capability, which turns on the PMOS transistors Q14 and Q15 in the first current adjustment circuit 16a and the NMOS transistors Q20 and Q21 in the second current adjustment circuit 16b, and turns off the PMOS transistor Q16 in the first current adjustment circuit 16a and the NMOS transistor Q22 in the second current adjustment circuit 16b. The solid waveform w3 represents the waveform during transmission capability, where PMOS transistors Q14 and Q15 in the first current adjustment circuit 16a and NMOS transistors Q20 and Q21 in the second current adjustment circuit 16b are turned off, and PMOS transistor Q16 in the first current adjustment circuit 16a and NMOS transistor Q22 in the second current adjustment circuit 16b are turned on. The solid waveform w4 represents the waveform with maximum transmission capability, where PMOS transistors Q14 to Q16 in the first current adjustment circuit 16a and NMOS transistors Q20 to Q22 in the second current adjustment circuit 16b are turned on. The dashed waveform w5 represents the upper limit of the preset design range. The dashed waveform w6 represents the lower limit of the preset design range. The solid waveform w7 represents the waveform of the optimal solution. The solid waveform w8 represents the waveform after adjustment with the adjustment signal.

[0073] As shown in Figure 5, by individually adjusting the transmission capability of each transmission circuit 3 with adjustment signals, the transmission capability can be kept within the design range, and the transmission capability can be optimized. Furthermore, since the first current adjustment circuit 16a and the second current adjustment circuit 16b can be adjusted independently, the combination is not limited to w1 to w4.

[0074] The circuit configuration of the transmission circuit 3 according to the first embodiment is not limited to Figure 4. Figure 6A is a circuit diagram of the first current adjustment circuit 16a according to the first modified example of the first embodiment, and Figure 6B is a circuit diagram of the second current adjustment circuit 16b according to the first modified example of the first embodiment.

[0075] The first current adjustment circuit 16a in Figure 6A includes three PMOS transistors Q11 to Q13 cascode-connected between the power supply voltage node and the source of the PMOS transistor 9 of the inverter IV5, a PMOS transistor Q14 connected between the power supply voltage node and the drain of PMOS transistor Q11, and a PMOS transistor Q15 connected between the power supply voltage node and the drain of PMOS transistor Q12. The gate of PMOS transistor Q14 is input to the adjustment signal Pgm0 supplied from the adjustment control circuit 4. The gate of PMOS transistor Q15 is input to the adjustment signal Pgm1 supplied from the adjustment control circuit 4.

[0076] The second current adjustment circuit 16b in Figure 6B includes three NMOS transistors Q17 to Q19 cascode-connected between the source of NMOS transistor Q8 of inverter IV5 and the ground voltage node, an NMOS transistor Q20 connected between the source of NMOS transistor Q18 and the ground voltage node, and an NMOS transistor Q21 connected between the source of NMOS transistor Q17 and the ground voltage node. The adjustment signal Ngm0 supplied from the adjustment control circuit 4 is input to the gate of NMOS transistor Q20. The adjustment signal Ngm1 supplied from the adjustment control circuit 4 is input to the gate of NMOS transistor Q21.

[0077] The first current adjustment circuit 16a in Figure 6A and the second current adjustment circuit 16b in Figure 6B have a narrower adjustment range for transmission capability using adjustment signals compared to the first and second current adjustment circuits 16a and 16b in Figure 4, making them effective when it is desired to narrow the adjustment range for transmission capability. Furthermore, the first current adjustment circuit 16a in Figure 6A and the second current adjustment circuit 16b in Figure 6B can reduce the number of transistors by one each compared to the first and second current adjustment circuits 16a and 16b in Figure 4, thereby reducing the circuit size of the transmission circuit 3.

[0078] Figure 7 is a circuit diagram of a transmission circuit 3 according to a second modification of the first embodiment. As shown in Figure 7, the transmission circuit 3 according to the second modification has a first current adjustment circuit 16a and a second current adjustment circuit 16b with different circuit configurations than those in Figure 4. Furthermore, the adjustment control circuit 4 according to the second modification has a different circuit configuration than those in Figure 4.

[0079] The first current adjustment circuit 16a in Figure 7 has a PMOS transistor (first transistor) Q23. The adjustment control circuit 4 has the PMOS transistor Q23 of the first current adjustment circuit 16a and a PMOS transistor (second transistor) Q24 that constitutes the current mirror circuit 17a. The source of the PMOS transistor Q23 is connected to the power supply voltage node, and the drain of the PMOS transistor Q23 is connected to the source of the PMOS transistor Q7 of the inverter IV5. The gate of the PMOS transistor Q23 is connected to the gate and drain of the PMOS transistor Q24 and the first current source 18a. The source of the PMOS transistor Q24 is connected to the power supply voltage node.

[0080] The second current adjustment circuit 16b in Figure 7 has an NMOS transistor Q25. The adjustment control circuit 4 has the NMOS transistor Q25 of the second current adjustment circuit 16b and an NMOS transistor Q26 that constitutes the current mirror circuit 17b. The source of the NMOS transistor Q25 is connected to the ground voltage node, and the drain of the NMOS transistor Q25 is connected to the source of the NMOS transistor Q8 of the inverter IV5. The gate of the NMOS transistor Q25 is connected to the gate and drain of the NMOS transistor Q26 and to the second current source 18b. The source of the NMOS transistor Q26 is connected to the ground voltage node.

[0081] A current corresponding to the current of the first current source 18a flows between the source and drain of the PMOS transistor Q24 in the adjustment control circuit 4. Since the PMOS transistors Q23 and Q24 constitute a current mirror circuit 17a, a current proportional to the source-drain current of the PMOS transistor Q24 flows between the source and drain of the PMOS transistor Q23 in the first current adjustment circuit 16a. Therefore, by variably controlling the current of the first current source 18a, the source-drain current of the PMOS transistor Q23 in the first current adjustment circuit 16a and the current flowing to the source of the PMOS transistor Q7 of the inverter IV5 can be adjusted.

[0082] Similarly, a current corresponding to the current of the second current source 18b flows between the drain and source of the NMOS transistor Q26 in the adjustment control circuit 4. Since the NMOS transistors Q25 and Q26 constitute the current mirror circuit 17b, a current proportional to the drain-source current of the NMOS transistor Q26 flows between the drain and source of the NMOS transistor Q25 in the second current adjustment circuit 16b. Therefore, by variably controlling the current of the second current source 18b, the drain-source current of the NMOS transistor Q25 in the second current adjustment circuit 16b and the current flowing to the source of the NMOS transistor Q8 of the inverter IV5 can be adjusted.

[0083] Thus, while the transmission circuit 3 in Figure 4 can adjust the transmission capability of inverter IV5 in steps by individually switching the adjustment signals Pgm0, Pgm1, Ngm0, and Ngm1 to high or low, the transmission circuit 3 in Figure 7 can finely adjust the transmission capability of inverter IV5 by precisely controlling the currents of the first current source 18a and the second current source 18b in the adjustment control circuit 4. Furthermore, since the first current adjustment circuit 16a and the second current adjustment circuit 16b in Figure 7 have a simpler circuit configuration than the first current adjustment circuit 16a and the second current adjustment circuit 16b in Figure 4, the size of each transmission circuit 3 can be reduced, and the pixel array unit 6 can be miniaturized.

[0084] Thus, in the first embodiment, the transmission capability of each of the multiple transmission circuits 3 that sequentially transmit the signal to be transmitted can be adjusted for each transmission circuit 3. This allows all transmission circuits 3 to transmit signals at the desired timing, while taking into account the influence of variations in at least one of the parasitic resistance or parasitic capacitance of the output lines of each stage of transmission circuit 3.

[0085] (Second Embodiment) Figure 8 is a block diagram of the semiconductor device 1 according to the second embodiment. The semiconductor device 1 according to the second embodiment shown in Figure 8 is shown as an example applied to a photodetector 2, similar to the first embodiment.

[0086] The light detection device 2 in Figure 8 includes a plurality of transmission circuits 3 arranged in a first direction Y (for example, the column direction). Each transmission circuit 3 is arranged for, for example, every two pixels px in the first direction Y, similar to the first embodiment. Also, similar to the first embodiment, a plurality of transmission circuit groups 7, each having a plurality of transmission circuits 3, are arranged in a second direction X (for example, the row direction). In two adjacent transmission circuit groups 7 in the second direction X, the row positions to which they are connected differ among the plurality of pixels px arranged in the first direction Y (column direction).

[0087] The multiple transmission circuits 3 each have a first transmission circuit 3a and a second transmission circuit 3b, which have different circuit configurations. The first transmission circuit 3a and the second transmission circuit 3b are connected alternately. For example, in the transmission circuit group 7 at the far left of Figure 8, the first stage first transmission circuit 3a is connected to the pixel px in the third row, and the second stage second transmission circuit 3b is connected to the pixel px in the seventh row. Also, in the transmission circuit group 7 in the second column from the left, the first stage first transmission circuit 3a is connected to the pixel px in the fifth row, and the second stage second transmission circuit 3b is connected to the pixel px in the ninth row.

[0088] Figure 9A is a circuit diagram of the first transmission circuit 3a in Figure 8, and Figure 9B is a circuit diagram of the second transmission circuit 3b in Figure 8. The first transmission circuit 3a in Figure 9A has a configuration in which inverter IV4 is omitted from the transmission circuit 3 in Figure 4, and the output node of inverter IV5 is connected to the input node of inverter IV6. The second transmission circuit 3b in Figure 9B has a configuration in which inverter IV4 is omitted from the transmission circuit 3 in Figure 4, and inverter IV7 is newly connected to the output node of inverter IV6. Inverter IV7 has a PMOS transistor Q27 and an NMOS transistor Q28 that are cascode-connected between the power supply voltage node and the ground voltage node.

[0089] Both the first transmission circuit 3a in Figure 9A and the second transmission circuit 3b in Figure 9B require one less inverter than the transmission circuit 3 in Figure 4, thus reducing the circuit size. The first transmission circuit 3a in Figure 9A inverts the signal to be transmitted input to the transmission circuit group 7 and outputs it. Therefore, one inverter IV6 is provided within the first transmission circuit 3a, and the pixel px receives a signal to be transmitted with the same signal logic as the signal to be transmitted input to the transmission circuit group 7. The second transmission circuit 3b also inverts the input signal to be transmitted using inverter IV5 and outputs it. By arranging the first transmission circuit 3a and the second transmission circuit 3b alternately, it is possible to output a signal to be transmitted with the same signal logic as the signal to be transmitted input to the transmission circuit group 7. In the second transmission circuit 3b, the output signal of inverter IV5 is supplied to the pixel px via two inverters IV6 and IV7. As a result, the pixel px receives a signal to be transmitted with the same signal logic as the signal to be transmitted input to the transmission circuit group 7.

[0090] The inverter IV6 in the second transmission circuit 3b only needs to be able to drive inverter IV7, so it can be smaller than the inverter IV6 in the first transmission circuit 3a. However, it is desirable to match the load capacity and load resistance of the inverter IV6 in the first transmission circuit 3a and the second transmission circuit 3b, so it is preferable to match the size of the inverter IV6 in the first and second transmission circuits 3a and 3b.

[0091] Figures 10A and 10B are circuit diagrams of a first transmission circuit 3a and a second transmission circuit 3b according to a modified example of the second embodiment. The first transmission circuit 3a in Figure 10A has a configuration in which inverter IV4 is omitted from the transmission circuit 3 in Figure 7, and the output node of inverter IV5 is connected to the input node of inverter IV6. The second transmission circuit 3b in Figure 10B has a configuration in which inverter IV4 is omitted from the transmission circuit 3 in Figure 7, and the output node of inverter IV5 is connected to the input node of inverter IV6.

[0092] The first and second transmission circuits 3a and 3b in Figures 10A and 10B can reduce the number of inverters IV4 by one compared to the first and second transmission circuits 3a and 3b in Figure 7, thereby reducing the circuit size.

[0093] Thus, in the second embodiment, multiple transmission circuits 3 are configured by alternately connecting the first transmission circuit 3a and the second transmission circuit 3b, and the number of inverters in the first transmission circuit 3a and the second transmission circuit 3b is reduced compared to the transmission circuit 3 in Figure 4. As a result, the circuit size of each transmission circuit 3 can be reduced, and power consumption can also be reduced. In the second embodiment, compared to the first embodiment, the first transmission circuit 3a and the second transmission circuit 3b have different circuit configurations, but since the transmission capability in each of the first transmission circuit 3a and the second transmission circuit 3b can be adjusted, the duty cycle of the signal to be transmitted can be correctly maintained even at the far end of each transmission circuit group 7.

[0094] (Third Embodiment) Figure 11 is a block diagram of the semiconductor device 1 according to the third embodiment. The semiconductor device 1 according to the third embodiment shown in Figure 11 is an example of being applied to a photodetector 2, similar to the first and second embodiments.

[0095] In addition to the configuration shown in Figure 11, the optical detection device 2 in Figure 11 receives stop switching instruction signals Dis and xDis output from the transmission control circuit 5, which are input to each transmission circuit 3. The stop switching instruction signals Dis and xDis are signals that instruct each transmission circuit 3 whether or not to adjust the transmission capability of the inverter IV 5. In the third embodiment, it is possible to select whether or not to adjust the transmission capability for each transmission circuit 3 included in the transmission circuit group 7.

[0096] In the third embodiment, similar to the first embodiment, a plurality of transmission circuits 3 are arranged in the first direction Y (for example, the column direction). The circuit configuration of the transmission circuit 3 according to the third embodiment differs in part from the circuit configuration of the transmission circuit 3 according to the first embodiment.

[0097] Figure 12 is a circuit diagram of the transmission circuit 3 according to the third embodiment. The transmission circuit 3 in Figure 12 differs from the transmission circuit 3 in Figure 4 in some of the internal configurations of the first current adjustment circuit 16a and the second current adjustment circuit 16b.

[0098] The first current adjustment circuit 16a in Figure 12 has a PMOS transistor Q31 in addition to the configuration of the first current adjustment circuit 16a in Figure 4. The source of PMOS transistor Q31 is connected to the power supply voltage node, and the drain of PMOS transistor Q31 is connected to the source of PMOS transistor Q14 and the source of PMOS transistor Q16. The gate of PMOS transistor Q31 is input to the stop switching instruction signal Dis output from the transmission control circuit 5.

[0099] The second current adjustment circuit 16b in Figure 12 has an NMOS transistor Q32 in addition to the configuration of the second current adjustment circuit 16b in Figure 4. The drain of the NMOS transistor Q32 is connected to the source of the NMOS transistors Q21 and Q22. The source of the NMOS transistor Q32 is connected to the ground voltage node. A stop switching instruction signal xDis is input to the gate of the NMOS transistor Q32. The stop switching instruction signal xDis is the inverse signal of the stop switching instruction signal Dis. The PMOS transistor Q31 and the NMOS transistor Q32 function as stop switching circuits that switch whether the corresponding first and second current adjustment circuits 16a and 16b perform the operation of adjusting the current flowing through the corresponding inverter IV5. The PMOS transistor Q31 and the NMOS transistor Q32 stop the operation of the corresponding first and second current adjustment circuits 16a and 16b adjusting the current flowing through the corresponding inverter IV5 when the stop switching instruction signals Dis and xDis are in a predetermined logic state.

[0100] When the stop switching instruction signal Dis is low and the stop switching instruction signal xDis is high, the first current adjustment circuit 16a and the second current adjustment circuit 16b in Figure 12 adjust the transmission capability of inverter IV5 in the same way as the first current adjustment circuit 16a and the second current adjustment circuit 16b in Figure 4. When the stop switching instruction signal Dis is high and the stop switching instruction signal xDis is low, the PMOS transistors Q14 to Q16 in the first current adjustment circuit 16a in Figure 12 are turned off, and the NMOS transistors Q20 to Q22 in the second current adjustment circuit 16b are also turned off. Therefore, the transmission capability of inverter IV5 becomes fixed.

[0101] Since the stop switching instruction signal is input to each of the multiple transmission circuits 3, the stop switching instruction signal can be used to switch whether or not to adjust the transmission capacity of all transmission circuits 3.

[0102] In Figure 12, when PMOS transistor Q31 is turned off, both adjustment signals Pgm0 and Pgm1 are disabled. However, it is also possible to disable only one of the adjustment signals Pgm0 or Pgm1. For example, to disable only adjustment signal Pgm0, PMOS transistor Q31 should be connected between the source of PMOS transistor Q14 and the power supply voltage node, and the source of PMOS transistor Q16 should be connected to the power supply voltage node. Alternatively, to disable only adjustment signal Pgm1, PMOS transistor Q31 should be connected between the source of PMOS transistor Q16 and the power supply voltage node, and the source of PMOS transistor Q14 should be connected to the power supply voltage node.

[0103] Similarly, to disable only the adjustment signal Pgm0, connect the NMOS transistor Q32 between the source of NMOS transistor Q20 and the power supply voltage node, and connect the source of NMOS transistor Q22 to the power supply voltage node. Also, to disable only the adjustment signal Pgm1, connect the NMOS transistor Q32 between the source of NMOS transistor Q22 and the power supply voltage node, and connect the source of NMOS transistor Q20 to the power supply voltage node.

[0104] As shown in Figure 11, the transmission control circuit 5 provides stop switching signals Dis and xDis for each of the multiple transmission circuit groups 7 arranged in the second direction X. Therefore, for each transmission circuit group 7, it is possible to switch whether or not to adjust the transmission capacity using the corresponding stop switching instruction signals Dis and xDis.

[0105] Figure 13 is a circuit diagram of a transmission circuit 3 according to a modified example of the third embodiment. The first current adjustment circuit 16a in the transmission circuit 3 of Figure 13 has a PMOS transistor Q31 in addition to the configuration of the first current adjustment circuit 16a of Figure 7. The source of the PMOS transistor Q31 is connected to the power supply voltage node, and the drain of the PMOS transistor Q31 is connected to the source of the PMOS transistor Q7 of the inverter IV5. A stop switching instruction signal Dis is input to the gate of the PMOS transistor Q31.

[0106] The second current adjustment circuit 16b in the transmission circuit 3 of Figure 13 has an NMOS transistor Q32 in addition to the configuration of the second current adjustment circuit 16b in Figure 7. The drain of the NMOS transistor Q32 is connected to the source of the NMOS transistor Q8 of the inverter IV5, the source of the NMOS transistor Q32 is connected to the ground voltage node, and the gate of the NMOS transistor Q32 is input to the stop switching instruction signal xDis.

[0107] When the stop switching instruction signal Dis is high and the stop switching instruction signal xDis is low, the first current adjustment circuit 16a and the second current adjustment circuit 16b in Figure 13 adjust the transmission capability of inverter IV5 in the same way as the first current adjustment circuit 16a and the second current adjustment circuit 16b in Figure 7. When the stop switching instruction signal xDis is low and the stop switching instruction signal Dis is high, both PMOS transistor Q31 and NMOS transistor Q32 are turned on. When PMOS transistor Q31 is turned on, the transconductance Gm of PMOS transistor Q31 becomes greater than the transconductance Gm of PMOS transistor Q23. Similarly, when NMOS transistor Q32 is turned on, the transconductance Gm of NMOS transistor Q32 becomes greater than the transconductance Gm of NMOS transistor Q32, and the transmission capability of inverter IV5 becomes almost fixed. Therefore, it becomes impossible to adjust the transmission capability of inverter IV5 using the adjustment signals Pgm and Ngm.

[0108] Thus, in the third embodiment, for each transmission circuit group 7, it is possible to switch whether or not to adjust the transmission capability of each transmission circuit 3 using a stop switching instruction signal. According to the third embodiment, for example, the transmission capability of the peripheral part of the pixel array 6 may not be adjusted in accordance with the drop in power supply voltage.

[0109] Furthermore, it is not necessary to supply a stop switching instruction signal to all transmission circuit groups 7. A stop switching instruction signal may be supplied to transmission circuit groups 7 in locations where a decrease in transmission capability will not affect image quality. In transmission circuit groups 7 that adjust transmission capability, it is desirable to fix the gate of the transistor to which the stop switching instruction signal is input to either on or off so that the adjustment of transmission capability is not hindered by this transistor. For example, in the transmission circuit 3 of Figure 12, the gate of PMOS transistor Q31 may be fixed low and the gate of NMOS transistor Q32 may be fixed high. Alternatively, in the transmission circuit 3 of Figure 13, the gate of PMOS transistor Q31 may be fixed high and the gate of NMOS transistor Q32 may be fixed low.

[0110] (Fourth Embodiment) Figure 14 is a block diagram of the semiconductor device 1 according to the fourth embodiment. The semiconductor device 1 according to the fourth embodiment shown in Figure 14 is shown as an example applied to a photodetector 2, similar to the first to third embodiments.

[0111] The optical detection device 2 in Figure 14 is characterized in that a group of transmission circuits 7, which includes multiple transmission circuits 3, transmits multiple signals to be transmitted.

[0112] The semiconductor device 1 according to the fourth embodiment has multiple transmission circuits 3, each having multiple inverter groups 19. The multiple inverter groups 19 are arranged in a second direction X that intersects the first direction Y, which is the arrangement direction of the multiple inverters, and each transmits a different signal to be transmitted.

[0113] Figure 15 is a circuit diagram of the transmission circuit 3 according to the fourth embodiment. The transmission circuit 3 in Figure 15 shows an example of transmitting two transmission target signals InA and InB, but there is no limit to the number of transmission target signals to be transmitted.

[0114] While the transmission circuit 3 in Figure 4 has one inverter group and one current adjustment circuit 16, the transmission circuit 3 in Figure 15 has two inverter groups 19 and one current adjustment circuit 16. The two inverter groups 19 transmit different transmission target signals InA or InB. The transmission target signals InA and InB transmitted by the two inverter groups 19 are input to the next stage transmission circuit 3 and are also input to different pixels px. The current adjustment circuit 16 adjusts the current flowing through multiple inverters in the corresponding stages of the multiple inverter groups.

[0115] Each of the multiple current adjustment circuits 16 in the transmission circuit 3 of Figure 15 adjusts the current flowing through the corresponding multiple inverters in the group of multiple inverters 19. As shown in Figure 15, each current adjustment circuit 16 is connected to the corresponding multiple inverters. Each current adjustment circuit 16 adjusts the current so that the current flowing through the corresponding multiple inverters is the same.

[0116] Figure 16 is a circuit diagram of a transmission circuit 3 according to a modified example of the fourth embodiment. While the transmission circuit 3 in Figure 7 has one inverter group 19 and one current adjustment circuit 16, the transmission circuit 3 in Figure 16 has two inverter groups 19 and one current adjustment circuit 16.

[0117] Thus, in the fourth embodiment, since multiple transmission signals can be transmitted by a single transmission circuit group 7, the transmission timing of multiple transmission signals can be synchronized. More specifically, the current adjustment circuit 16 in each transmission circuit 3 included in the transmission circuit group 7 adjusts the current flowing to multiple inverters that transmit multiple transmission signals, so that the transmission timing of multiple transmission signals can be synchronized with a small circuit size. It is desirable that the multiple transmission signals operate mutually exclusive so as not to interfere with each other.

[0118] (Fifth Embodiment) The semiconductor device 1 according to the fifth embodiment has a block configuration similar to that of Figure 1, for example. The semiconductor device 1 according to the fifth embodiment is applied to the photodetector 2, similar to the first to fourth embodiments. The photodetector 2 according to the fifth embodiment includes a plurality of transmission circuits 3, similar to the first to fourth embodiments.

[0119] Figure 17 is a circuit diagram of a transmission circuit 3 according to the fifth embodiment. The transmission circuit 3 in Figure 17 includes first and second inverters IV4 and IV5 connected in series, a third inverter IV6 connected to the output node of the first stage first inverter IV4, and a capacitance adjustment circuit 20 that adjusts at least one of the wiring capacitance or parasitic capacitance of the output wiring of the transmission circuit 3 (output wiring of the second inverter IV5). In this specification, unless wiring capacitance and parasitic capacitance are described separately, the term "parasitic capacitance" may be used to include wiring capacitance as described above. The capacitance adjustment circuit 20 adjusts at least one of the wiring capacitance or parasitic capacitance of the output wiring of each transmission circuit 3 based on a plurality of adjustment signals output from the adjustment control circuit 4.

[0120] The capacitance adjustment circuit 20 includes first and second capacitance adjustment units 20a and 20b connected in parallel between the power supply voltage node and the output wiring of the transmission circuit 3, and third and fourth capacitance adjustment units 20c and 20d connected in parallel between the output wiring of the transmission circuit 3 and the ground voltage node.

[0121] The first capacitance adjustment unit 20a has a first capacitor C1 and a first PMOS transistor Q35 connected in series between the power supply voltage node and the output wiring of the transmission circuit 3. The second capacitance adjustment unit 20b has a second capacitor C2 and a second PMOS transistor Q36 connected in series between the power supply voltage node and the output wiring of the transmission circuit 3. The third capacitance adjustment unit 20c has a first NMOS transistor Q37 and a third capacitor C3 connected in series between the output wiring of the transmission circuit 3 and the ground voltage node. The fourth capacitance adjustment unit 20d has a second NMOS transistor Q38 and a fourth capacitor C4 connected in series between the output wiring of the transmission circuit 3 and the ground voltage node.

[0122] The adjustment signal Pgm0 output from the adjustment control circuit 4 is input to the gate of the first PMOS transistor Q35. The adjustment signal Pgm1 output from the adjustment control circuit 4 is input to the gate of the second PMOS transistor Q36. The adjustment signal Ngm0 output from the adjustment control circuit 4 is input to the gate of the first NMOS transistor Q37. The adjustment signal Ngm1 output from the adjustment control circuit 4 is input to the gate of the second NMOS transistor Q38.

[0123] The first to fourth capacitors C1 to C4 may be MOS capacitors, MOM (Metal-Oxide-Metal) capacitors which are interwiring capacitors, or MIM (Metal-Insulator-Metal) capacitors. An MIM capacitor, for example, has a structure in which multiple thin films with different dielectric constants are stacked.

[0124] Figure 18 shows the arrangement of the capacitance adjustment circuit 20 connected to the output wiring (output wiring of the second inverter IV5) of each transmission circuit 3 in a plurality of transmission circuits 3. Figure 17 shows an example in which the capacitance adjustment circuit 20 has first to fourth capacitance adjustment sections 20a to 20d, but the number of capacitance adjustment sections provided in the capacitance adjustment circuit 20 is arbitrary. In the example of Figure 17, the capacitance adjustment circuit 20 has first to sixth capacitance adjustment sections 20a to 20f. In Figure 17, the first to third capacitance adjustment sections 20a to 20c have a capacitor and a PMOS transistor connected in series between the power supply voltage node and the output wiring of inverter IV5, and the fourth to sixth capacitance adjustment sections 20d to 20f have a capacitor and an NMOS transistor connected in series between the output wiring of inverter IV5 and the ground voltage node.

[0125] Each capacitance adjustment unit 20a to 20d within the capacitance adjustment circuit 20 does not need to be located in the immediate vicinity of the second inverter IV5, and may be distributed along the output wiring of the transmission circuit 3. Alternatively, each capacitance adjustment unit may be located in an empty area of ​​the pixel array unit 6. Alternatively, the delay characteristics of each transmission circuit 3 may be adjusted more precisely by adjusting the location of each capacitance adjustment unit.

[0126] The capacitance adjustment circuit 20 according to the fifth embodiment may be provided in the transmission circuit 3 according to the first to fourth embodiments. This allows for simultaneous adjustment of the current flowing through each inverter of the inverter group 19 and adjustment of at least one of the wiring capacitance or parasitic capacitance of the output lines of each transmission circuit 3. Furthermore, as in the fourth embodiment, it may be possible to switch whether or not to perform capacitance adjustment by the capacitance adjustment circuit 20 using a stop switching instruction signal.

[0127] Thus, in the fifth embodiment, the capacitance adjustment circuit 20 adjusts at least one of the wiring capacitance or parasitic capacitance of the output line of each transmission circuit 3 in the plurality of transmission circuits 3, so that the transmission capability of each transmission circuit 3, including its delay characteristics, can be adjusted to a desired value.

[0128] (Sixth Embodiment) The photodetector 2 according to the sixth embodiment is characterized by grouping a plurality of transmission circuits 3. In the photodetector 2 according to the sixth embodiment, the plurality of transmission circuits 3 are classified into two or more groups, the adjustment control circuit 4 generates an adjustment signal supplied to each of the two or more groups, and the transmission capability of each transmission circuit belonging to each of the two or more groups is adjusted based on the corresponding adjustment signal.

[0129] Each transmission circuit 3 according to the first to fourth embodiments has a current adjustment circuit 16, and each transmission circuit 3 according to the fifth embodiment has a capacitance adjustment circuit 20. The current adjustment circuit 16 or capacitance adjustment circuit 20 is supplied with an adjustment signal from the adjustment control circuit 4. The adjustment control circuit 4 may supply different adjustment signals to each of the multiple current adjustment circuits 16 or multiple capacitance adjustment circuits 20 in the multiple transmission circuits 3, or it may supply adjustment signals that overlap in at least part.

[0130] Figure 19A shows a first example of adjustment signals supplied from the adjustment control circuit 4 to multiple current adjustment circuits 16 or multiple capacitance adjustment circuits 20. In the first example, the adjustment control circuit 4 supplies different adjustment signals to multiple current adjustment circuits 16 or multiple capacitance adjustment circuits 20 within multiple transmission circuits 3. This makes it possible to individually adjust at least one of the current flowing through each transmission circuit 3, or the wiring capacitance or parasitic capacitance of the output node of each transmission circuit 3.

[0131] Figure 19B shows a second example of adjustment signals supplied from the adjustment control circuit 4 to multiple current adjustment circuits 16 or capacitance adjustment circuits 20. The adjustment control circuit 4 in the second example repeatedly supplies M (where M is an integer of 2 or more, for example M=4) types of adjustment signals in sequence to multiple current adjustment circuits 16 or capacitance adjustment circuits 20.

[0132] Figure 19C shows a third example of adjustment signals supplied from the adjustment control circuit 4 to multiple current adjustment circuits 16 or capacitance adjustment circuits 20. In the third example, the adjustment control circuit 4 supplies the same type of adjustment signal N (where N is an integer of 2 or more, for example N=3) consecutive times to multiple current adjustment circuits 16 or capacitance adjustment circuits 20.

[0133] The current adjustment circuit 16 or capacitance adjustment circuit 20, to which the same type of adjustment signal is supplied, adjusts the transmission characteristics of the transmission circuit 3 in the same way.

[0134] Thus, in the sixth embodiment, the transmission characteristics of each transmission circuit 3 can be optimized by making all the adjustment signals supplied to the multiple transmission circuits 3 different. Furthermore, by making the adjustment signals supplied to some of the transmission circuits 3 the same, the number of types of adjustment signals supplied from the adjustment control circuit 4 to the multiple transmission circuits 3 can be reduced, thereby reducing the circuit size of the adjustment control circuit 4 and reducing the effort required to test whether the adjustment control circuit 4 is functioning correctly.

[0135] (Seventh Embodiment) As the functionality of the pixel circuit improves, the pixel size decreases, and the resolution increases, there is an increasing trend to construct the light detection device 2 by stacking multiple substrates. When stacking multiple substrates, the semiconductor processes of each substrate are not necessarily the same. Furthermore, even if multiple substrates are formed with the same semiconductor process, variations in the semiconductor process mean that the electrical characteristics of each substrate will not be the same.

[0136] Figure 20 is a layout diagram of the photodetector 2 according to the seventh embodiment. The photodetector 2 according to the seventh embodiment is constructed by stacking a first substrate 21 and a second substrate 22. Multiple transmission circuits 3 are arranged separately on the first substrate 21 and the second substrate 22. For example, a first portion of at least one of the multiple transmission circuits 3 is arranged on the first substrate 21, and a second portion different from the first portion is arranged on the second substrate 22. In addition, at least some of the multiple transmission circuits 3 may be arranged so as to overlap in the stacking direction of the first substrate 21 and the second substrate 22.

[0137] The first board 21 and the second board 22 each include a transmission circuit group 7 (repeater) in which multiple transmission circuits 3 are connected in series. Hereinafter, the transmission circuit group 7 of the first board 21 will be referred to as the first transmission circuit group 7, and the transmission circuit group 7 of the second board 22 will be referred to as the second transmission circuit group 7. The first transmission circuit group 7 transmits the first transmission target signal InA, and the second transmission circuit group 7 transmits the second transmission target signal InB. The first board 21 may include multiple first transmission circuit groups 7, and the second board 22 may include multiple second transmission circuit groups 7.

[0138] Each transmission circuit 3 in the first transmission circuit group 7 and each transmission circuit 3 in the second transmission circuit group 7 have the same configuration as the transmission circuit 3 according to any of the first to sixth embodiments. In addition, a first adjustment control circuit 4 for supplying adjustment signals to each transmission circuit 3 in the first transmission circuit group 7 is arranged on the first board 21. A second adjustment control circuit 4 for supplying adjustment signals to each transmission circuit 3 in the second transmission circuit group 7 is arranged on the second board 22.

[0139] Even if the first substrate 21 and the second substrate 22 are formed using the same semiconductor process, their electrical characteristics may not necessarily be the same due to manufacturing variations, etc. Therefore, it is desirable to supply adjustment signals to each transmission circuit 3 to adjust the transmission characteristics of each transmission circuit 3.

[0140] A single transmission circuit group 7 may be arranged using both the first substrate 21 and the second substrate 22. Figure 21 shows the first to fourth transmission circuit groups 7a to 7d arranged on both the first substrate 21 and the second substrate 22.

[0141] Each of the first to fourth transmission circuit groups 7a to 7d in Figure 21 has a first portion arranged on the first substrate 21 and a second portion arranged on the second substrate 22. The first portion and the second portion are connected by Cu-Cu junctions, bumps, or vias. The first transmission circuit group 7a and the second transmission circuit group 7b are arranged in the second direction X. The third transmission circuit group 7c and the fourth transmission circuit group 7d are arranged to overlap in the stacking direction.

[0142] By arranging the transmission circuit group 7 using multiple substrates 21 and 22, even if there are variations in the electrical characteristics of each substrate, the effects of these variations in the electrical characteristics of each substrate can be more easily absorbed.

[0143] Thus, in the seventh embodiment, a transmission circuit group 7 is provided on each of the multiple stacked substrates 21 and 22, and the transmission characteristics of each transmission circuit 3 are adjusted by adjustment signals supplied from an adjustment control circuit 4 provided on each substrate. This makes it possible to adjust the transmission characteristics of each transmission circuit 3 to a desired value, even if the electrical characteristics of each substrate are not the same. Furthermore, the transmission circuit groups 7a to 7d may be operated simultaneously, or only one of them may be operated selectively.

[0144] (Eighth Embodiment) Figure 22 is a layout diagram of the light detection device 2 according to the eighth embodiment. The light detection device 2 according to the eighth embodiment includes a monitoring unit 23 that monitors the signal transmission in the transmission circuit group 7 according to any of the first to seventh embodiments.

[0145] The monitor unit 23 in Figure 22 includes a plurality of monitor circuits 24, a plurality of first amplifiers (AMPs) 25, a second amplifier (AMP) 26, and an output unit (OUT) 27. The plurality of monitor circuits 24 have the same circuit configuration as the plurality of transmission circuits 3. The plurality of monitor circuits 24 receive the same adjustment signals as the transmission circuits 3 in the same stage. The transmission characteristics of each monitor circuit 24 are adjusted by the corresponding adjustment signals. The row of monitor circuits 24, including the plurality of monitor circuits 24, transmits, for example, a plurality of monitor signals MinA and MinB. The first amplifiers 25 are connected to at least some of the output wiring of the transmission control circuit 5 and the plurality of monitor circuits 24. The output nodes of the plurality of first amplifiers 25 are all connected to the input nodes of the second amplifier 26.

[0146] Of the multiple first amplifiers 25, the first-stage first amplifier 25 receives two monitor signals MinA and MinB output from the transmission control circuit 5, and two transmission target signals InA and InB output from the transmission control circuit 5 and input to the transmission circuit group 7. The final-stage first amplifier 25 receives two monitor signals MoutA and MoutB output from the monitor circuit group, and two transmission target signals OutA and OutB output from the transmission circuit group 7. The first amplifiers 25 other than the first and final stages receive monitor signals output from their corresponding monitor circuits 24.

[0147] Each of the multiple first amplifiers 25 amplifies the input monitor signal or the signal to be transmitted, switches one of them, and inputs it to the second amplifier 26. The output unit 27 outputs the voltage level of the output wire selectively selected from among the multiple output wires via the first amplifiers 25 and the second amplifiers 26.

[0148] To directly monitor the signal being transmitted by the transmission circuit group 7, it is necessary to connect the output lines of each transmission circuit 3 in the transmission circuit group 7 to the monitor circuit 24. In this case, new wiring is required to connect the output nodes of each transmission circuit 3 to the monitor circuit 24, which may cause fluctuations in the transmission characteristics of each transmission circuit 3. Therefore, in the monitoring unit 23 of Figure 22, a new monitor circuit 24 with the same circuit configuration as the transmission circuit group 7 is provided to monitor the monitor signal transmitted by the monitor circuit group, which includes multiple monitor circuits 24.

[0149] Figure 23A is a circuit diagram showing the internal configuration of the first amplifier 25. As shown in Figure 23A, the first amplifier 25 includes a differential amplifier 28, first to fourth switches SW1 to SW4 connected to the positive input terminal of the differential amplifier 28, and a fifth switch SW5 connected to the output terminal of the differential amplifier 28. The first to fourth switches SW1 to SW4 selectively select one of two monitor signals and two transmission target signals and input it to the positive input terminal of the differential amplifier 28. The negative input terminal and output terminal of the differential amplifier 28 are short-circuited. When the fifth switch SW5 is ON, the differential amplifier 28 amplifies the monitor signal or transmission target signal selected by the first to fourth switches SW1 to SW4 and outputs it.

[0150] Figure 23B is a circuit diagram showing the internal configuration of the second amplifier 26. The second amplifier 26 has a differential amplifier 29. The positive input terminal of the differential amplifier 29 is connected to the output node of the first amplifier 25. The negative input terminal of the differential amplifier 29 is short-circuited to the output terminal. The differential amplifier 29 amplifies the monitor signal or the signal to be transmitted amplified by the first amplifier 25 and outputs it. The output signal of the second amplifier 26 is output to the output unit 27.

[0151] Thus, in the eighth embodiment, in order to monitor the signal to be transmitted by the transmission circuit group 7, a new monitoring circuit group with the same circuit configuration as the transmission circuit group 7 is provided, and the monitoring signal transmitted by the monitoring circuit group is monitored. This makes it possible to monitor whether or not the transmission circuit group 7 is transmitting signals correctly without affecting the transmission characteristics of the transmission circuit group 7. Furthermore, with respect to InA / InB and OutA / OutB, it is desirable to be able to selectively monitor not only in the row direction of MinA / MinB and MoutA / MoutB, but also in the column direction.

[0152] <Examples of application to mobile devices> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0153] Figure 24 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0154] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 24, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0155] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0156] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0157] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0158] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0159] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0160] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0161] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0162] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0163] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 24, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0164] Figure 25 shows an example of the installation position of the imaging unit 12031.

[0165] In Figure 25, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0166] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0167] Figure 25 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0168] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0169] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0170] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0171] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0172] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein may be applied to the imaging unit 12031, etc., among the configurations described above.

[0173] Furthermore, this technology can take the following configurations: (1) A semiconductor device comprising: a plurality of transmission circuits connected in series to sequentially transmit a signal to be transmitted; and an adjustment control circuit for individually adjusting the transmission capability of each of the plurality of transmission circuits. (2) The semiconductor device according to (1), wherein the plurality of transmission circuits are arranged in a first direction, and a plurality of transmission circuit groups are arranged in a second direction intersecting the first direction, each having the plurality of transmission circuits, and the adjustment control circuit individually adjusts the transmission capability of each of the plurality of transmission circuits in each of the plurality of transmission circuit groups. (3) The semiconductor device according to (1) or (2), wherein the adjustment control circuit individually adjusts the current flowing through the plurality of transmission circuits. (4) The semiconductor device according to (3), wherein the adjustment control circuit outputs a plurality of adjustment signals for individually adjusting the transmission capability of the plurality of transmission circuits, and the plurality of transmission circuits comprises: at least one inverter connected in series to sequentially transfer the signal to be transmitted; and a plurality of current adjustment circuits that adjust the current flowing through the at least one inverter based on the plurality of adjustment signals output from the adjustment control circuit. (5) The semiconductor device according to (4), wherein the current adjustment circuit includes a normally-on circuit. (6) The semiconductor device according to (4), wherein the current adjustment circuit has a first transistor that adjusts the current flowing to the corresponding inverter, and the adjustment control circuit has a second transistor that can adjust the source-drain current and forms a current mirror circuit with the first transistor. (7) The semiconductor device according to any one of (4) to (6), wherein each of the plurality of transmission circuits has a stop switching circuit that switches whether the corresponding current adjustment circuit performs or stops the operation of adjusting the current flowing to the corresponding inverter. (8) The semiconductor device according to (7), wherein each of the plurality of stop switching circuits corresponding to the plurality of transmission circuits stops the operation of the corresponding current adjustment circuit adjusting the current flowing to the corresponding inverter when the stop switching instruction signal is of a predetermined logic.(9) The semiconductor device according to (8), wherein the plurality of transmission circuits are arranged in a first direction, and further comprises a plurality of transmission circuit groups arranged in a second direction intersecting the first direction, each having the plurality of transmission circuits, the stop switching instruction signal is provided for each of the plurality of transmission circuit groups, and each of the plurality of transmission circuit groups switches whether or not to perform an operation to adjust the current flowing to the inverter based on the corresponding stop switching instruction signal. (10) The semiconductor device according to any one of (4) to (9), wherein a plurality of inverters are arranged in a first direction, the plurality of transmission circuits are each arranged in a second direction intersecting the first direction, each having a plurality of inverter groups including the plurality of inverters, and each of the plurality of current adjustment circuits adjusts the current flowing to the plurality of inverters of the corresponding stage in the plurality of inverter groups. (11) The semiconductor device according to any one of (4) to (10), wherein each of the plurality of transmission circuits has a capacitance adjustment circuit that adjusts at least one of the wiring capacitance or parasitic capacitance of each output wiring of the plurality of transmission circuits based on the plurality of adjustment signals output from the adjustment control circuit. (12) The semiconductor device according to (11), wherein the capacitance adjustment circuit has a capacitor and a transistor connected in series between the output wiring and the reference voltage node, and the adjustment control circuit outputs the adjustment signal which switches the transistor in each of the plurality of transmission circuits on or off. (13) The semiconductor device according to any one of (1) to (12), wherein the plurality of transmission circuits are classified into two or more sets, and the adjustment control circuit generates an adjustment signal which is supplied to each of the two or more sets, and the transmission capability of each of the two or more sets is adjusted based on the corresponding adjustment signal. (14) The semiconductor device according to any one of (1) to (13), comprising a stacked first substrate and a second substrate, wherein the plurality of transmission circuits are arranged separately on the first substrate and the second substrate.(15) The semiconductor device according to (14), wherein a first portion of at least one of the plurality of transmission circuits is arranged on the first substrate, and a second portion different from the first portion is arranged on the second substrate. (16) The semiconductor device according to (14), wherein at least some of the plurality of transmission circuits are arranged to overlap in the stacking direction of the first substrate and the second substrate. (17) The semiconductor device according to any one of (1) to (16), comprising: a plurality of monitor circuits having the same circuit configuration as the plurality of transmission circuits; a plurality of amplifiers connected to a plurality of output wirings in the plurality of monitor circuits; and an output unit that outputs the voltage level of the plurality of output wirings amplified by the plurality of amplifiers. (18) The semiconductor device according to (17), wherein the output unit outputs the voltage level of an output wiring selectively selected from the plurality of output wirings. (19) A light detection device comprising: a plurality of pixels arranged in a first direction and a second direction that intersect each other; a plurality of transmission circuits arranged between groups of pixels including two or more pixels arranged in the first direction and connected in series to sequentially transmit a signal to be transmitted; and an adjustment control circuit for individually adjusting the transmission capability of each of the plurality of transmission circuits, wherein the signal to be transmitted output from each of the plurality of transmission circuits is supplied to the corresponding pixel. (20) The light detection device according to (19), comprising a plurality of transmission circuit groups arranged in the second direction and each including the plurality of transmission circuits, wherein the signal to be transmitted output from two adjacent transmission circuits in the second direction is supplied to pixels shifted in the first direction.

[0174] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0175] 1 Semiconductor device, 2 Photodetector, 3 Transmission circuit, 3a First transmission circuit, 3b Second transmission circuit, 4 Adjustment control circuit, 5 Transmission control circuit, 6 Pixel array section, 7 Transmission circuit group, 7a First transmission circuit group, 7b Second transmission circuit group, 7c Third transmission circuit group, 7d Fourth transmission circuit group, 9 PMOS transistor, 11 Light receiving section, 12 Counter, 13 Selection switch, 15 Detection circuit, 16 Current adjustment circuit, 16a First current adjustment circuit, 16b Second current adjustment circuit, 17a Current mirror circuit, 17b Current mirror circuit, 18a First current source, 18b Second current source, 19 Inverter group, 20 Capacitance adjustment circuit, 20a First capacitance adjustment section, 20b Second capacitance adjustment section, 20c Third capacitance adjustment section, 20d Fourth capacitance adjustment section, 20e Fifth capacitance adjustment section, 20f Sixth capacitance adjustment section, 21 First substrate, 22 22 board, 23 monitor section, 24 monitor circuit, 25 first amplifier, 26 second amplifier, 27 output section, 28 differential amplifier, 29 differential amplifier

Claims

1. A semiconductor device comprising: a plurality of transmission circuits connected in series to sequentially transmit a signal to be transmitted; and an adjustment control circuit for individually adjusting the transmission capability of each of the plurality of transmission circuits.

2. The semiconductor device according to claim 1, wherein the plurality of transmission circuits are arranged in a first direction, and the plurality of transmission circuit groups are arranged in a second direction intersecting the first direction, each having the plurality of transmission circuits, and the adjustment control circuit adjusts the transmission capability of each of the plurality of transmission circuits in each of the plurality of transmission circuit groups individually.

3. The semiconductor device according to claim 1, wherein the adjustment control circuit adjusts the current flowing through the plurality of transmission circuits individually.

4. The semiconductor device according to claim 3, wherein the adjustment control circuit outputs a plurality of adjustment signals for individually adjusting the transmission capabilities of the plurality of transmission circuits, and the plurality of transmission circuits each comprises at least one inverter connected in series to sequentially transfer the transmission target signals, and a plurality of current adjustment circuits that adjust the current flowing through the at least one inverter based on the plurality of adjustment signals output from the adjustment control circuit.

5. The semiconductor device according to claim 4, wherein the current adjustment circuit includes a normally-on circuit.

6. The semiconductor device according to claim 4, wherein the current adjustment circuit has a first transistor that adjusts the current flowing through the corresponding inverter, and the adjustment control circuit has a second transistor that can adjust the source-drain current and forms a current mirror circuit with the first transistor.

7. The semiconductor device according to claim 4, wherein each of the plurality of transmission circuits has a stop switching circuit that switches whether the corresponding current adjustment circuit performs or stops the operation of adjusting the current flowing to the corresponding inverter.

8. The semiconductor device according to claim 7, wherein each of the plurality of stop switching circuits corresponding to the plurality of transmission circuits stops the operation of the corresponding current adjustment circuit to adjust the current flowing to the corresponding inverter when the stop switching instruction signal is of a predetermined logic.

9. The semiconductor device according to claim 8, wherein the plurality of transmission circuits are arranged in a first direction, and further comprises a plurality of transmission circuit groups arranged in a second direction intersecting the first direction, each having the plurality of transmission circuits, the stop switching instruction signal is provided for each of the plurality of transmission circuit groups, and each of the plurality of transmission circuit groups switches whether or not to perform an operation to adjust the current flowing to the inverter based on the corresponding stop switching instruction signal.

10. The semiconductor device according to claim 4, wherein a plurality of inverters are arranged in a first direction, the plurality of transmission circuits are each arranged in a second direction intersecting the first direction, and each has a plurality of inverter groups including the plurality of inverters, and each of the plurality of current adjustment circuits adjusts the current flowing to the plurality of inverters of the corresponding stage in the plurality of inverter groups.

11. The semiconductor device according to claim 4, wherein each of the plurality of transmission circuits has a capacitance adjustment circuit that adjusts at least one of the wiring capacitance or parasitic capacitance of the output wiring of each of the plurality of transmission circuits based on the plurality of adjustment signals output from the adjustment control circuit.

12. The semiconductor device according to claim 11, wherein the capacitance adjustment circuit has a capacitor and a transistor connected in series between the output wiring and the reference voltage node, and the adjustment control circuit outputs the adjustment signal which switches the transistor in each of the plurality of transmission circuits on or off.

13. The semiconductor device according to claim 1, wherein the plurality of transmission circuits are classified into two or more sets, the adjustment control circuit generates an adjustment signal supplied to each of the two or more sets, and the transmission capability of each of the two or more sets is adjusted based on the corresponding adjustment signal.

14. The semiconductor device according to claim 1, comprising a first substrate and a second substrate that are stacked, wherein the plurality of transmission circuits are arranged separately on the first substrate and the second substrate.

15. The semiconductor device according to claim 14, wherein a first portion of at least one of the plurality of transmission circuits is arranged on the first substrate, and a second portion different from the first portion is arranged on the second substrate.

16. The semiconductor device according to claim 14, wherein at least some of the plurality of transmission circuits are arranged to overlap in the stacking direction of the first substrate and the second substrate.

17. The semiconductor device according to claim 1, comprising: a plurality of monitor circuits having the same circuit configuration as the plurality of transmission circuits; a plurality of amplifiers connected to a plurality of output wirings in the plurality of monitor circuits; and an output unit that outputs the voltage levels of the plurality of output wirings amplified by the plurality of amplifiers.

18. The semiconductor device according to claim 17, wherein the output unit outputs the voltage level of an output wire selectively selected from the plurality of output wires.

19. A light detection device comprising: a plurality of pixels arranged in a first and second direction that intersect each other; a plurality of transmission circuits arranged between groups of pixels including two or more pixels arranged in the first direction, connected in series to sequentially transmit a signal to be transmitted; and an adjustment control circuit for individually adjusting the transmission capability of each of the plurality of transmission circuits, wherein the signal to be transmitted output from each of the plurality of transmission circuits is supplied to the corresponding pixel.

20. The photodetector according to claim 19, comprising a plurality of transmission circuit groups arranged in the second direction, each including the plurality of transmission circuits, wherein the transmission target signals output from two adjacent transmission circuits in the second direction are supplied to pixels shifted in the first direction.

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