Differential amplifier circuit

Abstract

This differential amplifier circuit includes: a first amplifier to which a first phase signal is input, a second amplifier to which a second phase signal is input; a first inductor having one end connected to an output terminal of the first amplifier and the other end connected to an output terminal of the second amplifier; a first capacitor; a second capacitor; a first switch connected to a node between one point of the first inductor and a reference potential and connecting or disconnecting the first capacitor; and a second switch connecting or disconnecting the second capacitor between the output terminal of the first amplifier and the output terminal of the second amplifier.

Description

Differential amplifier circuit

[0001] This disclosure relates to a differential amplifier circuit.

[0002] Patent Document 1, listed below, describes a differential amplifier circuit that switches characteristics related to the second harmonic.

[0003] Japanese Patent Publication No. 2022-2360

[0004] However, while the differential amplifier circuit described in Patent Document 1 takes into consideration switching the characteristics related to the second harmonic, there is room for improvement in switching the characteristics related to other harmonics.

[0005] This disclosure is made in view of the above and aims to switch characteristics other than the second harmonic.

[0006] A differential amplifier circuit according to one aspect of the present disclosure includes: a first amplifier whose input terminal is electrically connected to a first terminal to which a first phase signal of a differential signal is input; a second amplifier whose input terminal is electrically connected to a second terminal to which a second phase signal of a differential signal is input; a first inductor with one end connected to the output terminal of the first amplifier and the other end connected to the output terminal of the second amplifier; one or more first capacitors; one or more second capacitors; one or more first switches connected to a node between a point on the first inductor and a reference potential, for connecting or disconnecting one or more first capacitors, respectively; and one or more second switches between the output terminal of the first amplifier and the output terminal of the second amplifier, for connecting or disconnecting one or more second capacitors, respectively.

[0007] A differential amplifier circuit according to one aspect of the present disclosure includes: a first amplifier whose input terminal is electrically connected to a first terminal into which a first phase signal of a differential signal is input; a second amplifier whose input terminal is electrically connected to a second terminal into which a second phase signal of a differential signal is input; a first inductor with one end connected to the output terminal of the first amplifier and the other end connected to the output terminal of the second amplifier; one or more first capacitors; one or more first switches connected to a node between a point of the first inductor and a reference potential, each connecting or disconnecting one or more first capacitors; a fourth capacitor and a third inductor connected in series; a fifth capacitor and a fourth inductor connected in series; a third switch connected to a node between the output terminal of the first amplifier and a reference potential, each connecting or disconnecting the fourth capacitor and the third inductor; and a fourth switch connected to a node between the output terminal of the second amplifier and a reference potential, each connecting or disconnecting the fifth capacitor and the fourth inductor.

[0008] According to this disclosure, it is possible to switch characteristics other than the second harmonic.

[0009] Figure 1 shows the circuit configuration of the differential amplifier circuit of the first embodiment. Figure 2 shows the circuit simulation results of the differential amplifier circuit of the first embodiment at low to medium output power. Figure 3 shows the circuit simulation results of the differential amplifier circuit of the first embodiment at low to medium output power. Figure 4 shows the circuit simulation results of the differential amplifier circuit of the first embodiment at high output power. Figure 5 shows the circuit simulation results of the differential amplifier circuit of the first embodiment at high output power. Figure 6 shows the configuration of the differential amplifier circuit of the second embodiment. Figure 7 shows the circuit simulation results of the differential amplifier circuit of the second embodiment at low to medium output power. Figure 8 shows the circuit simulation results of the differential amplifier circuit of the second embodiment at low to medium output power. Figure 9 shows the circuit simulation results of the differential amplifier circuit of the second embodiment at low to medium output power. Figure 10 shows the circuit simulation results of the differential amplifier circuit of the second embodiment at low to medium output power. Figure 11 shows the circuit simulation results of the differential amplifier circuit of the second embodiment at high output power. Figure 12 shows the circuit simulation results for the differential amplifier circuit of the second embodiment at high output power. Figure 13 shows the circuit simulation results for the differential amplifier circuit of the second embodiment at high output power. Figure 14 shows the circuit simulation results for the differential amplifier circuit of the second embodiment at high output power. Figure 15 shows the circuit simulation results for the output voltage of the differential amplifier circuit of the second embodiment. Figure 16 shows the circuit simulation results for the output voltage of the differential amplifier circuit of the second embodiment. Figure 17 shows the circuit simulation results for the output voltage of the differential amplifier circuit of the second embodiment. Figure 18 shows the circuit simulation results for the output current of the differential amplifier circuit of the second embodiment. Figure 19 shows the circuit simulation results for the output current of the differential amplifier circuit of the second embodiment. Figure 20 shows the circuit simulation results for the output current of the differential amplifier circuit of the second embodiment. Figure 21 shows the circuit simulation results for the output voltage and output current of the differential amplifier circuit of the second embodiment.Figure 22 shows the circuit simulation results of the output voltage and output current of the differential amplifier circuit of the second embodiment. Figure 23 shows the circuit simulation results of the output voltage and output current of the differential amplifier circuit of the second embodiment. Figure 24 shows the configuration of the differential amplifier circuit of the third embodiment. Figure 25 shows the configuration of the differential amplifier circuit of the fourth embodiment. Figure 26 shows the configuration of the differential amplifier circuit of the fifth embodiment. Figure 27 shows the configuration of the differential amplifier circuit of the sixth embodiment. Figure 28 shows the impedance of the differential amplifier circuit of the sixth embodiment. Figure 29 shows the impedance of the differential amplifier circuit of the sixth embodiment. Figure 30 shows the configuration of the first modified differential amplifier circuit of the sixth embodiment. Figure 31 shows the configuration of the second modified differential amplifier circuit of the sixth embodiment.

[0010] The embodiments of this disclosure will be described in detail below with reference to the drawings. However, the present invention is not limited by these embodiments. Each embodiment is illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. In the second and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects and advantages due to similar configurations will not be mentioned sequentially for each embodiment.

[0011] <First Embodiment> (Circuit Configuration) Figure 1 shows the circuit configuration of the differential amplifier circuit according to the first embodiment.

[0012] The differential amplifier circuit 1 amplifies the high-frequency differential signal RFin and outputs the amplified single-ended high-frequency signal RFout to one end of the load 102 via the matching circuit 101. In this embodiment, the load 102 is a resistor, but the disclosure is not limited thereto.

[0013] The first phase high-frequency signal RF1 of the high-frequency differential signal RFin is input to terminal 1a of the differential amplifier circuit 1. The second phase high-frequency signal RF2 of the high-frequency differential signal RFin is input to terminal 1b of the differential amplifier circuit 1. A single-ended high-frequency signal RFout is output from terminal 1c of the differential amplifier circuit 1.

[0014] Terminal 1a corresponds to an example of the "first terminal" of this disclosure. Terminal 1b corresponds to an example of the "second terminal" of this disclosure.

[0015] In this embodiment, the first phase is positive (positive polarity) and the second phase is negative (negative polarity), but this disclosure is not limited to this. The first phase may be negative and the second phase may be positive.

[0016] The differential amplifier circuit 1 includes an amplifier 11, an amplifier 12, a transformer 13, a switch 14, a capacitor 15, a switch 16, and a capacitor 17.

[0017] The transformer 13 includes a first winding 13a, a second winding 13b, and a core 13c. The first winding 13a and the second winding 13b are wound around the core 13c. The first winding 13a and the second winding 13b are magnetically coupled. The transformer 13 may also be a balun.

[0018] Each element may be an SMD (Surface Mount Device) or may be formed within a semiconductor device. The transformer 13 may be an SMD or may be formed as a wiring pattern on a substrate (for example, a Printed Wiring Board (PWB)).

[0019] Amplifier 11 corresponds to an example of the “first amplifier” in this disclosure. Amplifier 12 corresponds to an example of the “second amplifier” in this disclosure. First winding 13a corresponds to an example of the “first inductor” in this disclosure. Second winding 13b corresponds to an example of the “second inductor” in this disclosure. Switch 14 corresponds to an example of “one or more first switches” in this disclosure. Capacitor 15 corresponds to an example of “one or more first capacitors” in this disclosure. Switch 16 corresponds to an example of “one or more second switches” in this disclosure. Capacitor 17 corresponds to an example of “one or more second capacitors” in this disclosure.

[0020] The input terminal of amplifier 11 is electrically connected to terminal 1a, and a high-frequency signal RF1 is input to it. Amplifier 11 amplifies the high-frequency signal RF1 and outputs the amplified high-frequency signal RF3.

[0021] The output terminal of the amplifier 11 is electrically connected to one end of the first winding 13a and one end of the switch 16. The other end of the switch 16 is electrically connected to one end of the capacitor 17.

[0022] The input terminal of amplifier 12 is electrically connected to terminal 1b, and a high-frequency signal RF2 is input to it. Amplifier 12 amplifies the high-frequency signal RF2 and outputs the amplified high-frequency signal RF4.

[0023] Hereafter, high-frequency signals RF1 to RF4 may be collectively referred to as "high-frequency signal RF".

[0024] The output terminal of the amplifier 12 is electrically connected to the other end of the first winding 13a and the other end of the capacitor 17.

[0025] A point 13a0 of the first winding 13a is electrically connected to the power supply potential Vcc. Preferably, point 13a0 is the midpoint of the first winding 13a, but the disclosure is not limited thereto. The collector of a transistor (not shown) in the amplifier 11 is supplied with the power supply potential Vcc via a first portion 13a1 of the first winding 13a. The first portion 13a1 of the first winding 13a is the portion from one end of the first winding 13a to point 13a0.

[0026] The collector of the transistor (not shown) in the amplifier 12 is supplied with the power supply potential Vcc via the second portion 13a2 of the first winding 13a. The second portion 13a2 of the first winding 13a is the portion from the other end of the first winding 13a to a point 13a0.

[0027] In the first winding 13a, the high-frequency signal RF3 and the high-frequency signal RF4 are superimposed (combined).

[0028] One end of the second winding 13b is electrically connected to terminal 1c. The other end of the second winding 13b is electrically connected to a reference potential. The reference potential is exemplified by, but is not limited to, the earth potential.

[0029] The first winding 13a and the second winding 13b are magnetically coupled. Therefore, the high-frequency signal generated in the first winding 13a propagates to the second winding 13b via the magnetic field coupling. The high-frequency signal RFout generated in the second winding 13b is then output from one end of the second winding 13b to one end of the matching circuit 101 via terminal 1c.

[0030] One end of the switch 14 is electrically connected to a point 13a0 of the first winding 13a. The other end of the switch 14 is electrically connected to one end of the capacitor 15. The other end of the capacitor 15 is electrically connected to a reference potential.

[0031] Switch 14 connects or disconnects capacitor 15 between a point 13a0 of the first winding 13a and a reference potential.

[0032] Switch 14 turns ON (conducts) when the power of the high-frequency signal RFout is below a predetermined threshold. As a result, capacitor 15 is connected between a point 13a0 on the first winding 13a and the reference potential.

[0033] Switch 14 turns off (non-conductive) when the power of the high-frequency signal RFout exceeds a threshold. As a result, the capacitor 15 is disconnected between a point 13a0 on the first winding 13a and the reference potential.

[0034] Hereafter, the case where the power of the high-frequency signal RFout is below the threshold may be referred to as "low to medium output power." Conversely, the case where the power of the high-frequency signal RFout is above the threshold may be referred to as "high output power."

[0035] Switch 16 connects or disconnects the capacitor 17 between the output terminal of amplifier 11 and the output terminal of amplifier 12.

[0036] Switch 16 turns ON (conducts) when the power of the high-frequency signal RFout is below a threshold. As a result, capacitor 17 is connected between the output terminal of amplifier 11 and the output terminal of amplifier 12.

[0037] When the power of the high-frequency signal RFout is equal to or higher than the threshold value, the switch 16 turns off (becomes non-conductive). As a result, the capacitor 17 is disconnected between the output terminal of the amplifier 11 and the output terminal of the amplifier 12.

[0038] (Circuit simulation result of impedance at low and medium output power of differential amplifier circuit) As described above, at low and medium output power, the switches 14 and 16 turn on (become conductive). At this time, the impedance Z Ｌ seen from the output terminal of the amplifier 11 to the subsequent circuit was obtained by circuit simulation.

[0039] Note that the impedance Z Ｌ seen from the output terminal of the amplifier 12 to the subsequent circuit is the same as the impedance Z Ｌ seen from the output terminal of the amplifier 11 to the subsequent circuit. Therefore, in the embodiment, the impedance Z Ｌ seen from the output terminal of the amplifier 11 to the subsequent circuit will be described, and the description of the impedance Z Ｌ seen from the output terminal of the amplifier 12 to the subsequent circuit will be omitted.

[0040] Hereinafter, the fundamental wave frequency of the high-frequency signal RF is referred to as frequency f ０ and the second harmonic frequency of the high-frequency signal RF is referred to as frequency 2f ０ and the third harmonic frequency of the high-frequency signal RF is referred to as frequency 3f ０ are called.

[0041] FIGS. 2 and 3 are diagrams showing the circuit simulation results of the differential amplifier circuit in the first embodiment at low and medium output power.

[0042] FIG. 2 is a Smith chart showing the impedance Z Ｌ for the second harmonic at low and medium output power.

[0043] Since the switch 14 is on (conductive), the capacitor 15 is connected between a point 13a0 of the first winding 13a and the reference potential. Generally, the capacitance of the capacitor 15 is at frequency 2f ０It is large enough to allow the second harmonic to pass through. Therefore, as shown at point 201, the impedance at point 13a0 with respect to the second harmonic is low impedance.

[0044] However, the first part 13a1 is electrically connected between the output terminal of the amplifier 11 and point 13a0. Due to the inductance of this first part 13a1, the impedance Z for the second harmonic is Ｌ It moves from point 201 along arrow 202 to point 203.

[0045] Thus, impedance Z Ｌ This tends to have a higher impedance with respect to the second harmonic.

[0046] At low to medium output power, the impedance Z of the first winding 13a and the capacitor 15 is such that the impedance Z of the second harmonic is such that the first portion 13a1 of the first winding 13a and the capacitor 15 are such that Ｌ This relates to the second part 13a2 of the first winding 13a and the capacitor 15, and the impedance Z for the second harmonic. Ｌ It is related to that.

[0047] Figure 3 shows the impedance Z for the third harmonic at low to medium power levels. Ｌ This is a Smith chart showing [something].

[0048] Since switch 16 is in the ON (conducting) state, capacitor 17 is connected between the output terminal of amplifier 11 and the output terminal of amplifier 12. Generally, the capacitance of capacitor 17 is such that at a frequency of 3f ０ It is large enough to allow the third harmonic to pass through.

[0049] Therefore, as shown at point 211, impedance Z Ｌ This results in low impedance with respect to the third harmonic.

[0050] At low to medium output power, the capacitor 17 has an impedance Z to the third harmonic. Ｌ It is related to that.

[0051] In summary, the differential amplifier circuit 1 has high impedance to the second harmonic and low impedance to the third harmonic at low to medium output power, thus becoming an amplifier similar to an inverse Class F amplifier.

[0052] (Circuit simulation results of impedance at high output power of differential amplifier circuit) As described above, at high output power, switches 14 and 16 are in the off (non-conducting) state. The impedance Z at this time is Ｌ This was determined by circuit simulation.

[0053] Figures 4 and 5 show the circuit simulation results of the differential amplifier circuit of the first embodiment at high output power.

[0054] Figure 4 shows the impedance Z for the second harmonic at high power output. Ｌ This is a Smith chart showing [something].

[0055] Since switch 14 is in the off (non-conductive) state, capacitor 15 is not connected between point 13a0 of the first winding 13a and the reference potential. Therefore, as shown by point 221, point 13a0 of the first winding 13a has a high impedance with respect to the second harmonic.

[0056] However, the first part 13a1 is electrically connected between the output terminal of the amplifier 11 and point 13a0. Due to the inductance of this first part 13a1, the impedance Z Ｌ It moves from point 221 along arrow 222 to point 223.

[0057] Thus, impedance Z Ｌ This results in a lower impedance relative to the second harmonic.

[0058] At high power output, the first portion 13a1 of the first winding 13a has an impedance Z to the second harmonic. Ｌ This relates to the second portion 13a2 of the first winding 13a, which has an impedance Z for the second harmonic. Ｌ It is related to that.

[0059] Figure 5 shows the impedance Z for the third harmonic at high power output.Ｌ This is a Smith chart showing [something].

[0060] Since switch 16 is in the off (non-conductive) state, capacitor 17 is not connected between the output terminal of amplifier 11 and the output terminal of amplifier 12. However, the first winding 13a is electrically connected between the output terminal of amplifier 11 and the output terminal of amplifier 12.

[0061] Therefore, as shown at point 231, impedance Z Ｌ This exhibits high impedance with respect to the third harmonic.

[0062] At high power output, the first portion 13a1 of the first winding 13a has an impedance Z to the third harmonic. Ｌ This relates to the impedance Z of the third harmonic. Similarly, the second portion 13a2 of the first winding 13a has an impedance Z of the third harmonic. Ｌ It is related to that.

[0063] In summary, the differential amplifier circuit 1 exhibits low impedance to the second harmonic and high impedance to the third harmonic at high output power, thus becoming an amplifier similar to a Class F amplifier.

[0064] (Effects) (1) When the differential amplifier circuit 1 is at low to medium output power, it becomes an amplifier similar to an inverse Class F amplifier. Furthermore, the differential amplifier circuit 1 can be constructed simply by adding amplifier 11, amplifier 12, transformer 13, switch 14, capacitor 15, switch 16, and capacitor 17.

[0065] Therefore, the differential amplifier circuit 1 has fewer components and can be miniaturized compared to a generally known inverse-F class amplifier.

[0066] (2) When the differential amplifier circuit 1 is at high output power, it becomes an amplifier similar to a Class F amplifier.

[0067] Therefore, the differential amplifier circuit 1 can suppress the amplitude of the output voltage when the output power is high, thereby reducing the possibility of damage to amplifiers 11 and 12.

[0068] In this embodiment, only an example has been given in which the amplifier functions as an inverse Class F amplifier at low to medium output power and as a Class F amplifier at high output power, but the disclosure is not limited thereto. The differential amplifier circuit of the first embodiment may be configured to function as a Class F amplifier at low to medium output power and as an inverse Class F amplifier at high output power.

[0069] (3) As described above, the differential amplifier circuit 1 can switch characteristics other than the second harmonic.

[0070] <Second Embodiment> (Circuit Configuration) Among the components of the differential amplifier circuit 1A of the second embodiment, components that are the same as those of the differential amplifier circuit 1 of the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0071] Figure 6 shows the configuration of the differential amplifier circuit according to the second embodiment.

[0072] The differential amplifier circuit 1A further includes a capacitor 18 compared to the differential amplifier circuit 1.

[0073] The capacitor 18 may be an SMD (Small Microdistributed Capacitor) or it may be formed inside the semiconductor device.

[0074] Capacitor 18 corresponds to an example of the "third capacitor" in this disclosure.

[0075] One end of the capacitor 18 is electrically connected to a point 13a0 of the first winding 13a. The other end of the capacitor 18 is electrically connected to a reference potential.

[0076] The capacitance of capacitor 18 may be the same as or different from the capacitance of capacitor 15.

[0077] (Circuit simulation results of impedance at low to medium output power of differential amplifier circuit) As described in the first embodiment, at low to medium output power, switches 14 and 16 are in the ON (conducting) state. The impedance Z when viewed from the output terminal of amplifier 11 to the subsequent circuit at this time is Ｌ This was determined by circuit simulation.

[0078] Figures 7 to 10 show the circuit simulation results of the differential amplifier circuit of the second embodiment at low to medium output power. In this circuit simulation, the fundamental frequency f of the high-frequency signal RF is used. ０ The frequency was varied from 100 MHz (megahertz) to 5 GHz (gigahertz).

[0079] Figure 7 shows the impedance Z for the fundamental wave, second harmonic, and third harmonic at low to medium power levels. Ｌ This is a Smith chart showing [something].

[0080] In Figure 7, line 241 represents the impedance Z for the fundamental wave. Ｌ This shows that point 242 is the frequency f of the fundamental wave. ０ The impedance Z for the fundamental wave when it is 1 GHz. Ｌ This indicates.

[0081] Line 243 represents the impedance Z for the second harmonic. Ｌ This shows that point 244 is the frequency f of the fundamental wave. ０ If it is 1 GHz (frequency 2f ０ The impedance Z for the second harmonic (in the case of 2 GHz) Ｌ This indicates.

[0082] Line 245 represents the impedance Z for the third harmonic. Ｌ This shows that point 246 is the fundamental frequency f. ０ If it is 1 GHz (frequency 3f ０ The impedance Z for the third harmonic (in the case of 3 GHz) Ｌ This indicates.

[0083] Figure 8 is a Smith chart that shows only line 241 and point 242 (fundamental wave) from Figure 7.

[0084] Figure 9 is a Smith chart that shows only line 243 and point 244 (second harmonic) from Figure 7.

[0085] Figure 10 is a Smith chart that shows only line 245 and point 246 (third harmonic) from Figure 7.

[0086] As shown at point 242 in Figures 7 and 8, the fundamental frequency f ０When it is 1 GHz, the impedance Z relative to the fundamental wave is Ｌ It is approximately 5 ohms.

[0087] As shown at point 244 in Figures 7 and 9, the fundamental frequency f ０ When the frequency is 1 GHz, the impedance Z for the second harmonic is Ｌ It leans towards high impedance.

[0088] As shown at point 246 in Figures 7 and 10, the fundamental frequency f ０ When the frequency is 1 GHz, the impedance Z for the third harmonic is Ｌ It leans towards low impedance.

[0089] In summary, the differential amplifier circuit 1A, at low to medium output power, exhibits high impedance to the second harmonic and low impedance to the third harmonic when the fundamental frequency is 1 GHz, thus becoming an amplifier similar to an inverse Class F amplifier.

[0090] (Circuit simulation results of impedance at high output power of differential amplifier circuit) As described in the first embodiment, at high output power, switches 14 and 16 are in the off (non-conductive) state. The impedance Z when viewed from the output terminal of amplifier 11 to the subsequent circuit at this time is Ｌ This was determined by circuit simulation.

[0091] Figures 11 to 14 show the circuit simulation results of the differential amplifier circuit of the second embodiment at high output power. In this circuit simulation, the fundamental frequency f of the high-frequency signal RF is used. ０ The frequency was varied from 100 MHz to 5 GHz.

[0092] Figure 11 shows the impedance Z for the fundamental wave, second harmonic, and third harmonic at high power output. Ｌ This is a Smith chart showing [something].

[0093] In Figure 11, line 251 represents the impedance Z for the fundamental wave. Ｌ This shows that point 252 is the frequency f of the fundamental wave. ０ The impedance Z for the fundamental wave when it is 1 GHz.Ｌ This indicates.

[0094] Line 253 represents the impedance Z for the second harmonic. Ｌ This shows that point 254 is the frequency f of the fundamental wave. ０ If it is 1 GHz (frequency 2f ０ The impedance Z for the second harmonic (in the case of 2 GHz) Ｌ This indicates.

[0095] Line 255 represents the impedance Z for the third harmonic. Ｌ This shows that point 256 is the frequency f of the fundamental wave. ０ If it is 1 GHz (frequency 3f ０ The impedance Z for the third harmonic (in the case of 3 GHz) Ｌ This indicates.

[0096] Figure 12 is a Smith chart that shows only line 251 and point 252 (fundamental wave) from Figure 11.

[0097] Figure 13 is a Smith chart that shows only line 253 and point 254 (second harmonic) from Figure 11.

[0098] Figure 14 is a Smith chart that shows only line 255 and point 256 (third harmonic) from Figure 11.

[0099] As shown at point 252 in Figures 11 and 12, the fundamental frequency f ０ When it is 1 GHz, the impedance Z relative to the fundamental wave is Ｌ It is closer to 5Ω.

[0100] As shown at point 254 in Figures 11 and 13, the fundamental frequency f ０ When the frequency is 1 GHz, the impedance Z for the second harmonic is Ｌ It leans towards low impedance.

[0101] As shown at point 256 in Figures 11 and 14, the fundamental frequency f ０ When the frequency is 1 GHz, the impedance Z for the third harmonic is Ｌ It leans towards high impedance.

[0102] In summary, the differential amplifier circuit 1A, at high output power, exhibits low impedance to the second harmonic and high impedance to the third harmonic when the frequency of the high-frequency signal RF is 1 GHz, thus becoming an amplifier similar to a Class F amplifier.

[0103] (Circuit simulation results of the output voltage of the differential amplifier circuit) Figures 15 to 17 show the circuit simulation results of the output voltage of the differential amplifier circuit of the second embodiment. In this circuit simulation, the power of the high-frequency signal RF1 was increased from -10 dBm to 10 dBm in 1 dBm increments.

[0104] Figure 15 shows the time-domain waveform of the high-frequency signal RFout from the differential amplifier circuit 1A.

[0105] In Figure 15, line 261 shows the voltage of the high-frequency signal RFout when switches 14 and 16 are in the ON (conducting) state.

[0106] Line 262 shows the voltage of the high-frequency signal RFout when switches 14 and 16 are in the off (non-conductive) state.

[0107] Figure 16 is a diagram that shows only line 261 in Figure 15 (when switch 14 and switch 16 are in the ON (conductive) state).

[0108] Figure 17 is a diagram that shows only line 262 in Figure 15 (when switches 14 and 16 are in the off (non-conductive) state).

[0109] As shown by arrow 263 in Figure 15, the peak voltage of the high-frequency signal RFout when switches 14 and 16 are in the off (non-conductive) state is lower than the peak voltage of the high-frequency signal RFout when switches 14 and 16 are in the on (conductive) state.

[0110] Thus, the differential amplifier circuit 1A can suppress the peak voltage of the high-frequency signal RFout when switches 14 and 16 are off (non-conductive), compared to when switches 14 and 16 are on (conductive).

[0111] Therefore, the differential amplifier circuit 1A can suppress the possibility of damage to amplifiers 11 and 12 when switches 14 and 16 are in the off (non-conductive) state.

[0112] (Circuit simulation results of the output current of the differential amplifier circuit) Figures 18 to 20 show the circuit simulation results of the output current of the differential amplifier circuit of the second embodiment. In this circuit simulation, the power of the high-frequency signal RF1 was increased from -10 dBm to 10 dBm in 1 dBm increments.

[0113] Figure 18 shows the time-domain waveform of the current of the high-frequency signal RFout from the differential amplifier circuit 1A.

[0114] In Figure 18, line 271 shows the current of the high-frequency signal RFout when switches 14 and 16 are in the ON (conducting) state.

[0115] Line 272 shows the current of the high-frequency signal RFout when switches 14 and 16 are in the off (non-conductive) state.

[0116] Figure 19 is a diagram that shows only line 271 in Figure 18 (when switches 14 and 16 are in the ON (conductive) state).

[0117] Figure 20 is a diagram that shows only line 272 in Figure 18 (when switches 14 and 16 are in the off (non-conductive) state).

[0118] As shown in Figure 18, the peak current of the high-frequency signal RFout when switches 14 and 16 are in the off (non-conductive) state is approximately the same as the peak current of the high-frequency signal RFout when switches 14 and 16 are in the on (conductive) state.

[0119] (Circuit simulation results of output voltage and output current of differential amplifier circuit) Figures 21 to 23 show the circuit simulation results of the output voltage and output current of the differential amplifier circuit of the second embodiment. In this circuit simulation, the power of the high-frequency signal RF1 was increased from -10 dBm to 10 dBm in 1 dBm increments.

[0120] Figure 21 shows a Lissajous curve representing the relationship between the voltage and current of the high-frequency signal RFout of the differential amplifier circuit 1A.

[0121] In Figure 21, line 281 shows a Lissajous curve representing the relationship between the voltage and current of the high-frequency signal RFout when switches 14 and 16 are in the ON (conducting) state.

[0122] Line 282 shows a Lissajous curve representing the relationship between the voltage and current of the high-frequency signal RFout when switches 14 and 16 are in the off (non-conductive) state.

[0123] Figure 22 is a diagram that shows only line 281 in Figure 21 (when switches 14 and 16 are in the ON (conductive) state).

[0124] Figure 23 is a diagram that shows only line 282 in Figure 21 (when switches 14 and 16 are in the off (non-conductive) state).

[0125] As indicated by arrow 283 in Figure 21, the peak voltage of the high-frequency signal RFout when switches 14 and 16 are in the off (non-conductive) state is lower than the peak voltage of the high-frequency signal RFout when switches 14 and 16 are in the on (conductive) state.

[0126] Thus, the differential amplifier circuit 1A can suppress the peak voltage of the high-frequency signal RFout when switches 14 and 16 are off (non-conductive), compared to when switches 14 and 16 are on (conductive).

[0127] Therefore, the differential amplifier circuit 1A can suppress the possibility of damage to amplifiers 11 and 12 when switches 14 and 16 are in the off (non-conductive) state.

[0128] (Effect) (1) Capacitor 18 is always electrically connected between a point 13a0 of the first winding 13a and the reference potential.

[0129] This results in the impedance Z for the second harmonic when switches 14 and 16 are in the off (non-conductive) state (similar to a Class F amplifier). ＬThis makes it easier to shift the impedance towards the low impedance side, even if the inductance of the first winding 13a is small.

[0130] Therefore, the differential amplifier circuit 1A can easily improve the characteristics when switches 14 and 16 are in the off (non-conductive) state (similar to a Class F amplifier).

[0131] (2) When switches 14 and 16 are in the off (non-conducting) state (similar to a Class F amplifier), the peak voltage of the high-frequency signal RFout is lower than the peak voltage of the high-frequency signal RFout when switches 14 and 16 are in the on (conducting) state (similar to an inverse Class F amplifier).

[0132] Thus, the differential amplifier circuit 1A can suppress the peak voltage of the high-frequency signal RFout compared to the case where switches 14 and 16 are on (conducting) (similar to an inverse Class F amplifier) ​​when switches 14 and 16 are off (non-conducting) (similar to an inverse Class F amplifier).

[0133] Therefore, the differential amplifier circuit 1A can suppress the possibility of damage to amplifiers 11 and 12 when switches 14 and 16 are in the off (non-conductive) state (similar to a Class F amplifier).

[0134] In this embodiment, only an example has been given in which the amplifier functions as an inverse Class F amplifier at low to medium output power and as a Class F amplifier at high output power, but the disclosure is not limited thereto. The differential amplifier circuit of the second embodiment may be configured to function as a Class F amplifier at low to medium output power and as an inverse Class F amplifier at high output power.

[0135] (3) As described above, the differential amplifier circuit 1A can switch characteristics other than the second harmonic.

[0136] <Third Embodiment> (Circuit Configuration) Among the components of the differential amplifier circuit 1B of the third embodiment, components that are the same as those of the differential amplifier circuit 1 of the first embodiment or the differential amplifier circuit 1A of the second embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0137] Figure 24 shows the configuration of a differential amplifier circuit according to the third embodiment.

[0138] Compared to differential amplifier circuit 1, differential amplifier circuit 1B includes a switch 19, a capacitor 20, an inductor 21, a switch 22, a capacitor 23, and an inductor 24, instead of the switch 16 and capacitor 17.

[0139] Each element may be an SMD (Small Microdistributed Metal) or may be formed within a semiconductor device. Inductors 21 and 24 may be SMDs or may be formed as wiring patterns on a substrate (for example, a printed circuit board (PWB)).

[0140] Switch 19 corresponds to an example of the “fifth switch” of this disclosure. Capacitor 20 corresponds to an example of the “fifth capacitor” of this disclosure. Inductor 21 corresponds to an example of the “fourth inductor” of this disclosure. Switch 22 corresponds to an example of the “sixth switch” of this disclosure. Capacitor 23 corresponds to an example of the “sixth capacitor” of this disclosure. Inductor 24 corresponds to an example of the “fifth inductor” of this disclosure.

[0141] One end of switch 19 is electrically connected to the output terminal of amplifier 11. The other end of switch 19 is electrically connected to one end of capacitor 20. The other end of capacitor 20 is electrically connected to one end of inductor 21. The other end of inductor 21 is electrically connected to a reference potential.

[0142] In other words, the capacitor 20 and the inductor 21 are connected in series.

[0143] The resonant frequency of the series-connected capacitor 20 and inductor 21 is 3f, which is the frequency of the third harmonic of the high-frequency signal RF. ０ An example of how it should be set is given.

[0144] Alternatively, one end of the inductor 21 may be electrically connected to the other end of the switch 19, the other end of the inductor 21 may be electrically connected to one end of the capacitor 20, and the other end of the capacitor 20 may be electrically connected to a reference potential.

[0145] Switch 19 connects or disconnects the capacitor 20 and inductor 21, which are connected in series, between the output terminal of the amplifier 11 and the reference potential.

[0146] Switch 19 is turned ON (conducts) when the output power is low to medium. As a result, the series-connected capacitor 20 and inductor 21 are connected between the output terminal of the amplifier 11 and the reference potential.

[0147] Switch 19 is turned off (non-conductive) when high output power is applied. As a result, the series-connected capacitor 20 and inductor 21 are disconnected from the output terminal of the amplifier 11 and the reference potential.

[0148] One end of switch 22 is electrically connected to the output terminal of amplifier 12. The other end of switch 22 is electrically connected to one end of capacitor 23. The other end of capacitor 23 is electrically connected to one end of inductor 24. The other end of inductor 24 is electrically connected to a reference potential.

[0149] In other words, the capacitor 23 and the inductor 24 are connected in series.

[0150] The resonant frequency of the series-connected capacitor 23 and inductor 24 is 3f, which is the frequency of the third harmonic of the high-frequency signal RF. ０ An example of how it should be set is given.

[0151] Alternatively, one end of the inductor 24 may be electrically connected to the other end of the switch 22, the other end of the inductor 24 may be electrically connected to one end of the capacitor 23, and the other end of the capacitor 23 may be electrically connected to a reference potential.

[0152] Switch 22 connects or disconnects the capacitor 23 and inductor 24, which are connected in series, between the output terminal of the amplifier 12 and the reference potential.

[0153] Switch 22 is turned ON (conducts) when the output power is low to medium. As a result, the series-connected capacitor 23 and inductor 24 are connected between the output terminal of amplifier 12 and the reference potential.

[0154] Switch 22 is turned off (non-conductive) when high output power is applied. As a result, the series-connected capacitor 23 and inductor 24 are disconnected from the output terminal of amplifier 12 and the reference potential.

[0155] At low to medium output power, the series-connected capacitor 20 and inductor 21 have an impedance Z to the third harmonic. Ｌ This relates to the impedance Z of the third harmonic of the series-connected capacitor 23 and inductor 24. Ｌ It is related to that.

[0156] (Effect) In differential amplifier circuit 1B, at low to medium output power (similar to an inverse Class F amplifier), the series-connected capacitor 20 and inductor 21 are electrically connected between the output terminal of amplifier 11 and the reference potential. In addition, in differential amplifier circuit 1B, the series-connected capacitor 23 and inductor 24 are electrically connected between the output terminal of amplifier 12 and the reference potential.

[0157] As a result, the differential amplifier circuit 1B, at low to medium output power (similar to an inverse class F amplifier), has an impedance Z for the third harmonic. Ｌ This makes it easier to lower the impedance. Therefore, the differential amplifier circuit 1B can be made easier to improve the characteristics at low to medium output power (similar to an inverse Class F amplifier).

[0158] As described above, the differential amplifier circuit 1B can switch characteristics other than the second harmonic.

[0159] (Modification) The third embodiment and the second embodiment may be combined. That is, the differential amplifier circuit 1B may include a capacitor 18 (see Figure 6).

[0160] In this embodiment, only an example has been given in which the amplifier functions as an inverse Class F amplifier at low to medium output power and as a Class F amplifier at high output power, but the disclosure is not limited thereto. The differential amplifier circuit of the third embodiment may be configured to function as a Class F amplifier at low to medium output power and as an inverse Class F amplifier at high output power.

[0161] <Fourth Embodiment> (Circuit Configuration) Among the components of the differential amplifier circuit 1C of the fourth embodiment, components that are the same as those of the differential amplifier circuit 1 of the first embodiment, the differential amplifier circuit 1A of the second embodiment, or the differential amplifier circuit 1B of the third embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0162] Figure 25 shows the configuration of the differential amplifier circuit according to the fourth embodiment.

[0163] The differential amplifier circuit 1C, compared to the differential amplifier circuit 1, includes switches 14-1, 14-2, ..., 14-N (where N is a natural number) and capacitors 15-1, 15-2, ..., 15-N, instead of switches 14 and capacitors 15.

[0164] The capacitances of capacitors 15-1, 15-2, ..., and 15-N may be the same or different.

[0165] Switches 14-1, 14-2, ..., 14-N correspond to examples of "one or more first switches" in this disclosure. Capacitors 15-1, 15-2, ..., 15-N correspond to examples of "one or more first capacitors" in this disclosure.

[0166] The connection relationships between point 13a0, switch 14-1, and capacitor 15-1, between point 13a0, switch 14-2, and capacitor 15-2, and between point 13a0, switch 14-N, and capacitor 15-N are the same as the connection relationship between point 13a0, switch 14, and capacitor 15, so their explanation is omitted.

[0167] At low to medium output power, at least one of switches 14-1, 14-2, ..., 14-N is turned ON (conducting). As a result, at least one of capacitors 15-1, 15-2, ..., 15-N is connected to the space between point 13a0 and the reference potential.

[0168] Furthermore, at high power output, at least one of switches 14-1, 14-2, ..., 14-N is turned ON (conductive). As a result, at least one of capacitors 15-1, 15-2, ..., 15-N is connected to the space between point 13a0 and the reference potential.

[0169] The capacitance between point 13a0 and the reference potential is the sum of the capacitances of the capacitors connected between point 13a0 and the reference potential, among capacitors 15-1, 15-2, ..., 15-N.

[0170] In other words, the capacitance electrically connected between a point 13a0 of the first winding 13a and the reference potential is determined by which switches 14-1, 14-2, ..., 14-N are turned on (conducted) and how many of them are turned on.

[0171] The number of switches 14-1, 14-2, ..., 14-N that are turned on (conducted) is determined by the frequency of the second harmonic, 2f. ０ It is exemplified that the capacitance between point 13a0 of the first winding 13a and the reference potential is set such that the second harmonic can be passed through or blocked between point 13a0 and the reference potential.

[0172] At low to medium power and at high power, the impedance Z of the second harmonic between the first part 13a1 and a capacitor electrically connected to one point 13a0 among capacitors 15-1, 15-2, ..., 15-N is ＬThis relates to the second part 13a2 and the capacitor electrically connected to one point 13a0 among capacitors 15-1, 15-2, ..., 15-N, which has an impedance Z for the second harmonic. Ｌ It is related to that.

[0173] (Effect) The differential amplifier circuit 1C can change the capacitance between point 13a0 and the reference potential when the output power is high (similar to a Class F amplifier). For example, the differential amplifier circuit 1C can change the capacitance between point 13a0 and the reference potential so that the second harmonic of the high-frequency signal RF can pass through. As a result, the differential amplifier circuit 1C can change the impedance Z when the output power is high (similar to a Class F amplifier). Ｌ The frequency of the second harmonic that results in low impedance is 2f ０ It can be changed.

[0174] Therefore, the differential amplifier circuit 1C can achieve a wide bandwidth when using high output power (similar to a Class F amplifier).

[0175] As described above, the differential amplifier circuit 1C can switch characteristics other than the second harmonic.

[0176] (Modification) The fourth embodiment and the second embodiment may be combined. That is, the differential amplifier circuit 1C may include a capacitor 18 (see Figure 6).

[0177] In this embodiment, only an example has been given in which the amplifier functions as an inverse Class F amplifier at low to medium output power and as a Class F amplifier at high output power, but the disclosure is not limited thereto. The differential amplifier circuit of the fourth embodiment may be configured to function as a Class F amplifier at low to medium output power and as an inverse Class F amplifier at high output power.

[0178] <Fifth Embodiment> (Circuit Configuration) Among the components of the differential amplifier circuit 1D of the fifth embodiment, components that are the same as those of the differential amplifier circuit 1 of the first embodiment, the differential amplifier circuit 1A of the second embodiment, the differential amplifier circuit 1B of the third embodiment, or the differential amplifier circuit 1C of the fourth embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0179] Figure 26 shows the configuration of a differential amplifier circuit according to the fifth embodiment.

[0180] The differential amplifier circuit 1D, compared to the differential amplifier circuit 1, includes switches 16-1, 16-2, ..., 16-M (where M is a natural number) and capacitors 17-1, 17-2, ..., 17-M, instead of switches 16 and capacitors 17.

[0181] The capacitances of capacitors 17-1, 17-2, ..., and 17-M may be the same or different.

[0182] Switches 16-1, 16-2, ..., and 16-M correspond to examples of "one or more second switches" in this disclosure. Capacitors 17-1, 17-2, ..., and 17-M correspond to examples of "one or more second capacitors" in this disclosure.

[0183] The connection relationships between amplifier 11, switch 16-1, capacitor 17-1, and amplifier 12, the connection relationships between amplifier 11, switch 16-2, capacitor 17-2, and amplifier 12, and the connection relationships between amplifier 11, switch 16-M, capacitor 17-M, and amplifier 12 are the same as the connection relationships between amplifier 11, switch 16, capacitor 17, and amplifier 12, so their explanation is omitted.

[0184] At low to medium output power, at least one of switches 16-1, 16-2, ..., 16-M is turned ON (conducting). As a result, at least one of capacitors 17-1, 17-2, ..., 17-M is connected to the output terminal of amplifier 11 and the output terminal of amplifier 12.

[0185] Furthermore, at high power output, at least one of switches 16-1, 16-2, ..., 16-M will be in the ON (conducting) state. As a result, at least one of capacitors 17-1, 17-2, ..., 17-M will be connected to the output terminal of amplifier 11 and the output terminal of amplifier 12.

[0186] The capacitance between the output terminal of amplifier 11 and the output terminal of amplifier 12 is the sum of the capacitances of the capacitors 17-1, 17-2, ..., 17-M that are connected between the output terminal of amplifier 11 and the output terminal of amplifier 12.

[0187] In other words, the capacitance electrically connected between the output terminals of amplifier 11 and amplifier 12 is determined by which switches 16-1, 16-2, ..., 16-M are turned on (conducted) and how many of them are turned on.

[0188] The number of switches 16-1, 16-2, ..., 16-M that are turned on (conducted) is determined by the frequency of the third harmonic, 3f. ０ It is exemplified that the capacitance between the output terminal of amplifier 11 and the output terminal of amplifier 12 is set so that the third harmonic can be passed through or not.

[0189] During low-to-medium output power and high output power, the capacitors 17-1, 17-2, ..., 17-M that are electrically connected between the output terminal of amplifier 11 and the output terminal of amplifier 12 have an impedance Z to the third harmonic. Ｌ It is related to that.

[0190] (Effect) The differential amplifier circuit 1D can change the capacitance between the output terminals of amplifier 11 and amplifier 12 when the output power is low to medium (similar to an inverse Class F amplifier). For example, the differential amplifier circuit 1D can change the capacitance between the output terminals of amplifier 11 and amplifier 12 so that the third harmonic can pass through. As a result, the differential amplifier circuit 1D can change the impedance Z when the output power is low to medium (similar to an inverse Class F amplifier). Ｌ The frequency of the third harmonic that results in low impedance is 3f ０ It can be changed.

[0191] Therefore, the differential amplifier circuit 1D can achieve a wide bandwidth at low to medium output power (similar to an inverse Class F amplifier).

[0192] As described above, the differential amplifier circuit 1D can switch characteristics other than the second harmonic.

[0193] (Modification) The fifth embodiment and the second embodiment may be combined. That is, the differential amplifier circuit 1D may include a capacitor 18 (see Figure 6).

[0194] Furthermore, the fifth embodiment and the fourth embodiment may be combined. That is, the differential amplifier circuit 1D may include switches 14-1, 14-2, ..., 14-N, capacitors 15-1, 15-2, ..., 15-N (see Figure 25).

[0195] In this embodiment, only an example has been given in which the amplifier functions as an inverse Class F amplifier at low to medium output power and as a Class F amplifier at high output power, but the disclosure is not limited thereto. The differential amplifier circuit of the fifth embodiment may be configured to function as a Class F amplifier at low to medium output power and as an inverse Class F amplifier at high output power.

[0196] <Sixth Embodiment> (Circuit Configuration) Among the components of the differential amplifier circuit 1E of the sixth embodiment, components that are the same as those of the differential amplifier circuit 1A of the second embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0197] Figure 27 shows the configuration of the differential amplifier circuit according to the sixth embodiment.

[0198] The differential amplifier circuit 1E further includes a capacitor 25 compared to the differential amplifier circuit 1A (see Figure 6).

[0199] The capacitor 25 may be an SMD (Small Microdistributed) capacitor, or it may be formed inside the semiconductor device.

[0200] Capacitor 25 corresponds to an example of the "fourth capacitor" in this disclosure.

[0201] One end of capacitor 25 is electrically connected to the output terminal of amplifier 11, one end of switch 16, and one end of the first winding 13a. The other end of capacitor 25 is electrically connected to the output terminal of amplifier 12, the other end of capacitor 17, and the other end of the first winding 13a.

[0202] In the sixth embodiment, the capacitance value of the capacitor 15 is set to be sufficiently large. The capacitance value of the capacitor 15 is exemplified as 1000 pF (picofarads), but this disclosure is not limited thereto.

[0203] In the sixth embodiment, the capacitance value of capacitor 18 is smaller than the capacitance value of capacitor 15. The capacitance value of capacitor 18 is 50 pF, but this disclosure is not limited thereto.

[0204] The differential amplifier circuit 1E is compatible with both ET (Envelope Tracking) and APT (Average Power Tracking).

[0205] Generally, the differential amplifier circuit 1E operates in ET mode at high output power and in APT mode at low output power to maximize efficiency during ET operation.

[0206] During ET operation, switch 14 is in the off state and switch 16 is in the on state.

[0207] When APT is in operation, switch 14 is in the ON state and switch 16 is in the OFF state.

[0208] By switching switches 14 and 16 on and off, the differential amplifier circuit 1E can switch between ET operation and APT operation characteristics.

[0209] (Characteristics during ET operation) During ET operation, the power supply potential Vcc changes in the envelope shape of the high-frequency signal. To prevent the change in the power supply potential Vcc from being suppressed, the capacitance value between the Vcc terminal and the reference potential needs to be small. Therefore, switch 14 is in the off state during ET operation. Switch 14 is in the on state during APT operation.

[0210] Figure 28 shows the impedance of the differential amplifier circuit in the sixth embodiment. Specifically, Figure 28 shows the impedance Z as seen from the Vcc terminal to the differential amplifier circuit 1E side. Ｌ２ This is a diagram showing the relationship between the frequency of a high-frequency signal and the given signal.

[0211] In Figure 28, line 301 represents the impedance Z during ET operation. Ｌ２ This shows the impedance Z during APT operation. Line 302 represents the impedance Z during APT operation. Ｌ２ This indicates.

[0212] As described above, during ET operation, switch 14 is in the off state. Therefore, the capacitance value between the Vcc terminal and the reference potential becomes the capacitance value of capacitor 18 (for example, 50 pF). As shown by line 301, impedance Z Ｌ２ It has high impedance below frequency Fc and low impedance above frequency Fc.

[0213] Furthermore, as described above, switch 14 is turned ON when APT is in operation. Therefore, the capacitance value between the Vcc terminal and the reference potential is the sum of the capacitance value of capacitor 15 (e.g., 1000 pF) and the capacitance value of capacitor 18 (e.g., 50 pF). As shown by line 302, impedance Z Ｌ２ It has high impedance below frequency Fd and low impedance above frequency Fd.

[0214] The frequency Fc is higher than the frequency Fd. The frequency Fc is exemplified by 1.4 GHz to 5 GHz, but the present disclosure is not limited thereto. The frequency Fd is exemplified by 100 MHz to 200 MHz, but the present disclosure is not limited thereto.

[0215] That is, the impedance Z Ｌ２ is relatively high impedance during ET operation and relatively low impedance during APT operation.

[0216] (Characteristics during APT operation) In order to increase the efficiency during APT operation, the impedance Z Ｌ during APT operation needs to be larger than the impedance Z Ｌ during ET operation. Therefore, the capacitance value between the output terminal of amplifier 11 and the output terminal of amplifier 12 needs to be (capacitance value during ET operation) > (capacitance value during APT operation). Therefore, switch 16 is in the off state during APT operation. Note that switch 16 is in the on state during ET operation.

[0217] FIG. 29 is a diagram showing the impedance of the differential amplifier circuit according to the sixth embodiment. Specifically, FIG. 29 is a diagram showing the relationship between the impedance Z Ｌ and the frequency of the high-frequency signal.

[0218] In FIG. 29, point 311 indicates the impedance Z Ｌ during ET operation. Point 312 indicates the impedance Z Ｌ during APT operation.

[0219] As described above, switch 16 is in the on state during ET operation. Therefore, the capacitance value between the output terminal of amplifier 11 and the output terminal of amplifier 12 is the sum of the capacitance values of capacitor 17 and capacitor 25. Therefore, as indicated by point 311, the impedance Z <OO00095> is relatively low impedance.

[0220] Also, as described above, during APT operation, switch 16 is in the OFF state. Therefore, the capacitance value between the output terminals of amplifier 11 and amplifier 12 becomes the capacitance value of capacitor 25. Thus, as shown at point 312, impedance Z Ｌ is relatively high impedance.

[0221] (Effect) (1) Differential amplifier circuit 1E can make impedance Z Ｌ２ relatively high impedance during ET operation compared to during APT operation. Thereby, differential amplifier circuit 1E can prevent the change in power supply potential Vcc from being suppressed, and can perform ET operation suitably.

[0222] (2) Differential amplifier circuit 1E can make impedance Z Ｌ relatively large during APT operation compared to during ET operation. Thereby, differential amplifier circuit 1E can improve the efficiency during APT operation.

[0223] (3) As described above, differential amplifier circuit 1E can switch characteristics other than the second harmonic.

[0224] (First Modified Example) FIG. 30 is a diagram showing the configuration of a first modified example of the differential amplifier circuit according to the sixth embodiment. This differential amplifier circuit 1E-1 is a circuit capable of switching the loads of amplifiers 11 and 12 according to the switching between ET operation and APT operation.

[0225] [[ID=2i]] Differential amplifier circuit 1E-1 further includes an inductor 26, and switches 27 and 28, compared to differential amplifier circuit 1E (see FIG. 29).

[0226] Inductor 26 is an example of the "third inductor" of the present disclosure. Switch 27 is an example of the "third switch" of the present disclosure. Switch 28 is an example of the "fourth switch" of the present disclosure.

[0227] One end of inductor 26 is electrically connected to one end of the second winding 13b. The other end of inductor 26 is electrically connected to one end of switch 27. The other end of switch 27 is electrically connected to terminal 1c.

[0228] One end of switch 28 is electrically connected to one end of the second winding 13b and one end of the inductor 26. The other end of switch 28 is electrically connected to the other end of switch 27 and terminal 1c.

[0229] During ET operation, switch 27 is turned ON and switch 28 is turned OFF. This connects the second winding 13b and the inductor 26 in series.

[0230] When the APT is in operation, switch 27 is in the off state and switch 28 is in the on state. As a result, inductor 26 is disconnected from the loads of amplifiers 11 and 12.

[0231] In this way, the differential amplifier circuit 1E-1 can switch the loads of amplifiers 11 and 12 in accordance with the switching between ET operation and APT operation.

[0232] As described above, the differential amplifier circuit 1E-1 can switch characteristics other than the second harmonic.

[0233] (Second Modification) Figure 31 shows the configuration of a second modification of the differential amplifier circuit of the sixth embodiment. This differential amplifier circuit 1E-2 is a circuit that enables switching of the loads of amplifiers 11 and 12 in accordance with the switching between ET operation and APT operation.

[0234] The differential amplifier circuit 1E-2 further includes an inductor 26 and a switch 27, compared to the differential amplifier circuit 1E (see Figure 29).

[0235] One end of switch 27 is electrically connected to one end of the second winding 13b and to terminal 1c. The other end of switch 27 is electrically connected to one end of inductor 26. The other end of inductor 26 is electrically connected to a reference potential.

[0236] During ET operation, switch 27 is turned off. This disconnects inductor 26 from the loads of amplifiers 11 and 12.

[0237] When the APT is in operation, switch 27 is turned ON. As a result, the second winding 13b and the inductor 26 are connected in parallel.

[0238] In this way, the differential amplifier circuit 1E-2 can switch the loads of amplifiers 11 and 12 in accordance with the switching between ET operation and APT operation.

[0239] As described above, the differential amplifier circuit 1E-2 can switch characteristics other than the second harmonic.

[0240] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. The present invention may be modified or improved without departing from its spirit, and equivalents thereof are also included.

[0241] 1, 1A, 1C, 1D, 1E, 1E-1, 1E-2 Differential amplifier circuit 11, 12 Amplifier 13 Transformer 13a First winding 13b Second winding 14, 14-1, ..., 14-N, 16, 16-1, ..., 16-M, 19, 22, 27, 28 Switch 15, 15-1, ..., 15-N, 17, 17-1, ..., 17-M, 18, 20, 23, 25 Capacitor 21, 24, 26 Inductor

Claims

1. A differential amplifier circuit comprising: a first amplifier whose input terminal is electrically connected to a first terminal to which a first phase signal of a differential signal is input; a second amplifier whose input terminal is electrically connected to a second terminal to which a second phase signal of the differential signal is input; a first inductor whose one end is connected to the output terminal of the first amplifier and whose other end is connected to the output terminal of the second amplifier; one or more first capacitors; one or more second capacitors; one or more first switches connected to a node between a point of the first inductor and a reference potential, for connecting or disconnecting each of the one or more first capacitors; and one or more second switches between the output terminal of the first amplifier and the output terminal of the second amplifier, for connecting or disconnecting each of the one or more second capacitors.

2. A differential amplifier circuit according to claim 1, further comprising a third capacitor, one end of which is connected to a point of the first inductor and the other end of which is connected to a reference potential.

3. A differential amplifier circuit according to claim 1 or 2, further comprising a second inductor which is magnetically coupled to the first inductor and has one end electrically connected to a reference potential.

4. A differential amplifier circuit according to claim 3, wherein one or more first switches connect or disconnect one or more first capacitors in accordance with the power of the high-frequency signal output from the other end of the second inductor, and one or more second switches connect or disconnect one or more second capacitors in accordance with the power of the high-frequency signal output from the other end of the second inductor, and a differential amplifier circuit.

5. A differential amplifier circuit according to claim 2, further comprising a fourth capacitor, one end of which is connected to the output terminal of the first amplifier and the other end of which is connected to the output terminal of the second amplifier.

6. A differential amplifier circuit according to claim 5, further comprising: a second inductor that is magnetically coupled with the first inductor and has one end electrically connected to a reference potential; a third inductor with one end connected to the other end of the second inductor; a third switch with one end connected to the other end of the third inductor; and a fourth switch with one end connected to the other end of the second inductor and the other end connected to the other end of the third switch.

7. A differential amplifier circuit according to claim 5, further comprising: a second inductor that is magnetically coupled with the first inductor and has one end electrically connected to a reference potential; a third switch with one end connected to the other end of the second inductor; and a third inductor with one end connected to the other end of the third switch and the other end connected to a reference potential.

8. A differential amplifier circuit comprising: a first amplifier whose input terminal is electrically connected to a first terminal to which a first phase signal of a differential signal is input; a second amplifier whose input terminal is electrically connected to a second terminal to which a second phase signal of the differential signal is input; a first inductor whose one end is connected to the output terminal of the first amplifier and whose other end is connected to the output terminal of the second amplifier; one or more first capacitors; one or more first switches connected to a node between a point of the first inductor and a reference potential, for connecting or disconnecting the one or more first capacitors, respectively; a fifth capacitor and a fourth inductor connected in series; a sixth capacitor and a fifth inductor connected in series; a fifth switch connected to a node between the output terminal of the first amplifier and a reference potential, for connecting or disconnecting the fifth capacitor and the fourth inductor; and a sixth switch connected to a node between the output terminal of the second amplifier and a reference potential, for connecting or disconnecting the sixth capacitor and the fifth inductor.

9. A differential amplifier circuit according to claim 8, further comprising a third capacitor, one end of which is connected to a point of the first inductor and the other end of which is connected to a reference potential.

10. A differential amplifier circuit according to claim 8 or 9, further comprising a second inductor which is magnetically coupled with the first inductor and has one end electrically connected to a reference potential.

11. A differential amplifier circuit according to claim 10, wherein one or more first switches connect or disconnect one or more first capacitors in accordance with the power of the high-frequency signal output from the other end of the second inductor, and one or more second switches connect or disconnect one or more second capacitors in accordance with the power of the high-frequency signal output from the other end of the second inductor.

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