Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device includes: a chip formed of a wide bandgap semiconductor, the chip having a main surface in which a semiconductor region of a first conductive type is formed; a base impurity region of a second conductive type formed in a surface layer part of the semiconductor region; a first impurity region of the first conductive type formed in a surface layer part of the base impurity region; and a second impurity region of the second conductive type formed in the surface layer part of the base impurity region, the second impurity region of the second conductive type being adjacent to the first impurity region in a first direction. The base impurity region includes an exposure part which is a region exposed to the main surface, where the exposure part extends in a belt shape in the first direction so as to cross the base impurity region in the first direction, and divides the first impurity region in a second direction orthogonal to the first direction.

Description

Semiconductor Device and Method of Manufacturing the Same Related Application

[0001] This application corresponds to Japanese Patent Application No. 2025-004941 filed with the Japan Patent Office on January 14, 2025, and the entire disclosure of this application is incorporated herein by reference.

[0002] This disclosure relates to a semiconductor device and a method of manufacturing the same.

[0003] Patent Document 1 discloses an n

[0006] -type SiC semiconductor device including a plurality of p-type body regions formed on the surface portion of an n-type SiC semiconductor layer, each of which constitutes a unit cell, an n-type source region formed inside the p-type body region, a gate electrode facing the p-type body region through a gate insulating film, an n ＋ -type drain region and a p ＋ -type collector region formed adjacent to each other on the back surface portion of the SiC semiconductor layer, and an n ＋ -type drift region between the p-type body region and the n － -type drain region.

[0004] Japanese Unexamined Patent Application Publication No. 2015-207588

[0005] [Summary] One embodiment of this disclosure provides a semiconductor device including a chip formed of a wide bandgap semiconductor and having a main surface on which a semiconductor region of a first conductivity type is formed, a base impurity region of a second conductivity type formed on the surface layer portion of the semiconductor region, a first impurity region of the first conductivity type formed on the surface layer portion of the base impurity region, and a second impurity region of the first conductivity type formed on the surface layer portion of the base impurity region and adjacent to the first impurity region in a first direction. The base impurity region may be a region exposed on the main surface, and may include an exposed portion that extends in a strip shape in the first direction so as to cross the base impurity region in the first direction and divides the first impurity region in a second direction orthogonal to the first direction.

[0006] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: preparing a wafer having a wafer main surface formed of a wide-bandgap semiconductor and having a semiconductor region of a first conductivity type formed thereon; selectively forming a plurality of body regions spaced apart in a first direction; forming a first mask that selectively covers each of the body regions; forming a first impurity region on the surface of the body regions by injecting a first conductivity type impurity into the body regions via the first mask, thereby leaving a contact pattern region consisting of a part of the body regions in the region covered by the first mask; forming a second mask having an opening that selectively exposes the contact pattern region and covering the first impurity region; forming a body contact region on the surface of the body regions by injecting a second conductivity type impurity into the contact pattern region via the second mask; and forming a gate electrode that covers a channel region formed in the region between the semiconductor region and the first impurity region on the surface of the body regions. The first mask may include a main body portion extending in a second direction perpendicular to the first direction, a first connecting portion projecting in a strip shape from the middle of the main body portion to one side in the first direction and mechanically connected to an adjacent first mask on one side of the first mask in the first direction, and a second connecting portion projecting in a strip shape from the middle of the main body portion to the other side in the first direction and mechanically connected to an adjacent first mask on the other side of the first mask in the first direction.

[0007] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface. Figure 4 is an enlarged plan view showing the main part of the first main surface. Figure 5 is an enlarged plan view showing further main parts of the first main surface. Figure 6 is an enlarged plan view showing the main part of Figure 5. Figure 7 is an enlarged view of the portion enclosed by the dashed line VII in Figure 6. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 6. Figure 10 is a cross-sectional view along the line XX shown in Figure 6. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 5. Figure 12 is a schematic diagram showing a wafer used in the manufacture of a semiconductor device. Figure 13A is a cross-sectional view showing a method for manufacturing a semiconductor device. Figure 13B is a cross-sectional view showing a process after Figure 13A. Figure 13C is a cross-sectional view showing a process after Figure 13B. Figure 13D is a cross-sectional view showing a process after Figure 13C. Figure 13E is a cross-sectional view showing a process after Figure 13D. Figure 13F is a cross-sectional view showing a process after Figure 13E. Figure 13G is a cross-sectional view showing a process after Figure 13F. Figure 13H is a cross-sectional view showing a process after Figure 13G. Figure 13I is a cross-sectional view showing a process after Figure 13H. Figure 13J is a cross-sectional view showing a process after Figure 13I. Figure 13K is a cross-sectional view showing a process after Figure 13J. Figure 13L is a cross-sectional view showing a process after Figure 13K. Figure 13M is a cross-sectional view showing a process after Figure 13L. Figure 13N is a cross-sectional view showing a process after Figure 13M. Figure 13O is a cross-sectional view showing a process after Figure 13N. Figure 13P is a cross-sectional view showing a process after Figure 13O. Figure 14 is a diagram showing the planar pattern of the first mask shown in Figure 13G. Figure 15 is a cross-sectional view along the line XV-XV shown in Figure 14. Figure 16 is a diagram showing the planar pattern of the second mask shown in Figure 13I. Figure 17 is a diagram showing a first modified example of the layout example of the first main surface, and corresponds to Figure 6. Figure 18 is a diagram showing a second modified example of the layout example of the first main surface, and corresponds to Figure 6. Figure 19 is a plan view showing a semiconductor device according to the second embodiment of the present invention, and corresponds to Figure 7. Figure 20 is a plan view showing the planar pattern of the first mask used in the manufacture of a semiconductor device according to the second embodiment of the present invention, and corresponds to Figure 14.Figure 21 is a plan view showing a semiconductor device according to the third embodiment of the present invention, and corresponds to Figure 6. Figure 22 is a plan view showing the planar pattern of a first mask used in the manufacture of a semiconductor device according to the third embodiment of the present invention, and corresponds to Figure 14.

[0008] [Detailed Description] The embodiments will be described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily correspond. Corresponding structures in the attached drawings are given the same reference numerals, and redundant descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description given before the omission or simplification applies.

[0009] Where the word "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are equal to the numerical values ​​(forms) being compared, but also numerical errors (form errors) within a range of ±10% from the numerical values ​​(forms) being compared. In the following descriptions, words such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0010] In the following explanation, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "p-type" is a conductivity type caused by trivalent elements, and "n-type" is a conductivity type caused by pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] Figure 1 is a plan view showing a semiconductor device 1 according to an embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example layout of the first main surface 3. Figure 4 is an enlarged plan view showing the main part of the first main surface 3. Figure 5 is an enlarged plan view showing further main parts of the first main surface 3.

[0012] Figure 6 is an enlarged plan view showing the main part of Figure 5. Figure 7 is an enlarged view of the area enclosed by the dashed line VII in Figure 6. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 6. Figure 10 is a cross-sectional view along the line XX shown in Figure 6. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 5.

[0013] Referring to Figures 1 to 3, semiconductor device 1 is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1 is a SiC semiconductor device having a chip 2 containing a SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip".

[0014] In this embodiment, chip 2 is made of a hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystals include multiple polytypes, such as 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 is made of a 4H-SiC single crystal, but chip 2 may be made of other polytypes.

[0015] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0016] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0017] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0018] In the following description, one side of the first direction X means the third side surface 5C, and the other side of the first direction X means the fourth side surface 5D. Also, one side of the second direction Y means the first side surface 5A, and the other side of the second direction Y means the second side surface 5B. In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Alternatively, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereafter, the direction extending along the first principal surface 3 may be expressed as the "horizontal direction". The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z. The XY plane containing the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. In the following, the axis extending along the vertical direction Z is sometimes referred to as the "vertical axis."

[0019] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is tilted at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is tilted by the off-angle from the vertical axis in the off-direction. Also, the c-plane of the SiC single crystal is tilted by the off-angle with respect to the horizontal plane.

[0020] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle is preferably 5° or less.

[0021] The first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 20 mm or less in a plan view. The length of the first to fourth sides 5A to 5D may be a value that falls within one of the following ranges: 0.5 mm or more and 1 mm or less, 1 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The length of the first to fourth sides 5A to 5D may be 5 mm or more.

[0022] Referring to Figure 2, the semiconductor device 1 includes an n-type first semiconductor region (semiconductor region) 6 formed in the region (surface layer) on the first main surface 3 side within the chip 2. The first semiconductor region 6 may also be called a "drift region," "drain drift region," "drain region," etc. A drain potential as a high potential (first potential) is applied to the first semiconductor region 6. The first semiconductor region 6 is formed in a layered manner extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 consists of an epitaxial layer (specifically, a SiC epitaxial layer).

[0023] Referring to Figure 2, the semiconductor device 1 includes an n-type second semiconductor region 7 formed in the region (surface layer) on the second main surface 4 side within the chip 2. A drain potential is applied to the second semiconductor region 7. The second semiconductor region 7 may also be referred to as the "drain region". The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6 within the chip 2.

[0024] The second semiconductor region 7 is formed in a layered manner extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 consists of a semiconductor substrate (specifically, a SiC substrate). In other words, the chip 2 has a stacked structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 has a thickness greater than the thickness of the first semiconductor region 6.

[0025] Referring to Figures 1 to 5, the semiconductor device 1 includes an active region 8 set on the chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. In a plan view, the active region 8 is set in the inner part of the chip 2, spaced apart from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). In a plan view, the active region 8 is set as a polygon (a quadrilateral in this form) having four sides parallel to the periphery of the chip 2. Preferably, the planar area of ​​the active region 8 is 50% to 90% of the planar area of ​​the first main surface 3.

[0026] Referring to Figures 1 to 5, the semiconductor device 1 includes an outer peripheral region 9 set outside the active region 8 on the chip 2. The outer peripheral region 9 is located in the area between the periphery of the chip 2 and the active region 8 in a plan view. In a plan view, the outer peripheral region 9 extends in a band shape along the active region 8 and is set in a polygonal ring (a quadrilateral ring in this embodiment) surrounding the active region 8.

[0027] Referring to Figures 2 to 5, the semiconductor device 1 includes a plurality of p-type body regions (base impurity regions) 20 formed on the surface layer of the first main surface 3 in the active region 8. The plurality of body regions 20 are assigned a source potential as a low potential (second potential) different from a high potential (first potential). The plurality of body regions 20 are arranged with spacing in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of body regions 20 are arranged in a stripe shape extending in the second direction Y.

[0028] Referring to Figures 6 and 7, the body region 20 has a width W2 in the first direction X. The width W2 of the body region 20 may be 1 μm or more and 5 μm or less. Preferably, the width W2 of the body region 20 is 1.5 μm or more and 4 μm or less. An example of the width W2 of the body region 20 is about 2 μm.

[0029] Referring to Figure 6, the spacing W3 between adjacent body regions 20 is narrower than the width W2 of the body region 20. The spacing W3 may be between 0.5 μm and 2 μm. An example of a spacing W3 is approximately 1 μm.

[0030] Referring to Figure 2, the multiple body regions 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 with a portion of the first semiconductor region 6 in between. Preferably, the multiple body regions 20 are formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3. The multiple body regions 20 are exposed from the first main surface 3.

[0031] Referring to Figure 6, the pitch P1 (cell pitch) of the multiple body regions 20 in the first direction may be between 2 μm and 4 μm. An example of a pitch P1 is approximately 3 μm.

[0032] Referring to Figures 2 to 5, the semiconductor device 1 includes a p-type outer body region 21 formed on the surface layer of the first main surface 3 in the outer peripheral region 9. Preferably, the outer body region 21 has a p-type impurity concentration that is approximately equal to that of the body region 20. Of course, the p-type impurity concentration of the outer body region 21 may be less than the p-type impurity concentration of the body region 20, or it may be higher than the p-type impurity concentration of the body region 20.

[0033] The outer body region 21 is formed at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the active region 8, and extends in a band shape along the active region 8. In a plan view, the outer body region 21 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y, and divides the active region 8 from multiple directions.

[0034] In this embodiment, the outer body region 21 surrounds the active region 8 in a plan view and is divided into a polygonal ring (a quadrangular ring in this embodiment) with four sides parallel to the periphery of the first main surface 3. In other words, the outer body region 21 forms the boundary between the active region 8 and the outer peripheral region 9. The outer body region 21 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape) in a plan view (Figure 4).

[0035] The outer body region 21 has an inner edge on the active region 8 side and an outer edge on the peripheral edge side of the first main surface 3. The inner edge of the outer body region 21 is connected to a plurality of body regions 20 in the portion extending in the first direction X. As a result, the outer body region 21 is fixed at the same potential as the plurality of body regions 20.

[0036] The outer body region 21 preferably has a width greater than the width (width W2) of the body region 20. The width of the outer body region 21 is the width in the direction perpendicular to the extending direction. Of course, the width of the outer body region 21 may be approximately equal to the width of the body region 20, or it may be less than the thickness of the body region 20.

[0037] The ratio of the width of the outer body region 21 to the width of the body region 20 may be between 10 and 50. Preferably, the width ratio is between 20 and 40.

[0038] The outer body region 21 is formed with a gap from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 with a portion of the first semiconductor region 6 in between. Preferably, the outer body region 21 is formed with a gap from the middle of the first semiconductor region 6 toward the first main surface 3. The outer body region 21 is exposed from the first main surface 3.

[0039] Preferably, the outer body region 21 has a thickness (depth) approximately equal to the thickness (depth) of the body region 20. Of course, the thickness of the outer body region 21 may be less than the thickness of the body region 20, or it may be greater than the thickness of the body region 20.

[0040] Referring to Figures 6 to 10, the semiconductor device 1 includes a plurality of n-type surface drift regions 22 formed on the surface of the first main surface 3. In this embodiment, each of the plurality of surface drift regions 22 consists of a part of the first semiconductor region 6. Of course, the plurality of surface drift regions 22 may have an n-type impurity concentration higher than that of the first semiconductor region 6, or they may have an n-type impurity concentration lower than that of the first semiconductor region 6.

[0041] The plurality of surface drift regions 22 are respectively partitioned in the regions between the plurality of body regions 20 adjacent to each other in the first direction X. Specifically, the plurality of surface drift regions 22 are respectively partitioned by the plurality of body regions 20 and the outer body region 21 in the surface portion of the first main surface 3. The plurality of surface drift regions 22 are arranged at intervals in the first direction X and are respectively formed in a strip shape extending in the second direction Y. That is, the plurality of surface drift regions 22 are formed in a stripe shape extending in the second direction Y.

[0042] The semiconductor device 1 includes n-type source regions (first impurity regions) 23 respectively formed in the surface portions of the plurality of body regions 20. The source region 23 has an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6. A source potential is applied to the source region 23.

[0043] The semiconductor device 1 includes a plurality of p-type body contact regions (second impurity regions) 25 respectively formed in the surface portions of the plurality of body regions 2 in the active region 8. The body contact region 25 may be referred to as a "back gate region". A source potential is applied to the plurality of body contact regions 25. The body contact region 25 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.

[0044] Referring to FIGS. 5 to 7, each body region 20 alternately has a plurality of first sections 10 and a plurality of second sections 11 in the second direction Y. A clear boundary may not be formed between the first section 10 and the second section 11. In FIGS. 5 to 7, for clarity, the boundary between the first section 10 and the second section 11 is indicated by a dashed line.

[0045] Referring to FIG. 6, in this embodiment, the first length L1 of the first section 10 in the second direction Y and the second length L2 of the second section 11 in the second direction Y are the same (substantially the same) as each other. Specifically, in the example of FIG. 6, the length ratio of the first length L1 to the second length L2 may be 1.0 or more and 1.05 or less.

[0046] In this configuration, both the first length L1 and the second length L2 are longer than the pitch P1 (cell pitch) of the multiple body regions 20 in the first direction. The ratio of the first length L1 to the pitch P1 may be greater than 1 and less than or equal to 2.

[0047] Multiple body contact regions 25 are arranged with spacing between each first section 10 so as to skip each second section 11 in the second direction Y. In the body region 20, the body contact regions 25 and the regions on both sides of the body contact regions 25 in the first direction X may be the first section 10. The second section 11 may be the region between multiple adjacent body contact regions 25 in the second direction Y.

[0048] Each body contact region 25 extends in a strip shape along the extending direction (second direction Y) of the body region 20. The body contact region 25 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the body contact region 25 is not formed in the outer body region 21. The body contact region 25 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the body region 20. Each body contact region 25 is formed at a distance from both the periphery on one side and the other side of the body region 20 in the first direction X. In this embodiment, the body contact region 25 is formed in the center of the body region 20 in the first direction X.

[0049] The body contact region 25 has a width W5 in the first direction X. As shown in Figure 7, in this embodiment, the width W5 of the body contact region 25 in the first direction X is narrower than the distance W4 between adjacent gate electrodes 32 (described later) and wider than the opening width W1 (described later) (W1 < W5 < W4). The width W5 may be the same as the opening width W1, or it may be narrower than the opening width W1. The width W5 of the body contact region 25 may be constant or approximately constant in the second direction Y.

[0050] The width W5 may be between 0.2 μm and 1 μm. The width W5 may be between 0.4 μm and 0.8 μm. An example of a width W5 is approximately 0.6 μm.

[0051] The body contact region 25 crosses the first section 10 of the body region 20 in the second direction Y and has its end at the boundary position between the first section 10 and the second section 11.

[0052] The formation of the body contact region 25 separates the source region 23 into multiple source regions 24A and 24B in the first section 10. In other words, one body contact region 25 is interposed in the region between the first source region 24A and the second source region 24B in the surface layer of the corresponding body region 20. Each body contact region 25 is sandwiched between the first source region 24A and the second source region 24B in the first direction X.

[0053] The multiple source regions 24A and 24B include a first source region 24A located on one side in the first direction X and a second source region 24B located on the other side in the first direction X in the surface layer of each body region 20. In this embodiment, with respect to the first direction X, one first source region 24A is formed on one end side of the body region 20 and one second source region 24B is formed on the other end side of the body region 20.

[0054] The first source region 24A is formed at a distance from one end to the other of the body region 20 and extends in a strip shape along the extending direction of the body region 20. The first source region 24A is formed at a distance from the bottom of the body region 20 toward the first main surface 3 and faces the first semiconductor region 6 across a portion of the body region 20.

[0055] The second source region 24B is formed with a gap between it and the other end of the body region 20, extending from the other end of the body region 20. The second source region 24B is formed with a gap between it and the one end of the body region 20, extending in a strip shape along the extending direction of the body region 20. The second source region 24B is formed with a gap between it and the first main surface 3, extending from the bottom of the body region 20, and faces the first semiconductor region 6 across a portion of the body region 20.

[0056] Referring to Figures 6 and 7, the body region 20 includes an exposed portion 12 that is exposed to the first main surface 3 in the first section 10. The exposed portion 12 crosses the body region 20 (first section 10) in the first direction X. The exposed portion 12 is formed as a strip extending in the first direction X. The exposed portion 12 divides the source region 23 in the second direction Y.

[0057] The exposed portion 12 includes a first exposed portion 13 that divides the first source region 24A of the source region 23 in the second direction Y, and a second exposed portion 14 that divides the second source region 24B of the source region 23 in the second direction Y. The first exposed portion 13 is formed on one side of the body contact region 25 in the first direction X. The second exposed portion 14 is formed on the other side of the body contact region 25 in the first direction X. In other words, one exposed portion 13 and one exposed portion 14 are formed on one side and the other side of the body contact region 25 in the first direction X. In this configuration, the first exposed portion 13 and the second exposed portion 14 are located at the center of the first section 10 in the second direction Y. The first exposed portion 13 and the second exposed portion 14 face each other in the first direction X with the body contact region 25 in between.

[0058] The first exposed portion 13 may be rectangular in plan view along the first direction X. In this embodiment, the first exposed portion 13 has an exposed width W (Figure 7) in the second direction Y. The exposed width W may be less than or equal to the width W5 of the body contact region 25 in the first direction X (W ≤ W5). Preferably, the exposed width W is less than the width W5 (W < W5). In the first section 10, the first channel region 26 is not formed for a length in the second direction Y corresponding to the exposed width W of the first exposed portion 13. In order to ensure that the distance at which the first channel region 26 can be formed in the first section 10 is as long as possible, it is preferable that the exposed width W is short. The exposed width W may be the same as the width W5.

[0059] The exposure width W of the first exposed portion 13 may be constant or approximately constant in the first direction X. The exposure width W may be, for example, 0.2 μm or more and 0.6 μm or less. An example of an exposure width W is approximately 0.4 μm.

[0060] The first exposed portion 13 has a first inner end 13a and a first outer end 13b with respect to a first direction X. The first inner end 13a is aligned with one end of the body contact region 25 in the first direction X. In other words, the first inner end 13a is in contact with the body contact region 25. The first outer end 13b is aligned with one end of the body region 20 in the first direction X.

[0061] The formation of the first exposed portion 13 separates the first source region 24A into multiple source regions 15A and 15B. In other words, one first exposed portion 13 is interposed in the region between source region 15A and source region 15B on the surface of the corresponding body region 20. The first exposed portion 13 is sandwiched between source region 15A and source region 15B in the second direction Y.

[0062] The second exposed portion 14 may be rectangular in plan view along the first direction X. In this embodiment, the second exposed portion 14 has an exposed width W in the second direction Y. The exposed width W may be less than or equal to the width W5 in the first direction X of the body contact region 25 (W ≤ W5). Preferably, the exposed width W is less than the width W2 (W < W5). In the first section 10, the second channel region 27 is not formed for a length in the second direction Y corresponding to the exposed width W of the second exposed portion 14. In order to ensure that the distance at which the second channel region 27 can be formed in the first section 10 is as long as possible, it is preferable that the exposed width W is short. The exposed width W may be the same as the width W5.

[0063] The exposure width W of the second exposed portion 14 may be constant or approximately constant in the first direction X. The exposure width W may be, for example, 0.2 μm or more and 0.6 μm or less. An example of an exposure width W is approximately 0.4 μm.

[0064] The second exposed portion 14 has a second inner end 14a and a second outer end 14b with respect to the first direction X. The second inner end 14a is aligned with the other end of the body contact region 25 in the first direction X. In other words, the second inner end 14a is in contact with the body contact region 25. The second outer end 14b is aligned with the other end of the body region 20 in the first direction X.

[0065] The formation of the second exposed portion 14 separates the second source region 24B into multiple source regions 16A and 16B. In other words, one second exposed portion 14 is interposed in the region between source region 16A and source region 16B on the surface of the corresponding body region 20. The second exposed portion 14 is sandwiched between source region 16A and source region 16B in the second direction Y.

[0066] Referring to Figures 6 to 8 and Figure 10, the semiconductor device 1 includes a plurality of p-type channel regions 26, 27 formed on the surface layer of the first main surface 3. The plurality of channel regions 26, 27 are respectively partitioned in the surface layer of the plurality of body regions 20 in the regions between the ends of the plurality of body regions 20 (a plurality of surface drift regions 22) and the periphery of the source region 23. In this embodiment, the plurality of channel regions 26, 27 are arranged with spacing in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the plurality of channel regions 26, 27 are arranged in a stripe shape extending in the second direction Y.

[0067] The multiple channel regions 26, 27 include multiple first channel regions 26 and multiple second channel regions 27. The multiple first channel regions 26 are formed in the region on the side of the multiple first source region 24A and form a current path extending horizontally. The multiple second channel regions 27 are formed in the region on the side of the multiple second source region 24B and form a current path extending horizontally.

[0068] The multiple channel regions 26 and 27 are not formed in the region where the exposed portion 12 is formed with respect to the second direction Y of the first section 10. In other words, the exposed portion 12 divides the first channel region 26 and the second channel region 27 in the second direction Y within the first section 10. In yet another way, the exposed portion 12 divides the source region 24A, source region 24B and the channel regions 26 and 27 in the second direction Y within the first section 10.

[0069] Referring to Figures 5 and 8 to 10, the semiconductor device 1 includes a plurality of planar electrode-type gate structures 30 arranged on the first main surface 3 in the active region 8. The plurality of gate structures 30 are arranged at intervals in the first direction X and each is formed in a strip shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in a stripe shape extending in the second direction Y. The direction of extension of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.

[0070] Each gate structure 30 is positioned on at least one channel region 26, 27. In this embodiment, each gate structure 30 is positioned to span two adjacent body regions 20 across one surface drift region 22, and covers multiple channel regions 26, 27. Specifically, each gate structure 30 is positioned to span a source region 23 on one body region 20 side and a source region 23 on the other body region 20 side, and covers the surface drift region 22, source regions 23 (first source region 24A and second source region 24B), first channel region 26, and second channel region 27.

[0071] Referring to Figures 8 to 10, the configuration of one gate structure 30 will be described below. The gate structure 30 has a laminated structure including an insulating film 31 and a gate electrode 32. The gate structure 30 does not have an insulating sidewall structure (spacer) on the side of the gate electrode 32. The insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 includes a silicon oxide film made of the oxide of the chip 2.

[0072] The insulating film 31 covers the first main surface 3 in a film-like manner and is positioned on at least one channel region 26, 27. In this embodiment, the insulating film 31 is positioned to span two adjacent body regions 20 across one surface drift region 22 and covers multiple channel regions 26, 27.

[0073] Specifically, the insulating film 31 is arranged to span the source region 23 on one body region 20 and the source region 23 on the other body region 20, and covers the surface drift region 22, the source regions 23 (first source region 24A and second source region 24B), the first channel region 26, and the second channel region 27.

[0074] In the first section 10, the insulating film 31 partially covers the first source region 24A at a distance from the body contact region 25, exposing a portion of the first source region 24A and the body contact region 25 from the first main surface 3. In the first section 10, the insulating film 31 partially covers the second source region 24B at a distance from the body contact region 25, exposing a portion of the second source region 24B and the body contact region 25 from the first main surface 3. In the second section 11, the insulating film 31 partially covers the source region 23, exposing a portion of the source region 23 from the first main surface 3.

[0075] The thickness of the insulating film 31 may be 10 nm or more and 150 nm or less. The thickness of the insulating film 31 may be a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. Preferably, the thickness of the insulating film 31 is 25 nm or more and 75 nm or less.

[0076] The gate electrode 32 is positioned on the insulating film 31 and faces at least one channel region 26, 27 across the insulating film 31. A gate potential is applied to the gate electrode 32 as a control potential. The gate electrode 32 controls the inversion and non-inversion of at least one channel region 26, 27 in response to the gate potential.

[0077] The gate electrode 32 comprises a conductive semiconductor polycrystal. The gate electrode 32 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved. The gate electrode 32 may be referred to as a "polysilicon gate," "polygate," etc.

[0078] The gate electrode 32 is formed in a strip shape extending in the second direction Y. That is, the direction of extension of the gate electrode 32 coincides with the off-direction of the SiC single crystal. In this embodiment, the gate electrode 32 is formed with respect to the first direction X, spaced inward from both ends of the insulating film 31, exposing both ends of the insulating film 31. The gate electrode 32 is positioned on the insulating film 31 so as to span two adjacent body regions 20 across one surface drift region 22, and faces multiple channel regions 26, 27 across the insulating film 31.

[0079] Specifically, the gate electrode 32 is positioned to straddle the source region 23 on one body region 20 and the source region 23 on the other body region 20, and faces the surface drift region 22, source regions 23 (first source region 24A and second source region 24B), first channel region 26 and second channel region 27 across the insulating film 31.

[0080] The gate electrode 32 has an electrode surface 33, a first side wall 34 on one side in the first direction X, and a second side wall 35 on the other side in the first direction X. The electrode surface 33 extends along the insulating film 31 (first main surface 3). The electrode surface 33 may also extend substantially parallel to the insulating film 31 (first main surface 3).

[0081] The first side wall 34 is formed with a gap between one end and the other end of the insulating film 31 in the first direction X, and extends in the vertical direction Z. The second side wall 35 is formed with a gap between the other end and the one end of the insulating film 31 in the first direction X, and extends in the vertical direction Z.

[0082] The first side wall 34 and the second side wall 35 may extend perpendicularly to the insulating film 31. In other words, the gate electrode 32 may be formed in a square shape (flat rectangle) in cross-section. The first side wall 34 and the second side wall 35 may be inclined obliquely toward the electrode surface 33. In other words, the gate electrode 32 may be formed in a tapered shape (preferably an isosceles trapezoid shape) in cross-section.

[0083] The width of the gate structure 30 may be 1 μm or more and 10 μm or less. The width of the gate structure 30 is the width in the direction perpendicular to the extension direction (i.e., the first direction X). Preferably, the width of the gate structure 30 is 1 μm or more and 5 μm or less.

[0084] The thickness of the gate structure 30 may be 0.1 μm or more and 2.0 μm or less. Preferably, the thickness of the gate structure 30 is 0.2 μm or more and 1.0 μm or less.

[0085] The spacing W4 (Figure 7) between adjacent gate electrodes 32 may be between 0.5 μm and 1.5 μm. An example of a spacing W4 is approximately 0.8 μm.

[0086] Referring to Figures 4, 5, and 11, the semiconductor device 1 includes a p-type termination region 45 formed on the first main surface 3 in the outer peripheral region 9. The termination region 45 may also be called a "well region," "terminating well region," etc. The termination region 45 may have a p-type impurity concentration approximately equal to that of the outer body region 21. The p-type impurity concentration of the termination region 45 may be higher than or lower than that of the outer body region 21.

[0087] The terminal region 45 is formed in the region between the periphery of the first main surface 3 and the outer body region 21, with a gap inward from the periphery of the first main surface 3. In a plan view, the terminal region 45 extends in a strip shape along the outer body region 21. In a plan view, the terminal region 45 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y, and divides the active region 8 from multiple directions.

[0088] In this embodiment, the terminal region 45 surrounds the outer body region 21 in a plan view and is divided into a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The terminal region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape) in a plan view (Figure 4).

[0089] The termination region 45 is formed with a gap from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 with a part of the first semiconductor region 6 in between. Preferably, the termination region 45 is formed with a gap from the middle part of the first semiconductor region 6 toward the first main surface 3. The termination region 45 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21. The thickness of the termination region 45 may be greater than or less than the thickness of the outer body region 21.

[0090] The terminal region 45 has an inner edge on the active region 8 side and an outer edge on the peripheral edge side of the first main surface 3. The inner edge of the terminal region 45 is connected to the outer edge of the outer body region 21. As a result, the terminal region 45 is fixed at the same potential as the outer body region 21 and is electrically connected to the multiple body regions 20 via the outer body region 21. In this configuration, the inner edge of the terminal region 45 is connected to the outer edge of the outer body region 21 around its entire circumference.

[0091] The terminal region 45 (inner edge) has an overlapping region 46 that overlaps the outer edge of the outer body region 21. The overlapping region 46 is a high-concentration region that includes the outer edge of the outer body region 21 and the inner edge of the terminal region 45. In other words, the overlapping region 46 contains both p-type impurities from the outer body region 21 and p-type impurities from the terminal region 45, and has a higher p-type impurity concentration than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the terminal region 45.

[0092] The overlap region 46 extends in a band shape along the outer body region 21 in a plan view. The overlap region 46 has a portion that extends in a band shape in a first direction X and a portion that extends in a band shape in a second direction Y in a plan view, and divides the active region 8 from multiple directions. In this embodiment, the overlap region 46 is divided into a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The width of the overlap region 46 is preferably greater than the width of the body region 20. Of course, the width of the overlap region 46 may be less than or equal to the width of the body region 20.

[0093] The semiconductor device 1 may have a relatively high-concentration p-type well region (46) instead of the overlap region 46. In this case, the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45. The well region (46) may be formed on either the surface layer of the outer body region 21 or the surface layer of the termination region 45, or both.

[0094] The semiconductor device 1 includes at least one (preferably two to twenty) p-type field regions 47 formed on the surface layer of the first main surface 3 in the outer peripheral region 9. The number of field regions 47 is typically three to eight. In this embodiment, the semiconductor device 1 includes three field regions 47. The multiple field regions 47 are formed in an electrically floating state and relax the electric field within the chip 2 at the periphery of the first main surface 3. The number, spacing, width, depth, and p-type impurity concentration of the field regions 47 are arbitrary and can take various values ​​depending on the electric field to be relaxed.

[0095] The field region 47 may have a p-type impurity concentration that is approximately equal to that of the body region 20 (terminal region 45). The p-type impurity concentration of the field region 47 may be higher than that of the body region 20 (terminal region 45), or lower than that of the body region 20 (terminal region 45).

[0096] Multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the active region 8, spaced inward from the periphery of the first main surface 3. More specifically, multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the outer body region 21. More specifically, multiple field regions 47 are arranged in the region between the periphery of the first main surface 3 and the terminal region 45, spaced apart from the terminal region 45 toward the periphery of the first main surface 3.

[0097] The multiple field regions 47 are formed in a strip shape extending along the active region 8 (terminal region 45) in a plan view. Each of the multiple field regions 47 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y. In this embodiment, the multiple field regions 47 are formed in a polygonal ring (a quadrilateral ring in this embodiment) surrounding the active region 8 (terminal region 45) in a plan view. The multiple field regions 47 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape) (Figure 4).

[0098] The multiple field regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 with a portion of the first semiconductor region 6 in between. Preferably, the multiple field regions 47 are formed at intervals from the middle portion of the first semiconductor region 6 toward the first main surface 3.

[0099] Referring to Figure 11, the semiconductor device 1 includes an outer peripheral insulating film 51 that covers the first main surface 3 in the outer peripheral region 9. The outer peripheral insulating film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the outer peripheral insulating film 51 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the outer peripheral insulating film 51 includes a silicon oxide film made of the oxide of the chip 2. It is preferable that the outer peripheral insulating film 51 is made of the same insulating material as the insulating film 31. It is preferable that the outer peripheral insulating film 51 has a thickness approximately equal to the thickness of the insulating film 31.

[0100] The outer insulating film 51 coats the first main surface 3 in a film-like manner in the outer peripheral region 9. The outer insulating film 51 collectively coats the outer body region 21, the terminal region 45, and the multiple field regions 47. The outer insulating film 51 is connected to the multiple insulating films 31 on the active region 8 side. Specifically, the outer insulating film 51 is formed integrally with the multiple insulating films 31, and together with the multiple insulating films 31, forms a single insulating film.

[0101] Referring to Figures 4, 5, and 11, the semiconductor device 1 includes gate wiring 52 arranged on the first main surface 3 in the outer peripheral region 9. The semiconductor device 1 does not have an insulating sidewall structure (spacer) on the side of the gate wiring 52. The gate wiring 52 is selectively routed on the first main surface 3 and has portions that extend in different directions from the plurality of gate electrodes 32. The gate wiring 52 is connected to the plurality of gate electrodes 32 and provides gate signals to the plurality of gate electrodes 32. The gate wiring 52 may also be referred to as "polysilicon gate wiring," "polygate wiring," "second gate electrode," etc.

[0102] The gate wiring 52 contains a conductive semiconductor polycrystal. The gate wiring 52 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the gate wiring 52 has the same conductivity type as the gate electrode 32. The conductivity type of the gate wiring 52 is adjusted according to the conductivity type of the gate electrode 32.

[0103] The gate wiring 52 is positioned on the outer insulating film 51 in the outer peripheral region 9. Specifically, the gate wiring 52 is positioned on the portion of the outer insulating film 51 that covers the outer body region 21, and faces the outer body region 21 across the outer insulating film 51. The gate wiring 52 is formed with a gap from the periphery of the first main surface 3 toward the active region 8, and extends in a strip shape along the active region 8. In a plan view, the gate wiring 52 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y, and divides the active region 8 from multiple directions.

[0104] In this embodiment, the gate wiring 52 surrounds the active region 8 in a plan view and is divided into a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The gate wiring 52 may be ended or endless. In this embodiment, the gate wiring 52 extends in a strip shape (annular in this embodiment) along the outer body region 21 in a plan view and faces the outer body region 21 across the entire area in the stacking direction, with the outer peripheral insulating film 51 in between. The gate wiring 52 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape) in a plan view (Figure 4).

[0105] The gate wiring 52 is formed to be narrower than the outer body region 21 in a plan view and is positioned on the outer body region 21 at a distance from its inner and outer edges. In other words, in this configuration, the multiple gate electrodes 32 are extended over the outer body region 21, and the gate wiring 52 is connected to the multiple gate electrodes 32 on the outer body region 21.

[0106] The width of the gate wiring 52 is preferably greater than the width of the gate electrode 32. The width of the gate wiring 52 is the width in the direction perpendicular to the extending direction. Of course, the width of the gate wiring 52 may be less than or equal to the width of the gate electrode 32. The width of the gate wiring 52 may be greater than the width of the outer body region 21. The thickness of the gate wiring 52 is preferably approximately equal to the thickness of the gate electrode 32.

[0107] The gate wiring 52 has a wiring surface 53, a first wiring sidewall 54 on the inner edge side, and a second wiring sidewall 55 on the outer edge side. The wiring surface 53 extends along the outer peripheral insulating film 51 (first main surface 3). The wiring surface 53 may extend substantially parallel to the outer peripheral insulating film 51 (first main surface 3). The first wiring sidewall 54 extends vertically in the Z direction on the outer peripheral insulating film 51, and the second wiring sidewall 55 extends vertically in the Z direction on the outer peripheral insulating film 51.

[0108] The first wiring side wall 54 is connected to a plurality of gate electrodes 32 (first side wall 34 and second side wall 35) in the portion extending in the first direction X. In other words, the gate wiring 52 has a plurality of portions connected in a T-shape to the plurality of gate electrodes 32. As a result, the gate wiring 52 is fixed at the same potential as the plurality of gate electrodes 32.

[0109] The first wiring sidewall 54 and the second wiring sidewall 55 may extend perpendicularly to the outer insulating film 51. In other words, the gate wiring 52 may be formed in a square shape (flat rectangle) in cross-section. The first wiring sidewall 54 and the second wiring sidewall 55 may be inclined obliquely toward the wiring surface 53. In other words, the gate wiring 52 may be formed in a tapered shape (preferably an isosceles trapezoid shape) in cross-section.

[0110] Referring to Figures 8 to 11, the semiconductor device 1 includes an insulating interlayer film 70 covering the first main surface 3. The interlayer film 70 may also be called an "interlayer insulating film," "intermediate insulating film," etc. The interlayer film 70 has an insulating surface 71 that extends along the first main surface 3. The interlayer film 70 covers the active region 8 and the outer peripheral region 9 on the first main surface 3 collectively.

[0111] The interlayer film 70 covers multiple gate structures 30 in the active region 8. With respect to each gate structure 30, the interlayer film 70 directly covers both the insulating film 31 and the gate electrode 32. In other words, the interlayer film 70 has portions that directly cover the electrode surface 33, the first side wall 34, and the second side wall 35 of the gate electrode 32.

[0112] Referring to Figure 11, the interlayer film 70 comprehensively covers the outer body region 21, the terminal region 45, and multiple field regions 47 in the outer peripheral region 9, sandwiching the outer peripheral insulating film 51. The interlayer film 70 directly covers both the outer peripheral insulating film 51 and the gate wiring 52. In other words, the interlayer film 70 has portions that directly cover the wiring surface 53, the first wiring sidewall 54, and the second wiring sidewall 55 of the gate wiring 52. In this embodiment, the interlayer film 70 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer film 70 may be formed with a gap inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3 (first semiconductor region 6).

[0113] Referring to Figures 8 to 10, in this embodiment, the interlayer film 70 has a laminated structure including a first oxide film 72 (first insulating film) and a second oxide film 73 (second insulating film) that are laminated in this order from the first main surface 3 side. In other words, the interlayer film 70 has an insulating surface 71 formed by the second oxide film 73. The first oxide film 72 has a single-layer structure consisting of an impurity-free silicon oxide film. The first oxide film 72 may also be called an NSG film (Nondoped Silicate Glass film).

[0114] The first oxide film 72 covers the active region 8 and the peripheral region 9 together. The first oxide film 72 covers multiple gate structures 30 together in the active region 8. With respect to each gate structure 30, the first oxide film 72 coats both the insulating film 31 and the gate electrode 32 in a film-like manner.

[0115] The first oxide film 72 has a first coating portion 74, a second coating portion 75, and a third coating portion 76. The first coating portion 74 extends horizontally in a film-like manner along the insulating film 31 (first main surface 3) and has a portion that contacts the first side wall 34 (second side wall 35) of the gate electrode 32. In this embodiment, the first coating portion 74 (first oxide film 72) has a thickness less than the thickness of the gate electrode 32 and covers the insulating film 31 with a gap from the height position of the electrode surface 33 of the gate electrode 32 toward the insulating film 31 side.

[0116] The second coating portion 75 is drawn out from the first coating portion 74 toward the electrode surface 33 in the stacking direction and directly coats the first side wall 34 (second side wall 35) in a film-like manner.

[0117] The third covering portion 76 extends from the second covering portion 75 toward the electrode surface 33 and extends horizontally in a film-like manner along the electrode surface 33. The third covering portion 76 directly covers the entire area of ​​the electrode surface 33 between the first side wall 34 and the second side wall 35. Preferably, the third covering portion 76, together with the second covering portion 75, forms an arc-shaped curved corner portion in the portion that covers the corner of the gate electrode 32. The arc-shaped corner portion may have its center of curvature on the gate electrode 32 side.

[0118] The first oxide film 72 comprehensively covers the outer body region 21, the terminal region 45, and multiple field regions 47 in the outer peripheral region 9, sandwiching the outer peripheral insulating film 51. The first oxide film 72 also covers the gate wiring 52 in the outer peripheral region 9.

[0119] The second oxide film 73 may have a single-layer structure consisting of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus. The silicon oxide film containing phosphorus may also contain boron. The silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass film). A silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass film).

[0120] The second oxide film 73 may have a single-layer structure consisting of a PSG film or a BPSG film laminated on the first oxide film 72. The second oxide film 73 may have a laminated structure including a PSG film laminated on the first oxide film 72 and a BPSG film laminated on the PSG film. The second oxide film 73 may have a laminated structure including a BPSG film laminated on the first oxide film 72 and a PSG film laminated on the BPSG film. In this embodiment, the second oxide film 73 has a single-layer structure consisting of a PSG film as an example.

[0121] The second oxide film 73 coats the first oxide film 72 in a film-like manner, and collectively coats the active region 8 and the outer peripheral region 9 with the first oxide film 72 in between. In the active region 8, the second oxide film 73 collectively coats the multiple gate structures 30 with the first oxide film 72 in between. Specifically, the second oxide film 73 coats both the insulating film 31 and the gate electrode 32 with the first oxide film 72 in a film-like manner.

[0122] The second oxide film 73 includes a first upper coating portion 80 and a second upper coating portion 81. The first upper coating portion 80 covers the first coating portion 74 of the first oxide film 72. In the portion of the first upper coating portion 80 located above the first coating portion 74, the insulating film 31 is applied with the first coating portion 74 in between.

[0123] The first upper covering portion 80 extends in a film-like manner in the stacking direction from above the first covering portion 74 along the second covering portion 75, and covers the first side wall 34 (second side wall 35) of the gate structure 30, sandwiching the second covering portion 75.

[0124] The second upper covering portion 81 covers the third covering portion 76 of the first oxide film 72. The second upper covering portion 81 extends horizontally in a film-like manner from the first upper covering portion 80 along the third covering portion 76, covering the electrode surface 33 of the gate structure 30 with the third covering portion 76 in between. The second upper covering portion 81 covers the entire area of ​​the electrode surface 33 with the third covering portion 76 in between the first side wall 34 and the second side wall 35. Preferably, the second upper covering portion 81 forms an arc-shaped curved corner portion together with the first upper covering portion 80 in the portion that covers the corner portion of the gate wiring 52. The arc-shaped corner portion may have its center of curvature on the gate wiring 52 side.

[0125] The second oxide film 73 comprehensively covers the outer body region 21, the terminal region 45, and multiple field regions 47 in the outer peripheral region 9, sandwiching the outer peripheral insulating film 51 and the first oxide film 72. The second oxide film 73 also covers the gate wiring 52 in the outer peripheral region 9, sandwiching the first oxide film 72.

[0126] Referring to Figures 8 to 10, the semiconductor device 1 includes a plurality of source openings 90 formed in the interlayer film 70 in the active region 8. The plurality of source openings 90 are formed in regions lateral to the plurality of gate electrodes 32, spaced apart from the plurality of gate electrodes 32, and exposing the first main surface 3 (chip 2). Specifically, the plurality of source openings 90 are formed in regions between the plurality of gate electrodes 32 and penetrate the insulating film 31 and the interlayer film 70.

[0127] Multiple source openings 90 penetrate both the first oxide film 72 and the second oxide film 73 and have wall surfaces partitioned by both the first oxide film 72 and the second oxide film 73. Multiple source openings 90 have open ends partitioned by the arc corners of the interlayer film 70. Multiple source openings 90 expose corresponding multiple source regions 23 (first source region 24A and second source region 24B) and body contact region 25, respectively.

[0128] In this embodiment, the multiple source openings 90 are formed at intervals in the first direction X and each is formed in a strip shape extending in the second direction Y. In other words, the multiple source openings 90 are formed in a stripe shape extending in the second direction Y. The multiple source openings 90 are formed at intervals in the second direction Y from the gate wiring 52. In other words, the multiple source openings 90 are formed in the region surrounded by the multiple gate electrodes 32 and the gate wiring 52.

[0129] Multiple source openings 90 may be formed in the region between two adjacent gate structures 30 in the first direction X. In this case, the multiple source openings 90 may be formed in a row with spacing in the second direction Y. Furthermore, in this case, each source opening 90 may be formed in a square shape, a rectangle extending in the first direction X, a rectangle extending in the second direction Y, a hexagon, a circle, etc., in a plan view.

[0130] Referring to Figures 7 to 10, the source opening 90 may have an opening width W1 of 0.2 μm or more and 3 μm or less. Preferably, the opening width W1 of the source opening 90 is 0.3 μm or more and 1 μm or less. An example of the opening width W1 of the source opening 90 is about 0.4 μm. The source opening 90 may have a depth D of 0.2 μm or more and 2 μm or less. Preferably, the depth D of the source opening 90 is 0.5 μm or more and 1 μm or less.

[0131] Referring to Figures 8 to 10, it is preferable that the source opening 90 has an aspect ratio D / W1 of 0.3 or more and 3 or less. The aspect ratio D / W1 is defined by the ratio of the depth D of the source opening 90 to the opening width W1 of the source opening 90. It is preferable that the aspect ratio D / W1 is 0.5 or more and 2 or less. It is particularly preferable that the aspect ratio D / W1 is greater than 1. With this configuration, a plurality of gate structures 30 are arranged at a narrow pitch.

[0132] Referring to Figures 4 and 5, the semiconductor device 1 includes a plurality of source recesses 91 formed on the first main surface 3 in the portions exposed from the plurality of source openings 90. The semiconductor device 1 does not necessarily have to have source recesses 91. Therefore, a configuration without source recesses 91 may be adopted.

[0133] Each of the multiple source recesses 91 has a planar shape that matches the planar shape of the corresponding source opening 90 and is recessed from the first main surface 3 toward the second main surface 4. The multiple source recesses 91 are formed at intervals from the bottom of the corresponding body region 20 toward the first main surface 3, exposing the corresponding multiple source regions 23 and body contact regions 25, respectively. Specifically, the multiple source recesses 91 are formed at intervals from the bottom of the corresponding multiple source regions 23 (body contact regions 25) toward the first main surface 3.

[0134] Referring to Figures 4, 5, and 11, the semiconductor device 1 includes at least one (in this embodiment, multiple) outer openings 92 formed in the interlayer film 70 in the outer peripheral region 9. The multiple outer openings 92 are formed in the portion of the interlayer film 70 that covers the terminal region 45. The multiple outer openings 92 penetrate the interlayer film 70, exposing the terminal region 45. In this embodiment, the multiple outer openings 92 are formed in the portion of the interlayer film 70 that covers the overlap region 46 of the terminal region 45, exposing the overlap region 46.

[0135] The multiple outer openings 92 may expose the outer body region 21 in place of or in addition to the terminal region 45 (overlap region 46). The multiple outer openings 92 penetrate both the first oxide film 72 and the second oxide film 73 and have wall surfaces partitioned by both the first oxide film 72 and the second oxide film 73. The multiple outer openings 92 have open ends partitioned by the arc corners of the interlayer film 70.

[0136] Multiple outer openings 92 are formed at intervals along the end region 45 (overlap region 46). Multiple outer openings 92 may be formed in a square, rectangular, hexagonal, circular, or the like in a plan view. Multiple outer openings 92 may be formed in a strip shape extending along the end region 45 (overlap region 46) in a plan view. The outer openings 92 may have an aspect ratio D / W1 (preferably greater than 1), similar to the source opening 90.

[0137] The semiconductor device 1 may have a single outer opening 92. The single outer opening 92 may be formed in a strip shape extending along the terminal region 45 (overlap region 46). The single outer opening 92 may have a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y in a plan view.

[0138] The single outer opening 92 may be formed as an ended or endless polygonal ring (in this embodiment, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3. The single outer opening 92 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape) in a plan view, following the end region 45 (overlap region 46) (Figure 4).

[0139] Referring to Figures 4, 5, and 11, the semiconductor device 1 includes a plurality of outer recesses 93 formed on the first main surface 3 in the portions exposed from the plurality of outer openings 92. The semiconductor device 1 does not necessarily need to have outer recesses 93. Therefore, a configuration without outer recesses 93 may be adopted.

[0140] Each of the multiple outer recesses 93 has a planar shape that matches the planar shape of the corresponding outer opening 92 and is recessed from the first main surface 3 toward the second main surface 4. The multiple outer recesses 93 are formed at intervals from the bottom of the end region 45 (overlap region 46) toward the first main surface 3, exposing the end region 45 (overlap region 46) in each case. When a single outer opening 92 is formed, a single outer recess 93 is formed that matches the planar shape of the single outer opening 92.

[0141] Referring to Figures 4, 5, and 11, the semiconductor device 1 includes at least one (or more in this embodiment) gate openings 94 formed in the interlayer film 70 in the outer peripheral region 9. The multiple gate openings 94 are formed in the portion of the interlayer film 70 that covers the gate wiring 52. The multiple gate openings 94 penetrate the interlayer film 70, exposing the wiring surface 53 of the gate wiring 52.

[0142] Multiple gate openings 94 penetrate both the first oxide film 72 and the second oxide film 73 and have wall surfaces partitioned by both the first oxide film 72 and the second oxide film 73. Multiple gate openings 94 have open ends partitioned by the arc-shaped corners of the interlayer film 70.

[0143] Multiple gate openings 94 are formed at intervals along the gate wiring 52 (Figures 4 and 5). The multiple gate openings 94 may be formed in a square, rectangular, hexagonal, circular, or other shape in a plan view. The multiple gate openings 94 may be formed in a strip shape extending along the gate wiring 52 in a plan view. The gate openings 94 may have an aspect ratio D / W1 (preferably greater than 1), similar to the source opening 90.

[0144] The semiconductor device 1 may have a single gate opening 94. The single gate opening 94 may be formed in a strip shape extending along the gate wiring 52. The single gate opening 94 may have a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y in a plan view.

[0145] A single gate opening 94 may be formed as an ended or endless polygonal ring (in this embodiment, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3. A single gate opening 94 may have an edge portion that connects the portion extending in a first direction X and the portion extending in a second direction Y in an arc shape (preferably a quarter-circular arc shape) in a plan view, following the gate wiring 52 (Figure 4).

[0146] Referring to Figure 1, etc., the semiconductor device 1 includes a source pad electrode 95 disposed on the interlayer film 70. The source pad electrode 95 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 95 may also be referred to as the "first pad electrode," "first main surface electrode," "first terminal electrode," etc.

[0147] The source pad electrode 95 is positioned on the portion of the interlayer film 70 that covers the active region 8. The source pad electrode 95 covers multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically isolated from the multiple gate electrodes 32 by the interlayer film 70. The source pad electrode 95 is electrically connected to multiple body regions 20, an outer body region 21, multiple source regions 23 (first source region 24A and second source region 24B), a body contact region 25, etc., via multiple source openings 90.

[0148] In this embodiment, the source pad electrode 95 has a first pad portion 96, a second pad portion 97, and a third pad portion 98. The first pad portion 96 has a relatively large planar area and forms the main body of the source pad electrode 95. In this embodiment, the first pad portion 96 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the tip 2 in a plan view, and is biased toward the fourth side surface 5D side relative to the central part of the active region 8. The first pad portion 96 covers a plurality of gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to a plurality of body regions 20 etc. via a plurality of source openings 90.

[0149] The second pad portion 97 has a planar area less than that of the first pad portion 96 and extends in a strip-like (square-shaped) manner from one end of the first pad portion 96 in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C side. The second pad portion 97 covers a plurality of gate electrodes 32 with the interlayer film 70 in between and is electrically connected to a plurality of body regions 20 etc. via a plurality of source openings 90.

[0150] The third pad portion 98 has a planar area less than that of the first pad portion 96, extends in a strip-like (square-shaped) manner from the other end of the first pad portion 96 in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C side, and faces the second pad portion 97 in the second direction Y. The third pad portion 98 covers a plurality of gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to a plurality of body regions 20 etc. via a plurality of source openings 90.

[0151] The surface area of ​​the third pad portion 98 may be approximately equal to the surface area of ​​the second pad portion 97. Of course, the surface area of ​​the third pad portion 98 may be larger than or less than the surface area of ​​the second pad portion 97. Either or both of the second pad portion 97 and the third pad portion 98 may be used as terminal portions for current monitoring.

[0152] The source pad electrode 95 does not necessarily have both the second pad portion 97 and the third pad portion 98 at the same time. The source pad electrode 95 may have only one of the second pad portion 97 or the third pad portion 98. Of course, the source pad electrode 95 may consist only of the first pad portion 96 and not have the second pad portion 97 or the third pad portion 98.

[0153] Referring to Figures 8 to 10, the source pad electrode 95 includes a first base electrode film 100 and a first main electrode film 102. The first base electrode film 100 may be referred to as the "source base electrode film," and the first main electrode film 102 may be referred to as the "source main electrode film."

[0154] The first base electrode film 100 forms the lower layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the interlayer film 70 in the active region 8. The first base electrode film 100 collectively covers the region of the interlayer film 70 in which multiple source openings 90 are formed. In other words, the first base electrode film 100 penetrates into the multiple source openings 90 from above the insulating surface 71.

[0155] The first base electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the plurality of source openings 90 in a film-like manner. The first base electrode film 100 demarcates recesses in the plurality of source openings 90. The first base electrode film 100 may have a portion that partially covers the gate wiring 52 with the interlayer film 70 in between. The first base electrode film 100 may be formed with a gap inward from the gate wiring 52 in a plan view.

[0156] In this embodiment, the first base electrode film 100 has a laminated structure including a first electrode film 103 laminated on the interlayer film 70 and a second electrode film 104 laminated on the first electrode film 103. In this embodiment, the first electrode film 103 includes a Ti film, and the second electrode film 104 includes a TiN film.

[0157] The first base electrode film 100 does not necessarily have a multilayer structure, and may have a single-layer structure consisting of either the first electrode film 103 (Ti film) or the second electrode film 104 (TiN film). The thickness of the first electrode film 103 may be 10 nm or more and 100 nm or less. The thickness of the second electrode film 104 may be 50 nm or more and 200 nm or less.

[0158] The first electrode film 103 comprehensively covers the region of the interlayer film 70 where multiple source openings 90 are formed, and penetrates the multiple source openings 90 from above the insulating surface 71. The first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner. The first electrode film 103 directly covers the insulating surface 71.

[0159] In other words, the first electrode film 103 directly covers the second oxide film 73 on the insulating surface 71. The first oxide film 72 faces multiple gate electrodes 32 across the interlayer film 70 in the portion that covers the insulating surface 71.

[0160] The first electrode film 103 follows the arc-shaped corner of the interlayer film 70 (second oxide film 73), covering the arc-shaped corner and extending into the source opening 90. In other words, the first electrode film 103 has a portion that extends in an arc shape at the arc-shaped corner. This improves the film-forming ability of the first electrode film 103 on the interlayer film 70 (wall surface of the source opening 90).

[0161] The first electrode film 103 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73. The first electrode film 103 faces the first side wall 34 (second side wall 35) of the gate electrode 32, with the interlayer film 70 in between.

[0162] The first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each source opening 90 and is electrically connected to the first main surface 3. Specifically, the first electrode film 103 has a portion that covers the bottom of each source opening 90 in a film-like manner and is electrically connected to a plurality of source regions 23 (first source region 24A and second source region 24B) and body contact region 25.

[0163] The second electrode film 104 comprehensively covers the region of the interlayer film 70 in which multiple source openings 90 are formed on the first electrode film 103. The second electrode film 104 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, sandwiching the first electrode film 103, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner, sandwiching the first electrode film 103.

[0164] The second electrode film 104 faces multiple gate electrodes 32 with the first electrode film 103 and the interlayer film 70 in between in the portion that covers the insulating surface 71.

[0165] The second electrode film 104, following the example of the first electrode film 103, coats the arc-shaped corners of the interlayer film 70 (second oxide film 73) in a film-like manner and penetrates into the source opening 90. In other words, the second electrode film 104 has a portion that extends in an arc shape at the arc-shaped corners of the interlayer film 70. This improves the film-forming ability of the second electrode film 104 on the interlayer film 70 (wall surface of the source opening 90).

[0166] The second electrode film 104 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 in between. The second electrode film 104 faces the first side wall 34 (second side wall 35) of the gate electrode 32 with the first electrode film 103 and the interlayer film 70 in between.

[0167] The second electrode film 104 has a portion that covers the bottom of each source opening 90 in a film-like manner, sandwiching the first electrode film 103, and is electrically connected to a plurality of source regions 23 (first source region 24A and second source region 24B) and a body contact region 25.

[0168] The first main electrode film 102 forms the upper layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the first base electrode film 100 in a film-like manner. The first main electrode film 102 contains a conductive material different from the conductive material of the first base electrode film 100.

[0169] The first main electrode film 102 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first base electrode film 100.

[0170] The thickness of the first main electrode film 102 may be 0.5 μm or more and 5 μm or less. The thickness of the first main electrode film 102 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or more and 5 μm or less.

[0171] The first main electrode film 102 is mechanically and electrically connected to the first base electrode film 100 in the portion that covers the insulating surface 71. As a result, the first main electrode film 102 faces multiple gate electrodes 32 with the first base electrode film 100 and the interlayer film 70 in between.

[0172] The semiconductor device 1 includes a source finger electrode 110 that is drawn out from a source pad electrode 95 onto the outer peripheral region 9. The source finger electrode 110 transmits the source potential applied to the source pad electrode 95 to the outer peripheral region 9. In this embodiment, the source finger electrode 110 is routed from the fourth side 5D side of the source pad electrode 95 (first pad portion 96) onto the portion of the interlayer film 70 that covers the outer peripheral region 9.

[0173] The source finger electrode 110 is extended over the termination region 45 and electrically connected to the termination region 45 via a plurality of outer openings 92. Specifically, the source finger electrode 110 is electrically connected to the overlapping region 46 of the termination region 45 via a plurality of outer openings 92.

[0174] The source finger electrode 110 extends in a strip shape along the terminal region 45 (overlap region 46). In a plan view, the source finger electrode 110 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y. In this embodiment, the source finger electrode 110 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 95. The source finger electrode 110 may have an edge portion that connects the portion that extends in the first direction X and the portion that extends in the second direction Y in an arc shape (preferably a quarter-circular arc shape) in a plan view (Figure 4).

[0175] The source finger electrode 110, like the source pad electrode 95, includes a first base electrode film 100 and a first main electrode film 102. The first base electrode film 100 forms the lower layer of the source finger electrode 110 and covers the interlayer film 70 in the outer peripheral region 9.

[0176] The first base electrode film 100 comprehensively covers the region of the interlayer film 70 where multiple outer openings 92 are formed. In other words, the first base electrode film 100 penetrates into the multiple outer openings 92 from above the insulating surface 71. The first base electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner. The first base electrode film 100 demarcates recesses within the multiple outer openings 92. The first base electrode film 100 has a laminated structure including a first electrode film 103 and a second electrode film 104, similar to the source pad electrode 95.

[0177] The first main electrode film 102 forms the upper layer of the source finger electrode 110 and covers the first base electrode film 100 in a film-like manner. The first main electrode film 102 is mechanically and electrically connected to the first base electrode film 100 in the portion that covers the insulating surface 71. In other words, the first main electrode film 102 is electrically connected to the terminal region 45 (overlap region 46) via the first base electrode film 100.

[0178] The semiconductor device 1 includes a gate finger electrode 115 selectively routed over the interlayer film 70. The gate finger electrode 115 transmits a gate potential to the gate wiring 52. The gate finger electrode 115 is routed over the portion of the interlayer film 70 that covers the gate wiring 52 (i.e., over the outer peripheral region 9) and is electrically connected to the gate wiring 52 via a plurality of gate openings 94.

[0179] The gate finger electrode 115 is positioned in the region between the source pad electrode 95 and the source finger electrode 110, spaced apart from the source pad electrode 95 and the source finger electrode 110. The gate finger electrode 115 is positioned on the gate wiring 52 and extends in a strip shape along the gate wiring 52. In a plan view, the gate finger electrode 115 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y.

[0180] In this embodiment, the gate finger electrode 115 is formed in the shape of an ended band having four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 95. The gate finger electrode 115 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape) in a plan view (Figure 4). The gate finger electrode 115 has a pair of open ends on the fourth side surface 5D side that allow the source finger electrode 110 to pass through.

[0181] Referring to Figure 11, the gate finger electrode 115 includes a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 may be referred to as the "gate base electrode film," and the second main electrode film 122 may be referred to as the "gate main electrode film."

[0182] The second base electrode film 120 forms the lower layer of the gate finger electrode 115 and covers the interlayer film 70 in the outer peripheral region 9. The second base electrode film 120 comprehensively covers the region of the interlayer film 70 in which multiple gate openings 94 are formed. In other words, the second base electrode film 120 penetrates into the multiple gate openings 94 from above the insulating surface 71. The second base electrode film 120 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner. The second base electrode film 120 partitions multiple recesses within the multiple gate openings 94.

[0183] The second base electrode film 120 has a laminated structure similar to that of the first electrode film 103 and the second electrode film 104 of the first base electrode film 100. The laminated structure of the second base electrode film 120 is the same as that of the first electrode film 103 and the second electrode film 104 of the first base electrode film 100, so a detailed explanation is omitted.

[0184] The second main electrode film 122 forms the upper layer of the gate finger electrode 115 and covers the second base electrode film 120 in a film-like manner. The second main electrode film 122 contains a conductive material different from the conductive material of the second base electrode film 120.

[0185] The second main electrode film 122 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. Preferably, the second main electrode film 122 contains the same type of conductive material as the first main electrode film 102. The second main electrode film 122 may have a thickness approximately equal to the thickness of the first main electrode film 102.

[0186] The second main electrode film 122 is mechanically and electrically connected to the second base electrode film 120 in the portion that covers the insulating surface 71.

[0187] The semiconductor device 1 includes a gate pad electrode 130 disposed on the interlayer film 70. The gate pad electrode 130 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 130 may also be called a "second pad electrode," "second main surface electrode," "second terminal electrode," etc. The gate pad electrode 130 is positioned at a distance from the source pad electrode 95 and the source finger electrode 110, in the region between the source pad electrode 95 and the source finger electrode 110.

[0188] In this configuration, the gate pad electrode 130 is positioned in the region on the third side surface 5C side relative to the first pad portion 96 and is sandwiched between the second pad portion 97 and the third pad portion 98. In other words, the gate pad electrode 130 faces the first pad portion 96 in the first direction X and faces the second pad portion 97 and the third pad portion 98 in the second direction Y.

[0189] The gate pad electrode 130 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 130 has a planar area less than that of the source pad electrode 95 (first pad portion 96). The gate pad electrode 130 may also have a planar area less than that of the second pad portion 97 (third pad portion 98).

[0190] The gate pad electrode 130 is positioned on the portion that covers the active region 8 and the outer peripheral region 9, and is connected to the gate finger electrode 115. The gate pad electrode 130 may cover a plurality of gate electrodes 32 with the interlayer film 70 in between, or it may cover the gate wiring 52 with the interlayer film 70 in between.

[0191] The gate pad electrode 130, like the gate finger electrode 115, includes a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 forms the lower layer of the gate pad electrode 130 and covers the interlayer film 70 in a film-like manner. The second main electrode film 122 forms the upper layer of the gate pad electrode 130 and covers the second base electrode film 120 in a film-like manner.

[0192] The gate potential applied to the gate pad electrode 130 is applied to the gate wiring 52 via the gate finger electrode 115. The gate potential is transmitted to multiple gate electrodes 32 via the wiring path (current path) along the gate wiring 52. As a result, multiple gate electrodes 32 are turned on, and the on / off state of multiple channel regions 26, 27 is controlled.

[0193] Referring to Figure 2, the semiconductor device 1 includes a drain pad electrode 140 covering the second main surface 4. The drain pad electrode 140 is a terminal electrode to which a drain potential is applied from the outside. The drain pad electrode 140 may also be called a "third pad electrode," "third main surface electrode," "third terminal electrode," etc. The drain pad electrode 140 is electrically connected to the second semiconductor region 7. The drain pad electrode 140 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain pad electrode 140 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0194] The breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or more and 3000V or less.

[0195] Figure 12 is a schematic diagram showing a wafer 150 used in the manufacture of semiconductor device 1. Referring to Figure 12, the wafer 150 is the substrate for the chip 2 and contains a SiC single crystal. The wafer 150 is formed in the shape of a flat disc. Of course, the wafer 150 may also be formed in the shape of a flat rectangular parallelepiped. The wafer 150 has a first wafer main surface (wafer main surface) 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0196] The first wafer main surface 151 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2. The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of a SiC single crystal. The first wafer main surface 151 is formed by the silicon plane of the SiC single crystal, and the second wafer main surface 152 is formed by the carbon plane of the SiC single crystal. The wafer 150 (first wafer main surface 151 and second wafer main surface 152) has the aforementioned off-direction and off-angle.

[0197] The wafer 150 has markings 154 on the wafer side surface 153 that indicate the crystal orientation of the SiC single crystal. The markings 154 may include either an orientation flat or an orientation notch, or both. An orientation flat consists of a notch that is cut out in a straight line in a plan view. An orientation notch consists of a notch that is cut out in a concave shape (for example, tapered shape) toward the center of the first wafer main surface 151 in a plan view.

[0198] The marker 154 may include either or both a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The marker 154 may also include either or both an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0199] The wafer 150 includes a first semiconductor region 6 in the region (surface layer) on the side of the first wafer main surface 151. The first semiconductor region 6 is formed in layers extending along the first wafer main surface 151. In this embodiment, the first semiconductor region 6 consists of an epitaxial layer (specifically, a SiC epitaxial layer).

[0200] The wafer 150 includes a second semiconductor region 7 in the region (surface layer) on the second wafer main surface 152 side. The second semiconductor region 7 is formed in layers extending along the second main surface 4 and is electrically connected to the first semiconductor region 6. In this embodiment, the second semiconductor region 7 consists of the wafer body (specifically, a SiC wafer). In other words, in this embodiment, the wafer 150 consists of an epitaxial wafer (a so-called epi-wafer) having a laminated structure including the wafer body and an epitaxial layer.

[0201] For example, the wafer 150 has multiple device regions 155 and multiple cutting lines 156 marked by alignment marks or the like. Each device region 155 corresponds to a semiconductor device 1. The multiple device regions 155 are each set in a rectangular shape when viewed from above.

[0202] In this configuration, the multiple device regions 155 are arranged in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 155 are each spaced inward from the periphery of the first wafer main surface 151 in a plan view. The multiple cutting lines 156 are arranged in a grid pattern extending along the first direction X and the second direction Y to demarcate the multiple device regions 155.

[0203] Figures 13A to 13P are cross-sectional views showing a method for manufacturing the semiconductor device 1. Figures 13A to 13P show a cross-section of a portion of the active region 8 of one device region 155. In Figures 13A to 13P, the left view corresponds to a portion of the cross-section in Figure 8, and the right view corresponds to a portion of the cross-section in Figure 9. Figure 14 is a diagram showing the planar pattern of the first mask 37 shown in Figure 13G. Figure 15 is a cross-sectional view along the XV-XV line shown in Figure 14. Figure 16 is a diagram showing the planar pattern of the second mask 56 shown in Figure 13I.

[0204] Referring to Figure 13A, first, the aforementioned wafer 150 is prepared. Next, referring to Figure 13B, a base mask 18 is formed on the first wafer main surface 151. The base mask 18 is preferably an inorganic mask (i.e., a hard mask). The base mask 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the base mask 18 consists of a silicon oxide film (insulating film). The base mask 18 may be formed by a CVD method. Next, the base mask 18 is patterned to form a base opening 19. The base opening 19 selectively exposes the areas on the first wafer main surface 151 that are to form a body region 20 and an outer body region 21 (not shown).

[0205] Next, referring to Figure 13C, p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation via the base mask 18, forming multiple body regions 20. Additionally, p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation via the base mask 18, forming an outer body region 21.

[0206] Next, referring to Figure 13D, a sidewall insulating film 28 is formed on the first wafer main surface 151 so as to cover the base mask 18 and the body region 20. The sidewall insulating film 28 is preferably an inorganic mask (i.e., a hard mask). The sidewall insulating film 28 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the sidewall insulating film 28 consists of a silicon oxide film (insulating film). The sidewall insulating film 28 may be formed by a CVD method.

[0207] Next, referring to Figure 13E, the sidewall insulating film 28 is etched back. The etching back continues until the surfaces of the base mask 18 and the body region 20 are exposed. This selectively leaves the portion of the sidewall insulating film 28 that is in contact with the side of the base mask 18, forming the sidewall 29. The sidewall 29 covers the periphery of each body region 20. The portion of the body region 20 covered by the sidewall 29 is a plurality of channel regions 26, 27.

[0208] Next, referring to Figure 13F, a mask material 36 is formed to cover the sidewall 29 and the base mask 18 so as to fill the base opening 19 of the base mask 18. The mask material 36 may be an organic material. The mask material 36 may include a positive-type or negative-type photosensitive resin film (i.e., a resist film) as an organic material. Of course, the mask material 36 may also be an inorganic material (for example, a silicon oxide film, a silicon nitride film, and a polysilicon film).

[0209] Next, referring to Figure 13G, the mask material 36 is patterned to form the first mask 37. The first mask 37 has a first opening 38 that exposes the area where the source region 23 (first source region 24A and second source region 24B) is to be formed.

[0210] Referring to Figure 14, multiple first masks 37 are arranged on multiple body regions 20. The multiple first masks 37 are aligned along a first direction X.

[0211] The first mask 37 includes a main body portion 39 extending in a strip shape in the second direction Y, and connecting portions 40 protruding from the middle of the main body portion 39 to both sides in the first direction X. The connecting portions 40 are for mechanically connecting the main body portion 39 to a first mask 37 adjacent to the first mask 37 in the first direction X.

[0212] The main body portion 39 coincides with the planar shape of the body contact region 25 (Figures 6 and 7). The main body portion 39 crosses the first section 10 of the body region 20 in the second direction Y and has an end at the boundary position between the first section 10 and the second section 11. The main body portion 39 may be referred to by other names depending on its planar shape. For example, as shown in Figure 14, if the assumed shape excluding the connecting portion 40 is a strip in plan view, the main body portion 39 may be referred to as a strip portion. In this embodiment, the main body portion 39 is formed in the center of the body region 20 in the first direction X.

[0213] The main body portion 39 has a width W7 in the first direction X (Figure 13G). The width W7 is constant in the second direction Y. This width W7 is the same as the width W5 in the first direction X of the body contact area 25 (Figure 7). The width of the main body portion 39 (width W7) may be, for example, 0.2 μm or more and 0.6 μm or less. An example of a width W7 is approximately 0.4 μm.

[0214] Referring to Figure 13G, the aspect ratio (height H / width W7 of the main body 39) of the first mask 37 may be 5 or more and 25 or less.

[0215] Referring to Figure 15, the connection portion 40 is located on the base mask 18 and the side wall 29 and spans multiple body regions 20, connecting two adjacent first masks 37 in the first direction X.

[0216] Referring to Figures 14 and 15, in this configuration, the connecting portion 40 includes a pair of connecting portions 41A and 41B that project from the center of the main body portion 39 in the second direction Y to both sides in the first direction X. That is, one connecting portion 41A and one connecting portion 41B are formed on one side (left side as shown in Figures 14 and 15) and the other side (right side as shown in Figures 14 and 15) of the main body portion 39 in the first direction X. In this configuration, the connecting portion 40 that projects to one side in the first direction X is the first connecting portion 41A, and the connecting portion 40 that projects to the other side in the first direction X is the second connecting portion 41B.

[0217] In this configuration, the first connecting portion 41A and the second connecting portion 41B protrude from the same position on the main body 39 toward opposite sides. In other words, the first connecting portion 41A and the second connecting portion 41B face each other in the first direction X with the main body 39 in between.

[0218] Referring to Figure 14, the first connecting portion 41A may be rectangular in plan view along the first direction X. In this configuration, the first connecting portion 41A has a constant width W8 in the second direction Y. The width of the first connecting portion 41A (width W8) is the same as the width W (Figure 7) of the first exposed portion 13 in the second direction Y. The width W8 may be less than or equal to the width W7 of the main body portion 39 (W8 ≤ W7). In other words, the width W8 may be the same as the width W7, or it may be narrower than the width W7.

[0219] Referring to Figures 14 and 15, the first connection portion 41A is mechanically connected to the second connection portion 41B of the first mask 37 adjacent to it on one side in the first direction X. Specifically, the first connection portion 41A is mechanically connected to the upper surface of the base mask 18 on one side in the first direction X, and to the side surface of the sidewall 29 on one side in the first direction X (the left side as shown in Figures 14 and 15). On the upper surface of the base mask 18, the first connection portion 41A is mechanically connected to the second connection portion 41B of the first mask 37 adjacent to it on one side in the first direction X.

[0220] Referring to Figure 14, the second connecting portion 41B may be rectangular in plan view along the first direction X. In this configuration, the second connecting portion 41B has a constant width W8 in the second direction Y. The width of the second connecting portion 41B (width W8) is the same as the width W (Figure 7) of the second exposed portion 14 in the second direction Y. The width W8 may be less than or equal to the width W7 of the main body portion 39 (W8 ≤ W7). In other words, the width W8 may be the same as the width W7, or it may be narrower than the width W7.

[0221] Referring to Figures 14 and 15, the second connection portion 41B is mechanically connected to the first connection portion 41A of the first mask 37 adjacent to the other side of the first direction X (the right side as shown in Figures 14 and 15). Specifically, the second connection portion 41B is mechanically connected to the upper surface of the base mask 18 on the other side of the first direction X, and to the side surface of the sidewall 29 on the other side of the first direction X. The second connection portion 41B is mechanically connected on the upper surface of the base mask 18 to the first connection portion 41A of the first mask 37 adjacent to the other side of the first direction X.

[0222] Next, referring to Figure 13H, n-type impurities are selectively introduced into the surface layer of the body region 20 by ion implantation via the first mask 37, forming the source region 23. Additionally, a contact pattern region 50 is formed, consisting of a portion of the body region 20 that was covered by the first mask 37. After the formation of the source region 23, the first mask 37 is removed.

[0223] Next, referring to Figure 13I, a mask material is formed to cover the sidewall 29 and the base mask 18. The mask material may be an organic material. The mask material may include a positive-type or negative-type photosensitive resin film (i.e., a resist film) as an organic material. Of course, the mask material may also be an inorganic material (for example, a silicon oxide film, a silicon nitride film, and a polysilicon film). Next, the mask material is patterned to form a second mask 56. The second mask 56 has a second opening 57 that exposes the area where the body contact area 25 is to be formed.

[0224] Referring to Figure 16, the second opening 57 of the second mask 56 has the same planar pattern as the main body 39 of the first mask 37. The planar pattern of the second opening 57 of the second mask 56 does not include the same planar pattern as the connection portion 40 of the first mask 37.

[0225] Next, referring to Figure 13J, p-type impurities are selectively introduced into the surface layer of the body region 20 by ion implantation via the second mask 56, forming the body contact region 25. The body contact region 25 is formed with the same planar pattern as the main body portion 39 of the first mask 37.

[0226] The planar pattern of the body contact region 25 does not include the planar pattern of the connection portion 40 of the first mask 37. Therefore, the exposed portion 12 of the body region 20 is formed in the area of ​​the surface layer of the body region 20 that was covered by the connection portion 40 in the process shown in Figure 13H. After the formation of the body contact region 25, the second mask 56 is removed.

[0227] Next, referring to Figure 13K, a base insulating film 58 is formed to cover the main surface 151 of the first wafer. The base insulating film 58 is the base for the insulating film 31 and the outer peripheral insulating film 51. The base insulating film 58 may be formed by CVD (Chemical Vapor Deposition) or an oxidation treatment method (e.g., thermal oxidation treatment).

[0228] Next, referring to Figure 13L, a base electrode is formed on the base insulating film 58. This base electrode is the base for the gate electrode 32 and gate wiring 52. The base electrode contains conductive polysilicon. The base electrode may be formed by CVD. Next, the gate electrode 32 and gate wiring 52 are formed by patterning the base electrode.

[0229] Next, referring to Figure 13M, an interlayer film 70 is formed on the main surface 151 of the first wafer. In this step, an interlayer film 70 is formed that has portions that directly cover the electrode surface 33, the first side wall 34, and the second side wall 35 of the gate electrode 32. In this embodiment, the interlayer film 70 has a laminated structure including a first oxide film 72 and a second oxide film 73. The first oxide film 72 includes an impurity-free silicon oxide film. The second oxide film 73 includes a silicon oxide film containing phosphorus. The first oxide film 72 may be formed by a CVD method. The second oxide film 73 may also be formed by a CVD method. After the formation of the second oxide film 73, a reflow process (heat treatment process) is performed on the interlayer film 70. This smooths out the corners and surface roughness of the interlayer film 70.

[0230] Next, referring to Figure 13N, a mask having a predetermined layout is placed on the interlayer film 70. The mask exposes the areas where multiple source openings 90, multiple outer openings 92 (Figures 4, 5, and 11), and multiple gate openings 94 (Figures 4, 5, and 11) are to be formed, and covers the other areas. Next, unnecessary portions of the interlayer film 70 and the base insulating film 58 are removed by etching through the mask.

[0231] In this step, unwanted portions of the second oxide film 73, the first oxide film 72, and the base insulating film 58 are removed in that order. The etching method may be a wet etching method and / or a dry etching method. The etching method is preferably an anisotropic dry etching method (for example, RIE (Reactive Ion Etching) method). This forms a plurality of source openings 90, a plurality of outer openings 92, and a plurality of gate openings 94 in the interlayer film 70. The insulating film 31 and the outer peripheral insulating film 51 are also formed. This step may include a step of forming a plurality of source recesses 91 and a step of forming a plurality of outer recesses 93. In this case, a step is performed to further excavate the portion of the first wafer main surface 151 that is exposed from the plurality of source openings 90 and the plurality of outer openings 92 toward the second wafer main surface 152. The mask is then removed.

[0232] Next, referring to Figure 13O, a surface that curves diagonally upward from the gate electrode 32 is formed on the upper corner of the interlayer film 70 by reflow processing. The reflow conditions are not particularly limited as long as they result in the upper corner of the interlayer film 70, which is pointed after etching as shown in Figure 13N, becoming arc-shaped. For example, they can be appropriately determined according to the thickness of the interlayer film 70, the film quality, the opening width of the source opening 90, etc.

[0233] Next, referring to Figure 13P, the first base electrode film 100 and the second base electrode film 120 are formed on the interlayer film 70. The first base electrode film 100 and the second base electrode film 120 may be formed by sputtering or vapor deposition. Next, the first main electrode film 102 and the second main electrode film 122 are formed on the first base electrode film 100 and the second base electrode film 120, respectively. The first main electrode film 102 and the second main electrode film 122 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 and the second main electrode film 122 may be formed by sputtering or vapor deposition.

[0234] Subsequently, a drain pad electrode 140 is formed on the second wafer main surface 152. The drain pad electrode 140 may be formed by sputtering or vapor deposition. Then, the wafer 150 is cut along the planned cutting line 156, and a plurality of semiconductor devices 1 are cut out. The semiconductor device 1 is manufactured through the above process.

[0235] For example, to meet the demand for miniaturization of devices, multiple gate structures 30 may be arranged at a narrow pitch. As the distance between adjacent gate structures 30 becomes narrower, the area for forming the source region 23 also becomes narrower. Therefore, the installation area of ​​the first mask 37 when forming the source region 23 is reduced.

[0236] Referring to Figure 13G (especially the left diagram in Figure 13G), the main body portion 39 of the first mask 37 is formed separately from the base mask 18 and the sidewalls 29, etc. Therefore, if the first mask 37 were to consist only of the main body portion 39 and no connecting portion 40 were provided for the first mask 37, there would be no support in the lateral direction. In this case, the durability against external forces would decrease, and it would be more prone to tipping over or tilting due to its own weight or external forces. If the first mask 37 tips over or tilts, there is a risk that the source region 23 and the body contact region 25 cannot be formed accurately.

[0237] In contrast, referring to Figures 14 and 15, according to the method described above, the first mask 37 has a pair of connecting parts 41A and 41B. The pair of connecting parts 41A and 41B are mechanically connected to adjacent first masks 37 in the first direction X. Since multiple first masks 37 are mechanically connected to each other, tilting and tilting of the first masks 37 can be suppressed.

[0238] In particular, in this configuration, the connecting parts 41A and 41B are mechanically connected to the base mask 18 and the side wall 29. The main body 39 of the first mask 37 is supported from the side by the connecting parts 41A and 41B that are in contact with the base mask 18 and the side wall 29. This makes it possible to more effectively suppress tilting or bending of the first mask 37.

[0239] As described above, according to this embodiment (first embodiment), the source region 23 can be formed with high precision even with a fine pattern.

[0240] Furthermore, chip 2 is a wide-bandgap semiconductor (SiC in this configuration). Wide-bandgap semiconductors have a low diffusion coefficient for implanted impurity ions. Therefore, when forming an impurity region in the downward direction of the wafer 150, a method using high-acceleration implantation is employed instead of thermal diffusion, which is used for Si, etc. To prevent high-energy accelerated impurity ions from penetrating the mask (resist) and being implanted, the mask needs to be made thicker. For example, in this configuration, the first mask 37 is made thicker to prevent n-type impurities from penetrating the first mask 37 and being implanted into the contact pattern region 50 when forming the source region 23. Specifically, the aspect ratio (height H / width W7 of the main body 39 of the first mask 37) is set to 5 or more and 25 or less. With such a high aspect ratio, there is a significant concern about the first mask 37 tilting or inclining. However, the presence of a pair of connecting parts 40 (first connecting part 41A, second connecting part 41B) eliminates such concerns.

[0241] Figure 17 shows a first modified example of the layout of the first main surface 3, and corresponds to Figure 6.

[0242] The difference between the layout example according to the first modification and the layout example shown in Figure 6 is that the first length L1 of the first section 10 and the second length L2 of the second section 11 are both shorter than the pitch P1 (cell pitch) of the multiple body regions 20. The length ratio of the first length L1 to the pitch P1 (L1 / P1) may be 0.5 or more and less than 1. The length ratio (L1 / P1) may be 0.8 or more and less than 1.

[0243] The ratio of the second length L2 to the pitch P1 (L2 / P1) may be 0.5 or more and less than 1. The length ratio (L2 / P1) may be 0.8 or more and less than 1.

[0244] In the first modified example shown in Figure 17, the first length L1 in the second direction Y of the first section 10 and the second length L2 in the second direction Y of the second section 11 are the same (approximately the same) as each other. The ratio of the first length L1 to the second length L2 may be 1.0 or more and 1.05 or less.

[0245] Figure 18 shows a second modified example of the layout of the first main surface 3, and corresponds to Figure 6.

[0246] The difference between the second modified layout example and the layout example shown in Figure 6 is that the first length L1 of the first section 10 is shorter than the second length L2 of the second section 11, or more specifically, the first length L1 is less than or equal to half the second length L2.

[0247] The ratio of the first length L1 to the second length L2 (L1 / L2) may be 0.2 or more and 0.5 or less. Preferably, the length ratio (L1 / L2) is 0.25 or more and 0.4 or less. More preferably, the length ratio (L1 / L2) is 0.3 or more and 0.35 or less.

[0248] In the second modified example shown in Figure 18, the length ratio (L1 / P1) of the first length L1 to the pitch P1 may be 0.5 or more and less than 1. The length ratio (L1 / P1) may also be 0.8 or more and less than 1.

[0249] The ratio of the second length L2 to the pitch P1 (L2 / P1) may be between 1 and 3. The length ratio (L2 / P1) may be between 1.5 and 2.5.

[0250] The second modified example shown in Figure 18 may be combined with the first modified example shown in Figure 17.

[0251] Figure 19 is a plan view showing a semiconductor device 201 according to a second embodiment of the present invention, and corresponds to Figure 7.

[0252] The difference between the semiconductor device 201 and the semiconductor device 1 according to the first embodiment is that multiple exposed portions 12 are formed on both one side and the other side of the body contact region 25 in the first direction X (two on each side in the example of Figure 19). Except for this point, the semiconductor device 201 is the same as the semiconductor device 1. In Figure 19, components equivalent to those in the first embodiment are given the same reference numerals as in Figure 7, etc., and their description is omitted.

[0253] The exposed portion 12 includes two first exposed portions 213 and two second exposed portions 214. Each first exposed portion 213 divides the first source region 24A of the source region 23 in the second direction Y. Each second exposed portion 214 divides the second source region 24B of the source region 23 in the second direction Y.

[0254] The first exposed portion 213 is formed on one side of the body contact area 25 in the first direction X (the left side as shown in Figure 19). The second exposed portion 214 is formed on the other side of the body contact area 25 in the first direction X (the right side as shown in Figure 19). In this configuration, each first exposed portion 213 and each second exposed portion 214 face each other in the first direction X with the body contact area 25 in between.

[0255] The first exposed portion 213 may be rectangular in plan view along the first direction X. In this embodiment, the first exposed portion 213 has an exposed width WA in the second direction Y. The exposed width WA may be less than or equal to half of the width W5 in the first direction X of the body contact region 25. Preferably, the exposed width WA is less than half of the width W5. In the first section 10, the first channel region 26 is not formed for a length in the second direction Y corresponding to the exposed width WA of the first exposed portion 213. In order to ensure that the distance at which the first channel region 26 can be formed in the first section 10 is as long as possible, it is preferable that the exposed width WA is short. The exposed width WA may also be the same as half of the width W5.

[0256] The exposure width WA of the first exposed portion 213 may be constant or approximately constant in the first direction X. The exposure width WA may be, for example, 0.1 μm or more and 0.3 μm or less. An example of the spacing W4 is approximately 0.2 μm.

[0257] The first exposed portion 213 has a first inner end 213a and a first outer end 213b with respect to a first direction X. The first inner end 213a is aligned with one end of the body contact region 25 in the first direction X. In other words, the first inner end 213a is in contact with the body contact region 25. The first outer end 213b is aligned with one end of the body region 20 in the first direction X.

[0258] In this configuration, the two first exposed portions 213 are formed in a region shifted in the second direction Y from the central position C of the first section 10 in the second direction Y. The two first exposed portions 213 sandwich the central position C of the first section 10 in the second direction Y in the second direction Y. The distance WB between two adjacent first exposed portions 213 in the second direction Y is wider than the exposed width WA of the first exposed portion 213 (WB > WA).

[0259] The second exposed portion 214 may be rectangular in plan view along the first direction X. In this embodiment, the second exposed portion 214 has an exposed width WA in the second direction Y. The exposed width WA may be less than or equal to half of the width W5 in the first direction X of the body contact region 25. Preferably, the exposed width WA is less than half of the width W5. In the first section 10, the second channel region 27 is not formed for a length in the second direction Y corresponding to the exposed width WA of the second exposed portion 214. In order to ensure that the distance at which the second channel region 27 can be formed in the first section 10 is as long as possible, it is preferable that the exposed width WA is short. The exposed width WA may be the same as half of the width W5.

[0260] The exposure width WA of the second exposed portion 214 may be constant or approximately constant in the first direction X. The exposure width WA may be, for example, 0.1 μm or more and 0.3 μm or less. An example of the spacing W4 is approximately 0.4 μm.

[0261] The second exposed portion 214 has a second inner end 214a and a second outer end 214b with respect to the first direction X. The second inner end 214a is aligned with one end of the body contact region 25 in the first direction X. In other words, the second inner end 214a is in contact with the body contact region 25. The second outer end 214b is aligned with one end of the body region 20 in the first direction X.

[0262] In this configuration, the two second exposed portions 214 are formed in a region shifted in the second direction Y from the central position C of the first section 10 in the second direction Y. The two second exposed portions 214 sandwich the central position C of the first section 10 in the second direction Y in the second direction Y. The distance WB between two adjacent second exposed portions 214 in the second direction Y is wider than the exposed width WA of the second exposed portion 214 (WB > WA).

[0263] Figure 20 is a plan view showing the planar pattern of the first mask 237 used in the manufacture of the semiconductor device 201 according to the second embodiment of the present invention, and corresponds to Figure 14.

[0264] The semiconductor device 201 is manufactured in the same manner as the semiconductor device 1, as described with reference to Figures 13A to 13P. In the process shown in Figures 13G and 13H, the first mask 237 is used instead of the first mask 37. In the first mask 237, multiple connection portions 40 are formed on both one side (the left side shown in Figure 20) and the other side (the right side shown in Figure 20) of the main body portion 39 in the first direction X (two on each side in the example of Figure 20).

[0265] The first mask 237 includes two first connecting portions 241A and two second connecting portions 241B. The two first connecting portions 241A protrude from the main body 39 to one side in the first direction X (the left side as shown in Figure 20). The two second connecting portions 241B protrude from the main body 39 to the other side in the first direction X (the right side as shown in Figure 20). The two first connecting portions 241A and the two second connecting portions 241B each face each other in the first direction X with the main body 39 in between.

[0266] The first connecting portion 241A may be rectangular in plan view along the first direction X. In this configuration, the first connecting portion 241A has a constant width W9 in the second direction Y. The width (width W9) of the first connecting portion 241A is the same as the exposed width WA of the first exposed portion 213 in the second direction Y (Figure 19).

[0267] The width W9 may be less than or equal to half the width W7 of the main body 39 (W9 ≤ W7). In other words, the width W9 may be the same as half the width W7, or it may be narrower than half the width W7.

[0268] The two first connection portions 241A are mechanically connected to two second connection portions 241B of the first mask 237 adjacent to the first mask 237 on one side in the first direction X. Specifically, the two first connection portions 241A are mechanically connected to the upper surface of the base mask 18 on one side in the first direction X, and to the side surface of the sidewall 29 on one side in the first direction X (the left side as shown in Figure 20). The two first connection portions 241A are mechanically connected to two second connection portions 241B of the first mask 237 adjacent to the first mask 237 on the upper surface of the base mask 18 on one side in the first direction X.

[0269] The second connecting portion 241B may be rectangular in plan view, projecting along the first direction X to the other side of the first direction X (the right side as shown in Figure 20). In this configuration, the second connecting portion 241B has a constant width W9 in the second direction Y. The width of the second connecting portion 241B (width W9) is the same as the width WA of the second exposed portion 214 in the second direction Y (Figure 19).

[0270] The width W9 may be less than or equal to the width W7 of the main body 39 (W9 ≤ W7). In other words, the width W9 may be the same as the width W7, or it may be narrower than the width W7.

[0271] The second connection portion 241B is mechanically connected to the first connection portion 241A of the first mask 237 adjacent to the other side of the first direction X (the right side as shown in Figure 20). Specifically, the second connection portion 241B is mechanically connected to the upper surface of the base mask 18 on the other side of the first direction X, and to the side surface of the sidewall 29 on the other side of the first direction X. On the upper surface of the base mask 18, the second connection portion 241B is mechanically connected to the first connection portion 241A of the first mask 237 adjacent to the other side of the first direction X.

[0272] According to the second embodiment, the same effects and advantages as those described in relation to the first embodiment are achieved.

[0273] In addition, the first mask 237 supports the main body 39 from the side by two first connecting parts 241A and two second connecting parts 241B spaced apart in the second direction Y, thereby providing stronger support to the main body 39. This makes it possible to more effectively suppress the tipping or tilting of the first mask 237.

[0274] In the second embodiment, at least one of the first modified example shown in Figure 17 and the second modified example shown in Figure 18 may be combined.

[0275] Figure 21 is a plan view showing a semiconductor device 301 according to a third embodiment of the present invention, and corresponds to Figure 6.

[0276] The difference between the semiconductor device 301 and the semiconductor device 1 according to the first embodiment is that the exposed portions 12 formed on one side and the other side in the first direction X with respect to the body contact region 25 are offset with respect to the second direction Y. Aside from this, the semiconductor device 301 is the same as the semiconductor device 1. In Figure 21, components equivalent to those in the first embodiment are given the same reference numerals as in Figure 6, etc., and their descriptions are omitted.

[0277] The exposed portion 12 includes one first exposed portion 313 and one second exposed portion 314. The first exposed portion 313 and the second exposed portion 314 are offset with respect to the second direction Y. The first exposed portion 313 and the second exposed portion 314 are not facing each other in the first direction X.

[0278] The multiple body regions 20 include first body regions 20A and second body regions 20B that are alternately arranged in a first direction X. The first body regions 20A and the second body regions 20B differ in that the positions of the exposed portions 12 (first exposed portion 313 and second exposed portion 314) are different in a second direction Y, and are common in all other respects.

[0279] In the first body region 20A, the first exposed portion 313 is located on one side of the second direction Y (upper side as shown in Figure 21) from the center position of the first section 10 in the second direction Y. The second exposed portion 314 is located on the other side of the second direction Y (lower side as shown in Figure 21) from the center position of the first section 10 in the second direction Y. The distances of the first exposed portion 313 and the second exposed portion 314 from the center position of the first section 10 in the second direction Y may be equal to each other.

[0280] In the second body region 20B, the first exposed portion 313 is located on the other side of the second direction Y (the lower side as shown in Figure 21) from the center position of the first section 10 in the second direction Y. The second exposed portion 314 is located on one side of the second direction Y (the upper side as shown in Figure 21) from the center position of the first section 10 in the second direction Y. The distances of the first exposed portion 313 and the second exposed portion 314 from the center position of the first section 10 in the second direction Y may be equal to each other.

[0281] The first exposed portion 313 has the same configuration as the first exposed portion 13 (Figures 6 and 7), except for its position in the second direction Y. Therefore, a detailed explanation of the first exposed portion 313 is omitted.

[0282] The second exposed portion 314 has the same configuration as the second exposed portion 14 (Figures 6 and 7), except for its position in the second direction Y. Therefore, a detailed explanation of the second exposed portion 314 is omitted.

[0283] Figure 22 is a plan view showing the planar pattern of the first mask 337 used in the manufacture of the semiconductor device 301 according to the third embodiment of the present invention, and corresponds to Figure 14.

[0284] The semiconductor device 301 is manufactured in the same manner as the semiconductor device 1, as described with reference to Figures 13A to 13P. In the process shown in Figures 13G and 13H, the first mask 337 is used instead of the first mask 337. In the first mask 337, the connection portions 40 formed on one side (left side as shown in Figure 22) and the other side (right side as shown in Figure 22) of the first direction X relative to the main body 39 are offset with respect to the second direction Y.

[0285] The first mask 337 includes a first connecting portion 341A and a second connecting portion 341B. The first connecting portion 341A and the second connecting portion 341B are offset with respect to the second direction Y. The first connecting portion 341A and the second connecting portion 341B are not facing the first direction X.

[0286] The first mask 337 includes a first pattern mask 337A in which the first pattern is adopted and a second pattern mask 337B in which the second pattern is adopted. The first pattern mask 337A is formed on the first body region 20A among the plurality of body regions 20. The second pattern mask 337B is formed on the second body region 20B among the plurality of body regions 20.

[0287] In the first pattern mask 337A, the first connecting portion 341A protrudes from a position on one side of the second direction Y (upper side in Figure 22) relative to the central position of the main body portion 39 in the second direction Y. In the first pattern mask 337A, the second connecting portion 341B protrudes from a position on the other side of the second direction Y (lower side in Figure 22) relative to the central position of the main body portion 39 in the second direction Y.

[0288] In the second pattern mask 337B, the first connecting portion 341A protrudes from a position on the other side of the second direction Y (the lower side in Figure 22) than the central position of the main body portion 39 in the second direction Y. In the second pattern mask 337B, the second connecting portion 341B protrudes from a position on one side of the second direction Y (the upper side in Figure 22) than the central position of the main body portion 39 in the second direction Y.

[0289] The first connection portion 341A has the same configuration as the first connection portion 41A (Figures 14 and 15), except for its position in the second direction Y. Therefore, a detailed explanation of the first connection portion 341A is omitted.

[0290] The second connection portion 341B has the same configuration as the second connection portion 41B (Figures 14 and 15), except for its position in the second direction Y. Therefore, a detailed explanation of the second connection portion 341B is omitted.

[0291] The first connection portion 341A of the first pattern mask 337A is in the same position as the second connection portion 341B of the second pattern mask 337B with respect to the second direction Y. The second connection portion 341B of the first pattern mask 337A is in the same position as the first connection portion 341A of the second pattern mask 337B with respect to the second direction Y.

[0292] In two first masks 337 adjacent to each other in the first direction X, the first connection portion 341A of the first mask 337 on one side in the first direction X (the left side as shown in Figure 22) is in the same position in the second direction Y as the second connection portion 341B of the first mask 337 on the other side in the first direction X (the right side as shown in Figure 22). In two first masks 337 adjacent to each other in the first direction X, the second connection portion 341B of the first mask 337 on one side in the first direction X (the left side as shown in Figure 22) is in the same position in the second direction Y as the first connection portion 341A of the first mask 337 on the other side in the first direction X (the right side as shown in Figure 22).

[0293] The first connection portion 341A is mechanically connected to the second connection portion 341B of the first mask 337 adjacent to it on one side in the first direction X. Specifically, the first connection portion 341A is mechanically connected to the upper surface of the base mask 18 on one side in the first direction X, and to the side surface of the sidewall 29 on one side in the first direction X (the left side as shown in Figure 22). On the upper surface of the base mask 18, the first connection portion 341A is mechanically connected to the second connection portion 341B of the first mask 337 adjacent to it on one side in the first direction X.

[0294] The second connection portion 341B is mechanically connected to the first connection portion 341A of the first mask 337 adjacent to it on the other side of the first direction X (the right side as shown in Figure 22). Specifically, the second connection portion 341B is mechanically connected to the upper surface of the base mask 18 on the other side of the first direction X, and to the side surface of the sidewall 29 on the other side of the first direction X. On the upper surface of the base mask 18, the second connection portion 341B is mechanically connected to the first connection portion 341A of the first mask 337 adjacent to it on the other side of the first direction X.

[0295] According to the third embodiment, the same effects and advantages as those described in relation to the first embodiment are achieved.

[0296] In the third embodiment, at least one of the first modified example shown in Figure 17 and the second modified example shown in Figure 18 may be combined.

[0297] The third embodiment may be combined with the second embodiment shown in Figures 19 and 20.

[0298] For example, in each of the embodiments described above, a configuration in which the relationship between the a-axis direction and the m-axis direction is reversed may be adopted. The specific configuration in this case can be obtained by reversing the "a-axis direction (off-direction)" and the "m-axis direction (direction perpendicular to the off-direction)" in the above description and attached drawings.

[0299] In each of the embodiments described above, a structure may be adopted in which the conductivity type of the "n-type" semiconductor region is inverted to "p-type" and the conductivity type of the "p-type" semiconductor region is inverted to "n-type". The specific configuration in this case can be obtained by replacing "n-type" with "p-type" and simultaneously replacing "p-type" with "n-type" in the above description and attached drawings.

[0300] In the embodiments described above, a chip 2 (first semiconductor region 6 and second semiconductor region 7) containing a SiC single crystal was used. However, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may also contain a single crystal of a wide-bandgap semiconductor other than a SiC single crystal. A wide-bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of wide-bandgap semiconductor single crystals include gallium nitride, diamond, and gallium oxide. Of course, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may also contain a silicon single crystal.

[0301] In the embodiments described above, an n-type second semiconductor region 7 was shown. However, a p-type second semiconductor region 7 may be used instead of the n-type second semiconductor region 7. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of a MISFET structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure. The p-type second semiconductor region 7 may also be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0302] [Note 1-1] A semiconductor device (1,201,301) comprising: a chip (2) formed of a wide bandgap semiconductor and having a main surface (3) on which a semiconductor region (6) of a first conductivity type is formed; a base impurity region (20) of a second conductivity type formed on the surface of the semiconductor region (6); a first impurity region (23) of a first conductivity type formed on the surface of the base impurity region (20); and a second impurity region (25) of a second conductivity type formed on the surface of the base impurity region (20) and adjacent to the first impurity region (23) in a first direction (X), wherein the base impurity region (20) is a region exposed on the main surface (3) and includes an exposed portion (12) that extends in a strip shape in the first direction (X) so as to cross the base impurity region (20) in the first direction (X) and divides the first impurity region (23) in a second direction (Y) perpendicular to the first direction (X).

[0303] [Note 1-2] The exposed portion (12) has an exposed width (W, WA) in the second direction that is less than or equal to the width (W5) in the first direction (X) of the second impurity region (25), as described in Note 1-1 (1, 201, 301).

[0304] [Appendix 1-3] The semiconductor device (1, 201, 301) according to Appendix 1-2, wherein the second impurity region (25) is formed in a strip shape extending in the second direction (Y) and is sandwiched between the first impurity region (23) on both sides in the first direction (X), and the exposed portion (12) includes a first exposed portion (13, 213, 313) that separates the first impurity region (24A) on one side of the second impurity region (25) in the first direction (X), and a second exposed portion (14, 214, 314) that separates the first impurity region (24B) on the other side of the second impurity region (25) in the first direction (X).

[0305] [Appendix 1-4] The semiconductor device (1, 201, 301) described in Appendix 1-3, wherein the first exposed portion (13, 213, 313) has a first inner end portion (13a, 213a) in contact with the second impurity region (25) and a first outer end portion (13b, 213b) aligned with the first direction (X) at one end of the base impurity region (20) in the first direction (X), and the second exposed portion (14, 214, 314) has a second inner end portion (14a, 214a) in contact with the second impurity region (25) and a second outer end portion (14b, 214b) aligned with the first direction (X) at the other end of the base impurity region (20) in the first direction (X).

[0306] [Appendix 1-5] The semiconductor device (1,201,301) described in Appendix 1-3 or Appendix 1-4, wherein the exposed width (W,WA) of the first exposed portion (13,213,313) is the same as the exposed width (W,WA) of the second exposed portion (14,214,314).

[0307] [Appendix 1-6] The semiconductor device (1,201) according to any one of Appendix 1-3 to 1-5, wherein the first exposed portion (13, 213) and the second exposed portion (14, 214) face each other in the first direction (X) with the second impurity region (25) in between.

[0308] [Appendix 1-7] The semiconductor device (301) according to any one of Appendix 1-3 to 1-5, wherein the first exposed portion (313) and the second exposed portion (314) are offset with respect to the second direction (Y).

[0309] [Appendix 1-8] The semiconductor device (1,301) described in any one of Appendix 1-3 to 1-7, wherein the first exposed portion (13,313) and the second exposed portion (14,314) are each one.

[0310] [Appendix 1-9] The semiconductor device (201) according to any one of Appendix 1-3 to 1-7, wherein the first exposed portion (213) and the second exposed portion (214) are each provided in multiple locations spaced apart in the second direction (Y).

[0311] [Appendix 1-10] A semiconductor device (1,201,301) according to any one of Appendix 1-1 to 1-9, comprising: a body region (20) as the base impurity region (20) formed on the surface of the semiconductor region (6); a first impurity region (23) formed on the surface of the body region (20); a body contact region (25) as the second impurity region (25) formed on the surface of the body region (20), penetrating the first impurity region (23) and connected to the body region (20); channel regions (26, 27) formed in the region between the semiconductor region (6) and the first impurity region on the surface of the body region (20); and a gate electrode (32) formed on the channel regions (26, 27) via an insulating film.

[0312] [Appendix 1-11] The semiconductor device (1, 201, 301) according to Appendix 1-10, wherein a plurality of body regions (20) are arranged in a stripe shape extending in the second direction (Y), each body region (20) alternately has a plurality of first sections (10) and a plurality of second sections (11) in the second direction (Y), and the plurality of body contact regions (25) are arranged with spacing between each first section (10) so as to skip each second section (11) in the second direction (Y).

[0313] [Appendix 1-12] The semiconductor device (1, 201, 301) according to Appendix 1-11, wherein the body region (20) includes the exposed portion (12) that crosses the first section (10) in the first direction (X) within each of the first sections (10).

[0314] [Appendix 1-13] The exposed portion (12) divides the first impurity region (23) and the channel region (26, 27) in each of the first sections (10), as described in Appendix 1-12 (1, 201, 301).

[0315] [Appendix 1-14] The semiconductor device (1,201,301) described in any one of the appendices 1-1 to 1-13, wherein the chip (2) is a SiC chip.

[0316] [Note 1-15] A wafer (150) having a wafer main surface (151) formed of a wide bandgap semiconductor and having a semiconductor region (6) of a first conductivity type formed thereon, is prepared, and a plurality of body regions (20) spaced apart in a first direction (X) are selectively formed, and a first mask (37, 237, 337) is formed to selectively cover each of the body regions (20), wherein the first mask (37, 237, 337) has a main body portion (39) extending in a second direction (Y) perpendicular to the first direction (X), and a front portion that protrudes in a band shape from the middle of the main body portion (39) to one side of the first direction (X) adjacent to the front of the first mask (37, 237, 337) on one side of the first direction (X). The process includes: first connecting parts (41A, 241A, 341A) mechanically connected to the first mask (37, 237, 337); and second connecting parts (41B, 241B, 341B) that protrude in a strip shape from the middle of the main body (39) to the other side in the first direction (X), and are mechanically connected to the adjacent first mask (37, 237, 337) on the other side in the first direction (X); The steps include: forming a first impurity region (23) on the surface of the body region (20) by injecting a first conductive impurity into the body region (20) via the first mask (37, 237, 337), and leaving a contact pattern region (50) consisting of a part of the body region (20) in the area covered by the first mask (37, 237, 337); forming a second mask (56) having an opening (57) that selectively exposes the contact pattern region (50) and covers the first impurity region (23); and forming a body contact region (25) on the surface of the body region (20) by injecting a second conductive impurity into the contact pattern region (50) via the second mask (56). A method for manufacturing a semiconductor device (1,201,301), comprising the step of forming a gate electrode (32) that covers a channel region (26,27) formed in the region between the semiconductor region (6) and the first impurity region (23) on the surface of the body region (20).

[0317] [Note 1-16] The process further includes: forming a hard mask (18) on the main surface (151) of the wafer, having selective openings (19) in the region where the body region (20) is to be formed; forming the body region (20) by injecting a second conductive impurity through the hard mask (18), and then forming a sidewall (29) on the side of the hard mask (18) that covers the region where the channel regions (26, 27) are to be formed; forming a mask material (36) that covers the sidewall (29) and the hard mask (18) so as to fill the openings (19) of the hard mask (18); and forming the first mask (37, 237, 337) by patterning the mask material (36). A method for manufacturing a semiconductor device (1,201,301) as described in Appendix 1-15, wherein the first connection portion (41A, 241A, 341A) and the second connection portion (41B, 241B, 341B) are mechanically connected to the side wall (29) and the hard mask (18).

[0318] [Appendix 1-17] The method for manufacturing a semiconductor device (1,201) according to Appendix 1-15 or Appendix 1-16, wherein the first connection portion (41A, 241A) and the second connection portion (41B, 241B) face each other in the first direction (X) with the main body portion (39) in between.

[0319] [Appendix 1-18] The method for manufacturing a semiconductor device (301) according to Appendix 1-15 or Appendix 1-16, wherein the first connection portion (341A) and the second connection portion (341B) are offset with respect to the second direction (Y).

[0320] [Appendix 1-19] A method for manufacturing a semiconductor device (1,301) according to any one of Appendix 1-15 to 1-18, wherein the first connection portion (41A, 341A) and the second connection portion (41B, 341B) are each one.

[0321] [Appendix 1-20] A method for manufacturing a semiconductor device (201) according to any one of Appendix 1-15 to 1-18, wherein the first connection portion (241A) and the second connection portion (241B) are each provided in a plurality at intervals in the second direction (Y).

[0322] 1: Semiconductor device, 2: Chip, 3: First main surface (main surface), 4: Second main surface, 5A: First side surface, 5B: Second side surface, 5C: Third side surface, 5D: Fourth side surface, 6: First semiconductor region (semiconductor region), 7: Second semiconductor region, 8: Active region, 9: Outer peripheral region, 10: First section, 11: Second section, 12: Exposed portion, 13: First exposed portion, 13a: First inner end, 13b: First outer end, 14: Second exposed portion, 14a: Second inner end, 14b: Second outer end, 15A: Source region, 15B: Source region, 16A: Source region, 16B: Source region, 18: Base mask, 19: Base opening, 20: Bo 20O: Base impurity region, 21: Outer body region, 22: Surface drift region, 23: Source region (first impurity region), 24A: First source region, 24B: Second source region, 25: Body contact region (second impurity region), 26: First channel region (channel region), 27: Second channel region (channel region), 28: Sidewall insulating film, 29: Sidewall, 30: Gate structure, 31: Insulating film, 32: Gate electrode, 33: Electrode surface, 34: First sidewall, 35: Second sidewall, 36: Mask material, 37: First mask, 37 b: Second part, 38: First opening, 39: Main body, 40: Connection part, 41A: First connection part, 41B: Second connection part, 45: Termination region, 46: Overlap region, 47: Field region, 50: Contact pattern region, 51: Outer peripheral insulating film, 52: Gate wiring, 53: Wiring surface, 54: First wiring sidewall, 55: Second wiring sidewall, 56: Second mask, 57: Second opening, 58: Base insulating film, 70: Interlayer film, 71: Insulating surface, 72: First oxide film, 73: Second oxide film, 74: First coating part, 75: Second coating part, 76: Third coating part, 80: First upper coating part, 81: Second upper coating part, 90: Source opening, 91: Source recess, 92: Outer opening, 93: Outer recess, 94: Gate opening, 95: Source pad electrode, 96: First pad portion, 97: Second pad portion, 98: Third pad portion, 100: First underlay electrode film, 102: First main electrode film, 103: First electrode film, 104: Second electrode film, 110: Source finger electrode, 115: Gate finger electrode, 120: Second underlay electrode film, 122: Second main electrode film, 130: Gate pad electrode, 140: Drain pad electrode, 150: Wafer, 151: First wafer main surface (wafer main surface), 152: Second wafer main surface,153: Wafer side, 154: Marker, 155: Device area, 156: Cutting line, 201: Semiconductor device, 213: First exposed area, 213a: First inner end, 213b: First outer end, 214: Second exposed area, 214a: Second inner end, 214b: Second outer end, 237: First mask, 241A: First connection, 241B: Second connection, 301: Semiconductor device, 313: First exposed area, 314: Second exposed area, 337: First mask, 337A: First pattern mask, 337B: Second pattern mask, 341A: First connection, 341B: Second connection, W: Exposure width, WA: Exposure width, X: First direction, Y: Second direction, Z: Vertical direction

Claims

1. A semiconductor device comprising: a chip formed of a wide-bandgap semiconductor having a main surface on which a semiconductor region of a first conductivity type is formed; a base impurity region of a second conductivity type formed on the surface of the semiconductor region; a first impurity region of the first conductivity type formed on the surface of the base impurity region; and a second impurity region of the second conductivity type formed on the surface of the base impurity region and adjacent to the first impurity region in a first direction, wherein the base impurity region is a region exposed on the main surface and includes an exposed portion that extends in a strip shape in a first direction so as to cross the base impurity region in the first direction and divides the first impurity region in a second direction perpendicular to the first direction.

2. The semiconductor device according to claim 1, wherein the exposed portion has an exposed width in the second direction that is less than or equal to the width of the second impurity region in the first direction.

3. The semiconductor device according to claim 2, wherein the second impurity region is formed in a strip shape extending in the second direction and is sandwiched between the first impurity regions from both sides in the first direction, and the exposed portion includes a first exposed portion that separates the first impurity region on one side in the first direction relative to the second impurity region, and a second exposed portion that separates the first impurity region on the other side in the first direction relative to the second impurity region.

4. The semiconductor device according to claim 3, wherein the first exposed portion has a first inner end in contact with the second impurity region and a first outer end aligned in the first direction at one end of the base impurity region in the first direction, and the second exposed portion has a second inner end in contact with the second impurity region and a second outer end aligned in the first direction at the other end of the base impurity region in the first direction.

5. The semiconductor device according to claim 3 or 4, wherein the exposed width of the first exposed portion is the same as the exposed width of the second exposed portion.

6. The semiconductor device according to any one of claims 3 to 5, wherein the first exposed portion and the second exposed portion face each other in the first direction with the second impurity region in between.

7. The semiconductor device according to any one of claims 3 to 5, wherein the first exposed portion and the second exposed portion are offset with respect to the second direction.

8. The semiconductor device according to any one of claims 3 to 7, wherein the first exposed portion and the second exposed portion are each one.

9. The semiconductor device according to any one of claims 3 to 7, wherein the first exposed portion and the second exposed portion are each provided in a plurality at intervals in the second direction.

10. A semiconductor device according to any one of claims 1 to 9, comprising: a body region as a base impurity region formed on the surface of the semiconductor region; a first impurity region formed on the surface of the body region; a body contact region as a second impurity region formed on the surface of the body region and connected to the body region by penetrating the first impurity region; a channel region formed in the region between the semiconductor region and the first impurity region on the surface of the body region; and a gate electrode formed on the channel region via an insulating film.

11. The semiconductor device according to claim 10, wherein a plurality of the body regions are arranged in a stripe shape extending in the second direction, each body region alternately having a plurality of first sections and a plurality of second sections in the second direction, and the plurality of body contact regions are arranged with spacing between each of the first sections so as to skip each of the second sections in the second direction.

12. The semiconductor device according to claim 11, wherein the body region includes the exposed portion that crosses the first section in the first direction in each first section.

13. The semiconductor device according to claim 12, wherein the exposed portion separates the first impurity region and the channel region in each first section.

14. The semiconductor device according to any one of claims 1 to 13, wherein the chip is a SiC chip.

15. A wafer having a wafer main surface formed of a wide-bandgap semiconductor and having a semiconductor region of a first conductivity type formed thereon, and a step of selectively forming a plurality of body regions spaced apart in a first direction; a step of forming a first mask that selectively covers each of the body regions, wherein the first mask includes a main body portion extending in a second direction perpendicular to the first direction, a first connecting portion protruding in a strip shape from the middle of the main body portion to one side in the first direction and mechanically connected to an adjacent first mask on one side of the first mask in the first direction, and a second connecting portion protruding in a strip shape from the middle of the main body portion to the other side in the first direction and mechanically connected to an adjacent first mask on the other side of the first mask in the first direction; a step of injecting a first conductivity type impurity into the body regions via the first mask to form a first impurity region on the surface layer of the body regions and leaving a contact pattern region consisting of a part of the body regions in the region covered by the first mask; and a step of forming a second mask having an opening that selectively exposes the contact pattern region and covers the first impurity region. A method for manufacturing a semiconductor device, comprising the steps of: forming a body contact region on the surface of the body region by injecting a second conductivity type impurity into the contact pattern region via the second mask; and forming a gate electrode that covers a channel region formed in the region between the semiconductor region and the first impurity region on the surface of the body region.

16. A method for manufacturing a semiconductor device according to claim 15, further comprising the steps of: forming a hard mask on the main surface of a wafer, having an opening selectively in a region to be formed in the body region; forming the body region by injecting a second conductive impurity through the hard mask, and then forming a sidewall on the side of the hard mask to cover the region to be formed in the channel region; forming a mask material to cover the sidewall and the hard mask so as to fill the opening in the hard mask; and forming the first mask by patterning the mask material, wherein the first connection portion and the second connection portion are mechanically connected to the sidewall and the hard mask.

17. The method for manufacturing a semiconductor device according to claim 15 or 16, wherein the first connecting portion and the second connecting portion are opposite each other in the first direction with respect to the main body portion.

18. The method for manufacturing a semiconductor device according to claim 15 or 16, wherein the first connection portion and the second connection portion are offset with respect to the second direction.

19. The method for manufacturing a semiconductor device according to any one of claims 15 to 18, wherein the first connection portion and the second connection portion are each one.

20. A method for manufacturing a semiconductor device according to any one of claims 15 to 18, wherein the first connection portion and the second connection portion are each provided in a plurality at intervals in the second direction.

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