Semiconductor device

Abstract

This semiconductor device comprises: a substrate having a main surface and a rear surface facing the main surface; a first transistor provided on the main surface and comprising a first source electrode, a first drain electrode, and a first gate electrode sandwiched between the first source electrode and the first drain electrode; a second transistor provided on the main surface and comprising a second source electrode electrically connected to the first source electrode, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode sandwiched between the second source electrode and the second drain electrode; first gate wiring provided on the main surface and electrically connected to the first gate electrode and the second gate electrode; a gate bus line provided on the main surface and electrically connected to the first gate wiring; and second gate wiring which is provided on the main surface between the gate bus line and the first gate wiring, electrically connects the gate bus line and the first gate wiring, and has a width smaller than the width of the first gate wiring.

Description

Semiconductor device

[0001] The present disclosure relates to a semiconductor device.

[0002] This application claims priority based on Japanese Patent Application No. 2025-007180 filed on January 17, 2025, and incorporates all the descriptions described in the Japanese application.

[0003] In a field effect transistor (FET: Field Effect Transistor) having finger-shaped source electrodes, gate electrodes, and drain electrodes, it is known to arrange a plurality of unit FETs having source electrodes, gate electrodes, and drain electrodes in the extending direction of the electrodes (for example, Patent Document 1). It is known to connect a resistor in series to the gate electrode (for example, Patent Document 2).

[0004] Japanese Patent Application Laid-Open No. 2002-299351, Japanese Patent Application Laid-Open No. 9-121130

[0005] An embodiment of the present disclosure includes a substrate having a main surface and a back surface facing the main surface, a first transistor provided on the main surface and including a first source electrode, a first drain electrode, and a first gate electrode sandwiched between the first source electrode and the first drain electrode, a second transistor provided on the main surface and including a second source electrode electrically connected to the first source electrode, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode sandwiched between the second source electrode and the second drain electrode, a first gate wiring provided on the main surface and electrically connected to the first gate electrode and the second gate electrode, a gate bus line provided on the main surface, and a second gate wiring provided between the gate bus line and the first gate wiring on the main surface, electrically connecting the gate bus line and the first gate wiring, and having a width smaller than the width of the first gate wiring.

[0006] Embodiments of the present disclosure are semiconductor devices comprising: a substrate having a main surface and a back surface facing the main surface; a transistor provided on the main surface and comprising a plurality of source electrodes and a plurality of drain electrodes, and a plurality of gate electrodes each sandwiched between one of the plurality of source electrodes and one of the plurality of drain electrodes; a first gate wiring provided on the main surface and electrically connecting at least two of the plurality of gate electrodes; a gate bus line provided on the main surface; and a second gate wiring provided between the gate bus line and the first gate wiring on the main surface, electrically connecting the gate bus line and the first gate wiring, and having a width of five times or less the width of the plurality of gate electrodes.

[0007] Figure 1 is a plan view of a semiconductor device in the first embodiment. Figure 2 is a cross-sectional view taken along line A-A in Figure 1. Figure 3 is a cross-sectional view taken along line B-B in Figure 1. Figure 4 is a cross-sectional view taken along line C-C in Figure 1. Figure 5 is a plan view of a semiconductor device in a comparative form. Figure 6 is a plan view of a semiconductor device in the second embodiment. Figure 7 is a cross-sectional view taken along line A-A in Figure 6. Figure 8 is a plan view of a semiconductor device in the third embodiment. Figure 9 is an enlarged plan view of gate wirings 15A and 15B in the third embodiment. Figure 10 is a plan view of a semiconductor device in a modification 1 of the third embodiment. Figure 11 is a plan view of a semiconductor device in the fourth embodiment. Figure 12 is a plan view of a semiconductor device in the fifth embodiment. Figure 13 is a cross-sectional view taken along line A-A in Figure 12. Figure 14 is a plan view of a semiconductor device in the sixth embodiment. Figure 15 is a cross-sectional view taken along line A-A in Figure 14. Figure 16 is a cross-sectional view taken along line B-B in Figure 14. Figure 17 is a plan view of a semiconductor device in the seventh embodiment. Figure 18 is a plan view of a semiconductor device in the eighth embodiment.

[0008] Connecting a resistor in series to the gate electrode can stabilize the operation of a transistor. However, when multiple transistors are arranged in the direction of electrode extension, it is difficult to appropriately provide the resistors connected to the gate electrode of each transistor.

[0009] This disclosure aims to provide a semiconductor device that allows for the appropriate provision of a resistor connected to the gate electrode.

[0010] According to this disclosure, it is possible to provide a semiconductor device that allows for the appropriate provision of a resistor connected to the gate electrode.

[0011] [Description of Embodiments of the Disclosure] First, embodiments of the Disclosure will be listed and described.

[0012] (1) Embodiments of the present disclosure are semiconductor devices comprising: a substrate having a main surface and a back surface facing the main surface; a first transistor provided on the main surface and comprising a first source electrode, a first drain electrode, and a first gate electrode sandwiched between the first source electrode and the first drain electrode; a second transistor provided on the main surface and comprising a second source electrode electrically connected to the first source electrode, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode sandwiched between the second source electrode and the second drain electrode; a first gate wiring provided on the main surface and electrically connected to the first gate electrode and the second gate electrode; a gate bus line provided on the main surface; and a second gate wiring provided between the gate bus line and the first gate wiring on the main surface, electrically connecting the gate bus line and the first gate wiring, and having a width smaller than the width of the first gate wiring. This makes it possible to appropriately provide resistors connected to the first gate electrode and the second gate electrode. (2) In (1) above, a first source connection wiring may be provided on the main surface, electrically connected to the first source electrode, and provided between the gate bus line and the first transistor. This reduces the inductance of the second gate wiring. (3) In (2) above, a back metal layer may be provided on the back surface, electrically connected to the first source connection wiring via via holes that overlap with the first source connection wiring when viewed from the thickness direction of the substrate. This reduces the inductance of the second gate wiring. (4) In (2) or (3) above, a third transistor may be provided on the main surface, comprising a third source electrode provided on the main surface and electrically connected to the first source connection wiring, a third drain electrode, and a third gate electrode sandwiched between the third source electrode and the third drain electrode, a third gate wiring provided on the main surface and electrically connected to the third gate electrode, and a fourth gate wiring provided on the main surface between the gate bus line and the third gate wiring, with a width smaller than the width of the third gate wiring. This reduces the mutual inductance between the second gate wiring and the fourth gate wiring.(5) In (4) above, the second gate wiring and the fourth gate wiring may be separated by the first source connection wiring. This reduces the mutual inductance between the second gate wiring and the fourth gate wiring. (6) In any of (2) to (5) above, a fourth transistor is provided on the main surface and comprises a fourth source electrode, a fourth drain electrode, and a fourth gate electrode sandwiched between the fourth source electrode and the fourth drain electrode and electrically connected to the first gate wiring, and a second source connection wiring is provided on the main surface, electrically connected to the fourth source electrode, and provided between the gate bus line and the fourth transistor, wherein the second gate wiring may be provided between the first source connection wiring and the second source connection wiring. This reduces the inductance of the second gate wiring. (7) In any of (2) to (6) above, the second gate wiring may be meander-shaped with a first protrusion protruding in the protruding direction. This reduces the inductance of the second gate wiring. (8) In (7) above, the second gate wiring may further have a second protrusion that protrudes in the opposite direction to the protrusion direction. This allows for miniaturization. (9) In (7) or (8), the first protrusion may protrude toward the first source connection wiring. This allows for a reduction in the inductance of the second gate wiring. (10) In any of (1) to (9) above, a gate pad may be provided on the second gate wiring with an insulating layer in between. This allows for a reduction in the inductance of the second gate wiring. It also allows for miniaturization. (11) In any of (1) to (10) above, the first gate wiring has a first metal layer and a second metal layer laminated on the first metal layer, and the second gate wiring may have the first metal layer but not the second metal layer. This allows for a reduction in the difference between the resistance value of the resistor between the first gate electrode and the gate bus line and the resistance value of the resistor between the second gate electrode and the gate bus line.(12) Embodiments of the present disclosure are semiconductor devices comprising: a substrate having a main surface and a back surface facing the main surface; a transistor provided on the main surface and comprising a plurality of source electrodes and a plurality of drain electrodes, and a plurality of gate electrodes, each sandwiched between one of the plurality of source electrodes and one of the plurality of drain electrodes; a first gate wiring provided on the main surface and electrically connecting at least two of the plurality of gate electrodes; a gate bus line provided on the main surface; and a second gate wiring provided between the gate bus line and the first gate wiring on the main surface, electrically connecting the gate bus line and the first gate wiring, and having a width of five times or less the width of the plurality of gate electrodes. This allows for the appropriate provision of a resistor connected to the gate electrode. (13) In (12) above, a source connection electrode provided on the main surface and electrically connected to the plurality of source electrodes, and provided between the gate bus line and the transistor, may be provided. This reduces the inductance of the second gate wiring. (14) In (13) above, a back metal layer may be provided on the back surface and electrically connected to the source connection electrode via a via hole that overlaps with the source connection electrode when viewed from the thickness direction of the substrate. This reduces the inductance of the second gate wiring. (15) In any of (12) to (14) above, the second gate wiring may be meander-shaped with a first convex portion protruding in the protruding direction. This reduces the inductance of the second gate wiring. (16) In (15) above, the second gate wiring may further have a second convex portion protruding in the opposite direction to the protruding direction. This allows for miniaturization. (17) In any of (12) to (16) above, a gate pad may be provided on the second gate wiring with an insulating layer in between. This reduces the inductance of the second gate wiring and allows for miniaturization. (18) In any of (12) to (17) above, the second gate wiring may be formed from the same material as the plurality of gate electrodes. This simplifies the manufacturing process and allows for higher resistance in the second gate wiring.

[0013] [Details of Embodiments of the Disclosure] Specific examples of semiconductor devices according to embodiments of the Disclosure will be described below with reference to the drawings. However, the Disclosure is not limited to these examples and is intended to include all modifications within the meaning and scope of the Claims, as indicated by the Claims.

[0014] (First Embodiment) A semiconductor device used in a mobile communication base station, for example, as an amplifier for amplifying high-frequency signals from 0.5 GHz to 20 GHz, will be described as an example. Figure 1 is a plan view of the semiconductor device in the first embodiment. Figures 2 to 4 are cross-sectional views taken along A-A, B-B, and C-C in Figure 1, respectively. The thickness direction of the substrate 10 is the Z direction, the extension direction of the finger-shaped source electrode 12, gate electrode 14, and drain electrode 16 is the Y direction, and the arrangement direction of the source electrode 12, gate electrode 14, and drain electrode 16 is the X direction. Note that in plan views such as Figure 1, the source metal layer 22A and source wiring layer 22B, the drain metal layer 26A and drain wiring layer 26B, and the gate metal layer 25A and gate wiring layer 25B become difficult to see when they overlap. Therefore, thick lines showing only the outer periphery of the source wiring layer 22B, drain wiring layer 26B, and gate wiring layer 25B are illustrated inside the source metal layer 22A, drain metal layer 26A, and gate metal layer 25A, respectively. The same applies to the following diagrams.

[0015] In each figure, the active region 11, source electrode 12, gate electrode 14, drain electrode 16, and transistor 35 (unit FET) represent general elements. The active regions 11A and 11B, source electrodes 12A to 12E, gate electrodes 14A to 14E, drain electrodes 16A to 16C, and transistors 35A to 35E represent specific elements included in the general elements. In the following, transistors 35A to 35E will be mainly explained using the active regions 11A and 11B, source electrodes 12A to 12E, gate electrodes 14A to 14E, drain electrodes 16A to 16C, gate wiring 15A, 15B, 17A to 17E, 24A, and 24B.

[0016] As shown in Figures 1 to 4, the semiconductor device 100 of the first embodiment comprises a substrate 10, transistors 35A to 35E, gate wirings 15A, 15B, 17A to 17E, 24A, 24B, a metal layer 28, a gate bus line 34, and a drain bus line 36. The substrate 10 has a main surface 50 and a back surface 52 facing the main surface 50. The transistors 35A to 35E, gate wirings 15A, 15B, 17A to 17E, 24A, 24B, the gate bus line 34, and the drain bus line 36 are provided on the main surface 50 of the substrate 10.

[0017] In the Y direction, the drain bus line 36 and the gate bus line 34 are provided on the main surface 50, sandwiching transistors 35A to 35D.

[0018] The transistors 35 closest to the drain bus line 36 are transistors 35A and 35C. The transistors 35 closer to the gate bus line 34 than transistors 35A and 35C are transistors 35B and 35D. In the Y direction, there is one transistor 35A and three transistors 35C. The number of transistors 35B is one or more, and the number of transistors 35D is one or more.

[0019] The substrate 10 comprises a substrate 10A and a semiconductor layer 10B provided on the substrate 10A. In the XY plane parallel to the X and Y directions, the region of the semiconductor layer 10B that has been deactivated by ion implantation or the like is the inactive region 13, and the regions that have not been deactivated (i.e., a part of the substrate 10 or an activated region) are the active regions 11A and 11B. Transistors 35A and 35C are provided in the active region 11A. Transistors 35B and 35D are provided in the active region 11B.

[0020] Transistor 35A (second transistor) comprises a source electrode 12A (second source electrode), a gate electrode 14A (second gate electrode), and a drain electrode 16A (second drain electrode). The source electrode 12A and the drain electrode 16A sandwich the gate electrode 14A in the X direction. The source electrode 12A, the gate electrode 14A, and the drain electrode 16A are arranged sequentially in the positive direction of the X direction.

[0021] Transistor 35B (first transistor) comprises a source electrode 12B (first source electrode), a gate electrode 14B (first gate electrode), and a drain electrode 16B (first drain electrode). The source electrode 12B and the drain electrode 16B sandwich the gate electrode 14B in the X direction. The source electrode 12B is located inside the source electrode 12A when viewed from the Y direction. That is, the source electrode 12B is not located outside the source electrode 12A when viewed from the Y direction. The drain electrode 16B overlaps the drain electrode 16A when viewed from the Y direction. The source electrode 12B, gate electrode 14B, and drain electrode 16B are arranged sequentially in the + direction of the X direction.

[0022] Transistor 35C comprises a source electrode 12C, a gate electrode 14C, and a drain electrode 16A. The drain electrode 16A is shared by transistors 35A and 35C. The source electrode 12C and the gate electrode 14A are sandwiched between the drain electrode 16A. The gate electrode 14C is sandwiched between the source electrode 12C and the drain electrode 16A in the X direction. The source electrode 12C, the gate electrode 14C, and the drain electrode 16A are arranged sequentially in the negative direction of the X direction.

[0023] Transistor 35D (third transistor) comprises a source electrode 12D (third source electrode), a gate electrode 14D (third gate electrode), and a drain electrode 16B (third drain electrode). The drain electrode 16B is shared by transistors 35B and 35D. The drain electrode 16B is sandwiched between the source electrode 12D and the gate electrode 14B. The gate electrode 14D is sandwiched between the source electrode 12D and the drain electrode 16B in the X direction. The source electrode 12D is located inside the source electrode 12C when viewed from the Y direction. That is, when viewed from the Y direction, the source electrode 12D is not located outside the source electrode 12C. The source electrode 12D, gate electrode 14D, and drain electrode 16B are arranged sequentially in the negative direction of the X direction.

[0024] Transistor 35E (the fourth transistor) comprises a source electrode 12E (the fourth source electrode), a gate electrode 14E (the fourth gate electrode), and a drain electrode 16C (the fourth drain electrode). The drain electrode 16B is shared by transistors 35B and 35E. The gate electrode 14E is sandwiched between the source electrode 12E and the drain electrode 16C in the X direction. The source electrode 12E is located inside the source electrode 12A when viewed from the Y direction. That is, the source electrode 12E is not located outside the source electrode 12A when viewed from the Y direction. The source electrode 12E, the gate electrode 14E, and the drain electrode 16C are arranged sequentially in the negative direction of the X direction.

[0025] In the X direction, gate wirings 24A (first gate wiring) and 24B (third gate wiring), which extend in the Y direction, are provided on two inert regions 13 that sandwich transistors 35B and 35D, respectively. Gate wiring 24A is provided within the source electrode 12A when viewed from the Y direction. That is, when viewed from the Y direction, gate wiring 24A is not provided outside the source electrode 12A. Gate wiring 24B is provided within the source electrode 12C when viewed from the Y direction. That is, when viewed from the Y direction, gate wiring 24B is not provided outside the source electrode 12C.

[0026] In the Y direction, a gate wiring 15A (second gate wiring) extending in the Y direction is provided on the inert region 13 sandwiched between the gate wiring 24A and the gate bus line 34. The gate wiring 15A electrically connects the gate wiring 24A and the gate bus line 34. The positive end of the gate wiring 15A in the Y direction is connected to the negative end of the gate wiring 24A in the Y direction. The negative end of the gate wiring 15A in the Y direction is connected to the gate bus line 34.

[0027] In the Y direction, a gate wiring 15B (fourth gate wiring) extending in the Y direction is provided on the inert region 13 sandwiched between the gate wiring 24B and the gate bus line 34. The gate wiring 15B electrically connects the gate wiring 24B and the gate bus line 34. The positive end of the gate wiring 15B in the Y direction is connected to the negative end of the gate wiring 24B in the Y direction. The negative end of the gate wiring 15B in the Y direction is connected to the gate bus line 34.

[0028] A gate wiring 17A extending in the X direction is provided in the inert region 13 between transistors 35A and 35B in the Y direction. The gate wiring 17A intersects the source wiring layer 22B non-contactually and electrically connects the gate wiring 24A and the gate electrode 14A. A gate wiring 17B extending in the X direction is provided in the inert region 13 between the two transistors 35B in the Y direction. The gate wiring 17B intersects the source wiring layer 22B non-contactually and electrically connects the gate wiring 24A and the gate electrode 14B.

[0029] A gate wiring 17C extending in the X direction is provided in the inert region 13 between transistors 35C and 35D in the Y direction. The gate wiring 17C intersects the source wiring layer 22B non-contactually and electrically connects the gate wiring 24B and the gate electrode 14C. A gate wiring 17D extending in the X direction is provided in the inert region 13 between two transistors 35D in the Y direction. The gate wiring 17D intersects the source wiring layer 22B non-contactually and electrically connects the gate wiring 24B and the gate electrode 14D.

[0030] A gate wiring 17E extending in the X direction is provided in the inert region 13 between the two transistors 35E in the Y direction. The gate wiring 17E intersects the source wiring layer 22B non-contactually and electrically connects the gate wiring 24A and the gate electrode 14E.

[0031] The source electrodes 12A to 12E have a source metal layer 22A provided in contact with the substrate 10 and a source wiring layer 22B provided in contact with the source metal layer 22A. The source metal layers 22A of transistors 35A and 35B are separated from each other and are electrically connected via the source wiring layer 22B. The drain electrodes 16A to 16C have a drain metal layer 26A provided in contact with the substrate 10 and a drain wiring layer 26B provided in contact with the drain metal layer 26A. The drain metal layers 26A of transistors 35A and 35B are separated from each other and are electrically connected via the drain wiring layer 26B. The drain bus line 36 has a drain wiring layer 26B and does not have a drain metal layer 26A.

[0032] The gate electrodes 14A to 14E and gate wirings 15A, 15B, and 17A to 17E have a gate metal layer 25A provided in contact with the substrate 10, but do not have a gate wiring layer 25B. The gate wirings 24A, 24B and gate bus lines 34 have a gate metal layer 25A and a gate wiring layer 25B provided in contact with the gate metal layer 25A. The gate wirings 24A and 24B may have a gate metal layer 25A but not a gate wiring layer 25B.

[0033] An insulating layer 30 is provided on the substrate 10 so as to cover the transistors 35A to 35E, gate wirings 15A, 15B, 17A to 17E, 24A, 24B, gate bus line 34, and drain bus line 36.

[0034] The via holes 20A and 20C penetrate the substrate 10. When viewed from the Z direction, the via holes 20A and 20C overlap the source electrodes 12A and 12C, respectively, and are connected to the source electrodes 12A and 12C, respectively. A metal layer 28 is provided on the back surface 52 of the substrate 10. A metal layer 28A is provided on the inner surfaces of the via holes 20A and 20C. As a result, the metal layer 28 (backside metal layer) is electrically connected to the source electrodes 12A and 12C, respectively, via the via holes 20A and 20C, and short-circuited. The via holes 20 are not connected to the source electrodes 12B, 12D, and 12E. The planar shape of the via holes 20A and 20C may be elliptical, oblong, rounded rectangle, or circular.

[0035] The source potential (a reference potential such as ground potential) is supplied from the metal layer 28 to the source electrodes 12A and 12C via the metal layer 28A in the via holes 20A and 20C. Furthermore, the source potential is supplied to the source electrodes 12B, 12D, and 12E via the source wiring layer 22B.

[0036] The gate potential (e.g., high-frequency signal and gate bias voltage) is supplied from the gate bus line 34 to the gate electrode 14A via gate wirings 15A, 24A, and 17A. The gate potential is supplied from the gate bus line 34 to the gate electrode 14B via gate wirings 15A, 24A, and 17B. The gate potential is supplied from the gate bus line 34 to the gate electrode 14E via gate wirings 15A, 24A, and 17E. The gate potential is supplied from the gate bus line 34 to the gate electrode 14C via gate wirings 15B, 24B, and 17C. The gate potential is supplied from the gate bus line 34 to the gate electrode 14D via gate wirings 15B, 24B, and 17D.

[0037] The positive terminals in the Y direction of gate electrodes 14B and 14D are not connected to the negative terminals in the Y direction of gate electrodes 14A and 14B. The positive terminals in the Y direction of gate electrodes 14C and 14D may be connected to the negative terminals in the Y direction of gate electrodes 14A and 14B.

[0038] If the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10A may be, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al) substrate. ２ O ３The substrate is a gallium arsenide (GaAs) substrate. The semiconductor layer 10B includes a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, or an indium gallium nitride (InGaN) layer. When transistors 35A to 35D are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10B comprises a gallium nitride channel layer provided on the substrate 10A and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs) based semiconductor device, the substrate 10A is, for example, a gallium arsenide substrate. The semiconductor layer 10B includes an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may also be a silicon semiconductor device such as an LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0039] The source metal layer 22A and the drain metal layer 26A are, for example, a titanium film and an aluminum film from the substrate 10 side. The source metal layer 22A and the drain metal layer 26A are formed simultaneously, may be made of the same material and have the same film thickness. The gate metal layer 25A is, for example, a nickel film and a gold film from the substrate 10 side. The source wiring layer 22B, the drain wiring layer 26B and the gate wiring layer 25B are metal layers such as a gold layer, a copper layer or an aluminum layer. The source wiring layer 22B, the drain wiring layer 26B and the gate wiring layer 25B are formed simultaneously, may be made of the same material and have the same film thickness. The insulating layer 30 is, for example, an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer.

[0040] The width of the source metal layer 22A of source electrodes 12A and 12B in the X direction is, for example, 50 μm or more and 150 μm or less. The width of the source metal layer 22A of source electrodes 12B, 12D and 12E in the X direction is, for example, 5 μm or more and 20 μm or less. The gate length of gate electrodes 14A to 14D in the X direction is, for example, 0.25 μm or more and 2 μm or less. The width of the drain metal layer 26A of drain electrodes 16A to 16C in the X direction is, for example, 5 μm or more and 150 μm or less. The width of gate wirings 24A and 24B in the X direction is, for example, 5 μm or more and 20 μm or less. The width of gate wirings 17A to 17E in the Y direction is, for example, 3 μm or more and 20 μm or less. To reduce gate resistance, the width W1 of gate wirings 24A and 24B in the X direction is greater than the gate length, for example, twice the gate length or more. The width W1 of gate wirings 24A and 24B is, for example, 5 μm or more and 50 μm or less. The gate width in the Y direction of transistors 35A to 35E is, for example, 100 μm or more and 400 μm or less. The width in the X direction of via holes 20A, 20C, and 20E is, for example, 10 μm or more and 60 μm or less. The length L1 of gate wirings 15A and 15B is, for example, 50 μm or more and 200 μm or less. The width W2 of gate wirings 15A and 15B is, for example, 0.5 μm or more and 5 μm or less.

[0041] The widths of the source wiring layer 22B and the drain wiring layer 26B in the X direction are the same as, or slightly smaller than, the widths of the source metal layer 22A and the drain metal layer 26A in the X direction, respectively. The thickness of the source wiring layer 22B and the drain wiring layer 26B is, for example, 1 μm or more and 20 μm or less.

[0042] (Comparative Embodiment) Figure 5 is a plan view of a semiconductor device according to the comparative embodiment. As shown in Figure 5, the semiconductor device 110 according to the comparative embodiment does not have gate wirings 15A and 15B. Gate wirings 24A and 24B are directly connected to the gate bus line 34. The other configurations are the same as in the first embodiment.

[0043] There are cases where a resistor is connected in series to the gate electrode. For example, when the transistor is unstable, such as loop oscillation at the operating frequency, providing a resistor in series with the gate electrode in the input matching circuit allows the transistor to operate stably. Connecting the series resistor near the gate electrode can further stabilize the transistor.

[0044] In the semiconductor device 110 of the comparative form, when connecting a resistor in series to the gate electrode, it is conceivable to form a semiconductor resistor using the semiconductor layer 10B. For example, considering a transistor used in a 2 GHz amplifier circuit, the resistance value of the resistor connected in series to the gate electrode to stabilize the operation is, for example, 10 Ω per 1 mm of the gate width of the transistor. The sheet resistance of the semiconductor layer 10B is, for example, 500 Ω / □. By forming a semiconductor resistor using the semiconductor layer 10B, a resistance value of about 10 Ω can be realized. However, semiconductor resistors have large temperature characteristics of the resistance value and large manufacturing variations.

[0045] Therefore, it is conceivable to use a metal resistor such as the gate metal layer 25A for the resistor connected in series to the gate electrode. Considering mass productivity, the thickness of the gate metal layer 25A is about 1 μm, and the sheet resistance of the gate metal layer 25A is, for example, 0.1 Ω / □. To achieve 10 Ω with the gate metal layer 25A, the width:length ratio is about 1:100.

[0046] To provide a resistor near the gate electrodes 14A to 14D, it is considered to connect a resistor between the gate electrodes 14A to 14D and the gate bus line 34. For example, when the region 25C of the gate wiring 24A in FIG. 5 is a 10 Ω metal resistor using the gate metal layer 25A, the length of the metal resistor is 100 times the width W1 in the X direction of the gate wirings 24A and 24B. Assuming the width W1 is 50 μm, the length of the metal resistor is 5000 μm, and the semiconductor device becomes larger.

[0047] When the widths W1 of the gate wirings 24A and 24B in the X direction are reduced, the length of the metal resistance becomes smaller. Considering mass productivity, for example, the width W1 is set to 1 μm. In this case, the length of the metal resistance becomes 100 μm, and the semiconductor device can be miniaturized. However, when the widths W1 of the gate wirings 24A and 24B become smaller, the ratio of the resistance components of the gate wirings 24A and 24B among the resistance components connected to the gate electrodes 14A and 14C of the transistors 35A and 35C increases. For this reason, the resistance value of the resistance connected to the gate electrodes 14A and 14C becomes higher than the resistance value of the resistance connected to the gate electrodes 14B and 14D of the transistors 35B and 35D, which are closest to the gate bus line 34. In addition, the inductance between the gate wirings 24A and 24B and the gate bus line 34 becomes large. As a result, the signals output by the transistors 35A and 35C and the signals output by the transistors 35B and 35D become non-uniform, and high-frequency characteristics such as the output power or efficiency output from the drain bus line 36 as a whole deteriorate.

[0048] It is also conceivable to use the gate wirings 17A to 17D between the gate wirings 24A and 24B and the gate electrodes 14A to 14D as metal resistances respectively. However, when resistances are provided individually to the gate electrodes 14A to 14D, in order to achieve the same stability as when providing one resistance in the region 25C, the resistances obtained by connecting the individual resistances in parallel for the number of transistors need to be equivalent to the resistance provided in the region 25C. For this reason, the resistance value of each individual resistance needs to be increased by the number of transistors 35A to 35D. For example, when the resistance value when providing a resistance in the region 25C is 10 Ω, the resistance value of the resistances individually connected to the eight gate electrodes 14A to 14D becomes 80 Ω. For this reason, the area of the resistance becomes large, and the semiconductor device becomes large-sized. As described above, it is difficult to appropriately provide the resistances connected to the gate electrodes 14A to 14D.

[0049] (Description of the First Embodiment) As shown in Figures 1 to 4, in the semiconductor device 100 of the first embodiment, transistors 35A and 35B overlap when viewed from the Y direction. When viewed from the Y direction, the source electrode 12B and gate wiring 24A are provided within the source electrode 12A. The gate wiring 24A (first gate wiring) is electrically connected to the gate electrodes 14A, 14B and 14E. The gate wiring 15A (second gate wiring) is electrically connected to the gate wiring 24A and the gate bus line 34. As a result, the gate wiring 15A can be used as a resistor without using a semiconductor resistor. Metal resistors have smaller temperature characteristics and less manufacturing variation compared to semiconductor resistors. Therefore, the temperature change and manufacturing variation of the resistance value of the resistor connected from gate electrode 14A to 14E can be reduced. Furthermore, since gate wiring 15A is provided in common to gate electrodes 14A, 14B, and 14E, the target resistance value can be lowered compared to the case where resistors are provided individually to gate electrodes 14A, 14B, and 14E, and the semiconductor device can be miniaturized.

[0050] The width W2 of the gate wiring 15A is made smaller than the width W1 of the gate wiring 24A. By making the width W2 smaller, the resistance value of the gate wiring 15A can be increased, so that the resistance connected to the gate electrodes 14A, 14B, and 14E can be formed in a small area using the gate wiring 15A. By making the width W1 larger, the resistance value and inductance of the gate wiring 24A can be sufficiently lowered. Therefore, the resistance value of the resistor connected to the gate electrode 14A can be made to be about the same as the resistance value of the resistors connected to the gate electrodes 14B and 14E. In addition, the inductance added to the gate electrode 14A can be reduced. In this way, the resistors connected to the gate electrodes 14A, 14B, and 14E can be appropriately provided. From the viewpoint of making the resistance value of the gate wiring 15A higher and the resistance value of the gate wiring 24A lower, the width W2 can be 1 / 2 or less of the width W1, or 1 / 5 or less.

[0051] Furthermore, transistors 35C and 35D share drain electrodes 16A and 16B with transistors 35A and 35B, respectively. Transistors 35C and 35D overlap when viewed from the Y direction. When viewed from the Y direction, the source electrode 12D and gate wiring 24B are located within the source electrode 12C. The gate wiring 24B (second gate wiring) is electrically connected to the gate electrodes 14C and 14D. The gate wiring 15B (fourth gate wiring) is electrically connected to the gate bus line 34. This allows a resistance to be formed using a metal layer, thereby reducing the temperature characteristics of the resistance value connected to the gate electrodes 14C and 14D, and reducing manufacturing variations in the resistance value. In addition, the width W2 of gate wiring 15B is smaller than the width W1 of gate wiring 24B. This allows the resistance value of gate wiring 15B to be increased, and the resistance value and inductance of gate wiring 24B to be reduced. This allows for the appropriate provision of resistance connected to gate electrodes 14C and 14D.

[0052] Gate wiring 15A is sandwiched between gate wiring 24A and gate bus line 34 in the Y direction, and gate wiring 15B is sandwiched between gate wiring 24B and gate bus line 34 in the Y direction. This allows gate wiring 15A to be connected between gate electrodes 14A and 14B and gate bus line 34, and gate wiring 15B to be connected between gate electrodes 14C and 14D and gate bus line 34.

[0053] As shown in Figure 3, gate wirings 24A and 24B have a gate metal layer 25A (first metal layer) and a gate wiring layer 25B (second metal layer) laminated on the gate metal layer 25A. As shown in Figure 4, gate wirings 15A and 15B have a gate metal layer 25A but no gate wiring layer 25B. This makes it possible to lower the resistance of gate wirings 24A and 24B and increase the resistance of gate wirings 15A and 15B. From the viewpoint of lowering the resistance of gate wirings 24A and 24B and increasing the resistance of gate wirings 15A and 15B, the resistance per unit cross-sectional area of ​​the gate wiring layer 25B can be made smaller than the resistance per unit cross-sectional area of ​​the gate metal layer 25A. Also, the thickness TA of the gate metal layer 25A can be made smaller than the thickness TB of the gate wiring layer 25B. The thickness TA can be 1 / 2 or less of the thickness TB, and can also be 1 / 5 or less. The thickness TA is, for example, 0.2 μm or more and 2 μm or less. The thickness TB is, for example, 1 μm or more and 20 μm or less.

[0054] (Second Embodiment) Figure 6 is a plan view of a semiconductor device according to the second embodiment. Figure 7 is a cross-sectional view taken along line A-A in Figure 6. As shown in Figures 6 and 7, in the semiconductor device 101 of the second embodiment, source connection wiring 23A is provided on an inert region 13 between transistors 35B and 35D and gate bus line 34 in the Y direction and between gate wirings 15A and 15B in the X direction. In the X direction, source connection wiring 23B is provided so as to sandwich the gate wiring 15A between source connection wiring 23A and 23B. Source connection wiring 23A and 23B have a source metal layer 22A and a source wiring layer 22B.

[0055] The via hole 20E overlaps with the source connection wiring 23A when viewed from the Z direction and is connected to the source connection wiring 23A. The metal layer 28 is electrically connected to the source connection wiring 23A via the via hole 20E and short-circuited. The other configurations are the same as in the first embodiment and will not be described.

[0056] In the semiconductor device 100 of the first embodiment, when the length L1 of each gate wiring 15A and 15B is 120 μm, the self-inductance of each gate wiring 15A and 15B is 0.14 nH. Furthermore, the direction of the current flowing through gate wirings 15A and 15B is the same. Therefore, the mutual inductance between gate wirings 15A and 15B increases. As a result, the inductance due to gate wirings 15A and 15B becomes larger.

[0057] In the semiconductor device 101 of the second embodiment, the source connection wiring 23A (first source connection wiring) is provided between the gate bus line 34 and the transistor 35B. This reduces the inductance of the gate wiring 15A.

[0058] The source connection wiring 23A is sandwiched between the gate wirings 15A and 15B in the X direction, electrically connecting the source electrodes 12B and 12D. This allows the source connection wiring 23A to shield the space between the gate wirings 15A and 15B, thereby reducing the mutual inductance between the gate wirings 15A and 15B. From the viewpoint of reducing mutual inductance, the length L2 of the source connection wiring 23A in the Y direction can be 0.3 times or more the distance D1 between the gate wirings 24A and 24B and the gate bus line 34, and can be 0.5 times or more. Also, the width W3 of the source connection wiring 23A in the X direction can be 0.3 times or more the distance D2 between it and the gate wirings 24A and 24B, and can be 0.5 times or more.

[0059] The source connection wiring 23B (second source connection wiring) is electrically connected to the source electrode 12E and is provided between the gate bus line 34 and the transistor 35E. The gate wiring 15A is provided between the source connection wirings 23A and 23B. This reduces the inductance of the gate wiring 15A.

[0060] The metal layer 28 (backside metal layer) is electrically connected to the source connection wiring 23A via the via hole 20E. By providing the via hole 20E between the gate wirings 15A and 15B in this way, the via hole 20E shields the space between the gate wirings 15A and 14B, thereby further reducing the mutual inductance between the gate wirings 15A and 14B. From the viewpoint of reducing mutual inductance, the width L3 of the via hole 20E in the Y direction can be 0.2 times or more the distance D1, and can be 0.4 times or more. The longitudinal direction of the via hole 20E may be other than the X direction, for example, the Y direction. The width of the via hole 20E in the Y direction can be 0.1 times or more the distance D1, and can be 0.3 times or more.

[0061] The metal layer 28 is electrically connected to the source electrodes 12A and 12C via via holes 20A and 20C, respectively. This allows a reference potential to be supplied to the source electrodes 12B and 12D via via holes 20A, 20C, and 20E. Thus, the source resistance and source inductance can be reduced. From the viewpoint of reducing the mutual inductance between gate wiring 15A and 15B, the width L3 in the Y direction of via hole 20E may be larger than the width of via holes 20A and 20C in the Y direction.

[0062] (Third Embodiment) Figure 8 is a plan view of the semiconductor device according to the third embodiment. As shown in Figure 8, in the semiconductor device 102 of the third embodiment, the gate wirings 15A and 15B are meander-shaped. The other configurations are the same as in the first embodiment and will not be described.

[0063] Figure 9 is an enlarged plan view of gate wiring 15A and 15B in the third embodiment. When the gate wiring 15A and 15B proceed from the gate bus line 34 toward the gate wiring 24A and 24B, they have a portion 55A that moves in the +Y direction, a portion 55B that moves in the +X direction, a portion 55C that moves in the +Y direction, a portion 55D that moves in the -X direction, and a portion 55E that moves in the Y direction.

[0064] Let the self-inductances of sections 55A to 55E be LA to LE, respectively. Sections 55B and 55D are adjacent, and a mutual inductance occurs between sections 55B and 55D. The direction of the current flowing through section 55B is 54A, and the direction of the current flowing through section 55D is 54B, which are opposite. As a result, the magnetic field generated by section 55B and the magnetic field generated by section 55D cancel each other out, so the mutual inductance M between sections 55B and 55D acts negatively. Therefore, the inductance L of gate wirings 15A and 15B is L = LA + LB + LC + LD + LE - M, with M being positive. Increasing the mutual inductance M can decrease the inductance L. Note that AC current flows through gate wirings 15A and 15B, but the directions of the currents 54A and 54B are shown as an example.

[0065] Let the lengths of sections 55A to 55E be DA to DE, respectively. The lengths of gate wiring 15A and 15B are L1 = DA + DB + DC + DD + DE, respectively. From the viewpoint of increasing the mutual inductance M and decreasing the inductance L, the total length DB + DD of sections 55B and 55D can be 0.1 times or more the length L1, and can be 0.3 times or more. The length DC of section 55C (corresponding to the distance between sections 55B and 55D) can be 0.5 times or less the length D1, and can be 0.3 times or less.

[0066] The gate wiring 15A is meander-shaped, having a protruding portion 56A (first protrusion) in the +X direction (protruding direction). This reduces the inductance of the gate wiring 15A.

[0067] The protruding portion 56A in gate wiring 15A and the protruding portion 56B in gate wiring 15B may protrude in opposite directions in the X direction (for example, +X direction and -X direction). In this case, since portions 56A and 56B are close together, the mutual inductance between gate wiring 15A and 15B increases. From the viewpoint of reducing the mutual inductance between gate wiring 15A and 15B, portions 56A and 56B can protrude in the same +X direction. Furthermore, when viewed from the X direction, at least a part of portion 56A overlaps with at least a part of portion 56B. This makes it possible to reduce the mutual inductance between portion 55C of gate wiring 15A and gate wiring 15B.

[0068] (Modification 1 of the Third Embodiment) Figure 10 is a plan view of a semiconductor device according to Modification 1 of the Third Embodiment. As shown in Figure 10, in the semiconductor device 103 of Modification 1 of the Third Embodiment, the gate wirings 15A and 15B have portions 56A and 56B that protrude in the +X direction, respectively, and portions 56C and 56D that protrude in the -X direction, respectively. The other configurations are the same as in the Third Embodiment and will not be described.

[0069] By providing locations 56A and 56B (first protrusions) and locations 56C and 56D (second protrusions) that protrude in the -X direction (opposite direction to the protrusion direction), the inductance of the gate wirings 15A and 15B can be reduced. Multiple locations 56A and 56B may be provided for each of the gate wirings 15A and 15B. Multiple locations 56C and 56D may be provided for each of the gate wirings 15A and 15B.

[0070] If multiple locations 56A and 56C are provided in the gate wiring 15A, the total length of the portion of the gate wiring 15A extending in the X direction can be set to 0.1 times or more the length L1 of the gate wirings 15A and 15B, and can also be set to 0.3 times or more. This reduces the mutual inductance between the gate wirings 15A and 15B.

[0071] (Fourth Embodiment) Figure 11 is a plan view of a semiconductor device according to the fourth embodiment. As shown in Figure 11, the semiconductor device 104 of the fourth embodiment is provided with source connection wiring 23A and via holes 20E, and gate wirings 15A and 15B are meander-shaped. This allows for a further reduction in the inductance of gate wirings 15A and 15B. Other configurations are the same as those of the second and third embodiments and will not be described.

[0072] In order to make the gate wirings 15A and 15B meander-shaped, a portion of the source connection wiring 23A is removed compared to Figure 6 of the second embodiment. That is, the side 57A of the source connection wiring 23A facing location 56A in the X direction is further in the X direction than the side 57C of the source electrode 12B facing the gate wiring 24A in the X direction, and further than the gate wiring 24A. In other words, the source connection wiring 23A is recessed in the direction of the protrusion of location 56A. Also, the side 57B of the source connection wiring 23A facing location 56B in the X direction is further in the X direction than the side 57D of the source electrode 12B facing the gate wiring 24B in the X direction, and further than the gate wiring 24B. In other words, the source connection wiring 23B is recessed in the direction of the protrusion of location 56D. This makes it possible to miniaturize the semiconductor device 104.

[0073] From the standpoint of miniaturization, the distance D4 in the X direction between sides 57A and 57C and the distance D4 in the X direction between sides 57B and 57D can be 0.1 times or more, and can be 0.2 times or more, the distance D5 between source electrodes 12B and 12 that sandwich the gate wiring 24A.

[0074] In the fourth embodiment, an example was described in which gate wiring 15A has locations 56A and 56C, and gate wiring 15B has locations 56B and 56D. Gate wiring 15A may have location 56A but not location 56C, and gate wiring 15B may have location 56B but not location 56D.

[0075] (Fifth Embodiment) Figure 12 is a plan view of a semiconductor device according to the fifth embodiment. Figure 13 is a cross-sectional view taken along line A-A in Figure 12. As shown in Figures 12 and 13, in the semiconductor device 105 of the fifth embodiment, the gate pad 34B is provided with an insulating layer 30 sandwiched between the gate wirings 15A and 15B. The insulating layer 30 between the gate pad 34B and the gate wirings 15A and 15B is an inorganic insulating layer such as a silicon nitride layer or a silicon oxide layer. The gate pad 34B is electrically connected to the gate bus line 34A at the -Y end. The gate wirings 15A and 15B are electrically connected to the gate bus line 34A. The gate bus line 34A has a gate metal layer 25A and does not have a gate wiring layer 25B. The gate pad 34B has a gate wiring layer 25B and does not have a gate wiring layer 25B.

[0076] An opening 30A of the insulating layer 30 is provided on the gate bus line 34A. A bonding wire 29, which is electrically connected to the gate pad 34B, is joined to the opening 30A. Current flows from the bonding wire 29 to the gate pad 34B. The direction of the current in the gate pad 34B is -Y direction 54C, and the direction of the current flowing through the gate wiring 15A is +Y direction 54D. As a result, the magnetic field is canceled out by the current flowing through the gate wiring 15A, so the inductance of the gate wiring 15A can be reduced. In addition, since the gate wirings 15A and 15B and the gate pad 34B overlap when viewed from the Z direction, the semiconductor device can be miniaturized.

[0077] The bonding wire 29 may be joined in the area between gate wirings 15A and 15B to avoid directly above them. Gate wirings 15A and 15B may be meander-shaped.

[0078] In the first to fifth embodiments, examples were described in which three transistors 35B and 35D are each arranged in the Y direction. However, transistors 35B and 35D may be arranged in the Y direction in units of one, two, or four or more. An example was described in which four transistors 35A and 35C are arranged in the X direction, and four transistors 35B and 35D are arranged in the X direction. Transistors 35A and 35C may be arranged in units of five or more in the X direction, and transistors 35B and 35D may be arranged in units of five or more in the X direction.

[0079] (Sixth Embodiment) The sixth embodiment is an example of a multi-finger type transistor. Figure 14 is a plan view of the semiconductor device in the sixth embodiment. Figures 15 and 16 are cross-sectional views taken along A-A and B-B in Figure 14, respectively.

[0080] As shown in Figures 14 to 16, the semiconductor device 106 of the sixth embodiment comprises a substrate 10, transistors 35, gate wiring 15 and 17, source wiring 24, a metal layer 28, a gate bus line 34, and a drain bus line 36. The substrate 10 has a main surface 50 and a back surface 52 facing the main surface 50. The transistors 35, gate wiring 15 and 17, source wiring 24, gate bus line 34, and drain bus line 36 are provided on the main surface 50 of the substrate 10.

[0081] The transistors 35 are arranged in the X direction on the active region 11. Each transistor 35 comprises a source electrode 12A or 12B, a gate electrode 14, and a drain electrode 16. The multiple source electrodes 12A or 12B and the multiple drain electrodes 16 are arranged alternately in the X direction. The multiple gate electrodes 14 are each sandwiched between one of the multiple source electrodes 12A or 12B and one of the multiple drain electrodes 16.

[0082] Source electrode 12A is electrically connected to the metal layer 28 via a via hole 20A and short-circuited. Source electrode 12B is not connected to the via hole 20A. Source wiring 24 extends in the X direction and crosses the gate electrode 14 non-contactingly on the inert region 13 outside the active region 11, electrically connecting and short-circuiting source electrodes 12A and 12B. Multiple drain electrodes 16 are electrically connected in common to the drain bus line 36 and short-circuited.

[0083] The gate wiring 17 extends in the X direction and electrically connects and short-circuits multiple gate electrodes 14 on the inert region 13 outside the active region 11. The gate wiring 15 is provided on the inert region 13 between the gate bus line 34 and the gate wiring 17 and electrically connects and short-circuits the gate bus line 34 and the gate wiring 17.

[0084] The source potential (e.g., a reference potential such as ground potential) is supplied from the metal layer 28 to the source electrode 12A via the metal layer 28A in the via hole 20A. Furthermore, the source potential is supplied to the source electrode 12B via the source wiring 24. The gate potential (e.g., a high-frequency signal and gate bias voltage) is supplied from the gate bus line 34 to the gate electrode 14 via the gate wirings 15 and 17.

[0085] The source electrodes 12A and 12B have a source metal layer 22A provided in contact with the substrate 10 and a source wiring layer 22B provided in contact with the source metal layer 22A. The drain electrode 16 has a drain metal layer 26A provided in contact with the substrate 10 and a drain wiring layer 26B provided in contact with the drain metal layer 26A. The source wiring 24 has a source wiring layer 22B but does not have a source metal layer 22A. The drain bus line 36 has a drain wiring layer 26B but does not have a drain metal layer 26A.

[0086] The gate electrode 14, gate wiring 15 and 17 have a gate metal layer 25A provided in contact with the substrate 10, but do not have a gate wiring layer 25B. The gate bus line 34 has a gate metal layer 25A and a gate wiring layer 25B provided in contact with the gate metal layer 25A. The dimensions and materials of each component may be the same as in the first embodiment. Other configurations are the same as in the first embodiment and will not be described.

[0087] (Second comparative form) In order to connect a resistor in series with the gate electrode 14, it is conceivable to provide gate wiring connecting the gate electrode 14 and the gate bus line 34 for each gate electrode 14. However, in the case of a transistor used in a 2GHz amplifier circuit, if gate wiring having the same width as the gate electrode 14 is used, the length of the gate wiring will be 480 μm as an example. If gate wiring of 480 μm length is provided in a straight line, the self-inductance will be 0.56 nH. When multiple gate wirings are adjacent, the direction of the current flowing through the multiple gate wirings is the same, so the mutual inductance becomes large. Also, if the length and width vary from gate wiring to gate wiring, the phase difference between gate wirings will become large.

[0088] (Description of the sixth embodiment) According to the sixth embodiment, the gate wiring 17 (first gate wiring) electrically connects at least two of the plurality of gate electrodes 14. The gate wiring 15 (second gate wiring) is provided between the gate bus line 34 and the gate wiring 17, and electrically connects the gate bus line 34 and the gate wiring 17. In this way, at least two gate electrodes 14 are used together as the gate wiring 15. This makes it possible to lower the target resistance value compared to the case where resistors are individually provided for each gate electrode 14, and to miniaturize the semiconductor device.

[0089] For example, when gate wiring 15 is provided in common to four gate electrodes 14, the resistance of one gate wiring 15 can be 1 / 4 of the resistance of one gate wiring in the second comparison configuration. Therefore, the length L1 of the gate wiring 15 can be shortened. This reduces the self-inductance of the gate wiring 15. Also, the spacing between the gate wirings 15 in the X direction can be widened. This reduces the mutual inductance. Furthermore, by providing gate wiring 15 in common to multiple gate electrodes 14, the phase difference between the gate electrodes 14 can be reduced.

[0090] By reducing the width W2 of the gate wiring 15, the resistance of the gate wiring 15 can be increased. From this viewpoint, the width W2 of the gate wiring 15 can be 5 times or less, 4 times or less, or 2 times or less, the width W4 of the gate electrode 14 in the X direction. This allows for the appropriate amount of resistance to be connected to the gate electrode 14. If the width W2 is too small, it becomes difficult to process the gate wiring 15 and the variation in width W2 increases. From this viewpoint, the width W2 can be set to 0.5 times or more the width W4.

[0091] When there are many gate electrodes 14 sharing a single gate wire 15, the resistance value of a single gate wire 15 may be low. For this reason, the width W2 of the gate electrode 14 may be increased. Therefore, when the number of gate electrodes 14 sharing a single gate wire 15 is N, the width W2 may be less than or equal to N times the width W4 of the gate electrode.

[0092] When there are many gate electrodes 14 sharing a single gate trace 15, the phase difference between the gate electrodes 14 tends to increase. From this perspective, the number of gate electrodes 14 sharing a single gate trace 15 can be limited to eight or fewer.

[0093] The gate wiring 15 may be formed from the same material as the multiple gate electrodes 14. The thickness of the gate wiring 15 may also be the same as the thickness of the multiple gate electrodes 14. This simplifies the manufacturing process and increases the resistance of the gate wiring 15.

[0094] (Seventh Embodiment) Figure 17 is a plan view of the semiconductor device in the seventh embodiment. As shown in Figure 17, in the semiconductor device 107 of the seventh embodiment, the gate wiring 15 may be meander-shaped with a protruding portion 56A (first protrusion) in the +X direction (protruding direction). This makes it possible to reduce the inductance of the gate wiring 15, as described in the third embodiment.

[0095] Furthermore, the gate wiring 15 may have a portion 56C (second protrusion) that protrudes in the opposite direction to the protrusion direction of portion 56A. This makes it possible to reduce the inductance of the gate wiring 15, as described in Modification 1 of the third embodiment.

[0096] From the viewpoint of reducing the mutual inductance of adjacent gate wirings 15, the locations 56A of adjacent gate wirings 15 can protrude in the same +X direction. Furthermore, when viewed from the X direction, at least a portion of location 56A overlaps with at least a portion of the adjacent location 56A. This makes it possible to reduce the mutual inductance between adjacent gate wirings 15. The example dimensions and material examples of each component may be the same as those of the third embodiment and modification 1. The other configurations are the same as those of the sixth embodiment and will not be described.

[0097] (Eighth Embodiment) Figure 18 is a plan view of the semiconductor device in the eighth embodiment. As shown in Figure 18, in the semiconductor device 108 of the eighth embodiment, a source connection electrode 23 may be provided on the main surface 50 between the gate wirings 15. The source connection electrode 23 may be electrically connected to the source electrode 12A and short-circuited. This makes it possible to reduce the mutual inductance of the gate wirings 15, as described in the second embodiment.

[0098] The source connection electrode 23 is electrically connected to the metal layer 28 via the via hole 20C and may be short-circuited. This reduces the mutual inductance of the gate wiring 15, as described in the second embodiment. The dimensions and materials of each component may be the same as in the second embodiment. The other configurations are the same as in the seventh embodiment and will not be described.

[0099] In the sixth to eighth embodiments, a gate pad may be provided on the gate wiring 15 with an insulating layer in between, as in the fifth embodiment. The dimensions and materials of each component may be the same as in the fifth embodiment.

[0100] In the sixth to eighth embodiments, an example was described in which eight transistors 35 were arranged in the X direction. The transistors 35 may be arranged in two to seven or nine or more locations in the X direction.

[0101] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications within the sense and scope equivalent to the claims are intended to be included. It should be understood that at least one configuration or feature described in each embodiment and example can be combined with or modified in other embodiments and examples.

[0102] 10, 10A Substrate 10B Semiconductor layer 11, 11A, 11 Active region 12, 12A (second source electrode), 12B (first source electrode), 12C, 12D (third source electrode), 12E (fourth source electrode) Source electrode 13 Inactive region 14, 14A (second gate electrode), 14B (first gate electrode), 14C, 14D (third gate electrode), 14E (fourth gate electrode) Gate electrode 15 (second gate wiring), 15A (second gate wiring), 15B (fourth gate wiring), 17 (first gate wiring), 17A, 17B, 17C, 17D, 17E, 24A (first gate wiring), 24B (third gate wiring) Gate wiring 16, 16A (first drain electrode, second drain electrode), 16B (third drain electrode), 16C (fourth drain electrode) Drain electrode 20, 20A, 20C, 20E Via holes 22A Source metal layer 22B Source wiring layer 23 Source connection electrodes 23A (first source connection wiring), 23B (second source connection wiring) Source connection wiring 24 Source wiring 25A Gate metal layer 25B Gate wiring layer 26A Drain metal layer 26B Drain wiring layer 28 (backside metal layer), 28A Metal layer 29 Bonding wire 30 Insulation layer 30A Opening 34, 34A Gate bus line 34B Gate pad 35, 35A (second transistor), 35B (first transistor), 35C, 35D (third transistor), 35E (fourth transistor) Transistor 36 Drain bus line 50 Main surface 52 Backside 55A, 55B, 55C, 55D, 55E section Locations 56A, 56B (first protrusion), 56C, 56D (second protrusion) Sides 57A, 57B, 57C, 57D 100, 101, 102, 103, 104, 105, 106, 107, 108, 110 Semiconductor

Claims

1. A semiconductor device comprising: a substrate having a main surface and a back surface facing the main surface; a first transistor provided on the main surface and comprising a first source electrode, a first drain electrode, and a first gate electrode sandwiched between the first source electrode and the first drain electrode; a second transistor provided on the main surface and comprising a second source electrode electrically connected to the first source electrode, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode sandwiched between the second source electrode and the second drain electrode; a first gate wiring provided on the main surface and electrically connected to the first gate electrode and the second gate electrode; a gate bus line provided on the main surface; and a second gate wiring provided between the gate bus line and the first gate wiring on the main surface, electrically connecting the gate bus line and the first gate wiring, and having a width smaller than the width of the first gate wiring.

2. The semiconductor device according to claim 1, further comprising a first source connection wiring provided on the main surface, electrically connected to the first source electrode, and provided between the gate bus line and the first transistor.

3. The semiconductor device according to claim 2, further comprising a back metal layer provided on the back surface and electrically connected to the first source connection wiring via via holes that overlap with the first source connection wiring when viewed from the thickness direction of the substrate.

4. The semiconductor device according to claim 2, comprising: a third transistor provided on the main surface and electrically connected to the first source connection wiring, a third drain electrode, and a third gate electrode sandwiched between the third source electrode and the third drain electrode; a third gate wiring provided on the main surface and electrically connected to the third gate electrode; and a fourth gate wiring provided on the main surface between the gate bus line and the third gate wiring, having a width smaller than the width of the third gate wiring.

5. The semiconductor device according to claim 4, wherein the second gate wiring and the fourth gate wiring sandwich the first source connection wiring.

6. A semiconductor device according to any one of claims 2 to 5, comprising: a fourth transistor provided on the main surface and comprising a fourth source electrode, a fourth drain electrode, and a fourth gate electrode sandwiched between the fourth source electrode and the fourth drain electrode and electrically connected to the first gate wiring; and a second source connection wiring provided on the main surface and electrically connected to the fourth source electrode, and provided between the gate bus line and the fourth transistor, wherein the second gate wiring is provided between the first source connection wiring and the second source connection wiring.

7. The semiconductor device according to any one of claims 2 to 6, wherein the second gate wiring is meander-shaped and has a first protrusion that protrudes in the protruding direction.

8. The semiconductor device according to claim 7, wherein the second gate wiring further has a second protrusion that protrudes in the direction opposite to the protrusion direction.

9. The semiconductor device according to claim 7 or claim 8, wherein the first protrusion protrudes toward the first source connection wiring, and the first source connection wiring is recessed in the direction of the protrusion.

10. The semiconductor device according to any one of claims 1 to 9, comprising a gate pad provided on the second gate wiring with an insulating layer in between.

11. The semiconductor device according to any one of claims 1 to 10, wherein the first gate wiring comprises a first metal layer and a second metal layer laminated on the first metal layer, and the second gate wiring has the first metal layer but does not have the second metal layer.

12. A semiconductor device comprising: a substrate having a main surface and a back surface facing the main surface; a transistor provided on the main surface and comprising a plurality of source electrodes and a plurality of drain electrodes, and a plurality of gate electrodes, each sandwiched between one of the plurality of source electrodes and one of the plurality of drain electrodes; a first gate wiring provided on the main surface and electrically connecting at least two of the plurality of gate electrodes; a gate bus line provided on the main surface; and a second gate wiring provided on the main surface between the gate bus line and the first gate wiring, electrically connecting the gate bus line and the first gate wiring, and having a width of five times or less the width of the plurality of gate electrodes.

13. The semiconductor device according to claim 12, further comprising a source connection electrode provided on the main surface, electrically connected to the plurality of source electrodes, and provided between the gate bus line and the transistor.

14. The semiconductor device according to claim 13, further comprising a back metal layer provided on the back surface and electrically connected to the source connection electrode via via holes that overlap with the source connection electrode when viewed in the thickness direction of the substrate.

15. The semiconductor device according to any one of claims 12 to 14, wherein the second gate wiring is meander-shaped and has a first protrusion that protrudes in the protruding direction.

16. The semiconductor device according to claim 15, wherein the second gate wiring further has a second protrusion that protrudes in the direction opposite to the protrusion direction.

17. The semiconductor device according to any one of claims 12 to 16, comprising a gate pad provided on the second gate wiring with an insulating layer in between.

18. The semiconductor device according to any one of claims 12 to 17, wherein the second gate wiring is formed from the same material as the plurality of gate electrodes.

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