Magnetoresistive element and storage device

Abstract

Provided is a magnetoresistive element which comprises: a multilayer structure that includes a non-magnetic layer, and first and second magnetic layers which hold the non-magnetic layer therebetween from above and below; and a first protective film that covers at least a part of the side surface of the multilayer structure. The first protective film is formed of silicon nitride, and the silicon nitride contains nitrogen in an amount of 28 at% to 53 at% inclusive.

Description

Magnetoresistive Element and Memory Device

[0001] The present disclosure relates to a magnetoresistive element and a memory device.

[0002] With the remarkable development of various information devices from large-capacity servers to mobile terminals, further high performance such as high integration, high speed, and low power consumption is being pursued in elements such as memories and logics that make up these devices. In particular, the progress of non-volatile semiconductor memories is remarkable. For example, flash memory as a large-capacity file memory is spreading rapidly with the momentum of driving out hard disk drives. On the other hand, in view of applications for code storage and further working memory, various types of semiconductor memories such as MRAM (Magnetic Random Access Memory) are being developed to replace currently commonly used NOR flash memories, DRAMs (Dynamic Random Access Memory), etc. Some of these have already been put into practical use.

[0003] MRAM records information according to the magnetization direction of the magnetic material of the MTJ (Magnetic Tunnel Junction) element (magnetoresistive element) that MRAM has. Also, by using the magnetoresistive effect in which the electrical resistance changes depending on the magnetization direction in the magnetic material and determining the magnitude of the electrical resistance of the MTJ element, the stored information can be read out.

[0004] Japanese Patent Application Laid-Open No. 2007-305645

[0005] In the manufacturing process of semiconductor devices, the characteristics of MTJ elements may deteriorate due to the thermal load applied. Therefore, the present disclosure proposes a magnetoresistive element and a memory device that can suppress deterioration of characteristics due to thermal load.

[0006] According to the present disclosure, there is provided a magnetoresistive element including a stacked structure including a non-magnetic layer, first and second magnetic layers sandwiching the non-magnetic layer from above and below, and a first protective film covering at least a part of the side surface of the stacked structure, the first protective film being made of silicon nitride, and the silicon nitride containing nitrogen in an amount of 28 at% or more and 53 at% or less.

[0007] Further, according to the present disclosure, there is provided a storage device having a memory cell array including a plurality of magnetoresistive elements, each of the magnetoresistive elements including a stacked structure including a non-magnetic layer and first and second magnetic layers sandwiching the non-magnetic layer from above and below, and a first protective film covering at least a part of side surfaces of the stacked structure, the first protective film being made of silicon nitride, the silicon nitride containing nitrogen in an amount of 28 at% or more and 53 at% or less.

[0008] This is a cross-sectional view showing the stacked structure of an MTJ element according to a comparative example. This is an explanatory diagram illustrating the problems of the MTJ element according to a comparative example. This is a cross-sectional view showing an example of an MTJ element according to the first embodiment of this disclosure. This is an explanatory diagram (part 1) illustrating the experimental results of an MTJ element according to the first embodiment of this disclosure. This is an explanatory diagram (part 2) illustrating the experimental results of an MTJ element according to the first embodiment of this disclosure. This is a cross-sectional view (part 1) showing the manufacturing method of an MTJ element according to the first embodiment of this disclosure. This is a cross-sectional view (part 2) showing the manufacturing method of an MTJ element according to the first embodiment of this disclosure. This is a cross-sectional view (part 3) showing the manufacturing method of an MTJ element according to the first embodiment of this disclosure. This is a cross-sectional view (part 1) showing an example of an MTJ element according to the second embodiment of this disclosure. This is a cross-sectional view (part 2) showing an example of an MTJ element according to the second embodiment of this disclosure. This is a cross-sectional view (part 3) showing an example of an MTJ element according to the second embodiment of this disclosure. This is a cross-sectional view (part 4) showing an example of an MTJ element according to the second embodiment of this disclosure. This is a block diagram showing an example of the system configuration according to the third embodiment of this disclosure. This is an explanatory diagram showing an example of the configuration of a storage device according to the third embodiment of this disclosure. This is a diagram showing an example of the schematic configuration of a memory cell according to the third embodiment of this disclosure. This is an explanatory diagram for explaining an example of a write operation to an MTJ element of a memory cell according to the third embodiment of this disclosure. This is an explanatory diagram for explaining an example of a read operation to an MTJ element of a memory cell according to the third embodiment of this disclosure. This is a flowchart showing the flow of a write process example of a storage device according to the third embodiment of this disclosure. This is a diagram showing an example of an application of a storage device to which the technology of this disclosure can be applied. This is a diagram showing an example of the configuration of an imaging device to which the technology of this disclosure can be applied. This is an explanatory diagram showing an example of a stacked structure of an imaging device to which the technology of this disclosure can be applied. This is a diagram showing an example of the configuration of a distance measuring device to which the technology of this disclosure can be applied.

[0009] Preferred embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numeral to avoid redundant explanation. In addition, in this specification and drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding a different alphabet after the same reference numeral. However, if there is no particular need to distinguish each of multiple components having substantially the same or similar functional configurations, only the same reference numeral will be used.

[0010] Furthermore, the drawings referenced in the following description are intended to illustrate and facilitate understanding of one embodiment of this disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from those of the actual product. In addition, the apparatus shown in the drawings may be modified in design as appropriate, taking into consideration the following description and known technology.

[0011] The descriptions of specific lengths and shapes in the following explanation do not necessarily refer only to mathematically defined numerical values ​​or geometrically defined shapes. More specifically, the descriptions of specific lengths and shapes in the following explanation include MTJ (Magnetic Tunnel Junction) elements, memory devices, their manufacturing processes, and any acceptable degree of difference (errors or distortions) in their use and operation, as well as shapes similar to those specified.

[0012] Furthermore, in the following descriptions of circuit configurations, unless otherwise specified, "connection" means electrically connecting multiple elements. Moreover, "connection" in the following descriptions includes not only cases where multiple elements are directly and electrically connected, but also cases where they are indirectly and electrically connected through other elements.

[0013] The explanation will be given in the following order: 1. Background to the creation of the embodiments of this disclosure 1.1 MTJ element 1.2 Background 2. First embodiment 2.1 Example of MTJ element configuration 2.2 Example of implementation 2.3 Manufacturing method 3. Second embodiment 4. Third embodiment 4.1 Example of system configuration 4.2 Example of memory device configuration 4.3 Example of memory cell configuration 4.4 Example of write operation and read operation 4.5 Example of write processing 5. Summary 6. Application examples 6.1 General 6.2 Imaging device 6.3 Distancing device 7. Supplementary information

[0014] <<1. Background to the Creation of the Embodiments of the Present Disclosure>> <1.1 MTJ Element> First, with reference to Figure 1, the basic structure of the MTJ element (magnetoresistive element) 1, which is a magnetic memory element of an MRAM (memory device), will be described. Figure 1 is a cross-sectional view showing the stacked structure (pillar structure) of an MTJ element 1a according to a comparative example, and here, the outline of the stacked structure of the MTJ element 1a according to the comparative example will be described. Here, the comparative example refers to the MTJ element 1a that the inventors had been studying before creating the embodiments of the present disclosure.

[0015] As explained earlier, MRAM stores information by utilizing the fact that the electrical resistance changes when the magnetization state of the magnetic material of the MTJ element 1a is changed. More specifically, the stored information can be read by determining the resistance state of the MTJ element 1a, which is determined by the change in the magnetization state, and more specifically, by determining the magnitude of the electrical resistance of the MTJ element 1a. In other words, the MTJ element 1a can be said to be a magnetic memory element that stores one piece of information (1 / 0).

[0016] Furthermore, address wiring (i.e., word lines and bit lines) (not shown) that are orthogonal to each other are provided above and below the MTJ element 1a, and the MTJ element 1a is connected to the word lines and bit lines near the intersection of these wirings. Details of the arrangement of the multiple MTJ elements 1a will be described later.

[0017] As shown in Figure 1, the MTJ element 1a has a structure in which a reference layer (first magnetic layer) 20 with a fixed magnetic moment in a predetermined direction, a barrier layer (non-magnetic layer) 30, a memory layer (second magnetic layer) 40 with a variable magnetic moment direction, and a cap layer (not shown) are sequentially stacked on a base layer (not shown) made of, for example, aluminum (Al), chromium (Cr), hafnium (Hf), molybdenum (Mo), nickel (Ni), palladium (Pd), platinum (Pt), ruthenium (Ru), silicon (Si), tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), etc. Note that the MTJ element 1a is not limited to being stacked in the order shown in Figure 1; for example, the memory layer 40 may be stacked on the base layer, the barrier layer 30 on the memory layer 40, and the reference layer 20 on the barrier layer 30.

[0018] In detail, the reference layer 20 is formed from a magnetic material containing a ferromagnetic material, and its high coercivity fixes the direction of its magnetic moment (magnetization direction). The barrier layer 30 is formed from various dielectric materials such as magnesium oxide (MgO) and is provided between the reference layer 20 and the memory layer 40. The memory layer 40 is formed from a magnetic material containing a ferromagnetic material, and its magnetic moment direction (magnetization direction) can be changed (reversed) in accordance with the information to be stored. Furthermore, the underlayer and cap layer can function as electrodes, crystal orientation control films, protective films, etc.

[0019] In the MTJ element 1a, applying a voltage to the MTJ element 1a changes the direction of the magnetic moment of the memory layer 40. This changes the overall resistance of the MTJ element 1a due to the difference in direction between the magnetic moment of the reference layer 20 and the memory layer 40. Specifically, when the magnetic moments of the reference layer 20 and the memory layer 40 are in the same direction, the resistance of the MTJ element 1a decreases, and when the magnetic moments of the reference layer 20 and the memory layer 40 are in different directions, the resistance of the MTJ element 1a increases. The MTJ element 1a can then store information by utilizing this change in resistance due to the change in magnetic moment.

[0020] Furthermore, as shown in Figure 1, the MTJ element 1a is sandwiched between an upper electrode 50 and a lower electrode 10, and is electrically connected to word lines, bit lines, signal lines (not shown), and a selection transistor (not shown) via these electrodes. Specifically, the reference layer 20 of the MTJ element 1a is electrically connected to the word lines and signal lines via the lower electrode 10 and the selection transistor, and the memory layer 40 of the MTJ element 1a is electrically connected to the bit lines via the upper electrode 50. As a result, when an MTJ element 1a is selected by the selection transistor, a voltage is applied between the lower electrode 10 and the upper electrode 50 of the MTJ element 1a via the signal lines and bit lines, and information is written to and read from the memory layer 40 of the MTJ element 1a.

[0021] Furthermore, the MRAM has multiple MTJ elements 1a, and an insulating film 90 is embedded between adjacent MTJ elements 1a to electrically isolate them. ｘ N ｙ Because it has excellent insulating and heat-resistant properties, and is easy to form into a film, it is often used as a material for insulating film 90.

[0022] <1.2 Background> Next, with reference to Figure 2, the background to the invention of the embodiments of the present disclosure will be explained. Figure 2 is an explanatory diagram illustrating the problems of the MTJ element 1a according to a comparative example.

[0023] As explained earlier, adjacent MTJ elements 1a are separated from each other by an insulating film 90 made of silicon nitride embedded between them. Silicon nitride (Si) is used as the insulating film 90. ｘ N ｙ The composition ratio of ) is the stoichiometric composition x=3, y=4 (Si ３ N ４ ) and silicon nitride is deposited as the insulating film 90 to achieve such a composition. For example, as the insulating film 90 that is in contact with the side surface of the MTJ element 1a, Si ３ Silicon nitride having a composition ratio close to that of N4 is deposited by CVD (Chemical Vapor Deposition) at a deposition temperature of 300°C or higher.

[0024] However, when such a film formation is performed, elements diffuse from the silicon nitride (Si ｘ N ｙ ), which is the insulating film 90, into the MTJ element, and the diffused elements react, causing the side surface and the inside of the stacked structure of the MTJ element 1a to deteriorate. When the side surface of the MTJ element 1a deteriorates, the characteristics (e.g., TMR ratio, coercive force) of the MTJ element 1a may decrease.

[0025] Specifically, when Si ３ N4 is formed as the insulating film 90 after the stacked structure of the MTJ element 1a is created, as shown by the broken line in FIG. 2, the TMR (Tunnel Magneto Resistance) ratio of the MTJ element 1 decreases due to the heat load during the film formation of Si ３ N4 and the heat load due to subsequent processes. The TMR ratio is the ratio of the resistance value (high resistance value) when the directions of the magnetic moments of the reference layer 20 and the storage layer 40 in the MTJ element 1a are different to the resistance value (low resistance value) when the directions of the magnetic moments of the reference layer 20 and the storage layer 40 are the same (details will be described later). The larger the difference between the low resistance value and the high resistance value, that is, the higher the TMR ratio, the higher the accuracy of detecting the resistance state of the MTJ element 1a. Therefore, it is preferable for the MTJ element 1a to have a high TMR ratio.

[0026] The decrease in the TMR ratio due to the heat load as described above is considered to be because nitrogen (N) diffuses from the Si ｘ N ｙ which is the insulating film 90 into the MTJ element 1a due to the heat load, causing the side surface and the inside of the stacked structure of the MTJ element 1a to deteriorate. That is, in the MTJ element 1a according to the comparative example, nitrogen diffuses from the insulating film 90 made of silicon nitride (Si ｘ N ｙ ) into the stack of the MTJ element 1a due to the heat load, and thus desired electrical characteristics may not be obtained.

[0027] Therefore, in the prior art, Si ｘ N ｙIt has been proposed that the decrease in TMR ratio can be suppressed by reducing the thermal load by depositing the film at a low temperature, for example, around 200°C. However, even when adopting such a method of depositing the insulating film 90 at a low temperature, it has been difficult to sufficiently suppress the decrease in TMR ratio (heat resistance).

[0028] Therefore, in light of these circumstances, the present inventors conducted thorough research and conceived the idea of ​​providing a protective film that covers the side surface of the stacked structure of the MTJ element 1, having the composition described later, and thus created the embodiment of the present disclosure.

[0029] <<2. First Embodiment>> <2.1 Example of MTJ Element Configuration> First, an example of the configuration of an MTJ element (magnetoresistive element) 1 according to the first embodiment of this disclosure will be described with reference to Figure 3. Figure 3 is a cross-sectional view showing an example of an MTJ element 1 according to the first embodiment of this disclosure.

[0030] As shown in Figure 3, the MTJ element 1 according to this embodiment includes a lower electrode 10, a reference layer (first magnetic layer) 20, a barrier layer (non-magnetic layer) 30, a memory layer (second magnetic layer) 40, an upper electrode 50, and a protective film (first protective film) 60. More specifically, the MTJ element 1 according to this embodiment has a laminated structure in which the lower electrode 10, reference layer 20, barrier layer 30, memory layer 40, and upper electrode 50 are stacked in the order described. Furthermore, in this embodiment, a protective film 60 is formed so as to cover the sides of the laminated structure. The MTJ element 1 is also referred to as, for example, a magnetoresistive element or a magnetic memory element. Note that the term "layer" may be interpreted as "film," and "layer" and "film" may be appropriately substituted within a range that does not contradict each other.

[0031] The lower electrode 10 and the upper electrode 50 are positioned so as to sandwich the laminate of the reference layer 20, barrier layer 30, and memory layer 40. These lower electrode 10 and upper electrode 50 function as conductive layers for supplying voltage to the laminate of the reference layer 20, barrier layer 30, and memory layer 40. The lower electrode 10 and upper electrode 50 are made of metals such as aluminum (Al), gold (Au), copper (Cu), iridium (Ir), molybdenum (Mo), platinum (Pt), ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), or alloys of these metals, or laminates thereof.

[0032] The reference layer 20 is a ferromagnetic layer that has magnetic anisotropy and invariant magnetic moment direction. For example, the magnetic moment direction of the reference layer 20 is controlled perpendicular to the layer surface (film surface) by magnetic anisotropy. The reference layer 20 can be formed from a magnetic material containing at least one of the following elements: aluminum (Al), boron (B), cobalt (Co), chromium (Cr), iron (Fe), gallium (Ga), germanium (Ge), iridium (Ir), manganese (Mn), molybdenum (Mo), nickel (Ni), osnium (Os), palladium (Pd), platinum (Pt), rhenium (Re), ruthenium (Ru), silicon (Si), tantalum (Ta), titanium (Ti), vanadium (V), and tungsten (W). More specifically, the reference layer 20 may include magnetic materials such as CoFeB. Furthermore, the reference layer 20 may be, for example, an artificial ferrimagnetic material formed by antiferromagnetic coupling.

[0033] The barrier layer 30 is provided adjacent to the reference layer 20 and the storage layer 40, and is located between the reference layer 20 and the storage layer 40. The barrier layer 30 may contain at least one of the following elements: aluminum (Al), barium (Ba), carbon (C), calcium (Ca), cobalt (Co), chromium (Cr), copper (Cu), europium (Eu), iron (Fe), gallium (Ga), hafnium (Hf), lanthanum (La), lithium (Li), magnesium (Mg), manganese (Mn), molybdenum (Mo), niobium (Nb), nickel (Ni), ruthenium (Ru), scandium (Sc), silicon (Si), strontium (Sr), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), yttrium (Y), zinc (Zn), and zirconium (Zr). Furthermore, the barrier layer 30 may be an oxide, nitride, fluoride, boride, sulfide, or a mixture or laminate thereof containing the aforementioned elements. More specifically, the barrier layer 30 may contain magnesium oxide (MgO).

[0034] The memory layer 40 is a ferromagnetic layer that has magnetic anisotropy and a variable direction of magnetic moment. In the memory layer 40, for example, the direction of the magnetic moment is controlled perpendicular to the layer surface (film surface) by magnetic anisotropy. The memory layer 40 is, for example, a layer that has the VCMA (Voltage Control of Magnetic Anisotropy) effect. The memory layer 40 can be formed from a magnetic material containing at least one element from among aluminum (Al), boron (B), cobalt (Co), chromium (Cr), iron (Fe), gallium (Ga), germanium (Ge), iridium (Ir), manganese (Mn), molybdenum (Mo), nickel (Ni), osnium (Os), palladium (Pd), platinum (Pt), rhenium (Re), ruthenium (Ru), silicon (Si), tantalum (Ta), titanium (Ti), vanadium (V), and tungsten (W). More specifically, the memory layer 40 may include magnetic materials such as CoFeB. Furthermore, the memory layer 40 may be an artificial ferrimagnetic material formed by antiferromagnetic coupling, for example.

[0035] As shown in Figure 3, the protective film 60 is provided so as to cover the entire side surface of the laminated structure of the MTJ element 1. For example, in a plan view (when the MTJ element 1 is viewed from above), the protective film 60 is provided so as to surround the laminated structure of the MTJ element 1.

[0036] In this embodiment, the protective film 60 is silicon nitride (Si) which has excellent insulating and heat-resistant properties and is easy to form. ｘ N ｙ It is formed from silicon nitride (Si) used as the protective film 60. ｘ N ｙ ) contains 28 at% or more nitrogen, preferably 36 at% or more. Furthermore, the protective film 60 contains silicon nitride (Si ｘ N ｙ The ) contains 53 at% or less nitrogen, preferably 51 at% or less. In this embodiment, by making the protective film 60 have such a composition, the Si to the MTJ element 1 due to thermal load is reduced. ｘ N ｙ The diffusion of elements can be suppressed. As a result, according to this embodiment, the decrease in the TMR ratio (heat resistance) can be suppressed.

[0037] In this embodiment, the protective film 60 is not limited to covering the entire side surface of the MTJ element 1's laminated structure, but only needs to cover at least a portion of the side surface. In this embodiment, it is preferable that the protective film 60 covers at least a portion of the side surface of the barrier layer 30 that affects the characteristics of the MTJ element 1, and it is more preferable that it covers the entire side surface of the barrier layer 30. If elements diffuse locally from the protective film 60 into the barrier layer 30 made of magnesium oxide (MgO), the side surface of the barrier layer 30 may become locally low-resistive, potentially causing minute current leakage or deterioration of heat resistance. Therefore, by covering the side surface of the barrier layer 30 with a protective film 60 having the composition described above, the diffusion of elements into the barrier layer 30 is suppressed. Furthermore, in this embodiment, it is preferable that the protective film 60 covers at least a portion of the side surface of the reference layer 20 and / or the storage layer 40, and it is more preferable that it covers the entire side surface of the reference layer 20 and / or the storage layer 40.

[0038] Furthermore, in this embodiment, the protective film 60 has a film thickness t of 3 nm or more, preferably 5 nm or more, in the direction normal to the side surface of the laminated structure of the MTJ element 1.

[0039] In the above description, the reference layer 20, barrier layer 30, and storage layer 40 were described as being stacked from bottom to top in the order they are described. However, in this embodiment, they may be stacked in the reverse order. In other words, in this embodiment, the storage layer 40, barrier layer 30, and reference layer 20 may be stacked in the order they are described.

[0040] Furthermore, in this embodiment, the stacked structure of the MTJ element 1 may have other layers besides those described above, as long as it includes at least a reference layer 20, a barrier layer 30, and a memory layer 40. The MTJ element 1 may include, for example, a magnetic field generating layer (magnetic field generation layer) (not shown) that functions as a bias layer. This magnetic field generating layer generates, for example, an external magnetic field in the horizontal direction. In this embodiment, methods other than the magnetic field generating layer may be used to generate the magnetic field. In this embodiment, for example, a method of providing a magnet layer above or below the MTJ element 1 or a method of arranging permanent magnets around the MTJ element 1 may be used. Alternatively, a method of utilizing an induced magnetic field by electric current may be used instead of a magnetic field generating layer.

[0041] Furthermore, in this embodiment, the direction of the magnetization moment of the memory layer 40 may be changed by spin injection. A memory device using such an element is called an STT (Spin Transfer Torque)-MRAM. STT-MRAM is a device that reverses the magnetization direction of a magnetic material using spin torque magnetization reversal, and while having advantages such as high-speed operation, it is possible to reduce power consumption and increase capacity.

[0042] Furthermore, in this embodiment, the reference layer 20 and the storage layer 40 may be formed from the same material, or they may be formed from different materials.

[0043] In this embodiment described above, the protective film 60 covering at least a part of the stacked structure of the MTJ element 1 is silicon nitride (Si) containing 28 at% or more and 53 at% or less of nitrogen. ｘ N ｙ By forming it from ), it is possible to suppress the decrease in the TMR ratio due to thermal load.

[0044] <2.2 Examples> Next, the effects of this embodiment will be explained with reference to Tables 1 and 2 and Figures 4 and 5. Tables 1 and 2 are tables showing the conditions of examples and comparative examples corresponding to this embodiment, and Figures 4 and 5 are explanatory diagrams illustrating the experimental results of the MTJ element 1 according to this embodiment. Note that this embodiment is not limited to the following examples.

[0045] First, a lower electrode 10, a reference layer 20, a barrier layer 30, and a memory layer 40 were sequentially laminated onto a silicon thermal oxide film substrate. Each of these layers was fabricated using known film deposition methods such as PVD (Physical Vapor Deposition).

[0046] Furthermore, Ion Beam Etting (IBE) was performed on the above stacked structure to fabricate a stacked structure of MTJ elements 1 with a diameter of 40 to 70 nm. Furthermore, silicon nitride (Si) was used to cover the stacked structure. ｘ N ｙ A protective film 60 made of silicon nitride (Si) was deposited using a sputtering apparatus. Specifically, the above silicon nitride (Si) ｘ N ｙ ) uses a silicon (Si) target (with dopant) to vary the composition ratio of silicon to nitrogen by using argon (Ar) gas and nitrogen (N ２ The material was fabricated by sputtering while changing the mixing ratio with gas. Furthermore, the composition ratio of silicon to nitrogen was the same as that of silicon nitride (Si) that was actually deposited. ｘ N ｙ The single film was identified separately by RBS (Rutherford Backscattering Spectroscopy) measurement. The protective film 60 was fabricated to cover the entire side surface of the stacked structure of the MTJ element 1 and to fill the gaps between adjacent MTJ elements 1.

[0047] Specifically, in Comparative Example 1, the stoichiometric composition was almost entirely Si. ３ N ４ Silicon nitride (Si) with the following composition (N = 57 at%) ｘ N ｙ ) was used as the protective film 60. In comparative examples 2, 3, and 4, silicon nitride (Si) was used with varying amounts of nitrogen (N = 0, 21, 56 at%). ｘ N ｙ ) was used as the protective film 60. Furthermore, in Examples 1 to 4, silicon nitride (Si) was used with varying amounts of nitrogen (N = 30, 38, 50, 52 at%). ｘ N ｙ The protective film 60 was made from the material shown below. The data summarizing the nitrogen content of the protective film 60 in Comparative Examples 1 to 4 and Examples 1 to 4 is shown in Table 1 below.

[0048] These samples were subjected to various processing and fabrication steps to create electrode patterns on the top and bottom of the MTJ element 1. Furthermore, post-annealing equivalent to the thermal load used in typical semiconductor back-end processes (400°C, 1 hour or more) was performed.

[0049] Then, a voltage is applied between the upper and lower electrodes of these samples, and the resistance value (R) of the MTJ element 1 in its high-resistance state is determined. Ｈ ) and the resistance value in the low-resistance state (R Ｌ The TMR ratio, which is the ratio of (R), was measured. In detail, the TMR ratio is {(R Ｈ -R Ｌ ) / R Ｌ It is defined as} × 100 (%).

[0050] The results obtained in this way are shown in Figure 4. In Figure 4, the horizontal axis represents the amount of nitrogen in the protective film 60 (at%), and the vertical axis represents the TMR ratio (%). The dashed line in Figure 4 indicates the lower limit of the TMR ratio required for the MTJ element 1 as a magnetic memory element.

[0051] Silicon nitride (Si ｘ N ｙIn Comparative Example 1, where the nitrogen content in the protective film 60 made of silicon nitride is 57 at%, the TMR ratio is lower compared to the other samples. In Comparative Example 1, there is sufficient nitrogen in the protective film 60 made of silicon nitride, and the protective film 60 has sufficient insulating properties. Therefore, it is considered that in Comparative Example 1, there is no decrease in the TMR ratio due to the generation of leakage current in the protective film 60 itself. However, in Comparative Example 1, it is considered that due to the thermal load, elements diffused from the protective film 60 to the MTJ element 1, altering the sides and the inside of the laminated structure of the MTJ element 1, and thus the TMR ratio decreased. Furthermore, in Comparative Example 1, since there is a large amount of nitrogen in the protective film 60 made of silicon nitride, it is considered that nitrogen diffuses easily.

[0052] Also, silicon nitride (Si ｘ N ｙ In Examples 1 to 4, where the nitrogen content in the protective film 60 made of silicon nitride (Si) is 28 at% or more and 53% or less, the TMR ratio is higher than the lower limit of the TMR ratio required for a magnetic memory element with respect to the MTJ element 1. ｘ N ｙ In Comparative Examples 1 and 4, where the nitrogen content in the protective film 60 (composed of ) was greater than 53 at%, the TMR ratio fell below the lower limit of the required TMR ratio. Therefore, it was found that Comparative Examples 1 and 4 did not meet the desired characteristics. This is thought to be because annealing equivalent to the process heat load made nitrogen diffusion from the protective film 60 to the MTJ element 1 more likely, resulting in a significant decrease in the TMR ratio.

[0053] From the results shown in Figure 4, silicon nitride (Si) used as the protective film 60 ｘ N ｙ It was found that the nitrogen content within the film should be between 28 at% and 53 at%. In the protective film 60 made of silicon nitride, this range of nitrogen content allows for the acquisition of the required insulating properties of the protective film 60 while suppressing deterioration of the sides and interior of the laminated structure of the MTJ element 1.

[0054] Furthermore, as can be seen from the results shown in Figure 4, Example 2 (N = 38 at%) and Example 3 (N = 50 at%) have high TMR ratios. Therefore, in this embodiment, in order to ensure a sufficient TMR ratio, silicon nitride (Si) is used as the protective film 60. ｘ N ｙ The nitrogen content within the ) is preferably between 36 at% and 51 at%.

[0055] In this embodiment, the protective film 60 covering at least a part of the laminated structure of the MTJ element 1 is silicon nitride (Si) containing 28 at% or more and 53 at% or less of nitrogen. ｘ N ｙ By forming it from the above materials, the decrease in the TMR ratio due to thermal load can be suppressed. Furthermore, for the layers constituting the stacked structure of the MTJ element 1, if the layers are made of any of the above materials, the decrease in the TMR ratio due to thermal load can be suppressed by applying the protective film 60 according to this embodiment. In particular, it is thought that the above effect can be significantly obtained when the layer includes an element that is more easily nitrided than silicon (Si) within the range of thermal load applied in a typical semiconductor back-end process (for example, 300 to 400°C) (for example, hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), boron (B), tantalum (Ta), magnesium (Mg), cobalt (Co), etc.). Moreover, since boron (B), tantalum (Ta), magnesium (Mg), and cobalt (Co) are often used for the layers constituting the stacked structure of the MTJ element 1, it is thought that an even more significant effect can be obtained by applying the protective film 60 according to this embodiment. Furthermore, the barrier layer 30 contributes to increasing the overall resistance of the MTJ element 1, and if leakage current occurs due to deterioration of the barrier layer 30 by nitrogen or the like, it will significantly affect the overall characteristics of the MTJ element 1. Therefore, it is believed that a more significant effect can be obtained by using the protective film 60 according to this embodiment as a film covering the sides of the barrier layer 30.

[0056] Furthermore, the film thickness t of the protective film 60 was investigated. Here, a laminated structure of the MTJ element 1 was fabricated under the same conditions as in Examples 1 to 4 and Comparative Examples 1 to 4 described above, and samples (Examples 5, 6, and 7) were prepared in which the protective film 60 was fabricated under the conditions of Example 3 (N = 50 at%) described above. In this case, the protective film 60 was formed to cover the entire side surface of the laminated structure of the MTJ element 1, and the film thickness t of the protective film 60 was set to 1 nm, 3 nm, and 5 nm in the direction normal to the side surface of the laminated structure of the MTJ element 1. Furthermore, as an insulating film 90 that fills the space between adjacent MTJ elements 1, a stoichiometric composition of approximately Si was used. ３ N ４ A silicon nitride film with the following composition (N = 57 at%) was deposited. The data summarizing the film thickness t of the protective film 60 for Comparative Examples 5 and 6 is shown in Table 2 below.

[0057] For these samples, electrode patterns were fabricated on the top and bottom of the MTJ element 1 under various processing and manufacturing conditions, similar to those described in Examples 1-4 and Comparative Examples 1-4 above. Furthermore, post-annealing was performed under thermal load conditions equivalent to those used in typical semiconductor back-end processes (400°C for 1 hour or more).

[0058] Then, a voltage is applied between the upper and lower electrodes of these samples, and the resistance value (R) of the MTJ element 1 in its high-resistance state is determined. Ｈ ) and the resistance value in the low-resistance state (R Ｌ The TMR ratio, which is the ratio of ), was measured.

[0059] The results obtained in this way are shown in Figure 5. In Figure 5, the horizontal axis represents the film thickness t (nm) of the protective film 60, and the vertical axis represents the TMR ratio (%). The dashed line in Figure 5 indicates the lower limit of the TMR ratio required for the MTJ element 1 as a magnetic memory element.

[0060] In Examples 6 and 7, where the thickness t of the protective film 60 was 3 nm to 5 nm, the TMR ratio was above the lower limit of the required TMR ratio. In Example 5, where the thickness t of the protective film 60 was 1 nm, the TMR ratio was below the lower limit of the required TMR ratio.

[0061] Therefore, the thickness t of the protective film 60 according to this embodiment is preferably 3 nm or more. In this way, Si is added to the outside of the protective film 60.３ N ４ Even when silicon nitride with a high nitrogen content and such a composition is provided, the diffusion of elements from the protective film 60, etc., into the sides and interior of the MTJ element 1's laminated structure due to thermal load was suppressed, and a decrease in the TMR ratio (characteristics) was prevented.

[0062] Furthermore, as shown in Figure 5, the TMR ratio is high in the case where the film thickness t of the protective film 60 according to this embodiment is 5 nm or more (Example 7). Therefore, it is more preferable that the film thickness t of the protective film 60 according to this embodiment is 5 nm or more. Moreover, in this embodiment, even if there is a residual of less than 1 nm due to IBE between the stacked structure of the MTJ element 1 and the protective film 60, the decrease in the TMR ratio (characteristics) was suppressed.

[0063] As described above, in this embodiment, the protective film 60 covering at least a part of the laminated structure of the MTJ element 1 is silicon nitride (Si) containing 28 at% or more and 53 at% or less of nitrogen. ｘ N ｙ By forming it from ), it is possible to suppress the decrease in the TMR ratio due to thermal load.

[0064] <2.3 Manufacturing Method> An example of the manufacturing process for the MTJ element 1 according to this embodiment will be described with reference to Figures 6A to 6C. Figures 6A to 6C are cross-sectional views showing the manufacturing method for the MTJ element 1 according to this embodiment.

[0065] First, as shown in the upper part of Figure 6A, a semiconductor layer 202 is laminated on the low dielectric constant layer 201. The semiconductor layer 202 can be formed from, for example, silicon carbide (SiC). Furthermore, a metal layer 201a is formed on the low dielectric constant layer 201. For example, copper (Cu) is used for the metal layer 201a. The low dielectric constant layer 201 and the semiconductor layer 202 form a semiconductor substrate, for example, containing wiring, transistors, etc.

[0066] Next, an insulating layer 203 is laminated on the semiconductor layer 202, and a lower electrode layer 204 is laminated on the insulating layer 203. The insulating layer 203 can be formed from, for example, silicon oxide (SiO). A metal layer 203a is formed on the semiconductor layer 202 and the insulating layer 203. The metal layer 203a functions as a contact layer that electrically connects the lower electrode layer 204 and the metal layer 201a. The metal layer 203a is formed from, for example, tungsten (W). The lower electrode layer 204 is formed from, for example, tantalum nitride (TaN).

[0067] Next, as shown in the middle section of Figure 6A, an MTJ layer 205 is formed on the lower electrode layer 204, and an upper electrode layer 206 is stacked on the MTJ layer 205. The upper electrode layer 206 is formed of, for example, tantalum (Ta). The MTJ layer 205 corresponds to, for example, the layers between the lower electrode 10 and the upper electrode 50 of the MTJ element 1 according to the above embodiment.

[0068] Subsequently, as shown in the lower part of Figure 6A, a protective layer 207 is laminated on the upper electrode layer 206, and an insulating layer 208 is laminated on the protective layer 207. The protective layer 207 and the insulating layer 208 function, for example, as a hard mask. The protective layer 207 is formed of, for example, silicon nitride. The insulating layer 208 is formed of, for example, silicon oxide (SiO).

[0069] Next, as shown in the upper part of Figure 6B, the protective layer 207 and the insulating layer 208 are processed based on a predetermined pattern. At this time, the upper electrode layer 206 is also processed based on a predetermined pattern. The predetermined pattern is, for example, a pattern for forming a plurality of MTJ elements 1 in a two-dimensional matrix shape in a plan view.

[0070] Then, as shown in the middle section of Figure 6B, the MTJ layer 205 and the insulating layer 203 are processed by etching to form a plurality of laminated structures, and a protective film 209 is laminated on the laminated structures and the insulating layer 203. The protective film 209 corresponds, for example, to the protective film 60 of the MTJ element 1 according to this embodiment described above.

[0071] Next, as shown in the lower part of Figure 6B, an insulating layer 210 is laminated on the protective film 209. The insulating layer 210 functions as an insulating film present between adjacent MTJ elements 1, for example. The insulating layer 210 is formed of, for example, silicon oxide (SiO).

[0072] Next, as shown in the upper part of Figure 6C, a plurality of contact holes 210b are formed in the insulating layer 210. These contact holes 210b are provided, for example, above the metal layer 203a and each MTJ element 1.

[0073] Furthermore, as shown in the middle section of Figure 6C, a metal layer 210a is formed within each contact hole 210b. The metal layer 210a functions, for example, as a contact layer. The metal layer 210a is formed of, for example, tungsten (W).

[0074] Next, as shown in the lower part of Figure 6C, a metal layer 211 is laminated on the insulating layer 210 and the metal layer 210a. The metal layer 211 functions, for example, as wiring. The metal layer 211 can be formed from, for example, copper (Cu).

[0075] It should be noted that the MTJ element 1 according to this embodiment is not limited to being manufactured by the method and sequence described above, but can also be manufactured using methods, apparatus, and conditions commonly used in the manufacture of semiconductor devices.

[0076] Furthermore, the methods mentioned above can be specifically exemplified by PVD, CVD, and ALD (Atomic Layer Deposition). PVD methods include vacuum deposition, electron beam (EB) deposition, various sputtering methods (magnetron sputtering, RF-DC coupled bias sputtering, ECR (Electron Cyclotron Resonance) sputtering, opposing target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. CVD methods include plasma CVD, thermal CVD, metal-organic (MO) CVD, and optical CVD. Furthermore, other methods include electrolytic plating, electroless plating, spin coating, immersion, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, as well as stamping, spraying, air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calender coater. In addition, patterning methods include chemical etching such as shadow masks, laser transfer, and photolithography, as well as physical etching using ultraviolet light or lasers. Furthermore, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0077] <<3. Second Embodiment>> Next, an MTJ element 1 according to the second embodiment of this disclosure will be described with reference to Figures 7 to 10. Figures 7 to 10 are cross-sectional views showing an example of an MTJ element 1 according to this embodiment. Since the MTJ element 1 according to the second embodiment has basically the same configuration as the MTJ element 1 according to the first embodiment (see Figure 3), the differences from the first embodiment will be explained here.

[0078] As shown in Figure 7, the MTJ element 1 according to the second embodiment has, in addition to the layers according to the first embodiment, a fixed layer 75, a spacer layer 80, a storage layer 85, and a contact layer 70. More specifically, the stacked structure of the MTJ element 1 is constructed by stacking the lower electrode 10, fixed layer 75, spacer layer 80, reference layer 20, barrier layer 30, storage layer 40, storage layer 85, contact layer 70, and upper electrode 50 in the order described. Furthermore, in this embodiment, similar to the first embodiment, the sides of the stacked structure of the MTJ element 1 are covered with a protective film 60. In addition, in this embodiment, an insulating film 90 is embedded between adjacent MTJ elements 1.

[0079] The fixed layer 75 is laminated on the lower electrode 10 and is a ferromagnetic layer having magnetic anisotropy and a fixed direction of magnetization moment. Due to the magnetic anisotropy, the direction of the magnetization moment of the fixed layer 75 is controlled to be perpendicular to the layer surface (film surface). The magnetization direction of the fixed layer 75 is, for example, antiparallel to the magnetization direction of the reference layer 20. Therefore, the fixed layer 75 has the function of canceling out the leakage magnetic field from the reference layer 20 to the memory layer 40. The fixed layer 75 may contain at least one of the following elements: cobalt (Co), iron (Fe), nickel (Ni), platinum (Pt), palladium (Pd), chromium (Cr), iridium (Ir), samarium (Sm), and neodymium (Nd).

[0080] The spacer layer 80 is provided between the fixed layer 75 and the reference layer 20, and is a layer that separates the fixed layer 75 and the reference layer 20. This spacer layer 80 is, for example, a layer that magnetically couples the magnetization moments of the fixed layer 75 and the reference layer 20 in an antiparallel direction. The spacer layer 80 may contain, for example, at least one element from among ruthenium (Ru), iridium (Ir), rhodium (Rh), and rhenium (Re).

[0081] The storage layer 85 is provided between the memory layer 40 and the contact layer 70 and is a layer for storing spin electrons. The storage layer 85 may contain a conductor such as a metal, alloy, or doped semiconductor. The storage layer 85 may also contain at least one of silver (Ag), copper (Cu), aluminum (Al), and graphene.

[0082] The contact layer 70 is provided between the storage layer 85 and the upper electrode 50 and is electrically connected to the upper electrode 50.

[0083] Furthermore, in the example shown in Figure 7, the entire side surface of the stacked structure of the MTJ element 1 is covered with a protective film 60. The protective film 60 corresponds to the protective film 60 according to the first embodiment described above, and more specifically, contains silicon nitride (Si) containing 28 at% or more and 53 at% or less of nitrogen. ｘ N ｙ ) is formed from. In addition, in the example shown in Figure 7, an insulating film 90 is formed to fill the space between adjacent MTJ elements 1.

[0084] The insulating film 90 is formed from a nitride, oxide, or carbide containing at least one metal element from among Si, Al, and Hf, and silicon nitride (Si ｘ N ｙ If formed from ), it is formed from a material containing more than 53 at% nitrogen.

[0085] Furthermore, in this embodiment, as shown in Figure 8, a protective film (first protective film) 62 may be formed to fill the space between adjacent MTJ elements 1. The protective film 62 has the same configuration as the protective film 60 according to the first embodiment described above, and more specifically, contains silicon nitride (Si) containing 28 at% or more and 53 at% or less of nitrogen. ｘ N ｙ It is formed from ).

[0086] Furthermore, in this embodiment, as shown in Figure 9, a protective film 60 may be formed to cover the entire side surface of the laminated structure of the MTJ element 1, and a protective film (second protective film) 64 may be formed to cover the protective film 60. The protective film 64 is formed from an insulating material consisting of a nitride, oxide, or carbide containing at least one metal element from among Si, Al, and Hf, and silicon nitride (Si ｘ N ｙ If formed from ), it is formed from a material containing more than 53 at% nitrogen.

[0087] Furthermore, in this embodiment, as shown in Figure 10, a protective film 60 may be formed to cover the entire side surface of the MTJ element 1, a protective film 64 may be formed to cover the protective film 60, and a protective film (third protective film) 66 may be formed to cover the protective film 64. The protective film 64 has the same configuration as the protective film 60 according to the first embodiment described above, and more specifically, silicon nitride (Si) containing 28 at% or more and 53 at% or less of nitrogen. ｘ N ｙ It is formed from ).

[0088] As described above, in this embodiment as well, similar to the first embodiment, the protective film 60 covering the stacked structure of the MTJ element 1 is silicon nitride (Si) containing 28 at% or more and 53 at% or less nitrogen. ｘ N ｙ By forming it from ), it is possible to suppress the decrease in the TMR ratio due to thermal load.

[0089] <<4. Third Embodiment>> <4.1 Example of System Configuration> Furthermore, the MTJ element 1 according to the embodiment of this disclosure can be applied to a storage device included in the system. An example of the system configuration will be described below with reference to Figure 11. Figure 11 is a block diagram showing an example of the system configuration according to the third embodiment of this disclosure. As shown in Figure 11, the system includes a host computer 150 and a storage device 100.

[0090] The host computer 150 controls the entire system. Specifically, the host computer 150 generates commands and data and supplies them to the storage device 100. The host computer 150 can also receive data read from the storage device 100. Here, the commands are for controlling the storage device 100 and include, for example, write commands that instruct the writing of data and read commands that instruct the reading of data.

[0091] The storage device 100 includes a memory controller (control unit) 120 and a storage unit 130. The memory controller 120 controls the storage device 100. When the memory controller 120 receives a write command and data from the host computer 150, it generates an error detection and correction code (ECC) from the data. The memory controller 120 accesses the storage unit 130 and writes the encoded data.

[0092] Furthermore, when the memory controller 120 receives a read command from the host computer 150, it accesses the storage unit 130 and reads the encoded data. The memory controller 120 then converts (decodes) the encoded data back into the original data before encoding. During decoding, the memory controller 120 detects and corrects errors in the data based on ECC. The memory controller 120 then supplies the corrected data to the host computer 150.

[0093] Furthermore, as shown in Figure 11, the memory controller 120 includes a read / write processing unit 122 and a refresh processing unit 124.

[0094] The read / write processing unit 122 accesses the storage unit 130 according to commands from the host computer 150 to read or write data. When writing data, the aforementioned ECC is generated and encoded data is written. When reading data, errors in the data are detected and corrected based on the ECC.

[0095] The refresh processing unit 124 controls the refresh process. During the refresh process, the refresh processing unit 124 reads data from the storage unit 130, corrects errors in the data using ECC, and then rewrites the corrected data.

[0096] The storage unit 130 stores data using the internal MTJ element 1 in accordance with the control of the memory controller 120. That is, the storage unit 130 includes the MTJ element 1 according to the embodiment of this disclosure.

[0097] <4.2 Example of Storage Device Configuration> Next, an example of the configuration of the storage device 100 described above will be explained with reference to Figure 12. Figure 12 is an explanatory diagram showing an example of the configuration of the storage device 100 according to this embodiment.

[0098] As shown in Figure 12, the storage device 100 includes a memory cell array 110. The storage device 100 is an example of a storage device having an MTJ element 1 according to each embodiment of the present disclosure.

[0099] The memory cell array 110 includes a plurality of memory cells 11. Each memory cell 11 is arranged in a two-dimensional matrix. Each of these memory cells 11 stores data. Each of the memory cells 11 is connected to a bit line BL, a source line SL, and a word line WL. For example, each of the plurality of word lines WL is wired to extend in the row direction, and each of the plurality of bit lines BL and the plurality of source lines SL is wired to extend in the column direction. Each of the bit lines BL, source lines SL, and word lines WL functions, for example, as a control line.

[0100] Each memory cell 11 has an MTJ element 1 and a selection transistor 2. The MTJ element 1 is the MTJ element 1 according to each embodiment of the present disclosure described above. In the example shown in Figure 12, each memory cell 11 shares one source line SL for every two columns in the column direction. That is, each memory cell 11 arranged in two columns in the column direction is connected to two bit lines BL and one source line SL (2BL / 1SL). Each memory cell 11 may have one source line SL for every column in the column direction. That is, each memory cell 11 arranged in one column in the column direction may be connected to one bit line BL and one source line SL (1BL / 1SL).

[0101] The MTJ element 1 is electrically connected between the bit line BL and the source line SL. In the example shown in Figure 12, one end of the MTJ element 1 is connected to the bit line BL, and the other end is connected to the source line SL via the selection transistor 2.

[0102] The selection transistor 2 is an example of a selection element for selecting a memory cell 11 from a plurality of memory cells 11 to be used for reading or writing data. Various types of transistors, such as field-effect transistors, can be used as the selection transistor 2.

[0103] The selection transistor 2 switches between a state that allows data access (reading and writing data) to the corresponding MTJ element 1 and a state that prevents data access. In the example shown in Figure 12, one of the source and drain of the selection transistor 2 is connected to the MTJ element 1, and the other is connected to the source line SL. The gate of the selection transistor 2 is connected to the word line WL. When the selection transistor 2 is turned on (conducting), data access to the MTJ element 1 to which the selection transistor 2 is connected becomes possible. When the selection transistor 2 is turned off (non-conducting), data access to the MTJ element 1 to which the selection transistor 2 is connected is blocked.

[0104] The memory device 100 includes various peripheral circuits in addition to the memory cell array 110. In the example shown in Figure 12, the peripheral circuits include an I / O (input / output circuit) 12, a control circuit 13, a voltage generation circuit 14, a bit line address decoder 15, a bit line control circuit 16, a word line address decoder 17, a word line control circuit 18, and a sense amplifier 19.

[0105] I / O 12 enables the exchange of commands related to reading and writing data, the address of the memory cell 11 to be accessed, and data between the external circuitry of the storage device 100 (for example, the central processing unit, arithmetic circuitry, etc.) and the control circuit 13 of the storage device 100.

[0106] The control circuit 13 controls the writing and reading of data to the memory cell 11, and more specifically, to the MTJ element 1 within the memory cell 11, in accordance with commands. For example, the control circuit 13 receives commands (such as write and read commands) from an external circuit and controls the writing and reading of data based on the received commands.

[0107] The voltage generation circuit 14 generates voltages used for writing and reading data from the memory cell 11 (e.g., data writing voltage and data reading voltage), and supplies the generated voltages (e.g., pulse voltage) to the bit line control circuit 16.

[0108] The bit line address decoder 15 selects a bit line BL of the memory cell array 110 based on a control signal from the control circuit 13. For example, the bit line address decoder 15 obtains the address of the bit line BL corresponding to the address received by the I / O 12 described above.

[0109] The bit line control circuit 16 selects and controls the bit line BL corresponding to the address of the bit line address decoder 15. Each bit line BL is connected to the bit line control circuit 16.

[0110] For example, writing data to the memory cell 11 using the data writing voltage generated by the voltage generation circuit 14, and reading data from the memory cell 11 using the data reading voltage generated by the voltage generation circuit 14, are performed via the bit line control circuit 16 or the like.

[0111] The word line address decoder 17 selects a word line WL of the memory cell array 110 based on a control signal from the control circuit 13. For example, the word line address decoder 17 obtains the address of the word line WL corresponding to the address received by the I / O 12 described above.

[0112] The word line control circuit 18 selects and controls the word line WL corresponding to the address of the word line address decoder 17. Each word line WL is connected to the word line control circuit 18.

[0113] The sense amplifier 19 detects the data read from the memory cell 11 via the source line SL, i.e., the resistance state (resistance value) of the MTJ element 1. Each source line SL is connected to the sense amplifier 19.

[0114] <4.3 Example of Memory Cell Configuration> Next, an example of the configuration of the memory cell 11 of the memory device 100 described above will be explained with reference to Figure 13. Figure 13 is a diagram showing an example of the schematic configuration of the memory cell 11 according to this embodiment. In Figure 13, in addition to the MTJ element 1 and the selection transistor 2 of the memory cell 11, the contact layer 4, semiconductor substrate 5, bit line BL, word line WL, and source line SL are shown.

[0115] The selection transistor 2 includes a source region 2a, a drain region 2b, and a gate electrode. The source region 2a and drain region 2b are formed on the semiconductor substrate 5. In the example shown in Figure 13, the gate electrode of the selection transistor 2 is shown as the word line WL.

[0116] The contact layer 4 is a layer that electrically connects several elements and is composed of, for example, vias. In the example shown in Figure 13, three contact layers 4 are shown: a contact layer 4 connecting the MTJ element 1 and the bit line BL, a contact layer 4 connecting the MTJ element 1 and the source region 2a, and a contact layer 4 connecting the drain region 2b and the source line SL.

[0117] <4.4 Examples of Writing and Reading Operations> Next, examples of writing and reading operations will be described with reference to Figures 14 and 15. Figure 14 is an explanatory diagram for illustrating an example of writing to the MTJ element 1 of the memory cell 11 according to this embodiment, and Figure 15 is an explanatory diagram for illustrating an example of reading to the MTJ element 1 of the memory cell 11 according to this embodiment. Here, for convenience, data corresponding to the low resistance state is set to 0, and data corresponding to the high resistance state is set to 1.

[0118] (Writing Operation) As shown in Figure 14, during the writing operation, when writing 0 (when 0 is written to the MTJ element 1), a data writing voltage is applied to the MTJ element 1 so that current flows from the lower electrode 10 to the upper electrode 50. This writes 0 to the MTJ element 1. On the other hand, during the writing operation, when writing 1 (when 1 is written to the MTJ element 1), a data writing voltage is applied to the MTJ element 1 so that current flows from the upper electrode 50 to the lower electrode 10. This writes 1 to the MTJ element 1. As described above, in this embodiment, the direction of the current during writing may be changed depending on the data to be written.

[0119] (Read Operation) As shown in Figure 15, during the read operation, when reading data, a data read voltage is applied to the MTJ element 1 so that current flows from the lower electrode 10 to the upper electrode 50, and the resistance value of the MTJ element 1 is detected. In this way, data is read from the MTJ element 1. Note that the current during the read operation is smaller than the current during the write operation.

[0120] <4.5 Example of Writing Process> Next, an example of the writing process of the storage device 100 described above will be explained with reference to Figure 16. Figure 16 is a flowchart showing the flow of the writing process of the storage device 100 according to this embodiment.

[0121] The control circuit 13 (for example, the state machine of the control circuit 13) controls the write process. The flowchart starts when a write command and write data are input to the control circuit 13 from I / O 12. Here, as explained above, for convenience, data corresponding to a low resistance state is set to 0 and data corresponding to a high resistance state is set to 1.

[0122] As shown in Figure 16, in step S1, an initial read operation is performed. In step S2, a comparison is performed between the read data and the write data. In step S3, it is determined whether the read data matches the write data. If it is determined that the read data matches the write data (step S3: Yes), the process ends. On the other hand, if it is determined in step S3 that the read data does not match the write data (step S3: No), in step S4, a write voltage is applied to the selected cell (selected memory cell 11). In step S5, a verify read operation is performed, and the process returns to step S2. After that, the process from step S2 onwards is executed again.

[0123] In the example shown in Figure 16, the number of iterations for verifying the read operation is not set, but it is possible to pre-set a maximum number of iterations. Alternatively, the process may be terminated without performing a verifying read operation. Furthermore, while Figure 16 shows an example of writing including initial read and verifying read operations, various read methods can be used in the read operation of this embodiment.

[0124] <<5. Summary>> As described above, according to the embodiments of this disclosure, the protective film 60 covering at least a part of the stacked structure of the MTJ element 1 is silicon nitride (Si) containing 28 at% or more nitrogen and 53 at% or more nitrogen. ｘ N ｙ By forming it from ), it is possible to suppress the decrease in the TMR ratio (characteristics) due to thermal load.

[0125] Furthermore, the MTJ element 1 according to the embodiment of this disclosure is not limited to use in a storage device 100, but may be used in, for example, a magnetic detection device. Specifically, the MTJ element 1 according to the embodiment of this disclosure may be applied to, for example, a magnetocardiograph or the like that can measure magnetocardiography (a magnetic field caused by a weak electric current generated when the heart muscle expands and contracts to pump blood into the body) with higher precision.

[0126] <<6. Application Examples>> <6.1 General> The technology relating to this disclosure (this technology) can be applied to a variety of other products. Referring to Figure 17, an example of the application of the storage device 100 according to the embodiment of this disclosure described above will be explained. Figure 17 is a diagram showing an example of the application of the storage device 100 to which the technology relating to this disclosure can be applied. The storage device 100 can be applied to a variety of cases, namely various devices (electronic devices), as follows.

[0127] As shown in Figure 17, the memory device 100 is used in, for example, "devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions," "devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles," "devices used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and perform device operations according to those gestures," "devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography by receiving infrared light," "devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition," "devices used for beauty purposes, such as skin measuring devices that capture images of the skin and microscopes that capture images of the scalp," "devices used for sports purposes, such as action cameras and wearable cameras for sports use," and "devices used for agriculture, such as cameras for monitoring the condition of fields and crops."

[0128] Furthermore, the technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as electronic equipment mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors). Alternatively, for example, the technology disclosed herein may be implemented as electronic equipment mounted on endoscopic surgical systems or microsurgical systems.

[0129] <6.2 Imaging Device> An imaging device 300 relating to an application example will be described with reference to Figure 18. Figure 18 is a diagram showing an example configuration of an imaging device 300 to which the technology of this disclosure can be applied. The imaging device 300 is an example of an electronic device to which the storage device 100 according to the embodiment of this disclosure described above is applied. Examples of imaging devices 300 include digital still cameras, video cameras, smartphones and mobile phones having imaging functions.

[0130] As shown in Figure 18, the imaging device 300 includes an optical system 301, a shutter device 302, an image sensor 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 can capture, for example, still images and moving images.

[0131] The optical system 301 has one or more lenses. This optical system 301 guides light from the subject (incident light) to the image sensor 303 and forms an image on the light-receiving surface of the image sensor 303.

[0132] The shutter device 302 is positioned between the optical system 301 and the image sensor 303. The shutter device 302 controls the light irradiation period and the light shielding period for the image sensor 303 according to the control of the control circuit 304.

[0133] The image sensor 303 accumulates signal charge for a certain period of time in response to light formed on the light-receiving surface via the optical system 301 and shutter device 302. The signal charge accumulated in the image sensor 303 is transferred according to a drive signal (timing signal) supplied from the control circuit 304. Examples of the image sensor 303 include solid-state imaging devices such as image sensors.

[0134] The control circuit 304 drives the image sensor 303 and the shutter device 302 by outputting drive signals that control the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302.

[0135] The signal processing circuit 305 performs various signal processing operations on the signal charge output from the image sensor 303. The image (image data) obtained by the signal processing circuit 305 is supplied to the monitor 306, and further supplied to the memory 307.

[0136] The monitor 306 displays video or still images captured by the image sensor 303 based on image data supplied from the signal processing circuit 305. For example, the monitor 306 can be a panel-type display device such as a liquid crystal panel or an organic EL (Electroluminescence) panel.

[0137] The memory 307 stores image data supplied from the signal processing circuit 305, that is, image data of moving or still images captured by the image sensor 303. The storage device 100 according to the embodiment of this disclosure described above can be used as the memory 307.

[0138] Furthermore, as shown in Figure 19, the image sensor 303, control circuit 304, signal processing circuit 305, and memory 307 of the imaging device 300 to which the technology of this disclosure may be applied may be composed of a stacked structure 310 of three chips 312, 314, and 316. Figure 19 is an explanatory diagram showing an example of a stacked structure of the imaging device 300 to which the technology of this disclosure may be applied.

[0139] In detail, chip 312 is equipped with a pixel array section of an image sensor, chip 314 is equipped with a logic circuit section for controlling the pixel array section, and chip 316 is equipped with a memory 307 to which the technology of this disclosure can be applied.

[0140] <6.3 Distance Measuring Device> Referring to Figure 20, a distance measuring device 400 according to an application example will be described. Figure 20 is a diagram showing an example configuration of a distance measuring device 400 to which the technology of this disclosure can be applied. The distance measuring device 400 is an example of an electronic device to which the storage device 100 according to the embodiment of this disclosure described above is applied.

[0141] As shown in Figure 20, the distance measuring device (distance image sensor) 400 comprises a light source unit 401, an optical system 402, an image sensor 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. The distance measuring device 400 emits light from the light source unit 401 toward the subject and receives the light (modulated light or pulsed light) reflected from the surface of the subject, thereby acquiring a distance image corresponding to the distance to the subject.

[0142] The light source unit 401 projects light toward the subject. As the light source unit 401, for example, a vertical cavity surface-emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line can be used. The laser diode array is supported by a predetermined drive unit (not shown) and is scanned in a direction perpendicular to the direction of the laser diode arrangement.

[0143] The optical system 402 has one or more lenses. The optical system 402 guides light from the subject (incident light) to the image sensor 403 and forms an image on the light-receiving surface (sensor part) of the image sensor 403.

[0144] The image sensor 403 accumulates signal charge in response to light formed on the light-receiving surface via the optical system 402. A distance signal indicating the distance, determined from the light-receiving signal (APD OUT) output from the image sensor 403, is supplied to the signal processing circuit 405. As the image sensor 403, for example, a solid-state imaging device such as an image sensor can be used.

[0145] The control circuit 404 outputs drive signals (control signals) that control the operation of the light source unit 401 and the image sensor 403, and drives the light source unit 401 and the image sensor 403.

[0146] The signal processing circuit 405 performs various signal processing operations on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing circuit 405 is supplied to the monitor 406, and further supplied to the memory 407.

[0147] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. For example, a panel-type display device such as a liquid crystal panel or an organic EL panel can be used as the monitor 406.

[0148] The memory 407 stores image data supplied from the signal processing circuit 405, that is, image data of the distance image captured by the image sensor 403. As the memory 407, the storage device 100 according to the embodiment of this disclosure described above can be used.

[0149] As described above, the storage device 100 according to the embodiment of this disclosure can be implemented in various electronic devices. For example, in addition to the imaging device 300 and the distance measuring device 400, the storage device 100 may be installed in various electronic devices such as HDDs (hard disk drives), notebook PCs (personal computers), mobile devices (e.g., smartphones and tablet PCs), PDAs (personal digital assistants), wearable devices, game devices, and music players. Furthermore, the storage device 100 according to the embodiment of this disclosure may be used as various types of memory, such as storage.

[0150] <<7. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person with ordinary skill in the art of the present disclosure may conceive of various modifications or alterations within the scope of the technical idea described in the claims, and these will naturally also be understood to fall within the technical scope of the present disclosure.

[0151] Furthermore, the effects described herein are merely descriptive or illustrative and not limiting. In other words, the technology relating to this disclosure may produce other effects that are obvious to those skilled in the art from the description herein, in addition to or instead of the effects described herein.

[0152] Furthermore, this technology can also take the following configurations: (1) A magnetoresistive element comprising: a laminated structure including a non-magnetic layer and first and second magnetic layers sandwiching the non-magnetic layer from above and below; and a first protective film covering at least a part of the side surface of the laminated structure, wherein the first protective film is made of silicon nitride, and the silicon nitride contains 28 at% to 53 at% of nitrogen. (2) The magnetoresistive element according to (1) above, wherein the silicon nitride contains 36 at% to 51 at% of nitrogen. (3) The magnetoresistive element according to (1) or (2) above, wherein the first protective film covers at least a part of the side surface of the non-magnetic layer. (4) The magnetoresistive element according to (3) above, wherein the first protective film covers the entire side surface of the non-magnetic layer. (5) The magnetoresistive element according to (4) above, wherein the first protective film covers at least a part of the side surface of the first magnetic layer. (6) The magnetoresistive element according to (5) above, wherein the first protective film covers the entire side surface of the first magnetic layer. (7) The magnetoresistive element according to any one of (4) to (6) above, wherein the first protective film covers at least a portion of the side surface of the second magnetic layer. (8) The magnetoresistive element according to (7) above, wherein the first protective film covers the entire side surface of the second magnetic layer. (9) The magnetoresistive element according to any one of (1) to (8) above, wherein the first protective film has a film thickness of 3 nm or more in the direction normal to the side surface of the laminated structure. (10) The magnetoresistive element according to (9) above, wherein the first protective film has a film thickness of 5 nm or more in the direction normal to the side surface of the laminated structure. (11) The magnetoresistive element according to any one of (1) to (10) above, further comprising a second protective film covering the first protective film. (12) The magnetoresistive element according to (11) above, further comprising a third protective film covering the second protective film, wherein the third protective film is made of silicon nitride containing 28 at% to 53 at% nitrogen.(13) The magnetoresistive element according to any one of (1) to (12) above, wherein the first and second magnetic layers are made of a magnetic material containing at least one element selected from the group consisting of Al, B, Co, Cr, Fe, Ga, Ge, Ir, Mn, Mo, Ni, Os, Pd, Pt, Re, Ru, Si, Ta, Ti, V, and W. (14) The magnetoresistive element according to (13) above, wherein the first and second magnetic layers include layers made of CoFeB. (15) The magnetoresistive element according to any one of (1) to (14) above, wherein the non-magnetic layer is made of an oxide, nitride, fluoride, boride, or sulfide containing at least one element selected from the group consisting of Al, Ba, C, Ca, Co, Cr, Cu, Eu, Fe, Ga, Hf, La, Li, Mg, Mn, Mo, Nb, Ni, Ru, Sc, Si, Sr, Ti, Ta, V, W, Y, Zn, and Zr. (16) The magnetoresistive element according to (15) above, wherein the non-magnetic layer includes a layer made of MgO. (17) A memory device having a memory cell array including a plurality of magnetoresistive elements, wherein each magnetoresistive element comprises: a laminated structure including a non-magnetic layer and first and second magnetic layers sandwiching the non-magnetic layer from above and below; and a first protective film covering at least a portion of the side surface of the laminated structure, wherein the first protective film is made of silicon nitride, and the silicon nitride contains 28 at% to 53 at% nitrogen. (18) The memory device according to (17), wherein the space between adjacent magnetoresistive elements is filled with the first protective film. (19) The memory device according to (17) or (18), further comprising a control unit for controlling the magnetoresistive elements in the memory cell array.

[0153] 1, 1a MTJ element 2 Select transistor 2a Source region 2b Drain region 4, 70 Contact layer 5 Semiconductor substrate 10 Lower electrode 11 Memory cell 12 I / O 13 Control circuit 14 Voltage generation circuit 15 Bit line address decoder 16 Bit line control circuit 17 Word line address decoder 18 Word line control circuit 19 Sense amplifier 20 Reference layer 30 Barrier layer 40 Memory layer 50 Upper electrode 60, 62, 64, 66, 209 Protective film 75 Fixed layer 80 Spacer layer 85 Storage layer 90 Insulating film 100 Memory device 110 Memory cell array 120 Memory controller 122 Read / write processing unit 124 Refresh processing unit 130 Storage unit 150 Host computer 201 Low dielectric constant layer 201a, 203a, 210a, 211 Metal layer 202 Semiconductor layer 203, 208, 210 Insulating layer 204 Lower electrode layer 205 MTJ layer 206 Upper electrode layer 207 Protective layer 210b Contact hole 300 Imaging device 301, 402 Optical system 302 Shutter device 303, 403 Image sensor 304, 404 Control circuit 305, 405 Signal processing circuit 306, 406 Monitor 307, 407 Memory 310 Stacked structure 312, 314, 316 Chip 400 Distancing device 401 Light source

Claims

1. A magnetoresistive element comprising: a laminated structure including a non-magnetic layer and first and second magnetic layers sandwiching the non-magnetic layer from above and below; and a first protective film covering at least a portion of the side surface of the laminated structure, wherein the first protective film is made of silicon nitride, and the silicon nitride contains 28 at% to 53 at% nitrogen.

2. The magnetoresistive element according to claim 1, wherein the silicon nitride contains 36 at% or more and 51 at% or less of nitrogen.

3. The magnetoresistive element according to claim 1, wherein the first protective film covers at least a portion of the side surface of the non-magnetic layer.

4. The magnetoresistive element according to claim 3, wherein the first protective film covers the entire side surface of the non-magnetic layer.

5. The magnetoresistive element according to claim 4, wherein the first protective film covers at least a portion of the side surface of the first magnetic layer.

6. The magnetoresistive element according to claim 4, wherein the first protective film covers at least a portion of the side surface of the second magnetic layer.

7. The magnetoresistive element according to claim 1, wherein the first protective film has a thickness of 3 nm or more in the direction normal to the side surface of the laminated structure.

8. The magnetoresistive element according to claim 7, wherein the first protective film has a thickness of 5 nm or more in the direction normal to the side surface of the laminated structure.

9. The magnetoresistive element according to claim 1, further comprising a second protective film covering the first protective film.

10. The magnetoresistive element according to claim 9, further comprising a third protective film covering the second protective film, wherein the third protective film is made of silicon nitride containing 28 at% to 53 at% nitrogen.

11. The magnetoresistive element according to claim 1, wherein the first and second magnetic layers are made of a magnetic material containing at least one element selected from the group consisting of Al, B, Co, Cr, Fe, Ga, Ge, Ir, Mn, Mo, Ni, Os, Pd, Pt, Re, Ru, Si, Ta, Ti, V, and W.

12. The magnetoresistive element according to claim 11, wherein the first and second magnetic layers include layers made of CoFeB.

13. The magnetoresistive element according to claim 1, wherein the non-magnetic layer is made of an oxide, nitride, fluoride, boride, or sulfide containing at least one element selected from the group consisting of Al, Ba, C, Ca, Co, Cr, Cu, Eu, Fe, Ga, Hf, La, Li, Mg, Mn, Mo, Nb, Ni, Ru, Sc, Si, Sr, Ti, Ta, V, W, Y, Zn, and Zr.

14. The magnetoresistive element according to claim 13, wherein the non-magnetic layer includes a layer made of MgO.

15. A memory device having a memory cell array including a plurality of magnetoresistive elements, wherein each magnetoresistive element comprises a laminated structure including a non-magnetic layer and first and second magnetic layers sandwiching the non-magnetic layer from above and below, and a first protective film covering at least a portion of the side surface of the laminated structure, wherein the first protective film is made of silicon nitride, and the silicon nitride contains nitrogen in an amount of 28 at% or more and 53 at% or less.

16. The storage device according to claim 15, wherein the space between adjacent magnetoresistive elements is filled with the first protective film.

17. The storage device according to claim 15, further comprising a control unit for controlling the magnetoresistive elements in the memory cell array.

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