Semiconductor device

Abstract

This semiconductor device comprises: a chip having a main surface; a device structure formed on the main surface; a metal electrode covering the main surface; an inorganic insulating film covering the metal electrode; and an organic insulating film covering the metal electrode with the inorganic insulating film interposed therebetween. The metal electrode has a pad electrode. The organic insulating film has a first organic opening exposing the pad electrode as a first pad and a second organic opening exposing the pad electrode as a second pad. The inorganic insulating film includes a first pad inorganic film having a first inorganic opening exposing the first pad and a second pad inorganic film having a second inorganic opening exposing the second pad. The first pad inorganic film and the second pad inorganic film are separated from each other and are not mechanically connected to each other.

Description

Semiconductor device Related application

[0001] This application corresponds to Japanese Patent Application No. 2025-005494 filed with the Japan Patent Office on January 15, 2025, and the entire disclosure of this application is incorporated herein by reference.

[0002] This disclosure relates to a semiconductor device.

[0003] Patent Document 1 discloses a SiC semiconductor device including a first inorganic insulating film, a first main surface electrode covering the first inorganic insulating film and having an electrode side wall on the first inorganic insulating film, a second inorganic insulating film having an inner covering portion covering the first main surface electrode so as to expose the electrode side wall, and an organic insulating film covering the electrode side wall.

[0004] International Publication No. 2021 / 261102

[0005] [Summary] One embodiment of this disclosure provides a semiconductor device including a chip having a main surface, a device structure formed on the main surface, a metal electrode covering the main surface, an inorganic insulating film covering the metal electrode, and an organic insulating film covering the metal electrode with the inorganic insulating film interposed therebetween. The metal electrode may have a pad electrode. The organic insulating film may have a first organic opening exposing the pad electrode as a first pad and a second organic opening exposing the pad electrode as a second pad. The inorganic insulating film may include a first pad inorganic film having a first inorganic opening exposing the first pad and a second pad inorganic film having a second inorganic opening exposing the second pad. The first pad inorganic film and the second pad inorganic film may be separated from each other. The first pad inorganic film and the second pad inorganic film may not be mechanically connected to each other.

[0006] Figure 1 is a plan view of a semiconductor device according to the first embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of a metal electrode layout. Figure 4 is a plan view showing an example of an inorganic insulating film layout. Figure 5 is a plan view showing an example of a first main surface layout of a chip. Figure 6 is an enlarged view of the portion enclosed by the dashed line VI in Figure 5. Figure 7 is a cross-sectional view taken along the line VII-VII shown in Figure 6. Figure 8A is a cross-sectional view taken along the line VIIIA-VIIIA shown in Figure 1. Figure 8B is a cross-sectional view taken along the line VIIIB-VIIIB shown in Figure 1. Figure 9 is an enlarged view of the portion enclosed by the dashed line IX in Figure 3. Figure 10 is an enlarged view of the portion enclosed by the dashed line X in Figure 9, and is a plan view showing a first embodiment of an aperture group. Figure 11 is an enlarged view of the portion enclosed by the dashed line XI in Figure 4. Figure 12 is an enlarged view of the portion enclosed by the dashed line XII in Figure 3. Figure 13 is an enlarged view of the area enclosed by the dashed line XIII in Figure 4. Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 9. Figure 15 is a cross-sectional view along the line XV-XV shown in Figure 1. Figure 16 is a plan view showing a second embodiment of the aperture group, corresponding to Figure 10. Figure 17 is a plan view showing a third embodiment of the aperture group, corresponding to Figure 10. Figure 18 is a plan view showing a fourth embodiment of the aperture group, corresponding to Figure 10. Figure 19 is a plan view showing a fifth embodiment of the aperture group, corresponding to Figure 10. Figure 20 is a plan view showing a sixth embodiment of the aperture group, corresponding to Figure 10. Figure 21 is a diagram showing a modified example in the first embodiment in which the second aperture is eliminated, and is a cross-sectional view corresponding to Figure 8B. Figure 22 is a plan view showing an example layout of a metal electrode according to the second embodiment of this disclosure. Figure 23 is a plan view showing an example layout of an inorganic insulating film according to the second embodiment of this disclosure. Figure 24 is a plan view showing an example layout of a metal electrode according to the third embodiment of this disclosure. Figure 25 is a plan view showing an example layout of an inorganic insulating film according to the third embodiment of this disclosure. Figure 26 is a cross-sectional view showing the main part of a semiconductor device according to the third embodiment of this disclosure. Figure 27 is a plan view showing an example layout of a metal electrode according to the fourth embodiment of this disclosure. Figure 28 is a plan view showing an example layout of an inorganic insulating film according to the fourth embodiment of this disclosure.Figure 29 is a cross-sectional view along the line XXIX-XXIX shown in Figure 27.

[0007] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The attached drawings are all schematic diagrams and not strictly accurate; the scale, proportions, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0009] Where the word "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are approximately equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% from the numerical value (form) being compared. In the following descriptions, words such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is the conductivity type due to pentavalent elements, and "p-type" is the conductivity type due to trivalent elements. Unless otherwise specified, trivalent elements are at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] Figure 1 is a plan view of a semiconductor device 1A according to the first embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example layout of the metal electrode 16. Figure 4 is a plan view showing an example layout of the inorganic insulating film 37. Figure 5 is a plan view showing an example layout of the first main surface 3 of the chip 2. In Figure 4, for ease of understanding, the reference numerals of the metal electrode 16 are shown in conjunction with the reference numerals of each part of the inorganic insulating film 37.

[0012] Semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure. The transistor structure Tr has a planar gate type vertical structure.

[0013] Referring to Figures 1 to 5, the semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1A is a "wide-bandgap semiconductor device". The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0014] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. In other words, semiconductor device 1A is a "SiC semiconductor device".

[0015] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may also contain other polytypes.

[0016] The chip 2 has a first main surface (main surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and less than or equal to 10°. The off-angle is preferably 5° or less.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this embodiment, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Alternatively, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal.

[0020] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0021] The first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 20 mm or less in a plan view. The length of the first to fourth sides 5A to 5D may be a value that falls within one of the following ranges: 0.5 mm or more and 1 mm or less, 1 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The length of the first to fourth sides 5A to 5D may be 5 mm or more.

[0022] Referring to Figure 2, the semiconductor device 1A includes an n-type first semiconductor region 6 formed on the surface layer of the second main surface 4. A drain potential, which is a first potential (high potential), is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as the "base region (layer)", "semiconductor region (layer)", "drain region (layer)", etc.

[0023] The first semiconductor region 6 extends in layers along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 consists of an n-type semiconductor layer. Specifically, the first semiconductor region 6 consists of a substrate (SiC substrate) containing a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the aforementioned off-direction and off-angle. The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less.

[0024] The semiconductor device 1A includes an n-type second semiconductor region 7 formed on the surface layer of the first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)," "drift region (layer)," etc. The second semiconductor region 7 has an n-type impurity concentration less than that of the first semiconductor region 6. In a cross-sectional view, the second semiconductor region 7 is formed in the region on the first main surface 3 side relative to the first semiconductor region 6 and is electrically connected to the first semiconductor region 6.

[0025] The second semiconductor region 7 extends in layers along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this configuration, the second semiconductor region 7 consists of an n-type semiconductor layer.

[0026] The second semiconductor region 7 consists of an epitaxial layer (SiC epitaxial layer) grown from the first semiconductor region 6. The second semiconductor region 7 has a lower end and an upper end. The lower end of the second semiconductor region 7 is the crystal growth starting point, and the upper end of the second semiconductor region 7 is the crystal growth ending point. The lower end of the second semiconductor region 7 is also the bottom of the second semiconductor region 7. Since the second semiconductor region 7 is grown continuously from the first semiconductor region 6, the lower end of the second semiconductor region 7 coincides with the upper end of the first semiconductor region 6.

[0027] The second semiconductor region 7 (epitaxial layer) has the aforementioned off-direction and off-angle. The thickness of the second semiconductor region 7 may be 5 μm or more and 15 μm or less. Preferably, the second semiconductor region 7 has a thickness less than the thickness of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be greater than the thickness of the first semiconductor region 6.

[0028] The second semiconductor region 7 includes an n-type drift region 8. In this embodiment, the drift region 8 is formed by a part (n-type portion) of the second semiconductor region 7.

[0029] Referring to Figure 5, the semiconductor device 1A includes an active region 9 and an outer peripheral region 10 set on the first main surface 3 of the chip 2. Figures 1, 3, 4, and 5 are diagrams showing the layer structure formed on the active region 9 and the outer peripheral region 10, layer by layer. Of Figures 1, 3, 4, and 5, Figure 5 shows the lowest layer, Figure 3 shows a layer above Figure 5, Figure 4 shows a layer above Figure 3, and Figure 1 shows a layer above Figure 3.

[0030] Referring to Figure 5, the active region 9 includes the device structure (i.e., the transistor structure Tr) and is the region where the output current (drain current) is generated. The active region 9 may also be called the element region. In a plan view, the active region 9 is set in the inner part of the chip 2, spaced apart from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). In a plan view, the active region 9 is formed in a polygonal shape with sides parallel to the periphery of the chip 2. In this embodiment, in a plan view, the active region 9 is formed in a polygonal shape with recesses along the gate pad electrodes 24, which will be described later. The active region 9 may also be formed in a quadrilateral shape in a plan view. Preferably, the planar area of ​​the active region 9 is 50% to 90% of the planar area of ​​the first main surface 3.

[0031] The outer peripheral region 10 is a region that does not include the device structure (transistor structure Tr). In a plan view, the outer peripheral region 10 is located in the region between the periphery of the chip 2 and the active region 9. In a plan view, the outer peripheral region 10 extends in a band shape along the active region 9 and is set as a polygonal annular shape (in this embodiment, a polygonal shape having recesses along the gate pad electrodes 24, which will be described later) surrounding the active region 9.

[0032] The semiconductor device 1A includes a plurality of planar electrode type gate structures 11 formed in the active region 9. The plurality of gate structures 11 are formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 10.

[0033] In this configuration, the multiple gate structures 11 are arranged at intervals in the second direction Y (m-axis direction) and each is formed in a strip-like shape extending in the first direction X (a-axis direction). In other words, the multiple gate structures 11 are arranged in a stripe-like shape extending in the first direction X (a-axis direction). The direction of extension of the multiple gate structures 11 coincides with the off-direction of the SiC single crystal.

[0034] The semiconductor device 1A includes a p-type outer well region 12 formed in the outer peripheral region 10. The outer well region 12 includes a first outer well region 13 and a plurality of second outer well regions 14.

[0035] Referring to Figure 5, the first outer well region 13 is an annular region demarcated by a thick solid line and a thick dashed line. The first outer well region 13 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, the first outer well region 13 is formed as a polygonal annular shape (a quadrilateral annular shape in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds a plurality of gate structures 11.

[0036] The first outer well region 13 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). In this embodiment, the first outer well region 13 is formed in the outer peripheral region 10 and surrounds the active region 9.

[0037] Each of the multiple second outer well regions 14 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, each second outer well region 14 is formed as a polygonal ring (a quadrilateral ring in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first outer well region 13.

[0038] Each of the multiple second outer well regions 14 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably in a quarter arc shape). In this embodiment, the multiple second outer well regions 14 are arranged in the outer peripheral region 10 at a distance from the first outer well region 13.

[0039] Referring to Figure 2, the semiconductor device 1A includes an insulating interlayer film 15 formed on the first main surface 3. The interlayer film 15 may, for example, be formed over the entire first main surface 3. The interlayer film 15 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the interlayer film 15 includes a silicon oxide film. The interlayer film 15 may be referred to as an "insulating film," "interlayer insulating film," "intermediate insulating film," etc.

[0040] Referring to FIGS. 2 and 3, the semiconductor device 1A includes a metal electrode 16 disposed on the interlayer film 15. For the sake of clarifying the positional relationship of the metal electrode 16, the outline of the metal electrode 16 is indicated by a dashed line in FIG. 1.

[0041] Referring to FIG. 3, in this embodiment, the metal electrode 16 includes a source metal 17 and a gate metal 18.

[0042] The source metal 17 is a film physically and electrically separated from the gate metal 18. The source metal 17 is disposed at an interval from the gate metal 18 on the interlayer film 15 (FIG. 2). The source metal 17 is an electrode to which a source potential is applied from the outside. The source metal 17 may be referred to as a "first main surface electrode", a "source pad electrode", a "source metal electrode", a "first pad electrode", or the like.

[0043] The source metal 17 includes a source pad electrode 19 and a source wiring 20 electrically connected to the source pad electrode 19.

[0044] The source pad electrode 19 is disposed on the first main surface 3 (FIG. 2). The source pad electrode 19 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 19 may be referred to as a "source electrode film", a "first pad electrode", a "first main surface electrode", a "first terminal electrode", or the like. The source pad electrode 19 is disposed on a portion of the interlayer film 15 (FIG. 2) that covers the active region 9.

[0045] In this embodiment, the source pad electrode 19 is positioned on the active region 9 in a plan view. The source pad electrode 19 is formed in a polygonal shape in a plan view. The source pad electrode 19 includes a first source pad electrode 21 and a second source pad electrode 22 that are separated from each other. The first source pad electrode 21 and the second source pad electrode 22 are examples of pad electrodes. In this embodiment, the source pad electrode 19 includes a first source pad electrode 21 positioned in a region on the third side surface 5C side of the center position in the first direction X of the active region 9 (first main surface 3), and a second source pad electrode 22 positioned in a region on the fourth side surface 5D side of the said center position. In this embodiment, the first source pad electrode 21 and the second source pad electrode 22 are connected to each other (mechanically connected) at their ends on the second side surface 5B side. The first source pad electrode 21 and the second source pad electrode 22 do not have to be connected to each other (mechanically connected).

[0046] The source wiring 20 is arranged around the source pad electrode 19 on the interlayer film 15 (Figure 2). The source wiring 20 is an example of wiring. The source wiring 20 is supplied with the same potential (source potential) as the potential supplied to the source pad electrode 19. The source wiring 20 may also be referred to as "termination electrode (wiring)", "wiring", "first wiring", "finger electrode", "source finger", etc.

[0047] The source wiring 20 has a wiring width less than the electrode width of the source pad electrode 19 and is selectively routed on the interlayer film 15 (Figure 2). In this configuration, the source wiring 20 is led out from the source pad electrode 19 to the second side surface 5B. Specifically, the source wiring 20 is led out to the second side surface 5B at the connection portion between the first source pad electrode 21 and the second source pad electrode 22. The source wiring 20 is led out from the active region 9 to the outer peripheral region 10.

[0048] The source wiring 20 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 9). In this embodiment, the source wiring 20 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (active region 9). The source wiring 20 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape). The source wiring 20 may be end-bound or endless.

[0049] The gate metal 18 is an electrode to which a gate potential is applied from the outside. The gate metal 18 may also be called the "second main surface electrode," "gate pad electrode," "gate metal electrode," "second pad electrode," etc.

[0050] The gate metal 18 includes a gate pad electrode 24 and gate wiring 25 electrically connected to the gate pad electrode 24.

[0051] The gate pad electrode 24 is positioned on the first main surface 3. The gate pad electrode 24 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 24 is an example of a pad electrode. The gate pad electrode 24 may also be referred to as "gate pad," "gate electrode film," "second pad electrode," "second main surface electrode," "second terminal electrode," etc.

[0052] The gate pad electrode 24 is positioned at a distance from the source pad electrode 19, on the portion of the interlayer film 15 (Figure 2) that covers the active region 9. In this configuration, the gate pad electrode 24 is positioned in the region on the first side surface 5A side relative to the first source pad electrode 21. The gate pad electrode 24 faces the first source pad electrode 21 in the first direction X and the second direction Y. The gate pad electrode 24 faces the second source pad electrode 22 in the first direction X and the second direction Y.

[0053] The gate pad electrode 24 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 24 has a planar area less than that of the source pad electrode 19. The gate pad electrode 24 has a planar area less than that of the first source pad electrode 21 (second source pad electrode 22).

[0054] The gate pad electrode 24 is located in a recess formed in the source pad electrode 19. The gate pad electrode 24 may be located in a region along the central part of any of the first to fourth side surfaces 5A to 5D. The gate pad electrode 24 may be located at any corner C of the tip 2 on the first main surface 3 in a plan view. The gate pad electrode 24 may be located in the central part of the first main surface 3 in a plan view. The gate pad electrode 24 may be located on the active region 9. In this embodiment, the gate pad electrode 24 is formed in a square shape in a plan view.

[0055] The gate wiring 25 is routed from the gate pad electrode 24 around the active region 9, encircling the active region 9. The gate wiring 25 transmits the gate potential applied to the gate pad electrode 24 to the multiple gate structures 11.

[0056] The gate wiring 25 includes base wiring 26 and finger wiring 27. The base wiring 26 is formed in an annular shape that surrounds the gate pad electrode 24 in a plan view. The base wiring 26 surrounds the gate pad electrode 24 in a plan view. The gate pad electrode 24 is formed with a gap between it and the base wiring 26.

[0057] The finger wiring 27 extends outward in a strip shape from the outer edge of the annular base wiring 26. The semiconductor device 1A includes a plurality of finger wirings 27, 27B, 27C that extend outward in strip shapes from the outer edge of the base wiring 26 in different directions. The plurality of finger wirings 27 to 27C are arranged in a non-parallel positional relationship with respect to each other. The plurality of finger wirings 27 to 27C may include a first finger wiring 27A, a second finger wiring 27B, and a third finger wiring 27C.

[0058] The first finger wiring 27A and the second finger wiring 27B extend from the base wiring 26 in opposite directions along the periphery of the chip 2, and together surround the source pad electrode 19. The first finger wiring 27A and the second finger wiring 27B are examples of gate periphery wiring.

[0059] In this configuration, the first finger wiring 27A extends from the base wiring 26 in the first direction X along the first side surface 5A, the third side surface 5C, and the second side surface 5B in that order, and has a first tip portion 28A in the center of the fourth side surface 5D in the first direction X. The second finger wiring 27B extends from the base wiring 26 in the first direction X along the first side surface 5A, the fourth side surface 5D, and the second side surface 5B in that order, and has a second tip portion 28B in the center of the fourth side surface 5D in the first direction X. The first tip portion 28A and the second tip portion 28B face each other in the first direction X with a space between them.

[0060] The first finger wiring 27A and the second finger wiring 27B each have a corner C1 at a position corresponding to the corner C of the chip 2. The first finger wiring 27A may be referred to as, for example, "first outer peripheral wiring," "first outer peripheral electrode," "first outer peripheral finger wiring," or "first outer peripheral finger electrode." The second finger wiring 27B may be referred to as, for example, "second outer peripheral wiring," "second outer peripheral electrode," "second outer peripheral finger wiring," or "second outer peripheral finger electrode." The first finger wiring 27A and the second finger wiring 27B may be collectively referred to as "outer peripheral wiring," "outer peripheral electrode," "outer peripheral finger wiring," or "outer peripheral finger electrode" surrounding the active region 9.

[0061] The third finger wiring 27C extends from the base wiring 26 toward the center of the chip 2 and crosses the source pad electrode 19. In other words, the third finger wiring 27C extends toward the center of the chip 2 and crosses the active region 9. The third finger wiring 27C is an example of gate central wiring. The third finger wiring 27C extends from the base wiring 26 toward the second side surface 5B and may divide the source pad electrode 19 into a first source pad electrode 21 and a second source pad electrode 22. The third finger wiring 27C has a third tip portion 28C inside the region enclosed by the first finger wiring 27A and the second finger wiring 27B. The third finger wiring 27C may be referred to, for example, "central wiring," "central electrode," "central finger wiring," "central finger electrode," etc.

[0062] Referring to Figures 1 and 2, the semiconductor device 1A includes an organic insulating film 30 that covers the interlayer film 15 on the first main surface 3 and selectively covers the metal electrode 16.

[0063] Referring to Figure 1, the organic insulating film 30 includes a first source pad opening 32 that exposes the inner portion of the first source pad electrode 21 as the first source pad (first pad) 31, and a second source pad opening 34 that exposes the inner portion of the second source pad electrode 22 as the second source pad (second pad) 33. The first source pad opening 32 and the second source pad opening 34 are examples of the first organic opening and the second organic opening, respectively. The organic insulating film 30 covers the peripheral portion of the first source pad electrode 21 and the peripheral portion of the second source pad electrode 22.

[0064] The first source pad opening 32 is formed in a polygonal shape along the periphery of the first source pad electrode 21 in a plan view. The second source pad opening 34 is formed in a polygonal shape along the periphery of the second source pad electrode 22 in a plan view. Preferably, the planar area of ​​the first source pad opening 32 and the second source pad opening 34 is larger than the planar area of ​​the gate pad opening 36.

[0065] The organic insulating film 30 includes a gate pad opening (second organic opening) 36 that exposes the inner portion of the gate pad electrode 24 as a gate pad (second pad) 35. The gate pad opening 36 is formed in a rectangular shape in plan view. The organic insulating film 30 covers the peripheral edge of the gate pad electrode 24.

[0066] The organic insulating film 30 may also be referred to as an "organic film," "resin film," etc. The organic insulating film 30 preferably contains a transparent resin or a light-transmitting resin. The organic insulating film 30 preferably contains a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic insulating film 30 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. In this embodiment, the organic insulating film 30 contains a polyimide film.

[0067] The third film thickness T3 of the organic insulating film 30 (Figures 8A, 8B, and 9) may be greater than the second film thickness T2 of the metal electrode 16 (Figures 8A to 10). Preferably, the third film thickness T3 of the organic insulating film 30 is less than the thickness of the chip 2. The third film thickness T3 of the organic insulating film 30 may be greater than the thickness of the second semiconductor region 7, or less than the thickness of the second semiconductor region 7.

[0068] Referring to Figures 1 and 2, the organic insulating film 30 is formed so as to span over the active region 9 and over the outer peripheral region 10. The organic insulating film 30 covers a portion of the source pad electrode 19 and a portion of the gate pad electrode 24. The organic insulating film 30 also covers the source wiring 20 and the gate wiring 25 (Figure 3).

[0069] Referring to Figure 4, the semiconductor device 1A includes an inorganic insulating film 37 disposed between the metal electrode 16 and the organic insulating film 30. The inorganic insulating film 37 may also be referred to as a "passivation film" or "passivation layer".

[0070] The inorganic insulating film 37 has a single-layer or multi-layer structure comprising at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the inorganic insulating film 37 contains an insulating material different from the interlayer film 15. In this embodiment, the inorganic insulating film 37 consists of a silicon nitride layer. The inorganic insulating film 37 is formed in a film-like manner along the electrode surface and sidewalls of the metal electrode 16. In this embodiment, the inorganic insulating film 37 may have a single-layer structure comprising a silicon nitride film.

[0071] The inorganic insulating film 37 includes a first source pad inorganic film 38 that covers the first source pad electrode 21, a second source pad inorganic film 39 that covers the second source pad electrode 22, a source wiring inorganic film 40 that covers the source wiring 20, a gate pad inorganic film 41 that covers the gate pad electrode 24, and a gate wiring inorganic film 42 that covers the gate wiring 25.

[0072] The first source pad inorganic film 38, the second source pad inorganic film 39, the source wiring inorganic film 40, the gate pad inorganic film 41, and the gate wiring inorganic film 42 are separated from each other. The first source pad inorganic film 38, the second source pad inorganic film 39, the source wiring inorganic film 40, the gate pad inorganic film 41, and the gate wiring inorganic film 42 are not connected to each other.

[0073] The first source pad inorganic film 38 is positioned between the first source pad electrode 21 and the organic insulating film 30. In other words, the first source pad inorganic film 38 is sandwiched between the first source pad electrode 21 and the organic insulating film 30. The first source pad inorganic film 38 is an example of the first pad inorganic film.

[0074] The first source pad inorganic film 38 has a first source inorganic opening 43. The first source inorganic opening 43 exposes the inner portion of the first source pad electrode 21 as the first source pad 31. In other words, the first source inorganic opening 43 exposes the first source pad 31. The first source inorganic opening 43 is an example of a first inorganic opening.

[0075] The second source pad inorganic film 39 is positioned between the second source pad electrode 22 and the organic insulating film 30. In other words, the second source pad inorganic film 39 is sandwiched between the second source pad electrode 22 and the organic insulating film 30. The second source pad inorganic film 39 covers the peripheral edge of the second source pad electrode 22. The second source pad inorganic film 39 is an example of a second pad inorganic film.

[0076] The second source pad inorganic film 39 has a second source inorganic opening 44. The second source inorganic opening 44 exposes the inner portion of the second source pad electrode 22 as the second source pad 33. In other words, the second source inorganic opening 44 exposes the second source pad 33. The second source inorganic opening 44 is an example of a second inorganic opening. The second source pad inorganic film 39 is separated from the first source pad inorganic film 38. The second source pad inorganic film 39 is not mechanically connected to the first source pad inorganic film 38.

[0077] The source wiring inorganic film 40 is positioned between the source wiring 20 and the organic insulating film 30. In other words, the source wiring inorganic film 40 is sandwiched between the source wiring 20 and the organic insulating film 30. In a plan view, the source wiring inorganic film 40 overlaps the entire area of ​​the source wiring 20.

[0078] The gate pad inorganic film 41 is positioned between the gate pad electrode 24 and the organic insulating film 30. In other words, the gate pad inorganic film 41 is sandwiched between the gate pad electrode 24 and the organic insulating film 30. The gate pad inorganic film 41 covers the peripheral edge of the gate pad electrode 24.

[0079] The source wiring inorganic film 40 is separated from the first source pad inorganic film 38, the second source pad inorganic film 39, and the gate pad inorganic film 41. The source wiring inorganic film 40 is not mechanically connected to the first source pad inorganic film 38, the second source pad inorganic film 39, or the gate pad inorganic film 41.

[0080] The gate pad inorganic film 41 has a gate inorganic pad opening 45. The gate inorganic pad opening 45 exposes the inner portion of the gate pad electrode 24 as the gate pad 35. In other words, the gate inorganic pad opening 45 exposes the gate pad 35. The gate inorganic pad opening 45 is an example of a second inorganic opening.

[0081] The gate pad inorganic film 41 is separated from the first source pad inorganic film 38. The gate pad inorganic film 41 is not mechanically connected to the first source pad inorganic film 38. The gate pad inorganic film 41 is separated from the second source pad inorganic film 39. The gate pad inorganic film 41 is not mechanically connected to the second source pad inorganic film 39.

[0082] The gate wiring inorganic film 42 is positioned between the gate pad electrode 24 and the organic insulating film 30. In other words, the gate wiring inorganic film 42 is sandwiched between the gate pad electrode 24 and the organic insulating film 30. In a plan view, the gate wiring inorganic film 42 overlaps the entire area of ​​the gate wiring 25.

[0083] The gate wiring inorganic film 42 is separated from the first source pad inorganic film 38, the second source pad inorganic film 39, the source wiring inorganic film 40, and the gate pad inorganic film 41. The source wiring inorganic film 40 is not mechanically connected to the first source pad inorganic film 38, the second source pad inorganic film 39, the source wiring inorganic film 40, or the gate pad inorganic film 41.

[0084] The gate wiring inorganic film 42 includes a first wiring inorganic film 42A covering the first finger wiring 27A, a second wiring inorganic film 42B covering the second finger wiring 27B, a third wiring inorganic film 42C covering the third finger wiring 27C, and a fourth wiring inorganic film 42D covering the base wiring 26. In this embodiment, the first wiring inorganic film 42A, the second wiring inorganic film 42B, the third wiring inorganic film 42C, and the fourth wiring inorganic film 42D are mechanically connected to each other. At least one of the inorganic films among the first wiring inorganic film 42A, the second wiring inorganic film 42B, the third wiring inorganic film 42C, and the fourth wiring inorganic film 42D may be separated from the other inorganic films among them.

[0085] Referring to Figure 2, the semiconductor device 1A includes a drain electrode 46 that covers the second main surface 4. The drain electrode 46 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 46 may also be called a "third pad electrode," "third main surface electrode," "third terminal electrode," etc.

[0086] The drain electrode 46 is electrically connected to the first semiconductor region 6. The drain electrode 46 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 46 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0087] The breakdown voltage that can be applied between the source pad electrode 19 and the drain electrode 46 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, 2500V or more and 2750V or more and 3000V or less.

[0088] Referring to Figures 2 and 5, semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure. The transistor structure Tr has a planar gate type vertical structure.

[0089] Figure 6 is an enlarged view of the area enclosed by the dashed line VI in Figure 5. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 6. Figure 8A is a cross-sectional view along the line VIIIA-VIIIA shown in Figure 1. Figure 8B is a cross-sectional view along the line VIIIB-VIIIB shown in Figure 1.

[0090] Referring to Figures 6 to 8B, the semiconductor device 1A includes a plurality of p-type body regions 50 formed on the surface layer of the first main surface 3 in the region where the transistor structure Tr (Figures 2 and 5) is formed (i.e., the active region 9) on the first main surface 3. In this embodiment, the plurality of body regions 50 are arranged at intervals in the second direction Y and are each formed in a strip shape extending in the first direction X. The plurality of body regions 50 are arranged in a stripe shape as a whole. The direction of extension of the plurality of body regions 50 coincides with the off-direction of the SiC single crystal. The plurality of body regions 50 may be formed at intervals in the second direction Y and each extend in a strip shape in the first direction X.

[0091] Each body region 50 provides a unit cell UC (Figures 6 to 8B, etc.) of a planar gate type transistor structure Tr. Each unit cell UC comprises at least a body region 50 and a source region 51, as described below, and may be the smallest unit that functions as an MIS transistor. Multiple body regions 50 may be, for example, 1 × 10 １５ cm －３ The above 1 x 10 １８ cm －３ The following p-type impurity concentrations may be present as peak values.

[0092] The semiconductor device 1A includes one or more n-type source regions 51 formed on the surface of a plurality of body regions 50 in the transistor structure Tr (Figures 2 and 5) formation region (i.e., the active region 9) on the first main surface 3. In this embodiment, a plurality (two in this embodiment) of source regions 51 are formed at intervals on the surface of each body region 50. The plurality of source regions 51 have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 8. The plurality of source regions 51 have a density of 1 × 10⁻¹⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following n-type impurity concentrations may be present as peak values.

[0093] The multiple source regions 51 may each extend in a strip-like manner along the extending direction of the corresponding body region 50. Of course, the multiple source regions 51 may be formed at intervals along the extending direction of the corresponding body region 50. The multiple source regions 51 may be formed at intervals from the bottom of the corresponding body region 50 toward the first main surface 3, and at intervals from the periphery of the corresponding body region 50 toward the inward side.

[0094] Referring to Figure 7, the multiple source regions 51 demarcate channel regions 52 along the first main surface 3 at the periphery of the body region 50.

[0095] Referring to Figures 6 and 7, the semiconductor device 1A includes one or more p-type body contact regions 53 formed on the surface of each of the multiple body regions 50. The body contact regions 53 may also be referred to as "back gate regions". In this configuration, one body contact region 53 is formed in the region between multiple adjacent source regions 51 on the surface of each body region 50.

[0096] The multiple body contact regions 53 may each extend in a strip-like manner along the extending direction of the corresponding body region 50. Of course, the multiple body contact regions 53 may be formed at intervals along the extending direction of the corresponding body region 50. The multiple body contact regions 53 are formed at intervals from the bottom of the corresponding body region 50 toward the first main surface 3, and at intervals from the peripheral edge of the corresponding body region 50 toward the inside.

[0097] As described above, the semiconductor device 1A includes a plurality of gate structures 11 in the active region 9. One gate structure 11 has a stacked structure including a gate insulating film 56 and a gate electrode 57. The gate structure 11 does not have an insulating sidewall structure (spacer) on the side of the gate electrode 57.

[0098] The gate insulating film 56 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 56 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 56 includes a silicon oxide film made of the oxide of the chip 2. The gate insulating film 56 is formed to cover the entire area of ​​the transistor structure Tr (Figure 5) formation region (i.e., the active region 9) on the first main surface 3. The gate insulating film 56 is not formed in the area outside the transistor structure Tr formation region (i.e., the outer peripheral region 10) on the first main surface 3.

[0099] The multiple gate electrodes 57 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. A gate potential is applied to the multiple gate electrodes 57 as a control potential.

[0100] In this embodiment, the multiple gate electrodes 57 are arranged at intervals in the second direction Y (m-axis direction) and are formed in a strip shape extending in the first direction X (a-axis direction). In this embodiment, the multiple gate electrodes 57 are arranged in a stripe shape extending in the a-axis direction (first direction X). The direction of extension of the multiple gate electrodes 57 coincides with the off-direction of the chip 2.

[0101] Multiple gate electrodes 57 are arranged at intervals on the first main surface 3 so as to overlap at least one channel region 52 in the stacking direction (vertical direction Z). The multiple gate electrodes 57 control the inversion and non-inversion of the channel (current path) within the body region 50 in response to the gate potential.

[0102] The interlayer film 15 has multiple source contact openings 58 that open directly above multiple body regions 50. The multiple source contact openings 58 are formed in the region between a pair of gate electrodes 57 that face each other in the second direction Y. The multiple source contact openings 58 penetrate the interlayer film 15 and the gate insulating film 56. The multiple source contact openings 58 are spaced apart in the direction in which the pair of gate electrodes 57 face each other, i.e., in the second direction Y.

[0103] Figure 9 is an enlarged view of the area enclosed by the dashed line IX in Figure 3. Figure 10 is an enlarged view of the area enclosed by the dashed line X in Figure 9, and is a plan view showing a first embodiment example of the aperture group 82. Figure 11 is an enlarged view of the area enclosed by the dashed line XI in Figure 4. Figure 12 is an enlarged view of the area enclosed by the dashed line XII in Figure 3. Figure 13 is an enlarged view of the area enclosed by the dashed line XIII in Figure 4. Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 9. Figure 15 is a cross-sectional view along the line XV-XV shown in Figure 1.

[0104] In this configuration, the metal electrode 16 has an aperture group 82 having a plurality of first apertures 81. The aperture group 82 is formed in an aperture group forming region 80 that is selectively set on the metal electrode 16.

[0105] Referring to Figures 14 and 15, the semiconductor device 1A includes an outer insulating film 62 formed on the first main surface 3 in the outer peripheral region 10. The outer insulating film 62 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the outer insulating film 62 has a single-layer structure made of a silicon oxide film. The outer insulating film 62 may also include a silicon oxide film made of the oxide of the chip 2. The outer insulating film 62 may be formed integrally with the gate insulating film 56.

[0106] The outer contact region 60 is formed on the surface of the first outer well region 13. In other words, the outer contact region 60 is formed in the thickness range between the first main surface 3 and the bottom of the first outer well region 13.

[0107] In this embodiment, the outer contact region 60 is formed as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the tip 2 in a plan view, and surrounds the inner portion (active region 9) of the first main surface 3. The outer contact region 60 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0108] Referring to Figures 14 and 15, the semiconductor device 1A includes at least one (one in this embodiment) outer opening 61 formed in the interlayer film 15 in the outer peripheral region 10. The outer opening 61 penetrates the outer insulating film 62 and the interlayer film 15, exposing the outer contact region 60. In a plan view, the outer opening 61 extends in a strip shape along the outer contact region 60.

[0109] In this embodiment, the outer opening 61 is formed in a polygonal ring shape (specifically, a quadrilateral ring shape) that surrounds the inner portion (active region 9) of the first main surface 3 along the outer contact region 60 in a plan view. The outer opening 61 may have an opening end that is curved in an arc shape. The semiconductor device 1A may have a plurality of outer openings 61. In this case, the plurality of outer openings 61 may be formed at intervals along the outer contact region 60 so as to surround the inner portion (active region 9) of the first main surface 3.

[0110] Referring to Figures 7, 8A, 8B, 14, and 15, the metal electrode 16 is formed from a metallic material containing aluminum (Al). The metal electrode 16 includes an Al-based metal film. The metal electrode 16 may include at least one of a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The metal electrode 16 has an electrode surface 70 and a side wall 71.

[0111] The metal electrode 16 has a second film thickness T2. The second film thickness T2 is preferably greater than the thickness of the interlayer film 15. The second film thickness T2 may be, for example, 4 μm or more and 10 μm or less. The second film thickness T2 may have a value that falls within at least one of the following ranges: 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less. For example, the second film thickness T2 is preferably 4 μm or more and 7 μm or less.

[0112] Referring to Figures 8A, 8B, 14, and 15, the metal electrode 16 has a plurality of first openings 81. The plurality of first openings 81 expose the interlayer film 15. The bottom of the inner wall of the plurality of first openings 81 penetrates the metal electrode 16 in the thickness direction (vertical direction Z).

[0113] Referring to Figures 9, 10, and 12, the metal electrode 16 has an aperture group 82 having a plurality of first apertures 81. The aperture group 82 is formed in an aperture group forming region 80 selectively set on the metal electrode 16. The aperture group forming region 80 is formed in a strip shape on the electrode surface 70 of the metal electrode 16 (Figure 7A, etc.). In Figure 9, for illustrative purposes, a portion of the aperture group forming region 80 is represented using dot hunting.

[0114] Referring to Figures 11 and 13 in conjunction with Figure 9, in this embodiment, the aperture group formation region 80 is formed in the region of the electrode surface 70 of the metal electrode 16 (Figure 7A, etc.) that is covered by the inorganic insulating film 37.

[0115] Referring to Figures 9 and 12, as described above, the metal electrode 16 includes a first source pad electrode 21, a second source pad electrode 22, a source wiring 20, a gate pad electrode 24, and a gate wiring 25. The aperture group forming region 80 includes a first aperture group forming region 80A (Figures 9 and 12) set on the first source pad electrode 21 and the second source pad electrode 22, a second aperture group forming region 80B (Figure 9) set on the source wiring 20, a third aperture group forming region 80C (Figure 12) set on the gate pad electrode 24, and a fourth aperture group forming region 80D (Figures 9 and 12) set on the gate wiring 25.

[0116] Referring mainly to Figure 9, the first aperture group forming region 80A is set on the periphery of the first source pad electrode 21 (second source pad electrode 22). The first aperture group forming region 80A has a portion extending in a first direction X and a portion extending in a second direction Y. The first aperture group forming region 80A is a polygonal annular (in this embodiment, a quadrilateral annular) region along the periphery of the first source pad electrode 21 (second source pad electrode 22). The first aperture group forming region 80A has an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape). The first aperture group forming region 80A has a constant first region width W11.

[0117] The first region width W11 may be, for example, 3 μm or more and 20 μm or less. The first region width W11 may have a value that belongs to at least one of the following ranges: 3 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, and 17.5 μm or more and 20 μm or less. The first region width W11 is preferably, for example, greater than 5 μm and 15 μm or less.

[0118] The first aperture group forming region 80A is not set on the first source pad 31 (second source pad 33) of the first source pad electrode 21 (second source pad electrode 22). In other words, the first aperture 81 is not formed on the first source pad 31 (second source pad 33) of the first source pad electrode 21 (second source pad electrode 22).

[0119] The first aperture group forming region 80A is arc-shaped (preferably quarter-circular) at the corners of the first source pad electrode 21 (second source pad electrode 22). The first aperture group forming region 80A is linear in the region excluding the corners of the first source pad electrode 21 (second source pad electrode 22).

[0120] The second aperture group forming region 80B has a second region width W12. In this configuration, the second aperture group forming region 80B is set to cover the entire width of the source wiring 20. Therefore, the second region width W12 matches the wiring width of the source wiring 20.

[0121] The second region width W12 may be, for example, 3 μm or more and 20 μm or less. The second region width W12 may have a value that belongs to at least one of the following ranges: 3 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, and 17.5 μm or more and 20 μm or less. In this embodiment, the second region width W12 is equivalent to the first region width W11 (W12 = W11). The second region width W12 may be wider than the first region width W11 (W12 > W11) or narrower than the first region width W11 (W12 < W11).

[0122] The second aperture group forming region 80B may be set over the entire area in the direction in which the source wiring 20 extends. That is, in this embodiment, the second aperture group forming region 80B is formed over the entire area of ​​the source wiring 20. The second aperture group forming region 80B may be divided in the direction in which the source wiring 20 extends.

[0123] As mentioned above, the source wiring 20 is polygonal annular (a quadrilateral annular in this configuration). In this configuration, the corners of the source wiring 20 are arc-shaped (preferably quarter-circular), as shown in Figure 9.

[0124] The second aperture group forming region 80B is arc-shaped (preferably quarter-circular arc-shaped) at the corners of the source wiring 20. The second aperture group forming region 80B is linear in the region excluding the corners of the source wiring 20.

[0125] Referring to Figure 12, the third aperture group forming region 80C is set on the periphery of the gate pad electrode 24. The third aperture group forming region 80C has a portion extending in a first direction X and a portion extending in a second direction Y. The third aperture group forming region 80C is a polygonal annular (in this embodiment, a quadrilateral annular) region along the periphery of the gate pad electrode 24. The third aperture group forming region 80C has a constant third region width W13.

[0126] The third region width W13 may be, for example, 3 μm or more and 20 μm or less. The third region width W13 may have a value that belongs to at least one of the following ranges: 3 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, and 17.5 μm or more and 20 μm or less. Preferably, the third region width W13 is greater than 5 μm and 15 μm or less. In this embodiment, the third region width W13 is equivalent to the first region width W11 (W13 = W11). The third region width W13 may be wider than the first region width W11 (W13 > W11) or narrower than the first region width W11 (W13 < W11).

[0127] Furthermore, the width of the third region W13 is equivalent to the width of the second region W12 (W13 = W12). The width of the third region W13 may be wider than the width of the second region W12 (W13 > W12). The width of the third region W13 may be narrower than the width of the second region W12 (W13 < W12).

[0128] Although not shown in the diagram, the third aperture group forming region 80C may be arc-shaped (preferably quarter-circular arc-shaped) at the corners of the gate pad electrode 24. In this case, the third aperture group forming region 80C is linear in the region excluding the corners of the gate pad electrode 24.

[0129] The fourth aperture group forming region 80D is set in the gate wiring 25 (base wiring 26, first finger wiring 27A, second finger wiring 27B, and third finger wiring 27C). The fourth aperture group forming region 80D has a fourth region width W14. In this embodiment, the fourth aperture group forming region 80D is set across the entire width of the gate wiring 25. Therefore, the fourth region width W14 matches the wiring width of the gate wiring 25.

[0130] The fourth region width W14 may be, for example, 3 μm or more and 20 μm or less. The fourth region width W14 may have a value that belongs to at least one of the following ranges: 3 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, and 17.5 μm or more and 20 μm or less. In this embodiment, the fourth region width W14 is equivalent to the third region width W13 (W14 = W13). The fourth region width W14 may be wider than the third region width W13 (W14 > W13) or narrower than the third region width W13 (W14 < W13).

[0131] Furthermore, in this configuration, the width of the fourth region W14 is equivalent to the width of the second region W12 (W14 = W12). The width of the fourth region W14 may be wider than the width of the second region W12 (W14 > W12). The width of the fourth region W14 may be narrower than the width of the second region W12 (W14 < W12).

[0132] In this configuration, the corners of the gate wiring 25 (base wiring 26, first finger wiring 27A, and second finger wiring 27B) are arc-shaped (preferably quarter-circular arc-shaped), as shown in Figure 9.

[0133] The fourth aperture group forming region 80D is arc-shaped (preferably quarter-circular) at the corners of the gate wiring 25 (base wiring 26, first finger wiring 27A, and second finger wiring 27B). The fourth aperture group forming region 80D is linear in the region excluding the corners of the gate wiring 25 (base wiring 26, first finger wiring 27A, and second finger wiring 27B).

[0134] Referring to Figure 10, the multiple first openings 81 included in the opening group forming region 80 will be described. The extension direction of the strip-shaped opening group forming region 80 is denoted as the extension direction D1, and the direction intersecting (orthogonal to) the extension direction D1 is denoted as the intersecting direction D2. In the opening group forming region 80 (first opening group forming region 80A, second opening group forming region 80B, third opening group forming region 80C, fourth opening group forming region 80D), the extension direction D1 is linear in areas excluding the corners. In the opening group forming region 80, the extension direction D1 is curved at the corners.

[0135] In the embodiment shown in Figure 10 (first embodiment example), the multiple first openings 81 are arranged in a staggered pattern along the extending direction D1 and the intersecting direction D2 in a plan view. The multiple first openings 81 face each other in the extending direction D1. The multiple first openings 81 face each other in the intersecting direction D2. The multiple first openings 81 are offset from each other in the extending direction D1 and the intersecting direction D2. In other words, the multiple first openings 81 do not face each other in the shortest distance direction. The staggered arrangement allows for appropriate distribution of the multiple first openings 81.

[0136] In this configuration, the multiple first openings 81 are not adjacent to the multiple first openings 81 in the extending direction D1, nor are they facing each other in the intersecting direction D2.

[0137] More specifically, the first end of each of the multiple first openings 81 (one end in the extending direction D1) is aligned with the second end of the adjacent first opening 81 in the extending direction D1 (the other end in the extending direction D1). The second end of each of the multiple first openings 81 is aligned with the first end of the adjacent first opening 81 in the extending direction D1. Therefore, the opening area of ​​each of the multiple first openings 81 can be increased.

[0138] One first opening 81 is formed in a long, strip-like shape in the extending direction D1 when viewed from above. In other words, one first opening 81 is slit-like along the extending direction D1 when viewed from above. If the extending direction D1 is linear, the first opening 81 may be a long, rectangular shape in the extending direction D1 when viewed from above. If the extending direction D1 is curved, the first opening 81 may be a long, curved strip-like shape in the extending direction D1 when viewed from above.

[0139] One first opening 81 has a first width W1 as the opening width. The first width W1 may be 0.5 μm or more and 2 μm or less. The first width W1 may have a value that belongs to at least one of the following ranges: 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0140] The first width W1 is narrower than the second film thickness T2 of the metal electrode 16. The first width W1 may be narrower than the first film thickness T1 of the inorganic insulating film 37 (Figure 8A, etc.) (W1 < T1). The first width W1 may be equal to the first film thickness T1 of the inorganic insulating film 37 (W1 = T1). The first width W1 may be wider than the first film thickness T1 of the inorganic insulating film 37 (W1 > T1).

[0141] One first opening 81 has a length L1. The length L1 may be 1 μm or more and 10 μm or less. The length L1 may have a value that falls within at least one of the following ranges: 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less.

[0142] The spacing W2 between the multiple first openings 81 facing each other in the intersecting direction D2 may be 0.5 μm or more and 5 μm or less. The spacing W2 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less.

[0143] Referring to Figures 7, 8A, 8B, 14, and 15, the semiconductor device 1A includes a lower electrode layer 63. The lower electrode layer 63 is a thin metal layer and is the base layer for the metal electrode 16. The lower electrode layer 63 and the metal electrode 16 are stacked in this order from the chip 2 side.

[0144] In this configuration, the lower electrode layer 63 is formed to cover the surface of the interlayer film 15, the surface of the outer insulating film 62, the inner surface of the source contact opening 58, the inner surface of the outer opening 61, and the inner surface of the gate opening (not shown).

[0145] The lower electrode layer 63 is primarily a diffusion prevention layer that suppresses or prevents the diffusion of the constituent material of the metal electrode 16 (for example, a metallic material containing aluminum) into its surroundings (the surface of the outer insulating film 62, the surface of the interlayer film 15, etc.). The lower electrode layer 63 is formed using a different metallic material than the metal electrode 16.

[0146] The lower electrode layer 63 includes, for example, one or both of Ti and TiN. The lower electrode layer 63 may be a laminated film in which a Ti film and a TiN film are stacked. Of course, the lower electrode layer 63 may consist of only one of the Ti film and the TiN film.

[0147] As described above, the semiconductor device 1A includes an inorganic insulating film 37.

[0148] The inorganic insulating film 37 has a first film thickness T1. The first film thickness T1 of the inorganic insulating film 37 is smaller than the second film thickness T2 of the metal electrode 16 (T1 < T2).

[0149] The first film thickness T1 may be 0.5 μm or more. The first film thickness T1 may be 1 μm or more. The first film thickness T1 may be, for example, 1 μm or more and 5 μm or less. The first film thickness T1 may have a value that belongs to at least one of the following ranges: 1 μm or more and 1.5 μm, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or more and 5 μm or less.

[0150] The film thickness ratio (T1 / T2) of the first film thickness T1 of the inorganic insulating film 37 to the second film thickness T2 of the metal electrode 16 may be 0.1 or more and less than 1.0. The film thickness ratio (T1 / T2) may be 0.25 or more and less than 1.0. The film thickness ratio (T1 / T2) may have a value that falls within at least one of the following ranges: 0.25 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0151] Referring to Figures 8A, 8B, 14, and 15, the inorganic insulating film 37 includes a main body portion 90 that covers the electrode surface 70 and side wall 71 of the metal electrode 16, and a plurality of anchor portions 91.

[0152] One anchor portion 91 penetrates into multiple first openings 81 of the metal electrode 16 and covers the inner walls of the first openings 81. The anchor portion 91 covers the entire inner wall of the first openings 81. The anchor portion 91 is thin film in shape. The bottom of the anchor portion 91 is in contact with the upper surface of the interlayer film 15. The inorganic insulating film 37 may further have peripheral covering portions 74 (Figures 14 and 15) that are continuous with the main body portion 90 and selectively cover the interlayer film 15.

[0153] The inorganic insulating film 37 has a plurality of second openings 86. The plurality of second openings 86 are formed in a plurality of anchor portions 91. The plurality of second openings 86 expose the interlayer film 15. In other words, the bottom of the inner wall of the plurality of second openings 86 penetrates the inorganic insulating film 37 (anchor portion 91) in the thickness direction.

[0154] Multiple second openings 86 correspond one-to-one with multiple first openings 81. One second opening 86 is formed in a long, strip-like shape in the extending direction D1 (Figure 10) when viewed from above. One second opening 86 overlaps with its corresponding first opening 81 in a plan view. In other words, one second opening 86 is slit-shaped along the extending direction D1 (Figure 10) when viewed from above.

[0155] The opening width of one second opening 86 is narrower than the first width W1 of the first opening 81. The length of one second opening 86 (length in the extending direction D1 (Figure 10)) is shorter than the length L1 of the first opening 81.

[0156] As described above, the inorganic insulating film 37 includes a first source pad inorganic film 38 that covers the first source pad electrode 21, a second source pad inorganic film 39 that covers the second source pad electrode 22, a source wiring inorganic film 40 that covers the source wiring 20, a gate pad inorganic film 41 that covers the gate pad electrode 24, and a gate wiring inorganic film 42 that covers the gate wiring 25.

[0157] Referring to Figures 8A and 14, the first source pad electrode 21 is positioned on the first main surface 3 in the active region 9 and the peripheral region 10. The first source pad electrode 21 has an electrode surface 70 and side walls 71. A recess 72 is formed in the electrode surface 70 of the first source pad electrode 21. The first source pad electrode 21 has a second film thickness T2.

[0158] The first source pad inorganic film 38 covers both the electrode surface 70 and the side wall 71 of the first source pad electrode 21. The first source pad inorganic film 38 has a first film thickness T1. As described above, the first source pad inorganic film 38 has a first source inorganic opening 43 (Figure 14).

[0159] Referring to Figures 4 and 8A, the first source inorganic aperture 43 is formed in a polygonal shape (for example, a quadrilateral shape) along the periphery of the first source pad electrode 21 in a plan view. In a plan view, the first source inorganic aperture 43 overlaps with the first source pad aperture 32 of the organic insulating film 30 (Figure 8A).

[0160] In this configuration, the inner wall of the first source inorganic opening 43 coincides with the inner wall of the first source pad opening 32 in a plan view. In other words, the inner wall of the first source inorganic opening 43 communicates with the inner wall of the first source pad opening 32. The inner wall of the first source inorganic opening 43 may be located inside the first source pad opening 32. The inner wall of the first source inorganic opening 43 may be located outside the first source pad opening 32.

[0161] Referring to Figure 14, the first source pad inorganic film 38 covers not only the side wall 71 of the first source pad electrode 21, but also the side wall 73 of the lower electrode layer 63 (the side wall of the portion of the lower electrode layer 63 corresponding to the first source pad electrode 21). As a result, the portion of the lower electrode layer 63 corresponding to the first source pad electrode 21 is protected by the first source pad inorganic film 38.

[0162] The first source pad inorganic film 38 includes a plurality of anchor portions 91 that fit into a plurality of first openings 81 formed on the electrode surface 70 of the first source pad electrode 21. The bottom of each anchor portion 91 is in contact with the upper surface of the interlayer film 15.

[0163] The first source pad inorganic film 38 has a plurality of second openings 86. The plurality of second openings 86 are formed in a plurality of anchor portions 91. The plurality of second openings 86 expose the interlayer film 15.

[0164] In this configuration, the organic insulating film 30 penetrates into the second opening 86 of the first source pad inorganic film 38. The bottom of the portion of the organic insulating film 30 that penetrates into the second opening 86 is in contact with the upper surface of the interlayer film 15.

[0165] Referring to Figure 8B, the second source pad electrode 22 is positioned on the first main surface 3 in the active region 9 and the peripheral region 10. The second source pad electrode 22 has an electrode surface 70 and side walls. A recess 72 is formed in the electrode surface 70 of the second source pad electrode 22. The second source pad electrode 22 has a second film thickness T2.

[0166] The second source pad inorganic film 39 covers both the electrode surface 70 and the side wall of the second source pad electrode 22. As described above, the second source pad inorganic film 39 has a first film thickness T1. The second source pad inorganic film 39 has a second source inorganic opening 44.

[0167] Referring to Figures 4 and 8B, the second source inorganic aperture 44 is formed in a polygonal shape (for example, a quadrilateral shape) along the periphery of the second source pad electrode 22 in a plan view. In a plan view, the second source inorganic aperture 44 overlaps with the second source pad aperture 34 of the organic insulating film 30 (Figure 8B).

[0168] In this configuration, the inner wall of the second source inorganic opening 44 coincides with the inner wall of the second source pad opening 34 in a plan view. In other words, the inner wall of the second source inorganic opening 44 communicates with the inner wall of the second source pad opening 34. The inner wall of the second source inorganic opening 44 may be located inside the second source pad opening 34. The inner wall of the second source inorganic opening 44 may be located outside the second source pad opening 34.

[0169] Although not shown in the diagram, the second source pad inorganic film 39 may cover not only the side wall 71 of the second source pad electrode 22, but also the side wall 73 of the lower electrode layer 63 (the side wall of the portion of the lower electrode layer 63 corresponding to the second source pad electrode 22). As a result, the portion of the lower electrode layer 63 corresponding to the second source pad electrode 22 is protected by the second source pad inorganic film 39.

[0170] The second source pad inorganic film 39 includes a plurality of anchor portions 91 that fit into a plurality of first openings 81 formed on the electrode surface 70 of the second source pad electrode 22. The bottom of each anchor portion 91 is in contact with the upper surface of the interlayer film 15.

[0171] The second source pad inorganic film 39 has a plurality of second openings 86. The plurality of second openings 86 are formed in a plurality of anchor portions 91. The plurality of second openings 86 expose the interlayer film 15.

[0172] In this configuration, the organic insulating film 30 penetrates into the second opening 86 of the second source pad inorganic film 39. The bottom of the portion of the organic insulating film 30 that penetrates into the second opening 86 is in contact with the upper surface of the interlayer film 15.

[0173] Referring to Figures 14 and 15, the source wiring 20 is positioned on the first main surface 3 in the outer peripheral region 10. The source wiring 20 has an electrode surface 70 and a side wall 71. The source wiring 20 has a second film thickness T2.

[0174] The source wiring inorganic film 40 covers both the electrode surface 70 and the side wall 71 of the source wiring 20. The source wiring inorganic film 40 has a first film thickness T1. Referring to Figures 4 and 11 in conjunction with Figures 14 and 15, the source wiring inorganic film 40 covers the source wiring 20 over its entire length in the direction of extension.

[0175] Referring to Figures 14 and 15, the source wiring inorganic film 40 covers not only the sidewalls of the source wiring 20 but also the sidewalls 73 of the lower electrode layer 63 (the sidewalls of the portion of the lower electrode layer 63 corresponding to the source wiring 20). As a result, the portion of the lower electrode layer 63 corresponding to the source wiring 20 is protected by the source wiring inorganic film 40.

[0176] The source wiring inorganic film 40 includes a plurality of anchor portions 91 that fit into a plurality of first openings 81 formed on the electrode surface 70 of the source wiring 20. The bottom of each anchor portion 91 is in contact with the upper surface of the interlayer film 15.

[0177] The source wiring inorganic film 40 has a plurality of second openings 86. The plurality of second openings 86 are formed in a plurality of anchor portions 91. The plurality of second openings 86 expose the interlayer film 15.

[0178] In this configuration, the organic insulating film 30 penetrates into the second opening 86 of the source wiring inorganic film 40. The bottom of the portion of the organic insulating film 30 that penetrates into the second opening 86 is in contact with the upper surface of the interlayer film 15.

[0179] Referring to Figure 3, the gate pad electrode 24 is positioned on the first main surface 3. In this embodiment, the gate pad electrode 24 is positioned on the first main surface 3 in the outer peripheral region 10. The gate pad electrode 24 may also be positioned on the first main surface 3 in the active region 9.

[0180] The gate pad inorganic film 41 covers both the electrode surface and the side wall of the gate pad electrode 24. The gate pad inorganic film 41 has the same layer thickness (first film thickness T1 (Figure 8)) as the source wiring inorganic film 40. As described above, a gate inorganic pad opening 45 is formed in the gate pad inorganic film 41.

[0181] Referring to Figures 1, 3, and 4, the gate inorganic pad opening 45 (Figure 4) is formed in a polygonal shape (for example, a quadrilateral shape) along the periphery of the gate pad electrode 24 (Figure 3) in a plan view. In a plan view, the gate inorganic pad opening 45 overlaps with the gate pad opening 36 (Figure 1) of the organic insulating film 30.

[0182] Referring to Figures 12 and 13, in this embodiment, the inner wall of the gate inorganic pad opening 45 coincides with the inner wall of the gate pad opening 36 in a plan view. In other words, the inner wall of the gate inorganic pad opening 45 communicates with the inner wall of the gate pad opening 36. The inner wall of the gate inorganic pad opening 45 may be located inside the gate pad opening 36. The inner wall of the gate inorganic pad opening 45 may be located outside the gate pad opening 36.

[0183] Although not shown in the diagram, the gate pad inorganic film 41 covers not only the side walls of the gate pad electrode 24 but also the side walls 73 of the lower electrode layer 63 (the side walls of the portion of the lower electrode layer 63 corresponding to the gate pad electrode 24). As a result, the portion of the lower electrode layer 63 corresponding to the gate pad electrode 24 is protected by the gate pad inorganic film 41.

[0184] Although not shown in the diagram, the gate pad inorganic film 41 includes a plurality of anchor portions 91 that fit into a plurality of first openings 81 formed on the electrode surface of the gate pad electrode 24. The bottom of each anchor portion 91 is in contact with the upper surface of the interlayer film 15. The gate pad inorganic film 41 has a plurality of second openings 86. The plurality of second openings are formed in the plurality of anchor portions 91. The plurality of second openings 86 expose the interlayer film 15. In this configuration, the organic insulating film 30 fits into the second openings 86 of the gate pad inorganic film 41. The bottom of the portion of the organic insulating film 30 that fits into the second openings is in contact with the upper surface of the interlayer film 15.

[0185] Referring to Figure 14, the gate wiring 25 (base wiring 26, first finger wiring 27A, second finger wiring 27B, and third finger wiring 27C) is arranged on the first main surface 3. The gate wiring 25 has an electrode surface 70 and side walls 71. The source wiring 20 has a second film thickness T2.

[0186] The gate wiring inorganic film 42 covers both the electrode surface 70 and the side wall 71 of the gate wiring 25. The gate wiring inorganic film 42 has a first film thickness T1. Referring together to Figures 4, 11, and 13, the gate wiring inorganic film 42 covers the gate wiring 25 (base wiring 26, first finger wiring 27A, second finger wiring 27B, and third finger wiring 27C) over the entire extent of the gate wiring 25 in its extending direction.

[0187] The gate wiring inorganic film 42 covers not only the side walls 71 of the gate wiring 25, but also the side walls 73 of the lower electrode layer 63 (the side walls of the portion of the lower electrode layer 63 corresponding to the gate wiring 25). As a result, the portion of the lower electrode layer 63 corresponding to the gate wiring 25 is protected by the gate wiring inorganic film 42.

[0188] The gate wiring inorganic film 42 includes a plurality of anchor portions 91 that fit into a plurality of first openings 81 formed in the gate wiring 25 (base wiring 26, first finger wiring 27A, second finger wiring 27B, and third finger wiring 27C). The bottom of the anchor portions 91 is in contact with the upper surface of the interlayer film 15.

[0189] The gate wiring inorganic film 42 has a plurality of second openings 86. The plurality of second openings 86 are formed in a plurality of anchor portions 91. The plurality of second openings 86 expose the interlayer film 15.

[0190] In this configuration, the organic insulating film 30 penetrates into the second opening 86 of the source wiring inorganic film 40. The bottom of the portion of the organic insulating film 30 that penetrates into the second opening 86 is in contact with the upper surface of the interlayer film 15.

[0191] Conventionally, a method has been employed in which at least one of the electrode surface and sidewall of a metal electrode is coated with an inorganic insulating film (passivation film) such as a SiN film.

[0192] However, if the metal electrode deforms due to thermal expansion / contraction, the inorganic insulating film may be damaged by the deformation of the metal electrode. In particular, if the thickness of the metal electrode 16 is large, the thermal expansion / contraction of the metal electrode will be large, raising concerns about damage (peeling) of the inorganic insulating film.

[0193] Specifically, in this configuration, the inorganic insulating film 37 has a first film thickness T1 that is smaller than the second film thickness T2 of the metal electrode 16. More specifically, the film thickness ratio of the first film thickness T1 to the second film thickness T2 (T1 / T2) is 0.1 or more and less than 1.0. In this case, for the reasons mentioned above, there is a concern that the inorganic insulating film 37 may be damaged (peeled).

[0194] In this embodiment, the first source pad inorganic film 38, the second source pad inorganic film 39, the source wiring inorganic film 40, the gate pad inorganic film 41, and the gate wiring inorganic film 42 are separated from each other. Furthermore, these inorganic films 38 to 42 are not mechanically connected to each other.

[0195] Therefore, compared to the case where some or all of these inorganic films 38-42 are mechanically connected to each other, the individual inorganic films 38-42 can move independently without being constrained by each other. As a result, even if the metal electrode 16 is deformed, the individual inorganic films 38-42 can move or deform independently. In other words, stress is less likely to be generated in the individual inorganic films 38-42 as a result of the deformation of the metal electrode 16. This helps to suppress damage to the individual inorganic films 38-42. Thus, a semiconductor device 1A can be provided in which damage to the inorganic insulating film 37 covering the metal electrode 16 is suppressed.

[0196] In particular, in this configuration, the first source pad inorganic film 38, the second source pad inorganic film 39, and the gate pad inorganic film 41 are separated from each other and are not mechanically connected to each other. These pad inorganic films 38, 39, and 41 each have an opening (first source inorganic opening 43, second source inorganic opening 44, and gate inorganic pad opening 45).

[0197] These pad inorganic films 38, 39, and 41 cover relatively large surface areas of the pad electrodes 21, 22, and 24. Therefore, the deformation of the pad electrodes 21, 22, and 24 due to thermal expansion / contraction is also relatively large. Consequently, there is a concern that the pad inorganic films 38, 39, and 41 may be damaged.

[0198] In this configuration, the pad inorganic films 38, 39, and 41 are separated from each other and not mechanically connected. Therefore, the pad inorganic films 38, 39, and 41 can move freely without being restricted by each other. As a result, even if the pad electrodes 21, 22, and 24 are deformed, stress is less likely to occur on the pad inorganic films 38, 39, and 41. This helps to suppress damage to the inorganic insulating film 37 covering the pad electrodes 21, 22, and 24.

[0199] Furthermore, since the first source pad electrode 21 and the second source pad electrode 22 are close to each other in the first direction X, it is conceivable to cover the first source pad electrode 21 and the second source pad electrode 22 together with an inorganic insulating film.

[0200] However, because the surface area of ​​the first source pad electrode 21 and the second source pad electrode 22 is large, as mentioned above, the amount of deformation of the source pad electrodes 21 and 22 due to thermal expansion / contraction of the source pad electrodes 21 and 22 is also relatively large.

[0201] In this configuration, the first source pad inorganic film 38 covering the first source pad electrode 21 and the second source pad inorganic film 39 covering the second source pad electrode 22 are separated from each other and are not mechanically connected to each other. Therefore, even if the source pad electrodes 21 and 22 are deformed, stress is less likely to occur on the source pad inorganic films 38 and 39. This helps to suppress damage to the inorganic insulating film 37 covering the source pad electrodes 21 and 22.

[0202] Furthermore, in this embodiment, each inorganic film 38 to 42 contained in the metal electrode 16 includes an aperture group forming region 80 (first aperture group forming region 80A, second aperture group forming region 80B, third aperture group forming region 80C, fourth aperture group forming region 80D) in which a plurality of first apertures 81 are formed. Each inorganic film 38 to 42 also includes a plurality of anchor portions 91 that penetrate into the plurality of first apertures 81. The plurality of anchor portions 91 are in contact with the interlayer film 15.

[0203] This allows individual inorganic films 38-42 to be connected to the interlayer film 15 via multiple anchor portions 91. Therefore, even if the metal electrode 16 deforms due to thermal expansion / contraction of the metal electrode 16, each part of the individual inorganic films 38-42 can move easily, thus reducing stress on the individual inorganic films 38-42. This helps to suppress damage to the individual inorganic films 38-42.

[0204] Furthermore, in this configuration, the multiple first openings 81 in the inorganic insulating film 37 are arranged in a staggered pattern in a plan view. The staggered arrangement allows for proper dispersion of the multiple first openings 81. This makes it possible to more effectively suppress damage to the individual inorganic films 38-42 (first source pad inorganic film 38, second source pad inorganic film 39, source wiring inorganic film 40, gate pad inorganic film 41, and gate wiring inorganic film 42).

[0205] Next, variations of the aperture group 82 will be described with reference to Figures 16 to 20. Figure 10 describes the first embodiment of the aperture group 82. Figures 16 to 20 are plan views showing the second to sixth embodiments of the aperture group 82, respectively. Figures 16 to 20 are plan views corresponding to Figure 10, respectively. In Figures 16 to 20, components equivalent to those shown in Figure 10 are given the same reference numerals, and their descriptions are omitted.

[0206] In the second embodiment of the aperture group 82 shown in Figure 16, the multiple first apertures 81 are arranged in a grid pattern along the extending direction D1 and the intersecting direction D2 in a plan view. The multiple first apertures 81 are aligned along both the extending direction D1 and the intersecting direction D2. The multiple first apertures 81 are arranged with a gap W3 in the extending direction D1. In other words, the multiple first apertures 81 are arranged with gaps W2 and W3 in both the intersecting directions D2.

[0207] The spacing W3 between the multiple first openings 81 may be 0.5 μm or more and 5 μm or less. The spacing W3 between the multiple first openings 81 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less.

[0208] The spacing W3 between the multiple first openings 81 may be shorter than the length L1 of the first opening 81 (W3 < L1). In the example in Figure 16, the spacing W3 is equivalent to the spacing W2 (W3 = W2). The spacing W3 may be wider than the spacing W2 (W3 > W2) or narrower than the spacing W2 (W3 < W2).

[0209] The third embodiment of the opening group 82 shown in Figure 17 differs from the first embodiment in that the opening group 82 includes a plurality of line-shaped (strip-shaped) first openings 81A extending along the extending direction D1. In this embodiment, the plurality of first openings 81A are arranged at intervals in the intersecting direction D2. In other words, the plurality of first openings 81A are arranged in a stripe-like pattern extending in the extending direction D1.

[0210] In the fourth embodiment of the aperture group 82 shown in Figure 18, similar to the first embodiment, the multiple first apertures 81 are arranged in a staggered pattern in a plan view. The multiple first apertures 81 face each other in the extending direction D1. The multiple first apertures 81 face each other in the intersecting direction D2. The multiple first apertures 81 are offset from each other in the extending direction D1 and the intersecting direction D2. In other words, the multiple first apertures 81 do not face each other in the shortest distance direction.

[0211] The fourth embodiment differs from the first embodiment in that the multiple first openings 81 are formed with a gap W3 in the extension direction D1 between them and the multiple first openings 81 adjacent to each other in the extension direction D1.

[0212] The fourth form also produces the same effects as the first form.

[0213] The fifth embodiment of the aperture group 82 shown in Figure 19 differs from the first to fourth embodiments in that the aperture group 82 includes a plurality of first apertures 81B that are approximately square in shape in plan view. In this embodiment, the plurality of first apertures 81B are arranged with spacing in the intersecting direction D2. That is, the plurality of first apertures 81B are arranged in a staggered pattern in plan view. The plurality of first apertures 81B face each other in the extending direction D1. The plurality of first apertures 81B face each other in the intersecting direction D2. The plurality of first apertures 81B are offset from each other in the extending direction D1 and the intersecting direction D2. In other words, the plurality of first apertures 81B do not face each other in the shortest distance direction.

[0214] The side width W4 of the multiple first openings 81B may be 0.5 μm or more and 5 μm or less. The spacing W4 between the multiple first openings 81B may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less.

[0215] In this configuration, the multiple first openings 81B are not opposite to the multiple first openings 81B adjacent to each other in the extending direction D1 in the intersecting direction D2. The multiple first openings 81B may be spaced apart with respect to the extending direction D1 from the multiple first openings 81B adjacent to each other in the extending direction D1.

[0216] The sixth embodiment of the aperture group 82 shown in Figure 20 differs from the first to fourth embodiments in that, like the fifth embodiment, the aperture group 82 includes a plurality of first apertures 81B that are approximately square in shape in plan view. In this embodiment, the plurality of first apertures 81B are arranged in a grid pattern along the extending direction D1 and the intersecting direction D2 in plan view. The plurality of first apertures 81 are aligned along both the extending direction D1 and the intersecting direction D2. The plurality of first apertures 81 are spaced apart in both the extending direction D1 and the intersecting direction D2.

[0217] In the fifth and sixth embodiments, the multiple first openings 81B are rectangular in shape (square) when viewed from above, but the multiple first openings 81B may be formed in the shape of a rectangle, hexagon, circle, or the like when viewed from above.

[0218] Figure 21 shows a modified example of the first embodiment in which the second opening 86 is eliminated, and is a diagram showing a cross-section at the same position as in Figure 8B.

[0219] In this modified example, multiple first openings 81 are filled with corresponding anchor portions 91. The width of each anchor portion 91 in the intersecting direction D2 (Figure 10) matches the opening width of the first opening 81. In this case, a large contact area can be secured between the inorganic insulating film 37 and the interlayer film 15 via the first openings 81 (opening group 82).

[0220] Figure 22 is a plan view showing an example layout of the metal electrode 16B according to the second embodiment of the present disclosure. Figure 23 is a plan view showing an example layout of the inorganic insulating film 37B according to the second embodiment of the present disclosure. In Figure 23, for ease of viewing, the reference numerals of the metal electrode 16B are shown in accordance with the reference numerals of each part of the inorganic insulating film 37B.

[0221] The semiconductor device 1B according to the second embodiment of this disclosure includes a metal electrode 16B instead of a metal electrode 16 (Figure 3). The metal electrode 16B does not include a source wiring 20 (Figure 3). Except for this point, the metal electrode 16B is the same as the metal electrode 16. The metal electrode 16B includes a gate wiring 25. In Figures 22 and 23, components equivalent to those in the first embodiment are given the same reference numerals as in Figures 1 to 21, and their descriptions are omitted.

[0222] The semiconductor device 1B is equipped with an inorganic insulating film 37B instead of the inorganic insulating film 37 (Figure 4). The inorganic insulating film 37B does not have a source wiring inorganic film 40 (Figure 4). Except for this point, the inorganic insulating film 37B is the same as the inorganic insulating film 37.

[0223] Semiconductor device 1B provides the same effects and benefits as those described in relation to semiconductor device 1A according to the first embodiment.

[0224] Figure 24 is a plan view showing an example layout of the metal electrode 16 according to the third embodiment of this disclosure. Figure 25 is a plan view showing an example layout of the inorganic insulating film 37 according to the third embodiment of this disclosure. Figure 26 is a cross-sectional view showing the main part of the semiconductor device 1C according to the third embodiment, and shows the cross-section at the same position as in Figure 8B. In Figures 24 to 26, components equivalent to those in the first embodiment are given the same reference numerals as in Figures 1 to 21, and their descriptions are omitted.

[0225] The semiconductor device 1C has a trench gate type vertical structure (trench structure) as an example of a transistor structure Tr, instead of a planar gate type vertical structure (planar structure).

[0226] The semiconductor device 1C includes a chip 2, similar to the semiconductor device 1A. The chip 2 has a stacked structure including an n-type first semiconductor region 6 and an n-type second semiconductor region 7, similar to the semiconductor device 1A, and includes a first main surface 3, a second main surface 4, and first to fourth side surfaces 5A to 5C. The second semiconductor region 7 has a drift region 8.

[0227] Referring to Figures 24 and 25, the semiconductor device 1C includes a metal electrode 16 and an inorganic insulating film 37. The metal electrode 16 includes a first source pad electrode 21, a second source pad electrode 22, a source wiring 20, a gate pad electrode 24, and a gate wiring 25. The inorganic insulating film 37 includes a first source pad inorganic film 38, a second source pad inorganic film 39, a source wiring inorganic film 40, a gate pad inorganic film 41, and a gate wiring inorganic film 42.

[0228] The first source pad inorganic film 38 has a first source inorganic opening 43. The first source inorganic opening 43 exposes the first source pad 31. The second source pad inorganic film 39 has a second source inorganic opening 44. The second source inorganic opening 44 exposes the second source pad 33. The gate pad inorganic film 41 has a gate inorganic pad opening 45. The gate inorganic pad opening 45 exposes the gate pad 35.

[0229] Referring to Figure 26, the semiconductor device 1C includes a plurality of trench gate structures 200. The plurality of trench gate structures 200 include a plurality of gate trenches 201 arranged in a stripe pattern extending along a first direction X, a gate insulating film 203 formed on the inner surface of the plurality of gate trenches 201, and gate electrodes 204 embedded in the plurality of gate trenches 201 via the gate insulating film 203.

[0230] Multiple gate trenches 201 are formed on the first main surface 3. The gate trenches 201 penetrate the source region 51 and the body region 50 and reach the drift region 8. Between adjacent gate trenches 201, mesa portions 202 are formed by a part of the second semiconductor region 7. The mesa portions 202 are strip-shaped and extend along the first direction X, and are arranged alternately in the second direction Y. Multiple mesa portions 202 are arranged in a stripe pattern as a whole.

[0231] Each mesa portion 202 provides a unit cell UC of a trench gate type transistor structure Tr. Each mesa portion 202 may be the smallest unit that functions as an MIS transistor, comprising at least a body region 50 and a source region 51. The body region 50 and the source region 51 are formed sequentially in the mesa portion 202 in the direction from the bottom of the gate trench 201 toward the first main surface 3.

[0232] The gate insulating film 203 covers the inner surface of the gate trench 201. The gate insulating film 203 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 203 has a single-layer structure made of a silicon oxide film. The gate insulating film 203 may also include a silicon oxide film made of the oxide of the chip 2.

[0233] The gate electrode 204 may also be referred to as an "embedded conductive layer." The gate electrode 204 faces the body region 50 (channel region 52) with the gate insulating film 203 in between. The gate electrode 204 may contain p-type or n-type conductive polysilicon.

[0234] In this embodiment, similar to the first embodiment, the metal electrode 16 (first source pad electrode 21, second source pad electrode 22, source wiring 20, gate pad electrode 24, and gate wiring 25) has an aperture group 82 having a plurality of first openings 81. The aperture group 82 is formed in an aperture group forming region 80 that is selectively set on the metal electrode 16.

[0235] Semiconductor device 1C provides the same effects and benefits as those described in relation to semiconductor device 1A according to the first embodiment.

[0236] Furthermore, the semiconductor device 1B according to the second embodiment may be combined with the semiconductor device 1C according to the third embodiment. That is, in the semiconductor device 1C in which a trench gate type vertical structure is adopted as the device structure, the metal electrode 16 does not need to have source wiring 20.

[0237] Figure 27 is a plan view showing an example layout of the metal electrode 16D according to the fourth embodiment of this disclosure. Figure 28 is a plan view showing an example layout of the inorganic insulating film 37 according to the fourth embodiment of this disclosure. Figure 29 is a cross-sectional view taken along the line XXIX-XXIX shown in Figure 27.

[0238] A semiconductor device 1D according to the fourth embodiment of this disclosure has a modified configuration of the device structure related to semiconductor device 1A. More specifically, semiconductor device 1D has a Schottky barrier diode 300 (Schottky Barrier Diode structure) on the first main surface 3 instead of an insulated gate type transistor structure Tr as a device structure. Semiconductor device 1D may also be referred to as a semiconductor rectifier.

[0239] The semiconductor device 1D includes a chip 2, similar to the semiconductor device 1A. The chip 2 has a stacked structure including an n-type first semiconductor region 6 and an n-type second semiconductor region 7, similar to the semiconductor device 1A, and includes a first main surface 3, a second main surface 4, and first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a drift region 8.

[0240] Referring to Figure 29, the semiconductor device 1D includes a p-type guard region 301 formed on the surface of the first main surface 3. The guard region 301 is an example of a second-conductivity anode region. The guard region 301 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The guard region 301 is formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.

[0241] The guard region 301 extends in a band shape along the periphery of the first main surface 3. In this configuration, the guard region 301 is formed in a polygonal ring (quadrilateral ring) shape surrounding the inner part of the first main surface 3. The guard region 301 is formed on the surface of the second semiconductor region 7 with a gap between it and the first main surface 3 from the first semiconductor region 6, and faces the first semiconductor region 6 with a portion of the second semiconductor region 7 in between.

[0242] Referring to Figures 27 to 29, the semiconductor device 1D includes an insulating interlayer film 15 that selectively covers the first main surface 3. The interlayer film 15 includes contact openings 303 that selectively expose the first main surface 3 and the guard region 301. The contact openings 303 expose the inner portion of the first main surface 3 and the inner edge of the guard region 301.

[0243] The semiconductor device 1D includes a metal electrode 16D disposed on the interlayer film 15. In this embodiment, the metal electrode 16D is an anode electrode 304 to which an anode potential is applied. The anode electrode 304 is an example of a Schottky electrode. The anode electrode 304 is an example of a pad electrode. In a plan view, the anode electrode 304 is formed in a rectangular shape having four sides parallel to the first to fourth sides 5A to 5D.

[0244] The anode electrode 304 comprehensively covers the region of the interlayer film 15 where the contact opening 303 is formed. The anode electrode 304 is mechanically and electrically connected to the second semiconductor region 7 and the guard region 301 on the first main surface 3. The anode electrode 304 forms a Schottky junction with the second semiconductor region 7. This forms a Schottky barrier diode 300, which is an example of a device structure.

[0245] The semiconductor device 1D includes an organic insulating film 30 that covers the interlayer film 15 on the first main surface 3 and selectively covers the metal electrode 16D. The organic insulating film 30 is formed in a rectangular shape with four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The peripheral edge of the organic insulating film 30 is formed with a gap in the inward region from the first to fourth side surfaces 5A to 5D, exposing the first main surface 3.

[0246] An anode opening 305 is formed in the inner part of the organic insulating film 30. In a plan view, the anode opening 305 is formed in a rectangular shape along the periphery of the anode electrode 304. The anode opening 305 exposes the inner part of the electrode surface of the anode electrode 304 as an anode pad 306.

[0247] The semiconductor device 1D includes an inorganic insulating film 37 disposed between the anode electrode 304 (metal electrode 16D) and the organic insulating film 30. The inorganic insulating film 37 includes an anode inorganic insulating film 307. The anode inorganic insulating film 307 covers the peripheral edge of the anode electrode 304.

[0248] An anode inorganic pad opening 308 is formed in the anode inorganic insulating film 307. In a plan view, the anode inorganic pad opening 308 is formed in a rectangular shape along the periphery of the anode electrode 304. The anode inorganic pad opening 308 exposes the inner part of the electrode surface of the anode electrode 304 as the anode pad 306. In a plan view, the anode inorganic pad opening 308 overlaps with the anode opening 305 of the organic insulating film 30.

[0249] In this configuration, the inner wall of the anode inorganic pad opening 308 is aligned with the inner wall of the anode opening 305 in a plan view. In other words, the inner wall of the anode inorganic pad opening 308 communicates with the inner wall of the anode opening 305. The inner wall of the anode inorganic pad opening 308 may be located outside the anode opening 305. The inner wall of the anode inorganic pad opening 308 may be located inside the anode opening 305.

[0250] In this configuration, the anode electrode 304 has an aperture group 82 having a plurality of first apertures 81. The aperture group 82 is formed in an aperture group forming region 80 selectively set on the metal electrode 16. The plurality of first apertures 81 expose the interlayer film 15. The bottom of the inner wall of the plurality of first apertures 81 penetrates the anode electrode 304 in the thickness direction (vertical direction Z).

[0251] The inorganic insulating film 37 includes a plurality of anchor portions 91. The bottom of each anchor portion 91 is in contact with the upper surface of the interlayer film 15. The inorganic insulating film 37 may have a plurality of second openings 86 formed in each of the plurality of anchor portions 91.

[0252] A cathode electrode 309 to which a cathode potential is applied is positioned on the second main surface 4.

[0253] The semiconductor device 1D provides the same effects and benefits as those described in relation to the semiconductor device 1A according to the first embodiment.

[0254] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0255] One of the objectives of this disclosure is to provide a semiconductor device in which damage to the inorganic insulating film covering the metal electrode is suppressed.

[0256] [Note 1-1] The device comprises a chip (2) having a main surface, a device structure (Tr) formed on the main surface (3), metal electrodes (16, 16B) covering the main surface (3), an inorganic insulating film (37, 37B) covering the metal electrodes (16, 16B), and an organic insulating film (30) covering the metal electrodes (16, 16B) with the inorganic insulating film (37, 37B) in between, wherein the metal electrodes (16, 16B) have pad electrodes (21, 22, 24), and the organic insulating film (30) has a first organic opening (32) that exposes the pad electrodes (21, 22, 24) as a first pad (31), and a second organic opening (34, 36) that exposes the pad electrodes (21, 22, 24) as a second pad (33, 35). The inorganic insulating film (37, 37B) includes a first pad inorganic film (38) having a first inorganic opening (43) that exposes the first pad (31), and a second pad inorganic film (39, 41) having a second inorganic opening (44, 45) that exposes the second pads (33, 35), wherein the first pad inorganic film (38) and the second pad inorganic films (39, 41) are separated and not mechanically connected to each other, in a semiconductor device (1A, 1B, 1C).

[0257] [Note 1-2] The semiconductor device (1A, 1B, 1C) according to Note 1-1, wherein the metal electrodes (16, 16B) include source pad electrodes (21, 22), the first pad inorganic film (38) includes a first source pad inorganic film (38) having a first source inorganic opening (43) that exposes the first source pad (31) as the first pad (31), and the second pad inorganic film (33) includes a second source pad inorganic film (33) having a second source inorganic opening (44) that exposes the second source pad (33) as the second pad (33).

[0258] [Note 1-3] The semiconductor device (1A, 1B, 1C) according to Note 1-1 or Note 1-2, wherein the inorganic insulating film (37, 37B) has a first film thickness (T1) that is smaller than the second film thickness (T2) of the metal electrode (16, 16B).

[0259] [Appendix 1-4] The semiconductor device (1A, 1B, 1C) according to Appendix 1-3, wherein the film thickness ratio of the first film thickness (T1) to the second film thickness (T2) is 0.1 or more and less than 1.0.

[0260] [Appendix 1-5] The semiconductor device (1A, 1B, 1C) according to Appendix 1-3 or Appendix 1-4, wherein the first film thickness (T1) is 1 μm or more.

[0261] [Appendix 1-6] The semiconductor device (1A, 1B, 1C) described in any one of Appendix 1-3 to 1-5, wherein the second film thickness (T2) is 4 μm or more.

[0262] [Appendix 1-7] The semiconductor device (1A, 1B, 1C) according to any one of the appendices 1-1 to 1-6, wherein the metal electrodes (16, 16B) include an aperture group forming region (80) in which a plurality of first apertures (81, 81A, 81B) are formed, and the inorganic insulating film (37, 37B) includes a plurality of anchor portions (91) that penetrate into the plurality of first apertures (81, 81A, 81B).

[0263] [Appendix 1-8] A semiconductor device (1A, 1B, 1C) according to Appendix 1-7, comprising an interlayer film (15) covering the main surface (3), wherein a plurality of first openings (81, 81A, 81B) expose the interlayer film (15), and a plurality of anchor portions (91) are in contact with the interlayer film (15).

[0264] [Note 1-9] The semiconductor device (1A, 1B, 1C) according to Note 1-8, wherein the inorganic insulating film (37, 37B) has a second opening (86) in the anchor portion (91) that exposes the interlayer film (15).

[0265] [Appendix 1-10] The semiconductor device (1A, 1B, 1C) according to Appendix 1-7 or Appendix 1-8, wherein the plurality of first openings (81, 81A) are slit-shaped.

[0266] [Appendix 1-11] The semiconductor device (1A, 1B, 1C) according to Appendix 1-10, wherein the aperture group forming region (80) is formed in a strip shape in plan view, and the plurality of first apertures (81, 81A) are slit-shaped along the direction in which the aperture group forming region (80) extends.

[0267] [Appendix 1-12] The semiconductor device (1A, 1B, 1C) according to Appendix 1-10 or Appendix 1-11, wherein the first opening (81, 81A) has a first width (W1), and the first width (W1) is narrower than the second film thickness (T2) of the metal electrode (16, 16B).

[0268] [Note 1-13] The semiconductor device (1A, 1B, 1C) described in Note 1-12, wherein the first width (W1) is 0.5 μm or more and 2 μm or less.

[0269] [Appendix 1-14] The semiconductor device (1A, 1B, 1C) according to any one of the appendices 1-7 to 1-13, wherein the plurality of first apertures (81, 81B) are arranged in a staggered pattern in plan view.

[0270] [Appendix 1-15] The semiconductor device (1A, 1B, 1C) according to any one of Appendix 1-7 to 1-13, wherein the plurality of first apertures (81, 81B) are arranged in a grid pattern in plan view.

[0271] [Appendix 1-16] The semiconductor device (1A, 1B, 1C) according to any one of Appendix 1-7 to 1-15, wherein the metal electrodes (16, 16B) include source pad electrodes (21, 22), a gate pad electrode (24), and wiring (20, 25) electrically connected to the source pad electrodes (21, 22) or the gate pad electrode (24), and the aperture group forming region (80) is formed on at least one of the periphery of the gate pad electrode (24), the periphery of the source pad electrodes (21, 22), and the wiring (20, 25).

[0272] [Appendix 1-17] The inorganic insulating film (37, 37B) contains SiN, and the semiconductor device (1A, 1B, 1C) is as described in any one of Appendix 1-1 to 1-16.

[0273] [Appendix 1-18] The semiconductor device (1A, 1B, 1C) according to any one of the appendices 1-1 to 1-17, wherein the metal electrodes (16, 16B) are formed from a metallic material including aluminum.

[0274] [Appendix 1-19] The organic insulating film (30) comprises polyimide or polyamide, as described in any one of Appendix 1-1 to 1-18, for the semiconductor device (1A, 1B, 1C).

[0275] [Appendix 1-20] The chip (2) is a semiconductor device (1A, 1B, 1C) as described in any one of Appendix 1-1 to 1-19, including a SiC chip.

[0276] [Appendix 1-21] A semiconductor device (1A, 1B) according to any one of Appendix 1-1 to 1-20, further comprising a semiconductor region (7) of a first conductivity type formed on the surface layer of the main surface (3), wherein the device structure (Tr) comprises a plurality of planar gate structures (11) having a plurality of gate electrodes (57) arranged in a stripe shape on the main surface (3), and a gate insulating film (56) between the plurality of gate electrodes (57) and the main surface (3), a plurality of body regions (50) of a second conductivity type formed on the surface layer of the semiconductor region (7) and facing the gate electrodes (57), and a source region (51) of a first conductivity type formed on the surface layer of each of the body regions (50).

[0277] [Appendix 1-22] The semiconductor device (1C) according to any one of Appendix 1-1 to 1-20, further comprising a semiconductor region (7) of a first conductivity type formed on the surface of the main surface (3), wherein the device structure (Tr) includes a body region (50) of a second conductivity type formed on the surface of the semiconductor region (7), a source region (51) of a first conductivity type formed on the surface of the body region (50), and a plurality of trench gate structures (200) having a plurality of gate trenches (201) arranged in a stripe pattern that penetrate the source region (51) and the body region (50) and reach the semiconductor region (6), a gate insulating film (203) formed on the inner surface of the plurality of gate trenches (201), and gate electrodes (204) embedded in the plurality of gate trenches (201) via the gate insulating film (203).

[0278] [Note 2-1] A semiconductor device (1A, 1B, 1C, 1D) comprising: a chip (2) having a main surface; a device structure (Tr, 300) formed on the main surface (3); metal electrodes (16, 16B, 16D) covering the main surface (3); an inorganic insulating film (37, 37B) covering the metal electrodes (16, 16B, 16D); and an organic insulating film covering the metal electrodes (16, 16B, 16D) with the inorganic insulating film (37, 37B) in between, wherein the metal electrodes (16, 16B, 16D) include an aperture group forming region (80) in which a plurality of first openings (81, 81A, 81B) are formed, and the inorganic insulating film (37, 37B) includes a plurality of anchor portions (91) that penetrate into the plurality of first openings (81, 81A, 81B).

[0279] [Note 2-2] The semiconductor device (1A, 1B, 1C, 1D) according to Note 2-1, wherein the inorganic insulating film (37, 37B) has a first film thickness (T1) that is smaller than the second film thickness (T2) of the metal electrode (16, 16B, 16D).

[0280] [Appendix 2-3] The semiconductor device (1A, 1B, 1C, 1D) described in Appendix 2-2, wherein the film thickness ratio of the first film thickness (T1) to the second film thickness (T2) is 0.1 or more and less than 1.0.

[0281] [Appendix 2-4] The semiconductor device (1A, 1B, 1C, 1D) described in Appendix 2-2 or Appendix 2-3, wherein the first film thickness (T1) is 1 μm or more.

[0282] [Appendix 2-5] A semiconductor device (1A, 1B, 1C, 1D) according to any one of the appendices 2-2 to 2-4, wherein the second film thickness (T2) is 4 μm or more.

[0283] [Appendix 2-6] A semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 2-2 to 2-5, comprising an interlayer film (15) covering the main surface (3), wherein a plurality of first openings (81, 81A, 81B) expose the interlayer film (15), and a plurality of anchor portions (91) are in contact with the interlayer film (15).

[0284] [Note 2-7] The semiconductor device (1A, 1B, 1C, 1D) according to Note 2-6, wherein the inorganic insulating film (37, 37B) has a second opening (86) in the anchor portion (91) that exposes the interlayer film (15).

[0285] [Appendix 2-8] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 2-1 to 2-7, wherein the plurality of first openings (81, 81A, 81B) are slit-shaped.

[0286] [Note 2-9] The semiconductor device (1A, 1B, 1C, 1D) according to Note 2-8, wherein the aperture group forming region (80) is formed in a strip shape in plan view, and the plurality of first apertures (81, 81A, 81B) are slit-shaped along the direction in which the aperture group forming region (80) extends.

[0287] [Appendix 2-10] The semiconductor device (1A, 1B, 1C) according to Appendix 2-8 or Appendix 2-9, wherein the first opening (81, 81A, 81B) has a first width (W1), and the first width (W1) is narrower than the second film thickness (T2) of the metal electrode (16, 16B, 16D).

[0288] [Note 2-11] The semiconductor device described in Note 2-10 (1A, 1B, 1C, 1D), wherein the first width (W1) is 0.5 μm or more and 2 μm or less.

[0289] [Appendix 2-12] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 2-1 to 2-11, wherein the plurality of first openings (81, 81B) are arranged in a staggered pattern in plan view.

[0290] [Appendix 2-13] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 2-1 to 1-11, wherein the plurality of first apertures (81, 81B) are arranged in a grid pattern in plan view.

[0291] [Appendix 2-14] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 2-5 to 2-13, wherein the metal electrodes (16, 16B, 16D) include source pad electrodes (21, 22), a gate pad electrode (24), and wiring (20, 25) electrically connected to the source pad electrodes (21, 22) or the gate pad electrode (24), and the aperture group forming region (80) is formed on at least one of the periphery of the gate pad electrode (24), the periphery of the source pad electrodes (21, 22), and the wiring (20, 25).

[0292] [Appendix 2-15] The inorganic insulating film (37, 37B) is a semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 2-1 to 2-14, including SiN.

[0293] [Appendix 2-16] The semiconductor device (1A, 1B, 1C, 1D) described in any one of Appendix 2-1 to 2-15, wherein the metal electrodes (16, 16B, 16D) are formed from a metallic material including aluminum.

[0294] [Appendix 2-17] The organic insulating film (30) comprises polyimide or polyamide, as described in any one of Appendix 2-1 to 2-18, for the semiconductor device (1A, 1B, 1C, 1D).

[0295] [Appendix 2-18] The chip (2) is a semiconductor device (1A, 1B, 1C, 1D) as described in any one of Appendix 2-1 to 2-17, including a SiC chip.

[0296] [Appendix 2-19] A semiconductor device (1A, 1B) according to any one of Appendix 2-1 to 2-18, further comprising a semiconductor region (7) of a first conductivity type formed on the surface layer of the main surface (3), wherein the device structure (Tr) comprises a plurality of planar gate structures (11) having a plurality of gate electrodes (57) arranged in a stripe shape on the main surface (3), and a gate insulating film (56) between the plurality of gate electrodes (57) and the main surface (3), a plurality of body regions (50) of a second conductivity type formed on the surface layer of the semiconductor region (7) and facing the gate electrodes (57), and a source region (51) of a first conductivity type formed on the surface layer of each of the body regions (50).

[0297] [Appendix 2-20] The semiconductor device (1C) according to any one of Appendix 2-1 to 2-18, further comprising a semiconductor region (7) of a first conductivity type formed on the surface of the main surface (3), wherein the device structure (Tr) includes a body region (50) of a second conductivity type formed on the surface of the semiconductor region (7), a source region (51) of a first conductivity type formed on the surface of the body region (50), and a plurality of trench gate structures (200) having a plurality of gate trenches (201) arranged in a stripe pattern that penetrate the source region (51) and the body region (50) and reach the semiconductor region (6), a gate insulating film (203) formed on the inner surface of the plurality of gate trenches (201), and gate electrodes (204) embedded in the plurality of gate trenches (201) via the gate insulating film (203).

[0298] [Appendix 2-21] A semiconductor device (1D) according to any one of Appendix 2-1 to 2-18, further comprising a semiconductor region (7) of a first conductivity type formed on the surface of the main surface (3), wherein the device structure (Tr) includes a Schottky barrier diode (300) which includes a second conductivity type anode region (301) formed on the surface of the semiconductor region (7) and a Schottky electrode (304) Schottky bonded to the anode region (301).

[0299] 1A: Semiconductor device, 1B: Semiconductor device, 1C: Semiconductor device, 1D: Semiconductor device, 2: Chip, 3: First main surface, 4: Second main surface, 5A: First side surface, 5B: Second side surface, 5C: Third side surface, 5D: Fourth side surface, 6: First semiconductor region, 7: Second semiconductor region, 8: Drift region, 9: Active region, 10: Outer periphery region, 11: Gate structure, 12: Outer well region, 13: First outer well region, 14: Second outer well region, 15: Interlayer film, 16: Metal electrode, 17: Source metal, 18: Gate metal, 19: Source pad electrode, 20: Source wiring, 21: First source pad 1: Pad electrode (pad electrode), 22: Second source pad electrode (pad electrode), 24: Gate pad electrode (pad electrode), 25: Gate wiring, 26: Base wiring, 27: Finger wiring, 27A: First finger wiring, 27B: Second finger wiring, 27C: Third finger wiring, 28A: First tip, 28B: Second tip, 28C: Third tip, 30: Organic insulating film, 31: First source pad (first pad), 32: First source pad opening (first organic opening), 33: Second source pad (second pad), 34: Second source pad opening (second organic opening), 35: Gate Pad (second pad), 36: Gate pad opening (second organic opening), 37: Inorganic insulating film, 38: First source pad inorganic film (first pad inorganic film), 39: Second source pad inorganic film (second pad inorganic film), 40: Source wiring inorganic film, 41: Gate pad inorganic film (second pad inorganic film), 42: Gate wiring inorganic film, 43: First source inorganic opening (first inorganic opening), 44: Second source inorganic opening (second inorganic opening), 45: Gate inorganic opening (second inorganic opening), 46: Drain electrode, 50: Body region, 51: Source region, 52: Channel region, 53: Body contact region, 5 6: Gate insulating film, 57: Gate electrode, 58: Source contact opening, 60: Outer contact region, 61: Outer opening, 62: Outer insulating film, 63: Lower electrode layer, 70: Electrode surface, 71: Side wall, 72: Recess, 73: Side wall, 80: Aperture group formation region, 80A: First aperture group formation region, 80B: Second aperture group formation region, 80C: Third aperture group formation region, 80D: Fourth aperture group formation region, 81: First opening, 82: Aperture group, 86: Second opening, 90: Main body, 91: Anchor part, 92: Insulating film coating part, 200: Trench gate structure, 201: Gate trench, 202: Mesa part,203: Gate insulating film, 204: Gate electrode, 300: Schottky barrier diode (device structure), 301: Guard region (anode region), 303: Contact opening, 304: Anode electrode (Schottky electrode), 305: Anode opening, 306: Anode pad, 307: Anode inorganic insulating film, 308: Anode inorganic pad opening, 309: Cathode electrode, C: Corner, C1: Corner, D1: Extension direction, D2: Crossing direction, T1: First film thickness, T2: Second film thickness, T3: Third film thickness, Tr: Transistor structure (device structure), UC: Unit cell, X: First direction, Y: Second direction, Z: Vertical direction

Claims

1. A semiconductor device comprising: a chip having a main surface; a device structure formed on the main surface; a metal electrode covering the main surface; an inorganic insulating film covering the metal electrode; and an organic insulating film covering the metal electrode with the inorganic insulating film in between, wherein the metal electrode has a pad electrode; the organic insulating film has a first organic opening that exposes the pad electrode as a first pad and a second organic opening that exposes the pad electrode as a second pad; the inorganic insulating film comprises a first pad inorganic film having a first inorganic opening that exposes the first pad and a second pad inorganic film having a second inorganic opening that exposes the second pad, wherein the first pad inorganic film and the second pad inorganic film are separated from each other and not mechanically connected to each other.

2. The semiconductor device according to claim 1, wherein the metal electrode includes a source pad electrode, the first pad inorganic film includes a first source pad inorganic film having a first source inorganic opening that exposes the first source pad as the first pad, and the second pad inorganic film includes a second source pad inorganic film having a second source inorganic opening that exposes the second source pad as the second pad.

3. The semiconductor device according to claim 1 or 2, wherein the inorganic insulating film has a first film thickness that is smaller than the second film thickness of the metal electrode.

4. The semiconductor device according to claim 3, wherein the film thickness ratio of the first film thickness to the second film thickness is 0.1 or more and less than 1.

0.

5. The semiconductor device according to claim 3 or 4, wherein the first film thickness is 1 μm or more.

6. The semiconductor device according to any one of claims 3 to 5, wherein the second film thickness is 4 μm or more.

7. The semiconductor device according to any one of claims 1 to 6, wherein the metal electrode includes an aperture group forming region in which a plurality of first apertures are formed, and the inorganic insulating film includes a plurality of anchor portions that have entered into the plurality of first apertures.

8. The semiconductor device according to claim 7, comprising an interlayer film covering the main surface, wherein a plurality of the first openings expose the interlayer film, and a plurality of the anchor portions are in contact with the interlayer film.

9. The semiconductor device according to claim 8, wherein the inorganic insulating film has a second opening in the anchor portion that exposes the interlayer film.

10. The semiconductor device according to claim 7 or 8, wherein the first opening is slit-shaped.

11. The semiconductor device according to claim 10, wherein the aperture group forming region is formed in a strip shape in a plan view, and the first aperture is slit-shaped along the direction in which the aperture group forming region extends.

12. The semiconductor device according to claim 10 or 11, wherein the first opening has a first width, and the first width is narrower than the second film thickness of the metal electrode.

13. The semiconductor device according to claim 12, wherein the first width is 0.5 μm or more and 2.0 μm or less.

14. The semiconductor device according to any one of claims 7 to 13, wherein the plurality of first apertures are arranged in a staggered pattern in plan view.

15. The semiconductor device according to any one of claims 7 to 13, wherein the plurality of first apertures are lattice-shaped in plan view.

16. The semiconductor device according to any one of claims 7 to 15, wherein the metal electrode includes a source pad electrode, a gate pad electrode, and wiring electrically connected to the source pad electrode or the gate pad electrode, and the aperture group forming region is formed on at least one of the periphery of the gate pad electrode, the periphery of the source pad electrode, and the wiring.

17. The semiconductor device according to any one of claims 1 to 16, wherein the inorganic insulating film includes SiN.

18. The semiconductor device according to any one of claims 1 to 17, wherein the metal electrode is formed of a metallic material including aluminum.

19. The semiconductor device according to any one of claims 1 to 18, wherein the organic insulating film comprises polyimide or polyamide.

20. The semiconductor device according to any one of claims 1 to 19, wherein the chip includes a SiC chip.

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