A method performed by a device, a device, and a storage medium

Abstract

A device shuffles variable nodes of a first low density parity check, LDPC, base matrix of size nc×nv to obtain a second LDPC base matrix of size nc×nv; and decoding coded blocks 0 to (L-1) based on the second LDPC base matrix to determine code blocks 0 to (L-1) for a transport block.

Description

A METHOD PERFORMED BY A DEVICE, A DEVICE, AND A STORAGE MEDIUM

[0001] The present invention relates to a wireless communication system.

[0002] A conventional low-density parity-check (LDPC) encoding method has been used in wireless communication systems such as the 5G new radio communication standard, WiFi standard IEEE 802.11ax, digital video broadcasting standard DVB-S2, and solid-state NAND flash memory. The LDPC encoding method is basically a type of linear block code and, therefore, operation of the LDPC encoding method is performed by multiplication of a parity check matrix by an input vector.

[0003] To support wide coverage of data transmission, it is necessary to support various code rates. To meet such a requirement, various encoding methods based on an LDPC code are under discussion.

[0004] As higher communication capacity and more reliable communications have been demanded, channel coding schemes providing greater channel coding efficiency are needed.

[0005] The technical objects that can be achieved through the present invention are not limited to what has been particularly described hereinabove and other technical objects not described herein will be more clearly understood by persons skilled in the art from the following detailed description.

[0006] In an aspect of the present disclosure, provided herein is a method performed by a device. In another aspect of the present disclosure, provided herein is a device, wherein the device comprises at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations. In a further aspect of the present disclosure, provided herein is a computer-readable storage medium configured to store at least one program code comprising instructions that, when executed, cause at least one processor to perform operations.

[0007] In each aspect of the present disclosure, shuffling variable nodes of a first low density parity check, LDPC, base matrix of size nc×nvto obtain a second LDPC base matrix of size nc×nv; and decoding coded blocks 0 to (L-1) based on the second LDPC base matrix to determine code blocks 0 to (L-1) for a transport block. In each aspect of the present disclosure, decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix may comprise: applying a windowed decoder to coded blocks i, i+1, ..., i+W-1 to obtain code blocks i, i+1, ..., i+k-1 based on a submatrix l for a window l of windowed decoding, where W ≥ w+k, w is a coupling width, k = n / m, and j = 0, ..., (L / k)-1; and applying windowed decoder to coded blocks i+k, ..., i+k+W-1 to obtain code blocks i+k to i+2k-1 based on a submatrix l+1 for a window l+1 of the window decoding. Shuffling the variable nodes of the first LDPC base matrix may comprise shuffling variable nodes for neighboring coded blocks j to j+k-1 such that a set of variable nodes for one of the neighboring coded blocks j to j+k-1 is connected to check nodes of another one of the neighboring coded blocks j to j+k-1, where j = 0, ..., L-k-1, wherein each of the submatrices l and (l+1) is a (W*bc)-by-(W*bv) matrix, where nc×nv= ((L+w)bc)×(Lbv).

[0008] In each aspect of the present disclosure, the second LDPC base matrix may beB[0, L-1], where , where , whereBis a base matrix for one code block.

[0009] In each aspect of the present disclosure, each of the submatrices l and (l+1) may beB[0, W-1]in the second LDPC base matrix.

[0010] In each aspect of the present disclosure, the method or the operations may further comprise: replacing component base matricesBw,Bw-1,...,Bw-sbyBw`to obtain a third LDPC base matrix, wheres is an integer larger than 1 and smaller than w, . In each aspect of the present disclosure, decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix may comprise: decoding the coded blocks 0 to (L-1) by using the third LDPC base matrix.

[0011] In each aspect of the present disclosure, the method or the operations may further comprise: each of the submatrices l and (l+1) may beB[0, W-1]in the third LDPC base matrix.

[0012] The above technical solutions are merely some parts of the examples of the present invention and various examples into which the technical features of the present invention are incorporated can be derived and understood by persons skilled in the art from the following detailed description of the present invention.

[0013] According to some implementations of the present disclosure, higher data throughput than the legacy LDPC codes may be achieved.

[0014] It will be appreciated by persons skilled in the art that that the effects that can be achieved through the present invention are not limited to what has been particularly described hereinabove and other advantages of the present invention will be more clearly understood from the following detailed description.

[0015] The accompanying drawings, which are included to provide a further understanding of the present disclosure, illustrate examples of implementations of the present disclosure and together with the detailed description serve to explain implementations of the present disclosure:

[0016] FIG. 1 illustrates an example of a communication system 1 to which implementations of the present disclosure are applied;

[0017] FIG. 2 is a block diagram illustrating examples of communication devices capable of performing a method according to the present disclosure;

[0018] FIG. 3 illustrates a process for processing a transport block (TB) on a transmitting side;

[0019] FIG. 4 is a diagram illustrating an example of TB encoding procedure

[0020] FIG. 5 is a diagram to explain a rate matching process according to some implementations of the present disclosure;

[0021] FIG. 6 is an example of a parity check matrix (PCM) of an LDPC code and the corresponding Tanner graph

[0022] FIG. 7 is an example of a codeword generated by encoding;

[0023] FIG. 8 shows an example of converting the PCM of an LDPC code from non-systematic form into a systematic form;

[0024] FIGS. 9 and 10 are illustrated to explain a parity check matrix of an LDPC code through a bipartite graph;

[0025] FIG. 11 shows an example of graphical representation of the concatenation of single parity check codes and repetition codes in an LDPC code;

[0026] FIG. 12 illustrates an example of edge spreading technique for an LDPC protograph;

[0027] FIG. 13 illustrates an example of constructing a spatially coupled (SC) LDPC code by edge spreading;

[0028] FIGS. 14 and 15 illustrate examples of a base matrix expressed by component base matrices;

[0029] FIG. 16 illustrates an example of copy-and-permute procedure applied to an SC LDPC protograph;

[0030] FIG. 17 illustrates an example of a PCM of an SC LDPC code;

[0031] FIG. 18 illustrates examples of encoding procedures for (a) block LDPC codes and (b) SC LDPC codes;

[0032] FIG. 19 illustrates an example of windowed decoding;

[0033] FIG. 20 illustrates an example of windowed decoding over a base matrix of a (3, 6, L)SC-LDPC code;

[0034] FIGS. 21 to 24 illustrate an example of sliding steps of windowed decoding for target sub-code block;

[0035] FIG. 25 illustrates an example of construction procedure of a (dv,dc,L,β) partial spatially coupled (PSC) LDPC code;

[0036] FIG. 26 illustrates an example of a parity check matrix (PCM) of a PSC LDPC code;

[0037] FIGS. 27 and 28 illustrate overall structures of PCMsHof PSC LDPC codes;

[0038] FIG. 29 illustrates an example of the base matrix view of the windowed decoding over a (3, 6,L,β) PSC LDPC code;

[0039] FIG. 30 illustrates an example of the window decoding step at the 2ndtarget sub-code block of a (3, 6,L,β) PSC LDPC code;

[0040] FIG. 31 illustrates an example of a block LDPC protograph;

[0041] FIG. 32 illustrates an example of shuffling between neighboring block protographs at different interval t;

[0042] FIG. 33 illustrates the shuffling of variable nodes of block LDPC protographs at different indexes from a matrix perspective;

[0043] FIG. 34 illustrates an example of coupling between neighboring sub-code blocks using the block LDPC connections;

[0044] FIG. 35 illustrates an example of windowed decoding according to some implementations of the present disclosure;

[0045] FIG. 36 shows examples of window configuration of first target sub-code block SC LDPC ensembles with component base matrices;

[0046] FIG. 37 shows an example of a window configuration for decoding a target sub-code block at the middle of the SC LDPC chain;

[0047] FIG. 38 shows an example of window configurations of W = 3 for SC LDPC ensembles;

[0048] FIG. 39 illustrates an example of edge-spreading technique with respect to the base matrix of an SC-LDPC protograph;

[0049] FIG. 40 illustrates an example of reducing the coupling width in the SC LDPC part of PSC LDPC codes according to some implementations of the present disclosure;

[0050] FIG. 41 shows an example of a base matrix of a PSC LDPC code and an example of a submatrix or window configuration for windowed decoding according to some implementations of the present disclosure;

[0051] FIG. 42 to 44 illustrates an example of PSC LDPC base matrix made according to some implementations of the present disclosure; and

[0052] FIG. 45 illustrates a channel decoding process according to some implementations of the present disclosure.

[0053] Hereinafter, implementations according to the present disclosure will be described in detail with reference to the accompanying drawings. The detailed description, which will be given below with reference to the accompanying drawings, is intended to explain exemplary implementations of the present disclosure, rather than to show the only implementations that may be implemented according to the present disclosure. The following detailed description includes specific details in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without such specific details.

[0054] In some instances, known structures and devices may be omitted or may be shown in block diagram form, focusing on important features of the structures and devices, so as not to obscure the concept of the present disclosure. The same reference numbers will be used throughout the present disclosure to refer to the same or like parts.

[0055] A technique, a device, and a system described below may be applied to a variety of wireless multiple access systems. The multiple access systems may include, for example, a code division multiple access (CDMA) system, a frequency division multiple access (FDMA) system, a time division multiple access (TDMA) system, an orthogonal frequency division multiple access (OFDMA) system, a single-carrier frequency division multiple access (SC-FDMA) system, a multi-carrier frequency division multiple access (MC-FDMA) system, etc. CDMA may be implemented by radio technology such as universal terrestrial radio access (UTRA) or CDMA2000. TDMA may be implemented by radio technology such as global system for mobile communications (GSM), general packet radio service (GPRS), enhanced data rates for GSM evolution (EDGE) (i.e., GERAN), etc. OFDMA may be implemented by radio technology such as institute of electrical and electronics engineers (IEEE) 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20, evolved-UTRA (E-UTRA), etc. UTRA is part of universal mobile telecommunications system (UMTS) and 3rd generation partnership project (3GPP) long-term evolution (LTE) is part of E-UMTS using E-UTRA. 3GPP LTE adopts OFDMA on downlink (DL) and adopts SC-FDMA on uplink (UL). LTE-advanced (LTE-A) is an evolved version of 3GPP LTE.

[0056] For convenience of description, description will be given under the assumption that the present disclosure is applied to LTE and / or new RAT (NR). However, the technical features of the present disclosure are not limited thereto. For example, although the following detailed description is given based on mobile communication systems corresponding to 3GPP LTE / NR systems, the mobile communication systems are applicable to other arbitrary mobile communication systems except for matters that are specific to the 3GPP LTE / NR system.

[0057] For terms and techniques that are not described in detail among terms and techniques used in the present disclosure, reference may be made to 3GPP based standard specifications, for example, 3GPP TS 36.211, 3GPP TS 36.212, 3GPP TS 36.213, 3GPP TS 36.321, 3GPP TS 36.300, 3GPP TS 36.331, 3GPP TS 37.213, 3GPP TS 38.211, 3GPP TS 38.212, 3GPP TS 38.213, 3GPP TS 38.214, 3GPP TS 38.300, 3GPP TS 38.321, 3GPP TS 38.331, etc.

[0058] In examples of the present disclosure described later, if a device "assumes" something, this may mean that a channel transmission entity transmits a channel in compliance with the corresponding "assumption". This also may mean that a channel reception entity receives or decodes the channel in the form of conforming to the "assumption" on the premise that the channel has been transmitted in compliance with the "assumption".

[0059] In the present disclosure, a user equipment (UE) may be fixed or mobile. Each of various devices that transmit and / or receive user data and / or control information by communicating with a base station (BS) may be the UE. The term UE may be referred to as terminal equipment, mobile station (MS), mobile terminal (MT), user terminal (UT), subscriber station (SS), wireless device, personal digital assistant (PDA), wireless modem, handheld device, etc. In the present disclosure, a BS refers to a fixed station that communicates with a UE and / or another BS and exchanges data and control information with a UE and another BS. The term BS may be referred to as advanced base station (ABS), Node-B (NB), evolved Node-B (eNB), base transceiver system (BTS), access point (AP), processing server (PS), etc. Particularly, a BS of a universal terrestrial radio access (UTRAN) is referred to as an NB, a BS of an evolved-UTRAN (E-UTRAN) is referred to as an eNB, and a BS of new radio access technology network is referred to as a gNB. Hereinbelow, for convenience of description, the NB, eNB, or gNB will be referred to as a BS regardless of the type or version of communication technology.

[0060] In the present disclosure, a node refers to a fixed point capable of transmitting / receiving a radio signal to / from a UE by communication with the UE. Various types of BSs may be used as nodes regardless of the names thereof. For example, a BS, NB, eNB, pico-cell eNB (PeNB), home eNB (HeNB), relay, repeater, etc. may be a node. Furthermore, a node may not be a BS. For example, a radio remote head (RRH) or a radio remote unit (RRU) may be a node. Generally, the RRH and RRU have power levels lower than that of the BS. Since the RRH or RRU (hereinafter, RRH / RRU) is connected to the BS through a dedicated line such as an optical cable in general, cooperative communication according to the RRH / RRU and the BS may be smoothly performed relative to cooperative communication according to BSs connected through a wireless link. At least one antenna is installed per node. An antenna may refer to a physical antenna port or refer to a virtual antenna or an antenna group. The node may also be called a point.

[0061] In the present disclosure, a cell refers to a specific geographical area in which one or more nodes provide communication services. Accordingly, in the present disclosure, communication with a specific cell may mean communication with a BS or a node providing communication services to the specific cell. A DL / UL signal of the specific cell refers to a DL / UL signal from / to the BS or the node providing communication services to the specific cell. A cell providing UL / DL communication services to a UE is especially called a serving cell. Furthermore, channel status / quality of the specific cell refers to channel status / quality of a channel or a communication link generated between the BS or the node providing communication services to the specific cell and the UE. In 3GPP-based communication systems, the UE may measure a DL channel state from a specific node using cell-specific reference signal(s) (CRS(s)) transmitted on a CRS resource and / or channel state information reference signal(s) (CSI-RS(s)) transmitted on a CSI-RS resource, allocated to the specific node by antenna port(s) of the specific node.

[0062] A 3GPP-based communication system uses the concept of a cell in order to manage radio resources, and a cell related with the radio resources is distinguished from a cell of a geographic area.

[0063] The "cell" of the geographic area may be understood as coverage within which a node may provide services using a carrier, and the "cell" of the radio resources is associated with bandwidth (BW), which is a frequency range configured by the carrier. Since DL coverage, which is a range within which the node is capable of transmitting a valid signal, and UL coverage, which is a range within which the node is capable of receiving the valid signal from the UE, depend upon a carrier carrying the signal, coverage of the node may also be associated with coverage of the "cell" of radio resources used by the node. Accordingly, the term "cell" may be used to indicate service coverage by the node sometimes, radio resources at other times, or a range that a signal using the radio resources may reach with valid strength at other times.

[0064] In 3GPP communication standards, the concept of the cell is used in order to manage radio resources. The "cell" associated with the radio resources is defined by a combination of DL resources and UL resources, that is, a combination of a DL component carrier (CC) and a UL CC. The cell may be configured by the DL resources only or by the combination of the DL resources and the UL resources. If carrier aggregation is supported, linkage between a carrier frequency of the DL resources (or DL CC) and a carrier frequency of the UL resources (or UL CC) may be indicated by system information. For example, the combination of the DL resources and the UL resources may be indicated by system information block type 2 (SIB2) linkage. In this case, the carrier frequency may be equal to or different from a center frequency of each cell or CC. When carrier aggregation (CA) is configured, the UE has only one radio resource control (RRC) connection with a network. During RRC connection establishment / re-establishment / handover, one serving cell provides non-access stratum (NAS) mobility information. During RRC connection re-establishment / handover, one serving cell provides security input. This cell is referred to as a primary cell (Pcell). The Pcell refers to a cell operating on a primary frequency on which the UE performs an initial connection establishment procedure or initiates a connection re-establishment procedure. According to UE capability, secondary cells (Scells) may be configured to form a set of serving cells together with the Pcell. The Scell may be configured after completion of RRC connection establishment and used to provide additional radio resources in addition to resources of a specific cell (SpCell). A carrier corresponding to the Pcell on DL is referred to as a downlink primary CC (DL PCC), and a carrier corresponding to the Pcell on UL is referred to as an uplink primary CC (UL PCC). A carrier corresponding to the Scell on DL is referred to as a downlink secondary CC (DL SCC), and a carrier corresponding to the Scell on UL is referred to as an uplink secondary CC (UL SCC).

[0065] In a wireless communication system, the UE receives information on DL from the BS and the UE transmits information on UL to the BS. The information that the BS and UE transmit and / or receive includes data and a variety of control information and there are various physical channels according to types / usage of the information that the UE and the BS transmit and / or receive.

[0066] The 3GPP-based communication standards define DL physical channels corresponding to resource elements carrying information originating from a higher layer and DL physical signals corresponding to resource elements which are used by the physical layer but do not carry the information originating from the higher layer. For example, a physical downlink shared channel (PDSCH), a physical broadcast channel (PBCH), a physical multicast channel (PMCH), a physical control format indicator channel (PCFICH), a physical downlink control channel (PDCCH), etc. are defined as the DL physical channels, and a reference signal (RS) and a synchronization signal (SS) are defined as the DL physical signals. The RS, which is also referred to as a pilot, represents a signal with a predefined special waveform known to both the BS and the UE. For example, a demodulation reference signal (DMRS), a channel state information RS (CSI-RS), etc. are defined as DL RSs. The 3GPP-based communication standards define UL physical channels corresponding to resource elements carrying information originating from the higher layer and UL physical signals corresponding to resource elements which are used by the physical layer but do not carry the information originating from the higher layer. For example, a physical uplink shared channel (PUSCH), a physical uplink control channel (PUCCH), and a physical random access channel (PRACH) are defined as the UL physical channels, and a DMRS for a UL control / data signal, a sounding reference signal (SRS) used for UL channel measurement, etc. are defined.

[0067] In the present disclosure, a PDCCH refers to a set of time-frequency resources (e.g., resource elements (REs)) carrying downlink control information (DCI), and a PDSCH refers to a set of time-frequency resources carrying DL data. A PUCCH, a PUSCH, and a PRACH refer to a set of time-frequency resources carrying UCI, a set of time-frequency resources carrying UL data, and a set of time-frequency resources carrying random access signals, respectively. In the following description, "the UE transmits / receives a PUCCH / PUSCH / PRACH" is used as the same meaning that the UE transmits / receives the UCI / UL data / random access signals on or through the PUCCH / PUSCH / PRACH, respectively. In addition, "the BS transmits / receives a PBCH / PDCCH / PDSCH" is used as the same meaning that the BS transmits the broadcast information / DCI / DL data on or through a PBCH / PDCCH / PDSCH, respectively.

[0068] In this specification, a radio resource (e.g., a time-frequency resource) scheduled or configured to the UE by the BS for transmission or reception of the PUCCH / PUSCH / PDSCH may be referred to as a PUCCH / PUSCH / PDSCH resource.

[0069] Since a communication device receives a synchronization signal block (SSB), DMRS, CSI-RS, PBCH, PDCCH, PDSCH, PUSCH, and / or PUCCH in the form of radio signals on a cell, the communication device may not select and receive radio signals including only a specific physical channel or a specific physical signal through a radio frequency (RF) receiver, or may not select and receive radio signals without a specific physical channel or a specific physical signal through the RF receiver. In actual operations, the communication device receives radio signals on the cell via the RF receiver, converts the radio signals, which are RF band signals, into baseband signals, and then decodes physical signals and / or physical channels in the baseband signals using one or more processors. Thus, in some implementations of the present disclosure, not receiving physical signals and / or physical channels may mean that a communication device does not attempt to restore the physical signals and / or physical channels from radio signals, for example, does not attempt to decode the physical signals and / or physical channels, rather than that the communication device does not actually receive the radio signals including the corresponding physical signals and / or physical channels.

[0070] FIG. 1 illustrates an example of a communication system 1 to which implementations of the present disclosure are applied. Referring to FIG. 1, the communication system 1 applied to the present disclosure includes wireless devices, BSs, and a network. Here, the wireless devices represent devices performing communication using RAT (e.g., 5G NR or LTE (e.g., E-UTRA)) and may be referred to as communication / radio / 5G devices. The wireless devices may include, without being limited to, a robot 100a, vehicles 100b-1 and 100b-2, an extended reality (XR) device 100c, a hand-held device 100d, a home appliance 100e, an Internet of Things (IoT) device 100f, and an artificial intelligence (AI) device / server 400. For example, the vehicles may include a vehicle having a wireless communication function, an autonomous driving vehicle, and a vehicle capable of performing vehicle-to-vehicle communication. Here, the vehicles may include an unmanned aerial vehicle (UAV) (e.g., a drone). The XR device may include an augmented reality (AR) / virtual reality (VR) / mixed reality (MR) device and may be implemented in the form of a head-mounted device (HMD), a head-up display (HUD) mounted in a vehicle, a television, a smartphone, a computer, a wearable device, a home appliance device, a digital signage, a vehicle, a robot, etc. The hand-held device may include a smartphone, a smartpad, a wearable device (e.g., a smartwatch or smartglasses), and a computer (e.g., a notebook). The home appliance may include a TV, a refrigerator, and a washing machine. The IoT device may include a sensor and a smartmeter. For example, the BSs and the network may also be implemented as wireless devices and a specific wireless device may operate as a BS / network node with respect to another wireless device.

[0071] The wireless devices 100a to 100f may be connected to a network 300 via BSs 200. AI technology may be applied to the wireless devices 100a to 100f and the wireless devices 100a to 100f may be connected to the AI server 400 via the network 300. The network 300 may be configured using a 3G network, a 4G (e.g., LTE) network, or a 5G (e.g., NR) network. Although the wireless devices 100a to 100f may communicate with each other through the BSs 200 / network 300, the wireless devices 100a to 100f may perform direct communication (e.g., sidelink communication) with each other without passing through the BSs / network. For example, the vehicles 100b-1 and 100b-2 may perform direct communication (e.g., vehicle-to-vehicle (V2V) / Vehicle-to-everything (V2X) communication). The IoT device (e.g., a sensor) may perform direct communication with other IoT devices (e.g., sensors) or other wireless devices 100a to 100f.

[0072] Wireless communication / connections 150a and 150b may be established between the wireless devices 100a to 100f and the BSs 200 and between the wireless devices 100a to 100f). Here, the wireless communication / connections such as UL / DL communication 150a and sidelink communication 150b (or, device-to-device (D2D) communication) may be established by various RATs (e.g., 5G NR). The wireless devices and the BSs / wireless devices may transmit / receive radio signals to / from each other through the wireless communication / connections 150a and 150b. To this end, at least a part of various configuration information configuring processes, various signal processing processes (e.g., channel encoding / decoding, modulation / demodulation, and resource mapping / demapping), and resource allocating processes, for transmitting / receiving radio signals, may be performed based on the various proposals of the present disclosure.

[0073] FIG. 2 is a block diagram illustrating examples of communication devices capable of performing a method according to the present disclosure. Referring to FIG. 2, a first wireless device 100 and a second wireless device 200 may transmit and / or receive radio signals through a variety of RATs (e.g., LTE and NR). Here, {the first wireless device 100 and the second wireless device 200} may correspond to {the wireless device 100x and the BS 200} and / or {the wireless device 100x and the wireless device 100x} of FIG. 1.

[0074] The first wireless device 100 may include one or more processors 102 and one or more memories 104 and additionally further include one or more transceivers 106 and / or one or more antennas 108. The processor(s) 102 may control the memory(s) 104 and / or the transceiver(s) 106 and may be configured to implement the below-described / proposed functions, procedures, and / or methods. For example, the processor(s) 102 may process information within the memory(s) 104 to generate first information / signals and then transmit radio signals including the first information / signals through the transceiver(s) 106. The processor(s) 102 may receive radio signals including second information / signals through the transceiver(s) 106 and then store information obtained by processing the second information / signals in the memory(s) 104. The memory(s) 104 may be connected to the processor(s) 102 and may store a variety of information related to operations of the processor(s) 102. For example, the memory(s) 104 may perform a part or all of processes controlled by the processor(s) 102 or store software code including instructions for performing the below-described / proposed procedures and / or methods. Here, the processor(s) 102 and the memory(s) 104 may be a part of a communication modem / circuit / chip designed to implement RAT (e.g., LTE or NR). The transceiver(s) 106 may be connected to the processor(s) 102 and transmit and / or receive radio signals through one or more antennas 108. Each of the transceiver(s) 106 may include a transmitter and / or a receiver. The transceiver(s) 106 is used interchangeably with radio frequency (RF) unit(s). In the present disclosure, the wireless device may represent the communication modem / circuit / chip.

[0075] The second wireless device 200 may include one or more processors 202 and one or more memories 204 and additionally further include one or more transceivers 206 and / or one or more antennas 208. The processor(s) 202 may control the memory(s) 204 and / or the transceiver(s) 206 and may be configured to implement the below-described / proposed functions, procedures, and / or methods. For example, the processor(s) 202 may process information within the memory(s) 204 to generate third information / signals and then transmit radio signals including the third information / signals through the transceiver(s) 206. The processor(s) 202 may receive radio signals including fourth information / signals through the transceiver(s) 106 and then store information obtained by processing the fourth information / signals in the memory(s) 204. The memory(s) 204 may be connected to the processor(s) 202 and may store a variety of information related to operations of the processor(s) 202. For example, the memory(s) 204 may perform a part or all of processes controlled by the processor(s) 202 or store software code including instructions for performing the below-described / proposed procedures and / or methods. Here, the processor(s) 202 and the memory(s) 204 may be a part of a communication modem / circuit / chip designed to implement RAT (e.g., LTE or NR). The transceiver(s) 206 may be connected to the processor(s) 202 and transmit and / or receive radio signals through one or more antennas 208. Each of the transceiver(s) 206 may include a transmitter and / or a receiver. The transceiver(s) 206 is used interchangeably with RF unit(s). In the present disclosure, the wireless device may represent the communication modem / circuit / chip.

[0076] The wireless communication technology implemented in the wireless devices 100 and 200 of the present disclosure may include narrowband Internet of things for low-power communication as well as LTE, NR, and 6G. For example, the NB-IoT technology may be an example of low-power wide-area network (LPWAN) technologies and implemented in standards such as LTE Cat NB1 and / or LTE Cat NB2. However, the NB-IoT technology is not limited to the above names. Additionally or alternatively, the wireless communication technology implemented in the wireless devices XXX and YYY of the present disclosure may perform communication based on the LTE-M technology. For example, the LTE-M technology may be an example of LPWAN technologies and called by various names including enhanced machine type communication (eMTC). For example, the LTE-M technology may be implemented in at least one of the following various standards: 1) LTE CAT 0, 2) LTE Cat M1, 3) LTE Cat M2, 4) LTE non-Bandwidth Limited (non-BL), 5) LTE-MTC, 6) LTE Machine Type Communication, and / or 7) LTE M, etc., but the LTE-M technology is not limited to the above names. Additionally or alternatively, the wireless communication technology implemented in the wireless devices XXX and YYY of the present disclosure may include at least one of ZigBee, Bluetooth, and LPWAN in consideration of low-power communication, but the wireless communication technology is not limited to the above names. For example, the ZigBee technology may create a personal area network (PAN) related to small / low-power digital communication based on various standards such as IEEE 802.15.4 and so on, and the ZigBee technology may be called by various names.

[0077] Hereinafter, hardware elements of the wireless devices 100 and 200 will be described more specifically. One or more protocol layers may be implemented by, without being limited to, one or more processors 102 and 202. For example, the one or more processors 102 and 202 may implement one or more layers (e.g., functional layers such as a physical (PHY) layer, medium access control (MAC) layer, a radio link control (RLC) layer, a packet data convergence protocol (PDCP) layer, radio resource control (RRC) layer, and a service data adaptation protocol (SDAP) layer). The one or more processors 102 and 202 may generate one or more protocol data units (PDUs) and / or one or more service data units (SDUs) according to the functions, procedures, proposals, and / or methods disclosed in the present disclosure. The one or more processors 102 and 202 may generate messages, control information, data, or information according to the functions, procedures, proposals, and / or methods disclosed in the present disclosure. The one or more processors 102 and 202 may generate signals (e.g., baseband signals) including PDUs, SDUs, messages, control information, data, or information according to the functions, procedures, proposals, and / or methods disclosed in the present disclosure and provide the generated signals to the one or more transceivers 106 and 206. The one or more processors 102 and 202 may receive the signals (e.g., baseband signals) from the one or more transceivers 106 and 206 and acquire the PDUs, SDUs, messages, control information, data, or information according to the functions, procedures, proposals, and / or methods disclosed in the present disclosure.

[0078] The one or more processors 102 and 202 may be referred to as controllers, microcontrollers, microprocessors, or microcomputers. The one or more processors 102 and 202 may be implemented by hardware, firmware, software, or a combination thereof. As an example, one or more application specific integrated circuits (ASICs), one or more digital signal processors (DSPs), one or more digital signal processing devices (DSPDs), one or more programmable logic devices (PLDs), or one or more field programmable gate arrays (FPGAs) may be included in the one or more processors 102 and 202. The functions, procedures, proposals, and / or methods disclosed in the present disclosure may be implemented using firmware or software, and the firmware or software may be configured to include the modules, procedures, or functions. Firmware or software configured to perform the functions, procedures, proposals, and / or methods disclosed in the present disclosure may be included in the one or more processors 102 and 202 or stored in the one or more memories 104 and 204 so as to be driven by the one or more processors 102 and 202. The functions, procedures, proposals, and / or methods disclosed in the present disclosure may be implemented using firmware or software in the form of code, commands, and / or a set of commands.

[0079] The one or more memories 104 and 204 may be connected to the one or more processors 102 and 202 and store various types of data, signals, messages, information, programs, code, commands, and / or instructions. The one or more memories 104 and 204 may be configured by read-only memories (ROMs), random access memories (RAMs), electrically erasable programmable read-only memories (EPROMs), flash memories, hard drives, registers, cash memories, computer-readable storage media, and / or combinations thereof. The one or more memories 104 and 204 may be located at the interior and / or exterior of the one or more processors 102 and 202. The one or more memories 104 and 204 may be connected to the one or more processors 102 and 202 through various technologies such as wired or wireless connection.

[0080] The one or more transceivers 106 and 206 may transmit user data, control information, and / or radio signals / channels, mentioned in the methods and / or operational flowcharts of the present disclosure, to one or more other devices. The one or more transceivers 106 and 206 may receive user data, control information, and / or radio signals / channels, mentioned in the functions, procedures, proposals, methods, and / or operational flowcharts disclosed in the present disclosure, from one or more other devices. For example, the one or more transceivers 106 and 206 may be connected to the one or more processors 102 and 202 and transmit and receive radio signals. For example, the one or more processors 102 and 202 may perform control so that the one or more transceivers 106 and 206 may transmit user data, control information, or radio signals to one or more other devices. The one or more processors 102 and 202 may perform control so that the one or more transceivers 106 and 206 may receive user data, control information, or radio signals from one or more other devices. The one or more transceivers 106 and 206 may be connected to the one or more antennas 108 and 208. The one or more transceivers 106 and 206 may be configured to transmit and receive user data, control information, and / or radio signals / channels, mentioned in the functions, procedures, proposals, methods, and / or operational flowcharts disclosed in the present disclosure, through the one or more antennas 108 and 208. In the present disclosure, the one or more antennas may be a plurality of physical antennas or a plurality of logical antennas (e.g., antenna ports). The one or more transceivers 106 and 206 may convert received radio signals / channels etc. from RF band signals into baseband signals in order to process received user data, control information, radio signals / channels, etc. using the one or more processors 102 and 202. The one or more transceivers 106 and 206 may convert the user data, control information, radio signals / channels, etc. processed using the one or more processors 102 and 202 from the base band signals into the RF band signals. To this end, the one or more transceivers 106 and 206 may include (analog) oscillators and / or filters.

[0081] In the present disclosure, the at least one memory (e.g., 104 or 204) may store instructions or programs, and the instructions or programs may cause, when executed, at least one processor operably connected to the at least one memory to perform operations according to some embodiments or implementations of the present disclosure.

[0082] In the present disclosure, a computer readable (non-transitory) storage medium may store at least one instruction or program, and the at least one instruction or program may cause, when executed by at least one processor, the at least one processor to perform operations according to some embodiments or implementations of the present disclosure.

[0083] In the present disclosure, a processing device or apparatus may include at least one processor, and at least one computer memory operably connected to the at least one processor. The at least one computer memory may store instructions or programs, and the instructions or programs may cause, when executed, the at least one processor operably connected to the at least one memory to perform operations according to some embodiments or implementations of the present disclosure.

[0084] In the present disclosure, a computer program may include program code stored on at least one computer-readable (non-transitory) storage medium and, when executed, configured to perform operations according to some implementations of the present disclosure or cause at least one processor to perform the operations according to some implementations of the present disclosure. The computer program may be provided in the form of a computer program product. The computer program product may include at least one computer-readable (non-transitory) storage medium.

[0085] A communication device of the present disclosure includes at least one processor; and at least one computer memory operably connected to the at least one processor and configured to store instructions for causing, when executed, the at least one processor to perform operations according to example(s) of the present disclosure described later.

[0086] FIG. 3 illustrates a process for processing a transport block (TB) on a transmitting side.

[0087] In order for a receiver to correct errors that radio signals experience in a radio channel, a transmitter encodes information using a forward error correction code and then transmits the encoded information. The receiver demodulates a received signal and decodes the error correction code to thereby recover the information transmitted by the transmitter. In this decoding procedure, errors in the received signal caused by a radio channel are corrected.

[0088] Data arrives at a coding block in the form of a maximum of two transport blocks every transmission time interval (TTI) in each DL / UL cell. The following coding steps may be applied to each transport block of the DL / UL cell:

[0089] - cyclic redundancy check (CRC) attachment to a transport block;

[0090] - code block segmentation and CRC attachment to a code block;

[0091] - channel coding;

[0092] - rate matching; and

[0093] - code block concatenation.

[0094] In an actual communication system, a transport block of a predetermined size or larger is divided into a plurality of smaller data blocks and then is encoded, to facilitate actual implementation of coding. The smaller data blocks are called code blocks. While the code blocks are generally of the same size, one of the code blocks may have a different size due to a limited size of an internal interleaver of a channel encoder. Error correction coding is performed on each code block of a predetermined interleaver size and then interleaving is performed to reduce the impact of burst errors that are generated during transmission over a radio channel. The error-corrected and interleaved code block is transmitted by being mapped to an actual radio resource. The amount of radio resources used for actual transmission is designated. Thus, the encoded code blocks are rate-matched to the amount of the radio resources. In general, rate matching is performed through puncturing or repetition. For example, if the amount of radio resources, i.e., the number of transmission bits capable of being transmitted on the radio resources, is M and if a coded bit sequence, i.e., the number of output bits of the encoder, is N, in which M is different from N, then rate matching is performed to match the length of the coded bit sequence to M. If M>N, then all or a part of bits of the coded bit sequence are repeated to match the length of the rate-matched sequence to M. If M<N, then a part of the bits of the coded bit sequence is punctured to match the length of the rate-matched sequence to M and the punctured bits are excluded from transmission.

[0095] In wireless communication systems, the transmitting side encodes data to be transmitted based on channel coding with a specific code rate. Then, the transmitting side adjusts the code rate of the data to be transmitted through a rate matching process involving puncturing and repetition.

[0096] A decoding procedure may be performed in a reverse order of the encoding procedure of FIG. 3. For example, a receiver may receive a sequence corresponding to one or more coded code blocks for a TB, dissociate the sequenced into coded code block(s), perform channel decoding for the coded code block to obtain CB CRC attached code block(s), remove CB CRC from each of the CB CRC attached code block(s) to obtain code block(s), and perform CRC checking for each code block using a corresponding CB CRC. If all CB(s) related to the TB is successfully decoded, then the receiver may determine a final TB from the CB(s), and perform CRC checking for the final TB using a corresponding TB CRC.

[0097] FIG. 4 is a diagram illustrating an example of TB encoding procedure.

[0098] FIG. 4 illustrates an encoding procedure of a TB corresponding to the above-described encoding procedure in relation to FIG. 3. First, a TB CRC is added to the TB. The TB CRC may be used to confirm the TB during a decoding procedure. If the TB CRC attached TB is not larger than a predetermined size, the TB CRC attached TB is encoded by a (channel) encoder. If the TB CRC attached TB is larger than the predetermined size, the TB CRC attached TB is segmented into multiple CBs. If the TB CRC attached TB is segmented into multiple CBs, CB CRCs are added to the respective CBs. The CB CRCs may be used to confirm the CBs by the receiver. Each of the multiple CB CRC attached CBs may be encoded through a (channel) encoder. In some implementations, the multiple CB CRC attached CBs may be encoded in parallel though respective (channel) encoders. In some implementations, the multiple CB CRC attached CBs may be encoded one by one through one (channel) encoder.

[0099] Hybrid Automatic Repeat Request (HARQ) is a technique that combines forward error correction (FEC) and automatic repeat request (ARQ). In other words, a transmitter transmits all or some of the coded bits encoded based on FEC, and a receiver detects errors in the received data and transmits a HARQ-ACK signal to the transmitter, which includes an acknowledgment (ACK) or a negative acknowledgment (NACK). If there are no errors in the received data, the transmitter transmits new data. However, if there are errors in the received data, the transmitter retransmits the corresponding data block. The receiver combines the retransmitted data block with the previously received data block and performs decoding to detect errors. This process may continue until errors are no longer detected or until a predetermined number of attempts is reached.

[0100] FIG. 5 is a diagram to explain a rate matching process according to some implementations of the present disclosure.

[0101] In the case of HARQ operation, the receiver generates an ACK or NACK for a received or scheduled packet and provides the ACK or NACK to the transmitter. If the transmitter receives the NACK for transmission, the transmitter may retransmit the required packet. The bits read from a circular buffer and transmitted whenever retransmission is performed may vary depending on the position of a redundancy version (RV). Referring to FIG. 5, there are multiple (e.g., 4) RVs that define the starting point of the bits read from the circular buffer.

[0102] The circular buffer is a crucial component for rate matching, which allows for puncturing and / or repetition of coded bits. Referring to FIG. 5, coded bits or output bits after sub-block interleaving of the coded bits are sequentially written into the circular buffer for the mother code. The coded bits are read in order from a specific starting point within the circular buffer, which is determined by the RV points in the circular buffer.

[0103] Forward error correction (FEC) codes are frequently used in communication systems to increase the system's resilience to a wide variety of impairments in the communication channel. In many modern communication systems, low-density parity-check (LDPC) codes are considered for FEC since they provide efficient encoding and decoding of data with low computational complexity. For example, in 5G NR, LDPC codes are used for data channel due to their good performance. However, future 6G communication is expected to support higher data rates for many new applications. New coding techniques for 6G communication need to support high throughput and low hardware complexity. In the data channel, the current 5G NR LDPC codes is not sufficient for data hungry applications, such as extended reality, 8K and higher streaming of videos. In the following description, LDPC codes, which may support high-speed data transfer and high-throughput applications, according to some implementations are described.

[0104] <1.1. LDPC Codes Overview>

[0105] LDPC codes are graph-based codes, which means that these codes can be represented by a bipartite graph, also known as a Tanner graph.

[0106] FIG. 6 is an example of a parity check matrixHof an LDPC code and the corresponding Tanner graph.

[0107] A Tanner graph consists of i) variable nodes (VNs) representing coded bits, ii) check nodes (CNs) representing parity check equations that the coded bits must satisfy, and iii) edges that connect VNs and CNs. Each edge in the Tanner graph corresponds to a non-zero entry (1 for binary LDPC codes) in the matrixH. In Tanner graphs, VNs are shown as circles, check nodes are shown as squares. The number of CNs and the number of VNs in the Tanner graph of an LDPC code represent M rows and N columns in the matrixH, respectively. A size M×N parity check matrixHmay also be used to represent these codes. A parity check matrixHis a binary matrix that defines the parity check equations of an LDPC code. Each column and row in the matrixHcorrespond to a VN and a CN, respectively. Entry Hijin the matrixHis 1 if variable node j participates in the parity check equation of check node i, and 0 otherwise. In other words, if entry Hijin the matrixHis equal to 1, then check node i is connected to variable node j by an edge in the Tanner graph; otherwise, there is no edge connecting these nodes. Properties of the matrixH, such as row and column weights, translate to node degrees in the Tanner graph. The sparsely distributed non-zero entries in the matrixHrepresent the edges in the graph. The sparsity of non-zero entries allows for efficient decoding of these codes using an iterative decoding algorithm known as the belief propagation (BP) algorithm.

[0108] LDPC codes are a class of linear block codes with capacity-achieving performance. These codes are decoded with a low-complexity iterative decoding algorithm known as the belief propagation (BP) decoder. A binary LDPC code is given by the null space of an M×N parity check matrixHover the Galois field GF(2). As the name suggests, the non-zero entries in LDPC codes have a low density (i.e., the non-zero entries are sparsely placed inH).

[0109] Referring to FIG. 6, the VNs represent N columns inH, and M parity check constraints are associated with the CNs in the graph. The construction of parity check matrixHof the LDPC codes is mainly divided into two classes, namely regular and irregular LDPC codes. The parity check matrix of an LDPC code is called (dv,dc)regularif each VN is connected todvfixed number of CNs and each CN is connected todcfixed number of VNs or code bits (also referred to as coded bits). For the parity check matrix shown in FIG. 6,dv=2 anddc=3. For an irregular LDPC code, the fraction of columns having weightiis specified by λiand the fraction of rows having weightiby ρi. The pair (λ, ρ) is called the degree distribution of the irregular LDPC codes, where λ = [λ1λ2λ3… ] and ρ = [ρ1ρ2ρ3… ].

[0110] <1.1.1. Code Rate of LDPC Codes>

[0111] Recall that for regular LDPC codes, the number of 1s in an M×N parity check matrixHis given by N*dv= M*dc. Similarly, for irregular LDPC codes, the number of 1s in the parity check matrix is given by the following equation.

[0112]

[0113] For a linear block code, the code rate may be determined by the following equation.

[0114]

[0115] IfHis a full rank matrix, then rank(H)=M. Now, for regular LDPC codes, the code rate may be given by the following equation.

[0116]

[0117] Similarly, for the irregular LDPC codes, the code rate is given by the following equation.

[0118]

[0119] <1.1.2. Encoding of LDPC Codes>

[0120] FIG. 7 is an example of a systematic codeword generated by encoding.

[0121] The parity-check matrix (PCM) of an LDPC code specify the set of all valid codewords. For LDPC codes, the valid codewords always satisfy the parity check constraints defined byxHT=0. The process of mapping the message bits into a valid codeword is called encoding. A codeword consist of message bitsu= [u1, u2, u3, ..., uK] and parity bitsp=[p1, p2, p3, ..., pN-K] mapped together by satisfying the constraints imposed by the PCM.

[0122] Since LDPC codes are linear block codes, encoding of the messageu=[u1, u2, u3,..., uK] to a codewordx= [x0, x1x2, ..., xn-1] can be expressed as a product ofuandGmatrices as follows:x=u·G, whereGis the generator matrix of dimension K×N. The generator matrix can be designed in systematic or non-systematic form, thus producing codewords withuandpsegmented and linked together in a concatenated fashion or message bits mapped at random locations of the codeword vector, respectively.

[0123] For systematic LDPC codes, the matrixGconsist of a K×K identity matrixIKand a (N-K )×K binary matrixA. With the generator matrix in the formG= [IKA], the first K codeword bits consist of message bits u1, u2, u3, ..., uK(which means that the ithmessage bit is mapped to the ithcodeword bit) and corresponding N-K codeword bits consist of parity bits p1, p2, p3, ..., pN-K(which are linear sums of the message bits). The generated codewordxmay be of a form shown by FIG. 7.

[0124] For a generator matrix in non-systematic form, the non-systematic form may be converted into systematic form by performing elementary operations on the rows and permuting the columns of the generator matrix in non-systematic form. Since columns are permuted, the codeword bits in the updated systematic generator matrix will follow a fixed permutation to revert the ordering of the bits to that of the non-systematic form. By applying elementary operations on row, the codeword set of an LDPC code does not change since the solution set of the system of linear equations in PCM does not change (see the document "T. J. Richardson and R. L. Urbanke, "Efficient encoding of low-density parity-check codes," in IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 638-656, Feb 2001.").

[0125] FIG. 8 shows an example of converting an LDPC code of non-systematic form into a systematic form.

[0126] FIG. 8(a) shows an example of converting an LDPC code represented by a parity check matrixH' in non-systematic form. One may change the parity check matrixH' by applying elementary operations on rows ofH' into a parity check matrixHrein row echelon form as shown in FIG. 8(b). By the same process (e.g., applying elementary operations on rows and / or permuting columns), the parity check matrixHrein row echelon form is converted into a parity check matrixHrrein reduce row echelon form as shown in FIG. 8(c). A parity check matrix corresponding to a systematic generator matrix may be obtained in a form given byH= [ATIK] as shown in FIG. 8(d) by applying column permutation onHrre. The parity-check matrixH= [ATIK] may be converted into a systematic generator matrixG= [IKAT] as shown in FIG. 8(e).

[0127] It may be observed that if matrix multiplication (mod 2) is applied toGandHT, the resultant matrix will be a null matrix. The matrixGis provided to the encoder which will then encodeuintoxthrough matrix multiplication given byx=u·G.

[0128] Another way of encoding LDPC codes is by directly usingHrather than finding and usingG. The advantage from this approach is linear-time encoding complexity that may be achieved by transformingHinto approximate lower triangular form (see the document "T. J. Richardson and R. L. Urbanke, "Efficient encoding of low-density parity-check codes," in IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 638-656, Feb 2001.").

[0129] FIGS. 9 and 10 are illustrated to explain a parity check matrixHof an LDPC code through a bipartite graph.

[0130] '1' in a row of the parity check matrix illustrated in FIG. 9(a) represents an edge connecting a check node to a particular variable node in the bipartite graph and '1' in a column of the parity check matrix represents an edge connecting a variable node to a particular check node. FIG. 9(b) illustrates a part of the bipartite graph corresponding to the parity check matrix illustrated in FIG. 9(a). Referring to FIG. 9(b), in the bipartite graph, the left nodes represent variable nodes and the right nodes represent check nodes.

[0131] FIG. 10 illustrates a parity check matrixHand corresponding bipartite lines.

[0132] Referring to FIG. 10, since the product of a parity check matrixHand a codewordc' should be '0', the mod-2 sum of values of a hard decision result from the variable nodes to the check nodes should be '0'. In FIG. 10(b), equations for hard decision for respective check nodes for a parity check matrixHshown in FIG. 10(a) are given. In a check node, checking whether the sum of bits from variable node(s) to the check node is '0' is referred to as a syndrome check.

[0133] <1.1.3. Decoding Algorithms of LDPC Codes>

[0134] FIG. 11 shows an example of graphical representation of the concatenation of single parity check codes and repetition codes in an LDPC code.

[0135] Due to the low density of 1s in the parity check matrix of an LDPC code, the iterative decoding algorithms show remarkable performance in a wide class of channels. The decoding algorithms used to iteratively decode LDPC codes are classified collectively into message-passing algorithms. The messages pass back and forward between the VNs and CNs in an iterative fashion through the connected edges. In general, the LDPC codes consist of a concatenation of two types of constituent codes (VNs as repetition codes and CNs as single parity check codes) connected through the edges in the Tanner graph. The message-passing decoder works in a distributed manner by passing the results of low-complexity local decoding at each individual node into the Tanner graph.

[0136] When Gallagar first invented LDPC codes in 1962, he introduced the sum-product algorithm (SPA) for decoding these codes. It is a general algorithm that provides suboptimal (or near-optimal) performance in a variety of channels. As discussed earlier, an LDPC code consists of the generalized concatenation of many repetition and single-parity check codes. A message-passing decoder for an LDPC code employs an individual decoder for each single parity check code, and these decoders operate cooperatively in a distributed fashion to determine the correct code bit values. A detailed description of the sum-product algorithm for decoding LDPC codes is given as follows.

[0137] >Step 1. Initialization:Initialize the messages sent from VNs to CNs and vice versa. These messages represent the likelihood of each codeword bit being 0 or 1. For all j, initialize Ljto received LLR from the channel. Then, for all i, j for which hij= 1, set Lj→i= Lj.

[0138] > Step 2. Message Passing (Iteration):

[0139] >>Check to Variable Messages:Each CN computes messages to be sent to connected VNs based on received information from neighboring VNs. Compute outgoing CN messages Li→jfor each CN using .

[0140] >>Variable to Check Messages:Each VN computes messages to be sent to connected CNs based on received information from neighboring CNs. Compute outgoing VN messages Lj→ifor each VN using .

[0141] >>Update:Update the messages at each node based on the received messages and compute the total LLR at each VN as follows: .

[0142] >Step 3. Check for Convergence:Check whether the decoding process has converged. Convergence can be determined based on predefined criteria such as the number of iterations or the change in the likelihood of the decoded codeword. For all VNs, set . If or the number of iterations equals the maximum limit, stop; else, go to Step 2.

[0143] >Step 4. Decoding:After convergence, estimate the transmitted codeword based on the final messages exchanged between VNs and CNs.

[0144] <1.2. Protograph-based Spatially Coupled LDPC Codes>

[0145] FIG. 12 illustrates an example of edge spreading technique for an LDPC protograph. In particular, FIG. 12 illustrates an example of edge spreading of a (3, 6) LDPC protograph.

[0146] Spatially coupled (SC) LDPC codes are constructed by coupling together a series of L disjoint, or uncoupled, LDPC code Tanner graphs into a single coupled chain. A (dv, dc, L) SC LDPC codes can be derived from spatial coupling of (dv, dc) block LDPC protographs. A technique called 'edge spreading' is used to couple L replicas of a block LDPC protograph (see the document "D. G. M. Mitchell, M. Lentmaier and D. J. Costello, "Spatially Coupled LDPC Codes Constructed from Protographs," in IEEE Transactions on Information Theory, vol. 61, no. 9, pp. 4866-4889, Sept. 2015.").

[0147] FIG. 13 illustrates an example of constructing an SC LDPC code by edge spreading. In particular, FIG. 13 illustrates an example of constructing a (dv, dc, L) = (3, 6, 4) SC LDPC code by applying edge spreading to a (dv, dc) = (3, 6) block LDPC code with a coupling width w = 2.

[0148] An SC LDPC protograph is constructed by first placing L block LDPC protographs at each time-index t. Then, coupling is performed for the L block LDPC protographs by spreading the edges emanating from VNs at t. The resulting base matrix of an SC-LDPC codes has a convolutional structure, i.e., the non-zero entries form a band diagonal stair-like structure. A (3, 6) block LDPC protograph, as shown in FIG. 13(a), is replicatedL= 4 times. This may be considered as transmission ofLcode blocks over time. In some implementations of the present disclosure, this may be considered as encodingLcode blocks over time. The three edges emanating from each variable node of a (3, 6) block LDPC protograph at time t are spread such that each edge connects to the variable nodes of the (3, 6) block LDPC protograph at time t to check nodes of (3, 6) block LDPC protographs at times t, t+1, ..., t+w, where w = 2, as shown in FIG. 13(b).

[0149] FIGS. 14 and 15 illustrate examples of a base matrix expressed by component base matrices. In FIG. 14, the blank parts in the matrixB[0, L-1]are comprised of elements, each representing a Z-by-Z zero matrix, where Z is a lifting size. In FIG. 15,0in the matrixB[0, 3]denotes a zero matrix.

[0150] A protograph may be represented by a bi-adjacency matrixB, known as a base matrix. The edge spreading decomposes the base matrixBinto component base matricesBj, j = 0, 1, ..., w, such that ,where w > 0 is the coupling width of the SC LDPC protograph, and eachBjcontains non-negative integer entries. For example, an nc×nv= ((L+w)bc)×(Lbv) base matrixB[0, L-1]corresponding to an SC LDPC protograph with coupling length 'L' and coupling width 'w' is expressed by bc×bvcomponent base matricesBj, j = 0, 1, ..., w, as shown in FIG. 14, where bv= dc / gcd(dv,dc) and bc= dv / gcd(dv,dc). bv= dc / gcd(dv,dc) and bc= dv / gcd(dv,dc), where gcd denotes Greatest Common Divisor. For example, for a (3, 6, L) LDPC code, bv=6 / 3=2 and bc=3 / 3=1, and thus each component base matrices are of order 1×2. The component base matricesBj, j = 0, 1, ..., w, represent edge connections from the bvvariable nodes at time t to the bccheck nodes at time t+ j.

[0151] The base matrix for the (3, 6) block LDPC protograph shown in FIG. 14(a) isB=

[0033] . After application of edge spreading, the base matrixBdecomposes intoB0=B1=B2=

[0011] . The base matrix of an (3, 6, 4) SC LDPC protograph shown in FIG. 13(b) is shown in FIG. 15.

[0152] <1.2.1. Construction of Finite Length Spatially Coupled LDPC Codes>

[0153] FIG. 16 illustrates an example of copy-and-permute procedure applied to an SC LDPC protograph with (dv, dc, L) = (3, 6, 4).

[0154] Similar to the code construction of block LDPC codes from protograph, the copy-and-permute procedure to lift the base matrixB[0, L-1]of SC LDPC codes is used to construct a finite length code.

[0155] In the copy-and-permute procedure, protograph is first copied Z times. Copying a protograph Z times is also referred to as lifting a base graph of the protograph, where Z is a lifting factor. Z is also referred to as a lifting size. The copied nodes and edges are then grouped together to form bundles of distinct edges, VNs and CNs as shown in FIG. 16. To obtain a large LDPC Tanner graph from a simple protograph, the edges within a bundle are permuted among the Z replicas. The permutation can be random or quasi cyclic (QC), however, the LDPC Tanner graph will preserve the structure of the original protograph (see the document "D. G. M. Mitchell, M. Lentmaier and D. J. Costello, "Spatially Coupled LDPC Codes Constructed from Protographs," in IEEE Transactions on Information Theory, vol. 61, no. 9, pp. 4866-4889, Sept. 2015.").

[0156] FIG. 17 illustrates an example of a parity check matrixHof an SC LDPC code. In FIG. 17, the blank parts in the parity check matrixH[0, L-1]are comprised of zeros.

[0157] In terms of lifting the base matrix, the copy-and-permute procedure is equivalent to replacing the entries of base matrixBi,j= 0 by the all-zero Z×Z matrices andBi,j= a by the summation of a Z×Z permutation matrices. In FIG. 17, a PCMHof a protograph-based SC LDPC code may be illustrated. In FIG. 17, each submatrixHi(t), i =0,1,...,w, may be given by the following equation :Hi(t) = [Q0,i(t) …Qk,i(t)], where,Qk,i(t) is a Z×Z binary matrix and k = (dc / dv) - 1 and t = 0,1,...,L-1. A binary matrix, also known as a logical matrix, Boolean matrix, relation matrix, or-matrix, or (0, 1)-matrix, is a matrix with entries that are either 0 or 1. In some implementations of the present invention, L may be the same as the number of code blocks obtained from a transport block.

[0158] <1.2.2. Encoding of Spatially Coupled LDPC Codes>

[0159] FIG. 18 illustrates an example of encoding procedures for LDPC codes. Difference between the block LDPC encoding and spatially coupled LDPC encoding are shown in FIG. 18. In particular, FIG. 18(a) illustrates an example of block wise encoding of LDPC codes, while FIG. 18(b) illustrates an example of convolutional encoding SC LDPC codes.

[0160] Memory is introduced in the code design from coupling the block LDPC codes, and the depth of coupling is defined as coupling width 'w'. Instead of transmitting multiple codewords, each encoded independently by a block LDPC code as shown in FIG. 18(a), the encoder of the SC LDPC code produces sub-codewords at differenttthat are coupled withwneighboring sub-codewords. In some implementations of the present disclosure, it may be understood as the encoder of the SC LDPC code producesLsub-codewords for code blocks 0 toL-1 for a transport block, where each sub-codeword is coupled withwneighboring sub-codewords.

[0161] The information and encoded sequences are recorded asu[0, L-1]=[u0,u1,u2,...,uL-1] andv[0, L-1]=[v0,v1,v2,...,vL-1], respectively, whereutis an information sequence input to an encoder at time index t. In some implementations of the present disclosure, an information sequence (also referred to as an information block) input to an encoder at time index t may be equivalent to a code block t among code blocks 0 to L-1 from a transport block. In some implementations of the present disclosure, an information sequence input to the encoder may be obtained by attaching a CB CRC to a corresponding code block (and, if necessary, adding filler bits to the CB CRC attached code block such that the block input to the encoder has the same size as a (predetermined or predefined) input size for the encoder).

[0162] For a systematic SC LDPC code, the encoded sequencevtat time index t may be divided into two parts, i.e.,vt= [vt0,vt1], 0 ≤ t ≤ L-1. First part ofvtcontains the information bitsvt0=ut, whereas the other part contains the parity bitsvt1=pt. Therefore,vt= [ut,pt] is the convolutional encoded sequence at each time index t. An essential feature of SC LDPC codes is that the (information) blocks at different time instants are interconnected. Instead of encoding all codewords independently, the blocks are coupled by the encoder to blocks at other time instants as shown in FIG. 18(b). For the coded sequence by SC LDPC code with L→∞ thenv[0,∞]satisfies the following equation:v[0,∞]HT[0,∞]=0.

[0163] For SC LDPC code with finite coupling lengthL, the encoding procedure may break into two parts:

[0164] > 1. Sequential encoding, and

[0165] > 2. Termination step.

[0166] Due to the convolutional structure of SC LDPC codes, sequential encoding of each code block inv[0, t]follow the procedure given below:

[0167] > For 0 ≤t≤L-1, the output of the encoder with encoded sequencev[0, t]=[v0,v1,v2,...,vt] will satisfy:

[0168] v[0, t]HT[0, t]= [0[0, t]zt+1]

[0169] , wherezt+1= [z0t+1,z1t+1,...,zw-1t+1] are partial syndromes for the nextw-1 code blocks that are coupled with the code block at time indext(see the document "A. E. Pusane, A. J. Feltstrom, A. Sridharan, M. Lentmaier, K. S. Zigangirov and D. J. Costello, "Implementation aspects of LDPC convolutional codes," in IEEE Transactions on Communications, vol. 56, no. 7, pp. 1060-1069, July 2008").

[0170] > To encode the next code block using the currently calculated partial syndrome, the encoded sequencevtat time index t may be expressed as follows:vt=ut[Q0,0(t)Q1,0(t) ...Qk-1,0(t)]T+zt0, where k = (dc / dv) - 1.

[0171] <1.2.2. Windowed Decoding of Spatially Coupled LDPC Codes>

[0172] The excellent error correction performance of the SC LDPC codes is associated with the wave-like decoding convergence of the error rate during the belief propagation (BP) decoding. The variable nodes (VNs) at the terminated sides which are at the start and end of the SC LDPC chain get decoded first, and this triggers the decoding of the consecutive neighboring VNs. However, the full-block BP decoding of long SC LDPC codes requires a large number of decoding iterations and high complexity, which does not make it suitable for applications with low latency and complexity requirements. A windowed decoding (WD) approach may be considered to ease the latency and complexity burden on the decoding of long SC LDPC chains (see the document "A. R. Iyengar, M. Papaleo, P. H. Siegel, J. K. Wolf, A. Vanelli-Corolli, and G. E. Corazza, "Windowed decoding of protograph-based LDPC convolutional codes over erasure channels," in IEEE Trans. Inf. Theory, vol. 58, no. 4, pp. 2303-2320, Apr. 2012."). The decoding is constrained inside a window of size W and sub-code blocks are decoded recursively by sliding the window down in the SC LDPC chain.

[0173] FIG. 19 illustrates an example of windowed decoding. In particular, FIG. 19 depicts window decoding (WD) of target nodes with window size W = 3 and at t-th spatial position, whereytdenotes a received codeword obtained from a channel for an information blockutat time index t.

[0174] The BP decoding steps are iteratively run inside the window until the target nodes are decoded. In FIG. 19, only the VNs at the time indextare considered as target nodes (the first sub-code block associated with the target nodes is called target sub-code block ), where a target sub-code block may denote a codeword obtained from one code block (which is obtained from a transport block. However, more sub-code blocks can be considered as target sub-code blocks in order to trade-off the error rate performance for reduced latency. Meanwhile, the smallest possible window size Wminfor a given number Tcwof target sub-code blocks is given by Wmin= (w+ Tcw), wherewis a coupling width. All the literature on WD of SC-LDPC codes consider only single sub-code block as target sub-code block. By increasing the number of target sub-code blocks, the performance decreases drastically due to increase in the severity of the error propagation.

[0175] FIG. 20 illustrates an example of windowed decoding over a base matrix of a (dv, dc, L) SC-LDPC code, where (dv, dc) = (3, 6). In particular, FIG. 20 shows the base matrix view of the windowed decoding for the same (3, 6,L) SC LDPC code as that shown in FIG. 19.

[0176] FIGS. 21 to 24 illustrate an example of sliding steps of windowed decoding for target sub-code block. In each of FIGS. 21 to 24, each sub-matrix in the PCMHis 1024-by-512 zero matrix consisting of all zeros. The order of each non-zero sub-matrix in the PCMHis mg×ng, where mg= bcZ and ng= bvZ, where Z is a lifting size.

[0177] The step-by-step sliding of the windowed decoder over a PCM constructed from a (3, 6, 16) SC LDPC base matrix is shown in FIGS. 21 to 24. The windowed decoding starts with the decoding of the upper leftmost sub-code block inside the window (called the target symbols and are represented by the area filled with vertical hatched lines in FIGS. 22 to 24). The windowed decoder then slides down and right to decode the consecutive sub-code blocks.

[0178] All the literature on WD of SC-LDPC codes consider only single sub-code block as target sub-code block. By increasing the number of target sub-code blocks, the performance decreases drastically due to increase in the severity of the error propagation. In latency-constrained applications such as data streaming and real-time communication, it is desirable to have a small W to maintain low latency and complexity at the decoder. However, severe error propagation across the SC LDPC chain may occur due to small W. For SC LDPC codes with a largeL, it is more likely that the error propagation may commence at any WD position at the time indext. One way to limit the error propagation is by taking a smallerL; however, this would have a significant penalty on the code rate of the SC LDPC code.

[0179] <1.3. Partial Spatially Coupled LDPC Codes>

[0180] Partial spatially coupled LDPC (PSC LDPC) codes are generalization of SC LDPC codes in the lifting dimension of the code design, introducing partial coupling through connectivity between block and coupled lifted protographs. PSC LDPC codes were recently proposed in the document "I. Ali and J. Ha, "Partial Spatial Coupling of LDPC Codes: Reducing the Gap to Capacity by Improving the Rate," in IEEE Transactions on Communications, vol. 71, no. 12, pp. 6898-6913, Dec. 2023" and it is shown that these codes provide many good attributes compared to the conventional SC LDPC codes. Partial spatial coupling helps in mitigating the rate loss associated with the SC LDPC codes, which aids in reducing the gap between the error rate performance of these codes and the Shannon capacity. In the document "I. Ali and J. Ha, "Partial Spatial Coupling of LDPC Codes: Reducing the Gap to Capacity by Improving the Rate," in IEEE Transactions on Communications, vol. 71, no. 12, pp. 6898-6913, Dec. 2023", it is shown that the PSC LDPC codes with a small coupling length 'L' have better error rate performance than the 5G NR LDPC codes. The PSC LDPC codes combine the structural properties of the block and SC LDPC codes to attain excellent coding gains, which is otherwise lacking in the standalone structures of the block and SC LDPC codes. 6G needs to encompass high-speed data transfer and also incorporate high-throughput applications such as fronthaul and backhaul transmission. PSC LDPC codes provide capacity-achieving performance with a simple BP decoding algorithm. Hence, these codes are suitable for many high performance applications in 6G.

[0181] PSC LDPC codes are constructed by following a multi-edge type (MET) connectivity between neighboring sub-code blocks. During the lifting procedure, the copies are divided into fraction β uncoupled sequence of block LDPC protographs andα= 1-β coupled protographs.

[0182] <1.3.1 Code Construction of PSC-LDPC Codes>

[0183] FIG. 25 illustrates an example of construction procedure of a (dv, dc, L, β) partial spatially coupled (PSC) LDPC code. In particular, FIG. 25 illustrates a visualized example of construction procedure of a (dv, dc, L, β) = (3, 6, 4, β) PSC LDPC code. In FIG. 25, edges in the same type of lines forms an edge bundle of same type. For example, the edges expressed in the single solid lines belong to one edge bundle, and the edges in the single dotted lines belong to another edge bundle. For a given time index t or for a given code block, the number of edges in an edge bundle of same type is equal to the number of edges β×Z copies of uncoupled sequence of block LDPC protographs (see the upper part of FIG. 25) plus the number of edges α×Z copies of coupled protographs (see the lower part of FIG. 25).

[0184] A code constructed from a protograph-based (dv, dc, L, β) PSC LDPC ensemble follows a MET framework at the lifting and edge permutation stage. During the lifting procedure, the protographs (that includes i) a sequence of L blocks of (dv, dc) LDPC protographs and ii) a (dv, dc, L) Spatially Coupled LDPC protograph) are segmented into β×Z copies of uncoupled sequence of block LDPC protographs and α×Z copies of coupled protographs. Referring to FIG. 25 that illustrates the code construction process, edges of same edge-type are uniquely expressed by a same type of lines to apply permutation in that edge bundle. Although, lifting can be segmented into D different protograph structures, in some implementations of the present disclosure, the code construction is limited to D = 2 (which makes it consistent with the general notion of partial coupling of block LDPC codes). First, one may take L block LDPC protographs and then apply edge spreading for L block LDPC protographs to form an SC LDPC protograph (as illustrated in FIG. 13). Then, at each spatial position, one again place original copies of block LDPC protographs. In this way, the edge-type is defined by characterizing an edge that is spread along the SC LDPC protograph with the original edge in the block LDPC protograph as shown in FIG. 25.

[0185] FIG. 26 illustrates an example of a parity check matrix (PCM) of a PSC LDPC code. A PCM of a (dv, dc, L, β) PSC LDPC code may have a form shown in FIG. 26. In FIG. 26, the blank part may consist of all zeros. In FIG. 26, submatrices0denote zero matrices.

[0186] At each time intervalt, 0 ≤t≤L-1, the coupling between the neighboring sub block is only associated with the submatricesHi(t)which relate to the SC LDPC code, wherei=0,1,...,w. In FIG. 26, the submatricesH(t) is associated to a block LDPC code and has no memory. The main essence of PSC LDPC codes lies in the fact that the memory is passively shared with the submatricesH(i) through the permuted / shared edges.

[0187] FIGS. 27 and 28 illustrate overall structures of PCMsHof PSC LDPC codes. In particular, FIG. 27 illustrates an overall structure of a PCMHof a (dv,dc,L,β) = (3, 6, 4, 0.75) PSC LDPC code with Z = 500, and FIG. 28 illustrates an overall structure of a PCMHof a (dv,dc,L,β) = (3, 6, 8, 0.5) PSC LDPC code with Z = 1000. Both codes in FIGS. 27 and 28 may be constructed from random permutation of edges whereby the PCMs have random edge connections where '1's in the PCMHare randomly placed according to some construction rules.

[0188] The random edge connections may mean that '1's in the PCMHare randomly placed. For example, QC LDPC codes have '1's placed in quasi-cyclic format, while in random LDPC codes '1's are placed randomly according to some construction rules.

[0189] In order to apply PSC LDPC codes for the future wireless communication system, an encoding procedure / technique for the PSC LDPC codes needs to be provided. In the following description, an encoding procedure / technique for LDPC codes according to some implementations of the present disclosure is described.

[0190] <1.3.2. Windowed Decoding of PSC-LDPC Codes>

[0191] The windowed decoding of the PSC LDPC codes is similar to that of the SC LDPC codes. Same decoding process and steps are followed, since PSC LDPC codes also have a diagonal band structure which is suitable for windowed decoding. FIG. 29 illustrates an example of the base matrix view of the windowed decoding over a (3, 6,L,β) PSC LDPC code. FIG. 30 illustrates an example of the window decoding step at the 2ndtarget sub-code block of a (3, 6,L,β) PSC LDPC code, where the 2ndtarget sub-block in a dotted-line box. Once the number of target sub-code blocks and window size W is fixed, the windowed decoder follows similar steps that were followed in the case of SC-LDPC code.

[0192] Hereinafter, described are some implementations of the present application that are related to an ensemble design methodology for partial spatially coupled LDPC codes. The design ensembles of codes are aimed at increasing the windowed decoding performance of the PSC LDPC codes.

[0193] <2.1. Coupling Between the Neighboring Sub-code blocks using the Block LDPC Connections>

[0194] In the conventional PSC LDPC codes, the β fraction of copied block LDPC protographs are placed according to the individual time-index as shown in FIGS. 25, 27 and 28, which means that it does not introduce coupling between neighboring sub-code blocks directly. However, the VNs of the block LDPC protographs are passively coupled by random exchange of edges between block and SC LDPC protographs. To increase the error-rate performance of the windowed decoder, some implementations of the present disclosure introduce coupling between neighboring sub-code blocks by using the block LDPC connections. Instead of placing the block LDPC protographs at an individual time-index, a method in which the VNs of the individual protograph are placed at different time-intervals may be used according to some implementations of the present disclosure. The number of VNs in a (dv, dc) block LDPC protograph is given by k=dc / dv. It means that the number of VNs that can be shuffled between neighboring protograph is k.

[0195] FIG. 31 illustrates an example of a block LDPC protograph, and FIG. 32 illustrates an example of shuffling between neighboring block protographs at different interval t. Variable shuffling between the neighboring sub-code blocks may be performed using block LDPC connections according to some implementations of the present disclosure as follows.

[0196] In some implementations of the present disclosure, the same protograph, which has 'k'VNs, as shown in FIG. 31 may be copied 'L'times and indexed as an interval or index 't'for a data transmission sequence, where t = 1, ...,L, as shown in FIG. 32(a).

[0197] In the conventional PSC-LDPC codes, the VNs of the block LDPC protographs are passively coupled by random exchange of edges between block and SC LDPC protographs. For example, in the conventional PSC-LDPC codes, VNs are not shuffled between neighboring sub-code blocks. To increase the error-rate performance of the windowed decoder, some implementations of the present disclosure introduce coupling between neighboring sub-code blocks by using the block LDPC connections. Instead of placing the block LDPC protographs at an individual time-index as shown in FIG. 32(a), a method in which the VNs of the individual protograph are shuffled to different time-intervals is used in some implementations of the present disclosure. It may mean thatkVNs in a protograph at time-interval 't'are shuffled between neighboringkprotographs, as shown in FIG. 32(b).

[0198] FIG. 33 illustrates the shuffling of variable nodes of block LDPC protographs at different indexes.

[0199] Let[1, L]be the vector representing the indices of the VNs of block LDPC protographs at different time-intervals. The vectorφ[1, L]may be expressed as follows:

[0200] φ[1, L]=[φ1,φ2, ...,φL]

[0201] , whereφi=[(1,i), (2,i), ..., (k,i)], 1≤i≤L,L∈Z+, whereZ+denotes positive real numbers. For defining the shuffling of VNs through these indices,ksubmatricesφi(wherei∈[1,k]) may be stacked as a row of the shuffling matrixSkХk, as shown in FIG. 33(a). In other words, the shuffling matrixSkХkis just a matrix in which the sub-matricesφiinφ[1, L]are stacked as rowsin the matrix. Therefore, this matrix is formed before shuffling.

[0202] By the shuffling of VNs,φ[1, L]is transformed intoφs[1, L]. Now, the shuffled indices of VNs (denoted byφs[1, L]) are found as the column entries ofSat each column 1≤i'≤L, as shown in FIG. 33(b). As it may be observed that the shuffling is performed over a group ofksub-matricesφi,L = k×NGmay be considered, whereNGis the number of VN groups. SinceSis ak-by-kmatrix, there is a VN at each time-intervaltthat do not shuffle its position to other time-indices. The shuffling procedure is repeatedNGtimes over a base matrix of a PSC LDPC code (or a PCMHof a PSC LDPC code).

[0203] FIG. 34 illustrates an example of coupling between neighboring sub-code blocks using the block LDPC connections.

[0204] For example, referring to the (3, 6,L,β) PSC LDPC shown in FIG. 25, the number of VNs in a block LDPC protograph isk =2, and the placement of the VNs are shuffled betweenk =2 protographs at consecutive time intervals without breaking the connection with the original protograph as shown in FIG. 34.

[0205] <2.1.1. Sliding Steps of Windowed Decoder Based on Block LDPC Connections>

[0206] FIG. 35 illustrates an example of windowed decoding according to some implementations of the present disclosure. In particular, FIG. 35 illustrates an example of windowed decoding the base matrix of a (3, 6,L,β) PSC-LDPC code according to some implementations of the present disclosure. A base matrix of (3, 6) PSC LDPC code shown in FIG. 29 may be changed into a base matrix of (3, 6) PSC LDPC code shown in FIG. 35 by the VN shuffling according to some implementations of the present disclosure.

[0207] The coupling between neighboring sub-code blocks in block LDPC parts will distribute the syndromes associated to the bits placed at different time-intervals. In this context, the sliding step of the windowed decoder will increase to a step size ofk, i.e., the target sub-code blocks to be decoded is equal tok. FIG. 35 shows the base matrix of the (3, 6,L,β) PSC LDPC ensemble designed according to coupling in block LDPC part. The base matrix view of the sliding step of the windowed decoder is also shown in FIG. 35. Sincek=2, the number of target sub-code blocks to be decoded by the windowed decoding is also equal to 2.

[0208] Referring to FIG. 29, decoding on a sub-codeword may be performed at a time by using a windowed decoder of window size W = 3 on a base matrix of a (3, 6,L,β) PSC LDPC code, whereby one target sub-code block may be decoded at a time. The base matrix of a (3, 6,L,β) PSC LDPC code, as shown in FIG. 29, may be changed into a base matrix of a (3, 6,L,β) PSC LDPC code, as shown in FIG. 35. The entries of the matrix corresponding to two consecutive blocks in a base matrix of a (3, 6,L,β) LDPC code, are coupled by shuffling the VNs of two block LDPC codes, whereby obtaining a shuffled base matrix of (3, 6,L,β) PSC LDPC code. Such a shuffling procedure is repeatedNGtimes over a base matrix of a (dv,dc,L,β) PSC LDPC code, whereNG= L / k, wherek=dc / dv. For a M-by-N parity check matrixH, N×dv= M×dc, and thereforek=dc / dvmay be also expressed ask= N / M. During windowed decoding at some time instance, a decoder according to some implementations of the present disclosure may obtain two decoded target sub-code blocks by using the windowed decoder over a sub-base matrix which includes at least two consecutive sub-code blocks in the base matrix obtained after the shuffling procedure.

[0209] <2.2. SC LDPC Protograph with Reduced Coupling Width>

[0210] Our goal is to design ensembles / protographs of PSC LDPC codes that perform close to the error-rate performance of the maximum a posteriori (MAP) decoder by using the low-complexity windowed decoder. The decoding complexity of the windowed decoder scales linearly with the size of the window W. However, the performance degrades by decoding with a small W, which means the complexity has a tradeoff with the error-rate performance. For some SC LDPC ensembles, it is shown through density evolution (DE) that the decoding threshold (a metric that determine the asymptotic performance behavior of the code) is zero for binary erasure channel (BEC) (see the document "A. R. Iyengar, M. Papaleo, P. H. Siegel, J. K. Wolf, A. Vanelli-Corolli, and G. E. Corazza, "Windowed decoding of protograph-based LDPC convolutional codes over erasure channels," in IEEE Trans. Inf. Theory, vol. 58, no. 4, pp. 2303-2320, Apr. 2012."). The performance loss is mainly due to stationary edges in the window configuration of the windowed decoder. The stationary edges are edges that are connected to the CNs outside the current decoding window. The stationary edges contain no information and do not pass any message during the decoding process.

[0211] FIG. 36 shows examples of window configuration of first target sub-code block SC LDPC ensembles with component base matrices (a) B0= B1= B2= [1, 1] and (b) B0= [1, 1], B1= [2, 2], where dv=3 and dc=6.

[0212] Some studies analyzed the adverse effects of the stationary edges on the performance of the windowed decoding (WD) for different window configurations (e.g., by considering different SC LDPC ensembles) (see the documents "A. R. Iyengar, M. Papaleo, P. H. Siegel, J. K. Wolf, A. Vanelli-Corolli, and G. E. Corazza, "Windowed decoding of protograph-based LDPC convolutional codes over erasure channels," in IEEE Trans. Inf. Theory, vol. 58, no. 4, pp. 2303-2320, Apr. 2012." and "I. Ali and J. Ha, "Partial Spatial Coupling of LDPC Codes: Reducing the Gap to Capacity by Improving the Rate," in IEEE Transactions on Communications, vol. 71, no. 12, pp. 6898-6913, Dec. 2023."). For small W, it is observed that the stationary edges at the tail of the window are the major cause of the performance loss in the WD. For example, the asymptotic WD threshold over BEC (denoted by ε*) for the SC LDPC ensemble with component base matrices B0= B1= B2= [1, 1] is zero for W = 3 and δ = 0 (where δ is predetermined target erasure probability), whereas the SC LDPC ensemble with component base matrices B0= [1, 1], B1= [2, 2] has a WD decoding threshold ε*= 0.3331 for W = 3 and δ = 0.

[0213] From the window configuration in FIG. 36(a), it may be observed that there are VNs of degree 1 that are connected to the same CNs. Since VNs with degree 1 is always passing the channel information, one may see that the DE threshold for this ensemble is zero. There is no VN with degree 1 for ensemble shown in FIG. 36(b). Due to memory in the code design of SC LDPC codes, the edges connected to the VNs of the previously decoded sub-code blocks only provide read access to the CNs in the current window. These edges are in a semi-active mode since the symbols decoded at the previous WD position do not require additional processing (i.e., no messages are passed from the CNs inside the current window to these VNs).

[0214] FIG. 37 shows an example of a window configuration for decoding a target sub-code block at the middle of the SC LDPC chain. In particular, FIG. 37 shows an example of a window configuration of SC LDPC ensemble with component base matrices B0= B1= B2= [1, 1]. The semi active edges are expressed in bold italic in FIG. 37. In FIG. 37, the edges connected to the VNs of the previously decoded sub-code blocks are 1s marked in bold italic.

[0215] FIG. 38 shows an example of window configurations of W = 3 for SC LDPC ensembles.

[0216] In terms of the performance and design of ensemble for SC LDPC codes, there is tradeoff between waterfall and error floor performance of different ensemble. To further analyze the factors which effect the performance of the windowed decoder, the example given in FIG. 38 may be considered for more clear explanation. An ensemble of SC LDPC codes is defined from component base matrices and a coupling length L. FIG. 38(a) shows a part of an ensemble A, and FIG. 38(b) shows a part of an ensemble B, where the ensemble with component base matrices B0= [2, 2], B1= [1, 1], is referred to as ensemble A, and the ensemble with component base matrices B0= [1, 1], B1= [2, 2], is referred to as ensemble B. The window configurations of windowed decoder with W=3 for ensemble A and B are as shown in FIG. 38(a) and (b), respectively.

[0217] Window configurations for SC LDPC ensembles A and B with W = 3 and at any position in the middle of SC LDPC chain may be considered as shown in FIG. 38. It may be seen that the number of edges in a box marked with "Weak Connectivity" ( due to the structure of ensemble A) is less than that of the edges in a box marked with "Strong Connectivity" ( due to the structure of ensemble B), and these edges in the boxes correspond to the previous target symbols of the previous position of a window. Since in windowed decoding, semi active edges share the extrinsic LLRs with the edges inside the window, ensemble B seems to have greater extrinsic information sharing capability due to the higher number of semi active edges than in ensemble A. Whereas, at the last sub-code block ensemble A seems to have no VNs with degree 1 and ensemble B has degree 1 VNs. As discuss earlier, we come across tradeoff because of the design of SC LDPC ensemble.

[0218] Now for design of PSC LDPC ensembles, this tradeoff may be significantly improved. To design SC LDPC part with reduced coupling width, first described is a procedure called 'edge spreading' that is used for introducing coupling between different block LDPC codes at different time intervals.

[0219] FIG. 39 illustrates an example of edge-spreading technique with respect to the base matrix of an SC-LDPC protograph.

[0220] In the edge spreading technique, the edges from the VNs of a block LDPC protograph at time-interval't'are spread and connected to CNs att+i,i=0, 1, 2, ...,w. The edge spreading decomposes the base matrixBinto component base matricesBj,j=0, 1, 2, ...,w, such that , wherew> 0 is the coupling width of the SC LDPC protograph. The edge spreading on base matrixBis shown in FIG. 39.

[0221] FIG. 40 illustrates an example of reducing the coupling width in the SC LDPC part of PSC LDPC codes according to some implementations of the present disclosure.

[0222] To describe some implementations of the present disclosure for reducing the coupling width in the SC LDPC part of PSC LDPC codes, the component base matrices after decomposition ofBare index byl∈ [0,w]. In some implementations of the present disclosure, component base matrices starting fromBwtoBw-sare summed with each other, whereby a single component base matrix corresponding to summed component base matrices starting fromBwtoBw-smay be obtained, where 's'denotes the number of component base matrices that are eliminated from the component base matricesBl, wherel∈ [0,w], to reduce the coupling widthwintow-s. Letw` be the required coupling width, then , wherew` =w-s.The reduction of coupling width of the base matrixBSCof the SC LDPC part is shown in FIG. 40.

[0223] <2.3. Overall Procedure for the Design of PSC-LDPC Ensembles for Windowed Decoding>

[0224] In some implementations of the present disclosure, the PSC LDPC ensembles may be obtained as follows.

[0225] > Step 1:Design block LDPC part by the passive coupling method defined in section 2.1.

[0226] > Step 2:Design of SC LDPC part by first defining component base matricesBi, withivarying from 0 tow. The coupling width 'w' may be reduced into 'w`' by summing the entries of component base matricesBw,Bw-1,...,Bw-s(where, 1 ≤s≤w). By summing the component base matricesBw,Bw-1,...,Bw-sensures that strong connectivity from the previously decoded sub-code block to the current sub-code block.

[0227] > Step 3:Only fractionαdegree-1 VNs remain at the last sub-code block and fraction (1-α) VNs of degreedvfrom the block LDPC part help reduce the error-rate. The required number of component base matrices and the value ofαadded together for optimal performance may be found by recursively adding and checking the performance by simulation or extrinsic information transfer (EXIT) chart method.

[0228] FIG. 41 shows an example of a base matrix of a PSC LDPC code and an example of a submatrix or window configuration for windowed decoding according to some implementations of the present disclosure.

[0229] For a received codeword corresponding toLcode blocks related to a transport block, a windowed decoder with a window size W decodes sub-codewordsvt, which respectively correspond to code blocksut, where t = 0, 1, ...,L-1. Starting from t=0, the target code blockut=0is decoded by using a sub-base matrixBsubin a base matrixBof a PSC LDPC code, where the base matrixBof a PSC LDPC code may be expressed as that shown in FIG. 41(a), andBsubmay be expressed asB'[0,W-1]as shown in FIG. 41(b), where W is a window size for windowed decoding. The window size may be defined as W≥w+1, wherewis a coupling width. After obtaining the target code blockut=i, then the windowed decoder slides a decoding window forward t=i+1 to next sub-codewords to be decoded, by using the sub-base matrixBsub.

[0230] In some implementations of the present disclosure, a new base matrixBPSCfor a (dv,dc,L,β) PSC LDPC code may be obtained by shuffling VNs fork=dc / dvneighboring sub-blocks in units ofk=dc / dvconsecutive sub-blocks. A windowed decoder decodes sub-codewordsvt, which respectively correspond to code blocksut, where t = 0, 1, ..., L-1. Starting from t=0, the windowed decoder produce k target code blocksut=0tout=kby using a sub-base matrixBPSC,subin the base matrixBPSC, whereBsubmay be expressed asBPSC,[0,W-1], where W is a window size for windowed decoding. After obtaining the target code blocksut=0tout=k, then the windowed decoder slides a decoding window forward by k sub-codewords and decodes, by using the sub-base matrixBPSC,sub, sub-codewordsvt=k+1tovt=2k, which respectively correspond to code blocksut=k+1tout=2k.

[0231] In some implementations of the present disclosure, another new base matrix for a (dv,dc,L,β) PSC LDPC code may be obtained by summing the component base matricesBw,Bw-1,...,Bw-sto obtain a new component base matrixBw`.

[0232] FIG. 42 to 44 illustrates an example of PSC LDPC base matrix, and corresponding PSC LDPC ensembles according to some implementations of the present disclosure.

[0233] FIG. 42 illustrates an example of (3, 6,L,β) PSC LDPC base matrix. The example of (3, 6,L,β) PSC LDPC codes as shown in FIG. 42 is used to explain the PSC LDPC ensembles with small window size and number of target symbols greater than 1 according to some implementations. The number of sub-code blocks to be decoded at a time by a windowed decoder for a (3, 6,L,β) PSC LDPC base matrix shown in FIG. 42 is 1.

[0234] In some implementations of the present disclosure, a new base matrix for a (3, 6,L,β) PSC LDPC code, as shown in FIG. 43, may be obtained by shuffling VNs fork=dc / dv=2 neighboring sub-code blocks in units ofk=dc / dv=2 consecutive sub-code blocks. The number of sub-code blocks to be decoded at a time increases from 1 tok=dc / dv=2.

[0235] In some implementations of the present disclosure, another new base matrix for a (3, 6,L,β) PSC LDPC code, as shown in FIG. 44, may be obtained by summing the last two component base matricesB1= [1, 1] andB2= [1, 1] to obtain a new component base matrixB1= [2, 2].

[0236] The codes from the ensembles according to some implementations of the present disclosure provide excellent bit error-rate (BER) and codeword error-rate (CER) performance. In FIG 44, the VNs at the last sub-code block share the block LDPC VNs with 2 sub-code blocks of CNs. This considerably improves the performance of the codes from these ensembles.

[0237] According to some implementations of the present disclosure, provided may be PSC-LDPC ensembles that provide good error-rate performance with a windowed decoder. According to some implementations of the present disclosure, provided may be ensembles of PSC LDPC codes that can provide optimal MAP decoding performance with a low complexity windowed decoder with small window size W. According to some implementations of the present disclosure, the efficient data transmissions through the communication channels may be achieved by using the PSC-LDPC codes.

[0238] FIG. 45 illustrates a channel decoding process according to some implementations of the present disclosure.

[0239] A communication device or decoder may perform operations related to channel decoding according to some implementations of the present disclosure. The communication device may include: at least one transceiver; at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure. A processing device for the communication device or decoder may include: at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform the operations according to some implementations of the present disclosure. A computer-readable (non-transitory) storage medium may store at least one computer program including instructions that, when executed by at least one processor, cause the at least one processor to perform the operations according to some implementations of the present disclosure. A computer program or computer program product may include instructions that are recorded in at least one computer-readable (non-transitory) storage medium and cause, when executed, (at least one processor) to perform the operations according to some implementations of the present disclosure. For the communication device, decoder, processing device, computer-readable (non-transitory) storage medium, and / or computer program product, the operations may include: receiving coded blocks 0 to (L-1) related to a transport block (S4501); shuffling variable nodes of a first low density parity check, LDPC, base matrix of size nc×nvto obtain a second LDPC base matrix of size nc×nv(S4503); and decoding coded blocks 0 to (L-1) based on the second LDPC base matrix to determine code blocks 0 to (L-1) for the transport block (S4505). In some implementations, decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix comprises: applying a windowed decoder (S4505) to coded blocks i, i+1, ..., i+W-1 to obtain code blocks i, i+1, ..., i+k-1 based on a submatrix l for a window l of windowed decoding, where W≥w+k, w is a coupling width, k = n / m, and j = 0, ..., (L / k)-1; and applying windowed decoder to coded blocks i+k, ..., i+k+W-1 to obtain code blocks i+k to i+2k-1 based on a submatrix l+1 for a window l+1 of the window decoding. Shuffling the variable nodes of the first LDPC base matrix may comprise shuffling variable nodes for neighboring coded blocks j to j+k-1 such that a set of variable nodes for one of the neighboring coded blocks j to j+k-1 is connected to check nodes of another one of the neighboring coded blocks j to j+k-1, where j = 0, ..., L-k-1, wherein each of the submatrices l and (l+1) is a (W*bc)-by-(W*bv) matrix, where nc×nv= ((L+w)bc)×(Lbv).

[0240] In some implementations, the second LDPC base matrix may beB[0, L-1], where , where , whereBis a base matrix for one code block.

[0241] In some implementations, each of the submatrices l and (l+1) may beB[0, W-1]in the second LDPC base matrix.

[0242] In some implementations, the method or the operations may further comprise: replacing component base matricesBw,Bw-1,...,Bw-sbyBw`to obtain a third LDPC base matrix, wheres is an integer larger than 1 and smaller than w, . In some implementations, decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix may comprise: decoding the coded blocks 0 to (L-1) by using the third LDPC base matrix.

[0243] In some implementations, the method or the operations may further comprise: each of the submatrices l and (l+1) may beB[0, W-1]in the third LDPC base matrix.

[0244] The examples of the present disclosure as described above have been presented to enable any person of ordinary skill in the art to implement and practice the present disclosure. Although the present disclosure has been described with reference to the examples, those skilled in the art may make various modifications and variations in the example of the present disclosure. Thus, the present disclosure is not intended to be limited to the examples set for the herein, but is to be accorded the broadest scope consistent with the principles and features disclosed herein

[0245] The implementations of the present disclosure may be used in a BS, a UE, or other equipment in a wireless communication system.

Claims

1.A method performed by a device, the method comprising:shuffling variable nodes of a first low density parity check, LDPC, base matrix of size nc×nvto obtain a second LDPC base matrix of size nc×nv; anddecoding coded blocks 0 to (L-1) based on the second LDPC base matrix to determine code blocks 0 to (L-1) for a transport block,wherein decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix comprises:applying a windowed decoder to coded blocks i, i+1, ..., i+W-1 to obtain code blocks i, i+1, ..., i+k-1 based on a submatrix l for a window l of windowed decoding, where W ≥ w+k, w is a coupling width, k = n / m, and j = 0, ..., (L / k)-1; andapplying the windowed decoder to coded blocks i+k, ..., i+k+W-1 to obtain code blocks i+k to i+2k-1 based on a submatrix l+1 for a window l+1 of the window decoding,wherein shuffling the variable nodes of the first LDPC base matrix comprises shuffling variable nodes for neighboring coded blocks j to j+k-1 such that a set of variable nodes for one of the neighboring coded blocks j to j+k-1 is connected to check nodes of another one of the neighboring coded blocks j to j+k-1, where j = 0, ..., L-k-1,wherein each of the submatrices l and (l+1) is a (W*bc)-by-(W*bv) matrix, where nc×nv= ((L+w)bc)×(Lbv).2.The method according to claim 1,wherein the second LDPC base matrix isB[0, L-1], where,where, whereBis a base matrix for one code block.3.The method according to claim 2,wherein each of the submatrices l and (l+1) isB[0, W-1]in the second LDPC base matrix.4.The method according to claim 2, further comprising:replacing component base matricesBw,Bw-1,...,Bw-sbyBw`to obtain a third LDPC base matrix, wheres is an integer larger than 1 and smaller than w,, andwherein decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix comprises:decoding the coded blocks 0 to (L-1) by using the third LDPC base matrix.5.The method according to claim 4, further comprising:wherein each of the submatrices l and (l+1) isB[0, W-1]in the third LDPC base matrix.6.A device comprising:at least one processor; andat least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations comprising:shuffling variable nodes of a first low density parity check, LDPC, base matrix of size nc×nvto obtain a second LDPC base matrix of size nc×nv; anddecoding coded blocks 0 to (L-1) based on the second LDPC base matrix to determine code blocks 0 to (L-1) for a transport block,wherein decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix comprises:applying a windowed decoder to coded blocks i, i+1, ..., i+W-1 to obtain code blocks i, i+1, ..., i+k-1 based on a submatrix l for a window l of windowed decoding, where W ≥ w+k, w is a coupling width, k = n / m, and j = 0, ..., (L / k)-1; andapplying the windowed decoder to coded blocks i+k, ..., i+k+W-1 to obtain code blocks i+k to i+2k-1 based on a submatrix l+1 for a window l+1 of the window decoding,wherein shuffling the variable nodes of the first LDPC base matrix comprises shuffling variable nodes for neighboring coded blocks j to j+k-1 such that a set of variable nodes for one of the neighboring coded blocks j to j+k-1 is connected to check nodes of another one of the neighboring coded blocks j to j+k-1, where j = 0, ..., L-k-1,wherein each of the submatrices l and (l+1) is a (W*bc)-by-(W*bv) matrix, where nc×nv= ((L+w)bc)×(Lbv).7.The device according to claim 6,wherein the second LDPC base matrix isB[0, L-1], where,where, whereBis a base matrix for one code block.8.The device according to claim 7,wherein each of the submatrices l and (l+1) isB[0, W-1]in the second LDPC base matrix.9.The device according to claim 7, wherein the operations further comprise:replacing component base matricesBw,Bw-1,...,Bw-sbyBw`to obtain a third LDPC base matrix, wheres is an integer larger than 1 and smaller than w,, andwherein decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix comprises:decoding the coded blocks 0 to (L-1) by using the third LDPC base matrix.10.The device according to claim 9, wherein the operations further comprise:wherein each of the submatrices l and (l+1) isB[0, W-1]in the third LDPC base matrix.11.A computer-readable non-transitory storage medium configured to store at least one program code comprising instructions that, when executed, cause at least one processor to perform operations comprising:shuffling variable nodes of a first low density parity check, LDPC, base matrix of size nc×nvto obtain a second LDPC base matrix of size nc×nv; anddecoding coded blocks 0 to (L-1) based on the second LDPC base matrix to determine code blocks 0 to (L-1) for a transport block,wherein decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix comprises:applying a windowed decoder to coded blocks i, i+1, ..., i+W-1 to obtain code blocks i, i+1, ..., i+k-1 based on a submatrix l for a window l of windowed decoding, where W ≥ w+k, w is a coupling width, k = n / m, and j = 0, ..., (L / k)-1; andapplying the windowed decoder to coded blocks i+k, ..., i+k+W-1 to obtain code blocks i+k to i+2k-1 based on a submatrix l+1 for a window l+1 of the window decoding,wherein shuffling the variable nodes of the first LDPC base matrix comprises shuffling variable nodes for neighboring coded blocks j to j+k-1 such that a set of variable nodes for one of the neighboring coded blocks j to j+k-1 is connected to check nodes of another one of the neighboring coded blocks j to j+k-1, where j = 0, ..., L-k-1,wherein each of the submatrices l and (l+1) is a (W*bc)-by-(W*bv) matrix, where nc×nv= ((L+w)bc)×(Lbv).12.The storage medium according to claim 11,wherein the second LDPC base matrix isB[0, L-1], where,where, whereBis a base matrix for one code block.13.The storage medium according to claim 12,wherein each of the submatrices l and (l+1) isB[0, W-1]in the second LDPC base matrix.14.The storage medium according to claim 12, wherein the operations further comprise:replacing component base matricesBw,Bw-1,...,Bw-sbyBw`to obtain a third LDPC base matrix, wheres is an integer larger than 1 and smaller than w,, andwherein decoding the coded blocks 0 to (L-1) based on the second LDPC base matrix comprises:decoding the coded blocks 0 to (L-1) by using the third LDPC base matrix.15.The storage medium according to claim 14, wherein the operations further comprise:wherein each of the submatrices l and (l+1) isB[0, W-1]in the third LDPC base matrix.

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