Silicon substrate-based distributed bragg reflector and vertical cavity surface-emitting laser comprising same
A DBR structure on a silicon substrate with stacked III-V semiconductor layers addresses scaling and cost issues in VCSELs by improving surface crystallinity and reducing defects, resulting in efficient and cost-effective VCSELs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- KOREA INST OF SCI & TECH
- Filing Date
- 2025-03-17
- Publication Date
- 2026-07-23
AI Technical Summary
Existing Vertical Cavity Surface Emitting Lasers (VCSELs) face challenges in scaling and cost-effectiveness due to the use of 2-inch or 3-inch GaAs wafers, leading to issues with size, surface crystallinity, surface roughness, and threading dislocation defects (TDD) in Distributed Bragg Reflector Mirrors (DBRs).
A DBR structure utilizing a silicon substrate with alternately stacked first and second III-V semiconductor material layers, including compounds like InX1As and X2As, provides improved surface crystallinity, surface roughness, and reduced TDD concentration, enabling scalability and cost-effectiveness.
The DBR structure on a silicon substrate achieves excellent size and economic efficiency, with enhanced surface properties and reflectance, supporting the development of scalable and cost-effective VCSELs.
Smart Images
Figure KR2025003382_23072026_PF_FP_ABST
Abstract
Description
Dispersive Bragg mirror based on a silicon substrate, and a surface reflection laser including the same
[0001] The present invention relates to a dispersed Bragg mirror and a surface reflection laser comprising the same.
[0002] A Vertical Cavity Surface Emitting Laser (VCSEL) refers to a laser that emits light vertically from a surface and is generally manufactured by epitaxially growing III-V semiconductor materials on a substrate. The Distributed Brag Reflector Mirror (DBR) included in the VCSEL reflects light upward to enable surface emission, thereby preserving the performance and lifespan of the VCSEL.
[0003] Currently, VCSELs and DBRs included in VCSELs are manufactured using an epitaxial growth process based on 2-inch or 3-inch GaAs wafers, and problems are being raised regarding scaling in a narrow area and high cost per unit area.
[0004] The technical problem that the present invention aims to solve is to provide a dispersion Bragg mirror with excellent size and cost-effectiveness, and improved surface crystallinity, surface roughness, and TDD concentration.
[0005] The technical problem that the present invention aims to solve is to provide a surface reflection laser with excellent size and cost-effectiveness.
[0006] A distributed Bragg reflector (DBR) according to some embodiments of the present invention may include a substrate comprising silicon and a stacked structure on the substrate. The stacked structure may include a first material layer and a second material layer on the first material layer. The first material layer may include a compound of [Chemical Formula 1] below.
[0007] [Chemical Formula 1]
[0008] InX 1 As
[0009] The above second material layer may include a compound of the following [Chemical Formula 2].
[0010] [Chemical Formula 2]
[0011] X 2 As
[0012] X of the above [Chemical Formula 1] 1 It is Ga or Al, and
[0013] The above X 1 When this is Ga, X of the above [Chemical Formula 2] 2 is Al,
[0014] The above X 1 When this is Al, X of the above [Chemical Formula 2] 2 is Ga.
[0015] A dispersion Bragg mirror according to some embodiments of the present invention may comprise a substrate comprising silicon, and first material layers and second material layers alternately stacked in a vertical direction on said substrate. Each of said first material layers may comprise a first III-V semiconductor material. Each of said second material layers may comprise a second III-V semiconductor material. The first III-V semiconductor material may comprise a plurality of group III elements. The plurality of group III elements may include indium and a first group III element different from indium. The second III-V semiconductor material may include indium and a second group III element different from the first group III element.
[0016] A Vertical Cavity Surface Emitting Laser (VCSEL) according to some embodiments of the present invention may include a dispersive Bragg mirror, a first doping structure on the dispersive Bragg mirror, an active layer on the first doping structure, and a second doping structure disposed on the active layer and doped with a different type from the first doping structure. The dispersive Bragg mirror may include a substrate comprising silicon and a stacked structure on the substrate. The stacked structure may include a first material layer and a second material layer on the first material layer. The first material layer may include a compound of [Chemical Formula 1] below.
[0017] [Chemical Formula 1]
[0018] InX 1 As
[0019] The above second material layer may include a compound of the following [Chemical Formula 2].
[0020] [Chemical Formula 2]
[0021] X 2 As
[0022] X of the above [Chemical Formula 1] 1 It is Ga or Al, and
[0023] The above X 1 When this is Ga, X of the above [Chemical Formula 2] 2 is Al,
[0024] The above X 1 When this is Al, X of the above [Chemical Formula 2] 2 is Ga.
[0025] The DBR according to the present invention provides a material and structure with improved surface crystallinity, surface roughness, and crystal defects based on a silicon substrate that is highly economical and scalable over a large area. As a result, a VCSEL comprising a DBR with excellent size and economic efficiency can be provided.
[0026] FIG. 1 is a cross-sectional view of a DBR according to some embodiments of the present invention.
[0027] FIG. 2 is a cross-sectional view of a VCSEL according to some embodiments of the present invention.
[0028] Figure 3a shows the results of observing the surface crystallinity of <Comparative Example>.
[0029] Figure 3b shows the results of observing the surface crystallinity of <Example 1>.
[0030] Figure 4a shows the surface roughness observation results of <Comparative Example>.
[0031] Figure 4b shows the surface roughness observation results of <Example 1>.
[0032] Figure 5a shows the results of the TDD (Threading Dislocation Defect) concentration analysis of the <Comparative Example>.
[0033] Figure 5b shows the TDD concentration analysis results of <Example 1>.
[0034] Figure 6 shows the reflectance measurement results of <Example 1>.
[0035] Figure 7 shows the photoluminescence (PL) measurement results of <Example 2>.
[0036]
[0037] Hereinafter, a gas storage device according to some embodiments of the present invention will be described in detail with reference to the drawings.
[0038] FIG. 1 is a cross-sectional view of a DBR according to some embodiments of the present invention.
[0039] Referring to FIG. 1, a DBR (10) according to some embodiments of the present invention may include a substrate (100), a nucleation layer (200), a first stacked structure (300), and a capping layer (600).
[0040] The substrate (100) may include silicon. The substrate (100) may include, for example, a 6-inch to 12-inch wafer.
[0041] A nucleation layer (200) may be provided on a substrate (100). The nucleation layer (200) may function as a buffer. The nucleation layer (200) may have substantially the same crystal orientation as the substrate (100).
[0042] Although not illustrated in FIG. 1, as another example, an intermediate layer (not illustrated) containing a first III-V semiconductor material may be interposed between the substrate (100) and the nucleation layer (200). The III-V semiconductor material may include, for example, GaP.
[0043] The nucleation layer (200) may include a second III-V semiconductor material. The second III-V semiconductor material may be, for example, GaAs. When an intermediate layer (not shown) is interposed between the substrate (100) and the nucleation layer (200), for example, the second III-V semiconductor material has the same group III elements as the first III-V semiconductor material and different group V elements, but is not limited thereto.
[0044] The nucleation layer (200) can be formed from a substrate (100) and / or an intermediate layer (not shown) through an epitaxial growth process. The epitaxial growth process can be performed, for example, at a low temperature (LT condition, Low temperature), and for example, the temperature during the epitaxial growth process can be 500°C.
[0045] The vertical thickness of the nucleation layer (200) is not limited, but may be, for example, 10 nm to 100 nm, or 30 nm to 70 nm. For example, the vertical thickness of the nucleation layer (200) may be smaller than the vertical thickness of the first material layer (310) and / or the vertical thickness of the second material layer (320).
[0046] A first stacked structure (300) may be provided on the nucleation layer (200). The first stacked structure (300) may be provided in multiple numbers and may be stacked vertically on the nucleation layer (200). The number of first stacked structures (300) in the DBR (10) is not limited, but the DBR (10) may include, for example, 2 to 100, 5 to 50, or 10 to 30 first stacked structures (300).
[0047] The first laminated structure (300) may include a first material layer (310) and a second material layer (320) on the first material layer (310). For example, in each of the first laminated structures (300), the level of the second material layer (320) may be higher than the level of the first material layer (310). In the DBR (10), the first material layer (310) and the second material layer (320) may be arranged alternately in a vertical direction.
[0048] The first material layer (310) may include a third III-V semiconductor material. The third III-V semiconductor material may include a plurality of group III elements. The plurality of group III elements may include indium and a first group III element different from indium. The third III-V semiconductor material may, for example, include a group V element different from the first III-V semiconductor material. The third III-V semiconductor material may, for example, include a group V element identical to the first III-V semiconductor material.
[0049] A third III-V semiconductor material can have the structure of [Chemical Formula 1] below as an example.
[0050] [Chemical Formula 1]
[0051] InX 1 As
[0052] X of the above [Chemical Formula 1] 1 It is Ga or Al.
[0053]
[0054] The compound of [Chemical Formula 1] can satisfy the following [Formula 1] as an example.
[0055] [Equation 1]
[0056]
[0057] In the above [Equation 1], a1 is the atomic percent of In relative to the compound of [Chemical Formula 1], and a2 is X relative to the compound of [Chemical Formula 1]. 1 It is the atomic ratio of.
[0058]
[0059] A third III-V semiconductor material can satisfy the following [Equation 2] as an example.
[0060] [Equation 2]
[0061]
[0062] In the above [Equation 2], a III is the atomic percent of the plurality of group III elements relative to the third group III-V semiconductor material, and a1 is the atomic percent of In relative to the third group III-V semiconductor material.
[0063]
[0064] The first stacked structure (300) may include a lower first stacked structure with the lowest level and an upper first stacked structure with the highest level. The first material layer (310) of the lower first stacked structure may have the same crystal direction as the nucleation layer (200). The first material layer (310) of the lower first stacked structure may be formed from the nucleation layer (200) through an epitaxial growth process, for example, the temperature during the epitaxial growth process may be 530°C. The first material layer (310) of the upper first stacked structure may have the same crystal direction as the lower second material layer (320). The first material layer (310) of the upper first stacked structure may be formed from the lower second material layer (320) through an epitaxial growth process, for example, the temperature during the epitaxial growth process may be 530°C.
[0065]
[0066] The second material layer (320) may include a fourth III-V semiconductor material. The fourth III-V semiconductor material may include a second III element different from indium. The second III element may be different from the first III element. The fourth III-V semiconductor material may, for example, include a group V element different from the first III-V semiconductor material. The fourth III-V semiconductor material may, for example, include a group V element identical to the first III-V semiconductor material.
[0067] A fourth III-V semiconductor material can have the structure of [Chemical Formula 2] below as an example.
[0068] [Chemical Formula 2]
[0069] X 2 As
[0070] X in the above [Chemical Formula 2] 2 is Al or Ga,
[0071] X of the above [Chemical Formula 1] 1 When this is Ga, X of the above [Chemical Formula 2]2 is Al,
[0072] X of the above [Chemical Formula 1] 1 When this is Al, X of the above [Chemical Formula 2] 2 is Ga.
[0073]
[0074] The third III-V semiconductor material and the fourth III-V semiconductor material can satisfy the following [Equation 3].
[0075] [Equation 3]
[0076]
[0077] In the above [Equation 3],
[0078] n1 is the refractive index of the third III-V semiconductor material, and
[0079] n2 is the refractive index of a 4th-class III-V semiconductor material.
[0080]
[0081] The vertical thickness of the first material layer (310) and the second material layer (320) can be determined based on the wavelength of light emitted by the target VCSEL by a method known to a person skilled in the art. For example, the vertical thickness of the second material layer (320) may be 90 nm to 110 nm. For example, the vertical thickness of the first material layer (310) may be 80 nm to 100 nm. For example, the vertical thickness of the second material layer (320) may be greater than the vertical thickness of the first material layer (310).
[0082]
[0083] The second material layer (320) may have the same crystal direction as the first material layer (310) below it. The second material layer (320) may be formed from the first material layer (310) below it through an epitaxial process, and as an example, the temperature during the epitaxial growth process may be 530°C.
[0084]
[0085] A capping layer (600) may be provided on a second material layer (320) included in the uppermost first laminated structure (300). The capping layer (600) may include substantially the same material as the first material layer (310) and may have the same thickness.
[0086]
[0087] A DBR according to some embodiments of the present invention provides a material and structure with improved surface crystallinity, surface roughness, and crystal defects based on a silicon substrate that is economical and scalable over a large area. As a result, a DBR with excellent size and economic efficiency can be provided.
[0088]
[0089] FIG. 2 is a cross-sectional view of a VCSEL according to some embodiments of the present invention.
[0090] Referring to FIG. 2, a VCSEL (1) according to some embodiments of the present invention may include a DBR (10), a first doping structure (20), a waveguide (31), an active layer (41), and a second doping structure (50).
[0091]
[0092] A first doping structure (20) may be provided on the DBR (10). The first doping structure (20) may, for example, include a buffer layer (21), a first grading layer (22a), a first cladding layer (23), and a second grading layer (22b). Each layer included in the first doping structure (20) may include a III-V semiconductor material or semiconductor materials doped with a first type. For example, the first doping structure (20) may include an n-type doped III-V semiconductor material or semiconductor materials.
[0093]
[0094] A buffer layer (21) may be provided on the DBR (10). Specifically, referring to FIG. 2 together with FIG. 1, a buffer layer (21) may be provided on the capping layer (600) of the DBR (10). The buffer layer (21) may include, for example, GaAs doped with a first type.
[0095] The buffer layer (21) may have the same crystal direction as the capping layer (600) of the DBR (10). The buffer layer (21) may be formed from the capping layer (600) of the DBR (10) through an epitaxial process.
[0096]
[0097] A first grading layer (22a) may be provided on the buffer layer (21). The first grading layer (22) is, for example, Al doped with a first type. x Ga 1-x As (단, 0≤x≤y, 0 <y<1, y는 제1 클래딩 층(23)에서 후술한다)를 포함할 수 있다. 제1 그래이딩층(22a)은 버퍼층(21)과 접촉하는 레벨에서는 제1 타입으로 도핑된 GaAs를 포함할 수 있다. 제1 그래이딩층(22a)은 후술할 제1 클래딩 층(23)과 접촉하는 레벨에서는 제1 타입으로 도핑된 Al y Ga 1-y As(Dan, 0 <y<1)를, 일 예로 제1 타입으로 도핑된 Al 0.4 Ga 0.6 It can include As.
[0098] The first grading layer (22a) may have the same crystal direction as the buffer layer (21). The first grading layer (22a) may be formed from the buffer layer (21) through an epitaxial process.
[0099]
[0100] A first cladding layer (23) may be provided on the first grading layer (22a). The first cladding layer (23) is, for example, Al doped with a first type. y Ga 1-yAs(0 <y<1)를 포함할 수 있다. 제1 클래딩 층(23)은 일 예로 제1 타입으로 도핑된 Al 0.4 Ga 0.6 It can include As.
[0101] The first cladding layer (23) may have the same crystal direction as the first grading layer (22a). The first cladding layer (23) may be formed from the first grading layer (22a) through an epitaxial process.
[0102]
[0103] A second grading layer (22b) may be provided on the first cladding layer (23). The second grading layer (22b) is, for example, Al doped with the first type. x Ga 1-x As (단, 0≤x≤y, 0 <y<1)를 포함할 수 있다. 제2 그래이딩층(22b)은 제1 클래딩 층(23)과 접촉하는 레벨에서는 제1 타입으로 도핑된 Al y Ga 1-y As(Dan, 0 <y<1)를, 일 예로 제1 타입으로 도핑된 Al 0.4 Ga 0.6 It may include As. The second grading layer (22b) may include GaAs doped with the first type at the level in contact with the first waveguide (31a).
[0104] The second grading layer (22b) may have the same crystal orientation as the first cladding layer (23). The second grading layer (22b) may be formed from the first cladding layer (23) through an epitaxial process.
[0105]
[0106] A first waveguide (31a) may be provided on the first doping structure (20). Specifically, the first waveguide (31a) may be provided on the second grading layer (22b) of the first doping structure (20). The first waveguide (31a) may include a group III-V semiconductor material, and may include GaAs as an example.
[0107] The first waveguide (31a) may have the same crystal direction as the second grading layer (22b). The first waveguide (31a) may be formed from the second grading layer (22b) through an epitaxial process.
[0108]
[0109] An active layer (41) may be provided on the first waveguide (31a). The active layer (41) may include a quantum well and a quantum dot within the quantum well. The quantum well and the quantum dot may each include a group III-V semiconductor material. As an example, the quantum well may include InGaAs, and the quantum dot may include InAs.
[0110] The active layer (41) may have the same crystal direction as the first waveguide (31a). The active layer (41) may be formed from the first waveguide (31a) through an epitaxial process.
[0111]
[0112] A second waveguide (31b) may be provided on the active layer (41). The second waveguide (31b) may include a III-V semiconductor material, and may include GaAs as an example.
[0113] The active layer (41) may have the same crystal direction as the second waveguide (31b). The active layer (41) may be formed from the second waveguide (31b) through an epitaxial process.
[0114]
[0115] A second doping structure (50) may be provided on the second waveguide (31b). The second doping structure (50) may, for example, include a third grading layer (52a), a second cladding layer (53), a fourth grading layer (52b), and a capping layer (51). Each layer included in the second doping structure (50) may include a III-V semiconductor material or semiconductor materials doped with a second type. The second type may be different from the first type. For example, the second doping structure (50) may include a III-V semiconductor material or semiconductor materials doped with a p-type.
[0116]
[0117] A third grading layer (52a) may be provided on the second waveguide (31b). The third grading layer (52a) is, for example, Al doped with the second type. x Ga 1-x As (단, 0≤x≤y, 0 <y<1)를 포함할 수 있다. 제3 그래이딩 층(52a)은 제2 도파로(31b)와 접촉하는 레벨에서는 제2 타입으로 도핑된 GaAs를 포함할 수 있다. 제3 그래이딩 층(52a)은 후술할 제2 클래딩 층(53)과 접촉하는 레벨에서는 제2 타입으로 도핑된 Al y Ga 1-y As(Dan, 0 <y<1)를, 일 예로 제2 타입으로 도핑된 Al 0.4 Ga 0.6 It can include As.
[0118] The third grading layer (52a) may have the same crystal direction as the second waveguide (31b). The third grading layer (52a) may be formed from the second waveguide (31b) through an epitaxial process.
[0119]
[0120] A second cladding layer (53) may be provided on the third grading layer (52a). The second cladding layer (53) is, for example, Al doped with the second type. 0.4 Ga 0.6It can include As.
[0121] The second cladding layer (53) may have the same crystal direction as the third grading layer (52a). The second cladding layer (53) may be formed from the third grading layer (52a) through an epitaxial process.
[0122]
[0123] A fourth grading layer (52b) may be provided on the second cladding layer (53). The fourth grading layer (52b) is, for example, Al doped with the second type. x Ga 1-x As (단, 0≤x≤y, 0 <y<1)를 포함할 수 있다. 제4 그래이딩 층(52b)은 제2 클래딩 층(53)과 접촉하는 레벨에서는 제2 타입으로 도핑된 Al y Ga 1-y As(Dan, 0 <y<1)를, 일 예로 제2 타입으로 도핑된 Al 0.4 Ga 0.6 It may include As. The fourth grading layer (52b) may include GaAs doped with the second type at the level in contact with the contact layer (51) to be described later.
[0124] The fourth grading layer (52b) may have the same crystal orientation as the second cladding layer (53). The fourth grading layer (52b) may be formed from the second cladding layer (53) through an epitaxial process.
[0125]
[0126] A contact layer (51) may be provided on the fourth grading layer (52b). The contact layer (51) may include, for example, GaAs doped with the second type.
[0127] The contact layer (51) may have the same crystal orientation as the fourth grading layer (52b). The contact layer (51) may be formed from the fourth grading layer (52b) through an epitaxial process.
[0128]
[0129] The effects and application examples of the present invention will be explained below through <Examples> and <Comparative Examples>.
[0130]
[0131] <Example 1>
[0132] The DBR (10) of Fig. 1 was manufactured.
[0133] Specifically, a silicon substrate was used as the substrate (100). GaP was used as the first III-V semiconductor material included in the intermediate layer (not shown). The second III-V semiconductor material included in the nucleation layer (200) was GaAs, and the thickness of the nucleation layer (200) in the vertical direction was 50 nm. The third III-V semiconductor material included in the first material layer (310) was In 0.1 The material was GaAs, and the fourth III-V semiconductor material included in the second material layer (320) was AlAs. The wavelength of the reflected light targeted by the DBR was set to 1230 nm to 1320 nm, and accordingly, the thicknesses of the first material layer (310) and the second material layer (320) were set to 87 nm and 103 nm, respectively, in a manner known to a person skilled in the art. A total of 20 stacked structures (300) were stacked. The capping layer (600) was formed with the same material and the same thickness as the first material layer (310).
[0134] All layers except the substrate (100) were manufactured by sequentially epitaxially growing from the substrate (100). The nucleation layer (200) was epitaxially grown at 500°C, which is lower than the other layers, and the other layers were epitaxially grown at 530°C.
[0135]
[0136] <Example 2>
[0137] The VCSEL (1) of Fig. 2 was manufactured.
[0138] Specifically, after manufacturing the DBR (10) of <Example 1>, each of the 2 layers was epitaxially grown from the capping layer (600) of the DBR (10) to manufacture the VCSEL (1).
[0139] An n-type doped GaAs layer with a thickness of 300 nm is used as the buffer layer (21), and an n-type doped Al layer with a thickness of 50 nm is used as the first grading layer (22a). x Ga 1-x As (where 0≤x≤0.4) layer, as the first cladding layer (23), Al with a thickness of 50 nm 0.4 Ga 0.6 As a layer, as a second grading layer (22b), n-type doped Al with a thickness of 50 nm x Ga 1-x As (where 0≤x≤0.4) layer, a GaAs layer with a thickness of 100 nm was used as the first waveguide (31a). As the active layer (41), an InGaAs quantum well and InAs quantum dots within the quantum well were grown to a thickness of 7 nm. As the second waveguide (31b), a GaAs layer with a thickness of 100 nm was used, and as the third grading layer (52a), a p-type doped Al with a thickness of 50 nm was used. x Ga 1-x As (where 0≤x≤0.4) layer, as the second cladding layer (53), p-type doped Al with a thickness of 50 nm 0.4 Ga 0.6 As a layer, as the fourth grading layer (52b), p-type doped Al with a thickness of 50 nm x Ga 1-x As (where 0≤x≤0.4) layer, a p-type doped GaAs layer with a thickness of 200 nm was used as the contact layer (51).
[0140]
[0141] <Comparative Example>
[0142] A DBR was manufactured in the same manner as in <Example>, except that GaAs was used as the third III-V semiconductor material and the thickness of the first material layer (310) was formed to be 90 nm.
[0143]
[0144] Figure 3a shows the results of observing the surface crystallinity of <Comparative Example>. Figure 3b shows the results of observing the surface crystallinity of <Example 1>.
[0145] Referring to Figures 3a and 3b, the surface crystallinity of <Comparative Example> and <Example 1> was observed using an optical microscope, and it can be confirmed that the surface crystal defects of <Example> were significantly reduced compared to <Comparative Example>.
[0146]
[0147] Figure 4a shows the surface roughness observation results of <Comparative Example>. Figure 4b shows the surface roughness observation results of <Example 1>. Table 1 shows the Root Mean Square surface roughness values of <Comparative Example> and <Example 1>.
[0148] <Comparative Example><Example 1> Root Mean Square Average Roughness Value (nm) 5.587 1.1211
[0149] Referring to FIGS. 4a, FIGS. 4b, and Table 1, it can be seen that the surface roughness of the DBR of <Example 1> is improved compared to the DBR of <Comparative Example>. Specifically, it can be seen that the <Comparative Example> exhibits a surface roughness value that is five times rougher than that of <Example 1>.
[0150] Figure 5a shows the results of the TDD (Threading Dislocation Defect) concentration analysis of <Comparative Example>. Figure 5b shows the results of the TDD concentration analysis of <Example 1>. Table 2 shows the TDD concentration values of <Comparative Example> and <Example 1>.
[0151] <Comparative Example><Example 1> TDD concentration (cm -2 )3.5 x 10 8 1.3 x 10 8
[0152] Referring to Figures 5a and 5b and Table 2, it can be seen that the DBR of <Example 1> has an improved TDD concentration compared to the DBR of <Comparative Example>. Specifically, it can be seen that the <Comparative Example> shows a TDD concentration three times higher than that of <Example 1>.
[0153] Figure 6 shows the reflectance measurement results of <Example 1>.
[0154] Referring to Fig. 6, it can be seen that the DBR of <Example 1> exhibits a reflectance of nearly 100% in the region close to the target wavelength of reflected light, which is 1230 nm to 1320 nm.
[0155]
[0156] Figure 7 shows the photoluminescence (PL) measurement results of <Example 2>.
[0157] Referring to Fig. 7, it can be seen that the VCSEL of <Example 2>, manufactured based on the DBR of <Example 1>, exhibits strong luminescence at around 1230 nm.
[0158]
[0159] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.
Claims
1. A substrate comprising silicon; and A laminated structure on the above substrate, comprising The above laminated structure is: First material layer; and It includes a second material layer on the first material layer, and The above first material layer comprises a compound of the following [Chemical Formula 1], and The above second material layer is a Distributed Bragg Reflector (DBR) comprising a compound of the following [Chemical Formula 2]: [Chemical Formula 1] InX 1 As [Chemical Formula 2] X 2 As X of the above [Chemical Formula 1] 1 It is Ga or Al, and The above X 1 When this is Ga, X of the above [Chemical Formula 2] 2 is Al, The above X 1 When this is Al, X of the above [Chemical Formula 2] 2 is Ga.
2. In Paragraph 1, A dispersed Bragg mirror satisfying the following [Equation 1]: [Equation 1] In the above [Equation 1], a1 is the atomic percent of In relative to the compound of [Chemical Formula 1], and a2 is X relative to the compound of [Chemical Formula 1]. 1 It is the atomic ratio of.
3. In Paragraph 1, It further includes a nucleation layer between the substrate and the stacked structure, The above nucleation layer is a dispersed Bragg reflector containing GaAs.
4. In Paragraph 3, A dispersion Bragg reflector in which the vertical thickness of the nucleation layer is smaller than the vertical thickness of the first material layer.
5. In Paragraph 3, A dispersion Bragg reflector in which the crystal direction of the nucleation layer and the crystal direction of the compound of [Chemical Formula 1] are the same.
6. In Paragraph 3, It further includes an intermediate layer between the substrate and the nucleation layer, The above intermediate layer is a dispersion Bragg reflector containing GaP.
7. In Paragraph 1, It further includes a capping layer on the above-mentioned laminated structure, The above laminated structure is interposed between the substrate and the capping layer, and The above capping layer is a dispersion Bragg reflector comprising the compound of [Chemical Formula 1].
8. In Paragraph 1, A dispersion Bragg reflector in which the vertical thickness of the second material layer is greater than the vertical thickness of the first material layer.
9. In Paragraph 1, A dispersion Bragg reflector in which the crystal direction of the compound of [Chemical Formula 1] and the crystal direction of the compound of [Chemical Formula 2] are the same.
10. A substrate comprising silicon; and The first material layers and the second material layers are alternately stacked in a vertical direction on the substrate, wherein Each of the above first material layers comprises a first III-V semiconductor material, and Each of the above second material layers comprises a second III-V semiconductor material, and The above-mentioned first III-V semiconductor material comprises a plurality of group III elements, and The above plurality of Group III elements include indium and a Group III element other than indium, and The above second III-V semiconductor material is a distributed Bragg reflector (DBR) comprising indium and a second III element different from the first III element.
11. In Paragraph 10, The second III-V semiconductor material is a dispersion Bragg reflector containing a group V element included in the first III-V semiconductor material.
12. In Paragraph 10, Dispersive Bragg mirror satisfying the following [Equation 2]: [Equation 2] In the above [Equation 2], n1 is the refractive index of the first III-V semiconductor material, and n2 is the refractive index of the above second III-V semiconductor material.
13. In Paragraph 10, A dispersed Bragg reflector in which the first material layers and the second material layers are each stacked in quantities of 5 to 50 on the substrate.
14. In Paragraph 10, The above substrate further comprises a nucleation layer, The above nucleation layer comprises a third III-V semiconductor material, and The above third III-V semiconductor material comprises the above first III element or the above second III element, and A dispersion Bragg reflector comprising a group V element included in the above-mentioned first III-V semiconductor material.
15. In Paragraph 14, The above substrate and the nucleation layer further include an intermediate layer between them, The above intermediate layer comprises a fourth III-V group semiconductor material, and The above-mentioned fourth III-V semiconductor material is a dispersion Bragg reflector containing a group V element different from the group V element contained in the above-mentioned third III-V semiconductor material.
16. In Paragraph 10, Dispersive Bragg mirror satisfying the following [Equation 3]: [Equation 3] In the above [Equation 3], a III is the atomic percent of the plurality of group III elements relative to the first group III-V semiconductor material, and a1 is the atomic percent of the indium relative to the first group III-V semiconductor material.
17. Dispersive Bragg mirror; A first doping structure on the above-mentioned dispersion Bragg reflector; An active layer on the first doping structure; and A second doping structure disposed on the active layer and doped with a different type from the first doping structure, comprising: The above dispersion Bragg reflector is: A substrate including silicon; and It includes a stacked structure on the above substrate, The above laminated structure is: First material layer; and It includes a second material layer on the first material layer, and The above first material layer comprises a compound of the following [Chemical Formula 1], and The above second material layer is a Vertical Cavity Surface Emitting Laser (VCSEL) comprising a compound of the following [Chemical Formula 2]: [Chemical Formula 1] InX 1 As [Chemical Formula 2] X 2 As X of the above [Chemical Formula 1] 1 It is Ga or Al, and The above X 1 When this is Ga, X of the above [Chemical Formula 2] 2 is Al, The above X 1 When this is Al, X of the above [Chemical Formula 2] 2 is Ga.
18. In Paragraph 17, A surface reflection laser in which the first doping structure is doped with n-type and the second doping structure is doped with p-type.
19. In Paragraph 17, The above active layer is: Quantum well containing InGaAs; and A surface reflection laser comprising a quantum dot containing InAs, disposed within the above-mentioned quantum well.
20. In Paragraph 17, The crystal direction of the second doping structure is the same as the crystal direction of the substrate, and the surface radiation laser.