Signal isolation circuit applying noise-robust feedback circuit

Abstract

Disclosed is a signal isolation circuit applying a noise-robust feedback circuit. Provided, according to one aspect of the present disclosure, is a signal isolation circuit for transmitting multiple signals from a first domain to a second domain, the signal isolation circuit comprising: a multi-signal encoder configured to encode a first signal, a second signal, and a third signal into a single fourth signal in the first domain; a transceiver configured to transfer the fourth signal from the first domain to the second domain; and a multi-signal decoder configured to decode the first signal, the second signal, and the third signal from the fourth signal in the second domain.

Description

Signal isolation circuit with a noise-robust feedback circuit

[0001] The present disclosure relates to a signal isolation circuit based on an on-off keying (OOK) signal transmission protocol.

[0002] The following description merely provides background information related to the present embodiment and does not constitute prior art.

[0003] A signal isolation circuit refers to a circuit that transmits and receives data signals between two electrically isolated systems and primarily operates at different GND potentials. Such signal isolation circuits require an isolated channel capable of electrical isolation, and generally utilize microtransformers, capacitors, magneto-resistors (giant magneto-resistors), or opto-electric devices.

[0004] OOK is a signal protocol that utilizes the digital state of a signal transmitted through an isolated channel. For example, when the digital signal is high, the signal is transmitted through the isolated channel, and when the digital signal is low, the signal is not transmitted through the isolated channel. In this case, the digital signal is modulated into a high-frequency signal at the transmitter and then transmitted through the isolated channel, and is restored at the receiver through demodulation.

[0005] In the case of digital isolators and gate drivers utilizing such isolation channels, there are many instances where two or more types of multiple signals need to be transmitted. For example, a smart gate driver that includes many protection circuit operation functions for switching elements is designed to transmit the results of each protection circuit operation through an isolation channel. In this case, to utilize the OOK signal transmission protocol, a transceiver circuit consisting of a transmitter, a receiver, and an isolation barrier is required. However, since conventional transceiver circuits can only transmit a single data signal in real time, the number of isolation channels required corresponds to the number of data signals to be transmitted. Furthermore, while multiple signals can be transmitted using serializers and deserializers, this method is unsuitable for applications such as gate drivers because it requires oscillators and complex logic. Furthermore, to minimize power consumption of the transceiver circuit, using an edge-triggered transceiver circuit requires using two isolated channels to transmit a single signal. While this method has the advantage of a simple circuit, it increases the chip area of ​​integrated circuits such as smart gate driving circuits or digital isolators that must process multiple signals, which can ultimately worsen product competitiveness due to increased manufacturing costs.

[0006] One objective of the present disclosure is to provide a signal isolation circuit capable of transmitting multiple signals through a single transceiver circuit comprising a single isolation channel.

[0007] One objective of the present disclosure is to provide a signal isolation circuit capable of preventing malfunction caused by fluctuations in power or ground when transmitting multiple signals to a single transceiver circuit.

[0008] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below.

[0009] According to one aspect of the present disclosure, a signal isolation circuit for transmitting multiple signals from a first domain to a second domain comprises: a multiple signal encoder configured to encode a first signal, a second signal, and a third signal in the first domain into a single fourth signal, generate a pulse train having different pulse widths in time intervals determined by a combination of the logic level of the first signal in the first domain and the logic level of the second signal, and adjust whether the pulse train is generated in at least two of the time intervals based on the third signal in the first domain; and a transceiver configured to transmit the fourth signal from the first domain to the second domain. The present invention provides a signal isolation circuit comprising a multi-signal decoder configured to decode the first signal, the second signal, and the third signal from the fourth signal in the second domain, wherein the logic levels of the first signal and the second signal in the second domain are switched based on the detection of a plurality of consecutive pulses having a corresponding pulse width in the fourth signal of the second domain, and the logic level of the third signal in the second domain is switched based on the time interval between the last pulse detected relative to the current time point among the pulses appearing in the fourth signal of the second domain and the current time point.

[0010] According to another aspect of the present disclosure, a multi-signal decoder for decoding a single input signal into multiple output signals comprises: a charge pump circuit that converts the input signal into a signal having a potential corresponding to the pulse width of each pulse appearing in the input signal; an analog-to-digital converter that compares the potential of the converted signal with a plurality of reference potentials to generate a plurality of one-hot encoded flag signals; a plurality of N-pulse detection circuits that detect a preset number of pulses from each of the plurality of flag signals to generate a plurality of detection signals; a plurality of latches that generate a first output signal and a second output signal based on the plurality of detection signals; and a pulse detection circuit that generates a third output signal based on the length of a time interval in which no pulse appears in the input signal.

[0011] In some embodiments, each of the plurality of N-pulse detection circuits may include a shift register configured to synchronously transmit data based on an input flag signal and comprising a plurality of flip-flops; and a multiplexer that selects the output of any one of the plurality of flip-flops as a detection signal corresponding to the input flag signal based on an externally applied selection signal. Each of the plurality of N-pulse detection circuits may further include a pulse detection circuit configured to switch the logic level of the output based on the length of the time interval during which no pulse appears in the input flag signal. The plurality of flip-flops may be reset based on a signal generated based on the selected detection signal among the first output signal and the second output signal, and the output of the pulse detection circuit.

[0012] In some embodiments, the analog-to-digital converter may be configured to generate a first flag signal based on the detection of a first pulse having a length longer than a first threshold pulse width in the input signal, generate a second flag signal based on the detection of a second pulse having a length shorter than the first threshold pulse width and longer than a second threshold pulse width in the input signal, and generate a third flag signal based on the detection of a third pulse having a length shorter than the second threshold pulse width and longer than a third threshold pulse width in the input signal. The plurality of N-pulse detection circuits may generate a first detection signal, a second detection signal, and a third detection signal from each of the first flag signal, the second flag signal, and the third flag signal. The plurality of latches include a first latch that receives the first detection signal as a set input or a reset input and generates the first output signal; and may include a second latch that receives the second detection signal and the third detection signal as either a set input or a reset input, respectively, and generates the second output signal. The second output signal may be generated based on a logical operation between the output of the second latch and the third output signal.

[0013] In some embodiments, the analog-to-digital converter may include a plurality of comparators that generate a thermometer code by comparing the potential of the converted signal with the plurality of reference potentials, respectively; and a masking circuit that converts the thermometer code into a plurality of one-hot encoded flag signals. The multi-signal decoder may further include a pulse detection circuit configured to generate the third output signal based on the least significant bit (LSB) of the thermometer code.

[0014] According to another aspect of the present disclosure, a multi-signal encoder for encoding multiple input signals into a single output signal comprises: a first pulse train generator that generates a second pulse signal including a series of second pulses based on the second input signal having a first logic level, wherein the first pulse train generator is selectively disabled based on the logic level of a third input signal, and each of the series of second pulses has a second pulse width; a second pulse train generator that generates a third pulse signal including a series of third pulses based on the second input signal having a second logic level different from the first logic level, wherein the second pulse train generator is selectively disabled based on the logic level of the third input signal, and each of the series of third pulses has a third pulse width different from the second pulse width; a third pulse train generator that generates a first pulse signal including a series of first pulses based on the first input signal having the first logic level, wherein each of the series of first pulses has a first pulse width different from the second pulse width and the third pulse width; A multi-signal encoder is provided, comprising a merging circuit that combines the first pulse signal, the second pulse signal, and the third pulse signal to generate the output signal.

[0015] In some embodiments, the number of consecutive first pulses appearing in the output signal is varied based on the length of the time interval during which the first input signal has the first logic level; the number of consecutive second pulses appearing in the output signal is varied based on the length of the time interval during which the first input signal has the second logic level and the second input signal has the first logic level; and the number of consecutive third pulses appearing in the output signal may be varied based on the length of the time interval during which the first input signal has the second logic level and the second input signal has the second logic level.

[0016] In some embodiments, the second pulse width may be smaller than the first pulse width, and the third pulse width may be smaller than the second pulse width.

[0017] In some embodiments, the merging circuit may include a logic gate that merges the second pulse signal and the third pulse signal; and a multiplexer that outputs one of the first pulse signal and the merged signal as the output signal based on the first pulse signal.

[0018] In some embodiments, the multi-signal encoder further includes an edge detection circuit that detects the rising edge and falling edge of the second input signal to generate an edge detection signal, and the merged signal may be masked by the edge detection signal.

[0019] In some embodiments, the first signal of the first domain is a short-circuit protection signal (SCP) output by a short-circuit protection circuit provided in the first domain, the second signal of the first domain is a pulse-width modulated signal based on a temperature detected from an external switch element, module, or PCB, and the third signal of the first domain may be a power supply-and-internal temperature sensing signal (RDY) indicating whether the power supply and internal temperature of the first domain are in a normal state.

[0020] According to an embodiment of the present disclosure, multiple signals can be transmitted through a single isolation channel with minimal chip area and minimal power consumption. While conventional signal isolation circuits require a maximum of four and a minimum of two transceiver circuits to transmit three types of multiple signals, the signal isolation circuit according to the present invention can transmit three types of multiple signals using only one transceiver circuit. Accordingly, the chip area and power consumption of the integrated circuit can be reduced, thereby achieving the effect of lowering manufacturing costs.

[0021] According to an embodiment of the present disclosure, when transmitting multiple signals to a single transceiver circuit, malfunctions caused by fluctuations in power or ground can be prevented. A multiple signal transmission technology robust to power noise can be applied to digital isolators or gate driving circuits in applications requiring high output current and / or high reliability. For example, it can be applied to automotive traction inverters or high-power power electronic systems with severe power noise to prevent malfunctions during multiple signal transmission and / or improve the reliability of the gate driving circuit.

[0022] The effects of the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below.

[0023] FIG. 1 is a schematic diagram showing the configuration of a signal isolation circuit according to one embodiment of the present disclosure.

[0024] FIG. 2 is a schematic diagram showing an example of the configuration of a multi-signal encoder according to a first embodiment of the present disclosure.

[0025] FIG. 3 is a timing diagram showing an example of the operation of a multi-signal encoder according to a first embodiment of the present disclosure.

[0026] FIG. 4 is a schematic diagram showing another example of the configuration of a multi-signal encoder according to the first embodiment of the present disclosure.

[0027] FIG. 5 is a timing diagram showing another example of the operation of a multi-signal encoder according to the first embodiment of the present disclosure.

[0028] FIG. 6 is a schematic diagram showing the configuration of a multi-signal decoder according to a first embodiment of the present disclosure.

[0029] FIG. 7 is a timing diagram showing the operation of a multi-signal decoder according to a first embodiment of the present disclosure.

[0030] FIG. 8 is a schematic diagram showing the configuration of an analog-to-digital converter according to one embodiment of the present disclosure.

[0031] FIG. 9 is a schematic diagram showing the configuration of a pulse detection circuit according to one embodiment of the present disclosure.

[0032] FIG. 10 is a waveform diagram showing the operation of a pulse detection circuit according to one embodiment of the present disclosure.

[0033] FIG. 11 is a timing diagram showing multiple input signals and multiple output signals of a signal isolation circuit according to a first embodiment of the present disclosure.

[0034] Figures 12 and 13 are referenced drawings to illustrate the effects of power noise or power bounce.

[0035] FIG. 14 is a schematic diagram showing the configuration of a multi-signal encoder according to a second embodiment of the present disclosure.

[0036] FIG. 15 is a timing diagram showing the operation of a multi-signal encoder according to a second embodiment of the present disclosure.

[0037] FIG. 16 is a schematic diagram showing the configuration of a multi-signal decoder according to a second embodiment of the present disclosure.

[0038] FIG. 17 is a timing diagram showing the operation of a multi-signal decoder according to a second embodiment of the present disclosure.

[0039] FIG. 18 is a schematic diagram showing the configuration of an N-pulse detection circuit according to a second embodiment of the present disclosure.

[0040] FIG. 19 is a timing diagram showing the operation of an N-pulse detection circuit according to a second embodiment of the present disclosure.

[0041] FIG. 20 is a timing diagram showing multiple input signals and multiple output signals of a signal isolation circuit according to a second embodiment of the present disclosure.

[0042] Some embodiments of the present disclosure are described in detail below with reference to exemplary drawings. It should be noted that in assigning reference numerals to the components of each drawing, the same components are given the same reference numeral whenever possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions could obscure the essence of the present disclosure, such detailed description is omitted.

[0043] In describing the components of the embodiments according to the present disclosure, symbols such as first, second, i), ii), a), b), etc., may be used. These symbols are intended only to distinguish the components from other components, and the essence, order, or sequence of the components is not limited by the symbols. When a part in the specification is described as 'comprising' or 'having' a component, this means that, unless explicitly stated otherwise, it does not exclude other components but may include additional components.

[0044] The detailed description set forth below, together with the accompanying drawings, is intended to describe exemplary embodiments of the present disclosure and is not intended to represent the only embodiment in which the present disclosure can be practiced.

[0045] FIG. 1 is a schematic diagram showing the configuration of a signal isolation circuit according to one embodiment of the present disclosure.

[0046] The signal isolation circuit (10) is a circuit that transmits multiple signals generated in a first domain to a second domain. The first domain and the second domain may be domains with different power levels or with separated power supplies. The signal isolation circuit (10) may include all or part of a multiple signal encoder (100), a transceiver (120), and a multiple signal decoder (140). The components illustrated in FIG. 1 represent functionally distinct elements, and at least one component may be implemented in a form that is integrated with each other in an actual physical environment.

[0047] The multi-signal encoder (100) encodes multiple input signals (SCP_HV, TSPWM_HV and RDY_HV) generated in the first domain into a single signal (TX_IN).

[0048] The encoded signal (TX_IN) is modulated into a high-frequency signal at the transmitter (122) of the transceiver (120), then transmitted to a second domain through an isolation channel (or isolation barrier) (124), and restored through demodulation at the receiver (126). The transmitter (122) and the receiver (126) can modulate or demodulate the signal based on an on-off keying (OOK) topology. Micro transformers, capacitors, magneto-resistors (giant magneto-resistors), or opto-electric devices may be used as the isolation channel (124), but are not limited to these examples, and the present disclosure does not limit them in a specific way.

[0049] The multi-signal decoder (140) decodes the demodulated signal (RX_OUT) into multiple output signals (SCP_LV, TSPWM_LV and RDY_LV).

[0050] For convenience of explanation, the present disclosure assumes that the first domain is a high voltage (HV) domain and the second domain is a low voltage (LV) domain, and that multiple input / output signals each include a short-circuit protection signal (SCP signal), an external temperature sensing signal (TSPWM signal), and a power supply and internal temperature sensing signal (RDY signal). The SCP signal is a short-circuit protection signal of the first domain and may be a signal output from a DESAT (DESATuration Sensing) protection circuit or an OCP (Over Current Protection) protection circuit. The TSPWM signal is a square wave signal representing the temperature of an external switch element, module, or PCB, and is generated using a pulse width modulation method in which the duty ratio of the signal varies according to the detected temperature. The RDY signal is a signal representing the power supply and internal temperature of the integrated circuit. For example, the RDY signal may have a logic high level when the power supply and internal temperature are suitable for the integrated circuit to operate, and the RDY signal may have a logic low level when the power supply or internal temperature is not suitable for the integrated circuit to operate.

[0051] However, it should be noted that the domain to which the signal isolation circuit (10) according to the present disclosure is applied and the type of input / output signal are not limited to these examples, and that the technical concept of the present disclosure may also be applied in cases where different types of signals are to be transmitted between different domains through a single transceiver.

[0052] FIG. 2 is a schematic diagram showing an example of the configuration of a multi-signal encoder according to a first embodiment of the present disclosure. FIG. 3 is a timing diagram showing an example of the operation of a multi-signal encoder according to a first embodiment of the present disclosure.

[0053] As illustrated in FIG. 2, a multi-signal encoder (100a) may include, in whole or in part, a pulse generator (200) that generates a first pulse signal (L_PW) based on an SCP signal (SCP_HV), a first pulse train generator (220) that generates a second pulse signal (M_PW) based on a combination of a TSPWM signal (TSPWM_HV) and an RDY signal (RDY_HV), a second pulse train generator (240) that generates a third pulse signal (S_PW) based on a combination of a TSPWM signal (TSPWM_HV) and an RDY signal (RDY_HV), and a merging circuit (260) that merges the first to third pulse signals (L_PW, M_PW, and S_PW) into a single signal (TX_IN).

[0054] The pulse generator (200) can be activated during a time interval in which the SCP signal (SCP_HV) has a first logic level (e.g., logic high). The first logic level may be, for example, a logic level output when a short circuit is detected. The first pulse signal (L_PW) may include one pulse during the time interval in which the SCP signal (SCP_HV) has the first logic level.

[0055] The first pulse train generator (220) can generate a second pulse signal (M_PW) by detecting the on-pulse of the TSPWM signal (TSPWM_HV). For example, the first pulse train generator (220) can be activated during a time interval in which the TSPWM signal (TSPWM_HV) has a first logic level (e.g., logic high). The number of pulses included in the second pulse signal (M_PW) can be varied according to the length of the on-pulse interval of the TSPWM signal (TSPWM_HV).

[0056] The second pulse train generator (240) can generate a third pulse signal (S_PW) by detecting the off-pulse of the TSPWM signal (TSPWM_HV). For example, the second pulse train generator (240) can be activated during a time interval in which the TSPWM signal (TSPWM_HV) has a second logic level (e.g., logic low). The number of pulses included in the third pulse signal (S_PW) can vary depending on the length of the off-pulse interval of the TSPWM signal (TSPWM_HV). The second pulse train generator (240) is implemented with the same circuit as the first pulse train generator (220) and can receive an inverted TSPWM signal (TSPWMB) to detect the off-pulse instead of the on-pulse.

[0057] The RDY signal (RDY_HV) can serve to control the transmission of the TSPWM signal (TSPWM_HV) to the second domain. To this end, the TSPWM signal (TSPWM_HV) and the inverted TSPWM signal (TSPWMB), which are input to the first pulse train generator (220) and the second pulse train generator (240), respectively, can be AND-gated by the RDY signal (RDY_HV). When the RDY signal (RDY_HV) is at a logic low level (i.e., when the supply power or internal temperature is not suitable for the integrated circuit to operate), the operation of the first pulse train generator (220) and the second pulse train generator (240) is deactivated, so that information regarding the TSPWM signal (TSPWM_HV) is not transmitted to the second domain. In another example, if the RDY signal (RDY_HV) is implemented to have a logic high level when the power supply or internal temperature is not appropriate, the TSPWM signal (TSPWM_HV) and the inverted TSPWM signal (TSPWMB) may be AND-gated by the inverted RDY signal (not shown).

[0058] Referring to FIG. 3, the first to third pulse signals (L_PW, M_PW, and S_PW) may each have different pulse widths. For example, the first pulse signal (L_PW) has a first pulse width (t) that is relatively longer compared to the other pulse signals (M_PW and S_PW). L _ PW It has ), and the second pulse signal (M_PW) has an intermediate level second pulse width (t M _ PW With ), the third pulse signal (S_PW) has a relatively short third pulse width (t) compared to the other pulse signals (L_PW and M_PW). S_ PW Can have ).

[0059] The merging circuit (260) can OR-gate the second pulse signal (M_PW) and the third pulse signal to merge them into a single fourth pulse signal (MS_PW), and can selectively output the first pulse signal (L_PW) or the fourth pulse signal (MS_PW) through a 2×1 multiplexer (MUX). The 2×1 MUX can receive the first pulse signal (L_PW) as a selection signal. That is, the signal (TX_IN) output by the 2×1 MUX can be selected based on the logic level of the first pulse signal (L_PW). For example, the 2×1 MUX can output the first pulse signal (L_PW) during the time interval when the first pulse signal (L_PW) has a logic high level, and output the fourth pulse signal (MS_PW) during the time interval when it has a logic low level. In another example, the merging circuit (260) may be implemented as a 3×1 MUX (not shown) that selectively outputs any one of the first to third pulse signals (L_PW, M_PW, and S_PW). In yet another example, the merging circuit (260) may generate an output signal (TX_IN) by OR gating the first pulse signal (L_PW) and the fourth pulse signal (MS_PW).

[0060] FIG. 4 is a schematic diagram showing another example of the configuration of a multi-signal encoder according to the first embodiment of the present disclosure. FIG. 5 is a timing diagram showing another example of the operation of a multi-signal encoder according to the first embodiment of the present disclosure.

[0061] The multi-signal encoder (100b) may further include an edge detection circuit (400) that detects the edge of a TSPWM signal (TSPWM_HV) and generates an edge detection signal (ED).

[0062] The edge detection circuit (400) may include a first detection circuit (402) that detects the on-pulse edge (typically, a rising edge) of the TSPWM signal (TSPWM_HV) and a second detection circuit (404) that detects the off-pulse edge (typically, a falling edge) of the TSPWM signal (TSPWM_HV). The first detection circuit (402) and the second detection circuit (404) are each triggered at the on-pulse edge and the off-pulse edge of the TSPWM signal (TSPWM_HV), and may generate a single pulse having a predetermined pulse width. The first detection circuit (402) and the second detection circuit (404) may be implemented, for example, as a combination of delay cells and logic gates, but are not limited to such examples.

[0063] The signals output by the first detection circuit (402) and the second detection circuit (404) can be NOR-gated to form an edge detection signal (ED). The edge detection signal (ED) can have a logic low level only for a certain period of time from the edge of the TSPWM signal (TSPWM_HV), and maintain a logic high level during the remaining time intervals.

[0064] FIG. 5 shows output signals (TX_IN) that can be generated when the multi-signal encoder (100a or 100b) includes and does not include an edge detection circuit (400), respectively. In this example, for the sake of brevity, the SCP signal (SCP_HV) is assumed to be fixed at a logic low level.

[0065] Referring to FIG. 5, depending on the length of the on-pulse interval or the off-pulse interval of the TSPWM signal (TSPWM_HV), a case may occur where the pulse of the second pulse signal (M_PW) and the pulse of the third pulse signal (S_PW) are connected to each other at the edge of the TSPWM signal (TSPWM_HV). For example, if the off-pulse edge of the TSPWM signal (TSPWM_HV) occurs before the pulse of the second pulse signal (M_PW) normally ends (or simultaneously with its end) and the pulse of the third pulse signal (S_PW) begins, the third pulse width (t S_PW Pulse width (t) longer than ) a + t S_PW A pulse having ) may appear in the fourth pulse signal (MS_PW) and the output signal (TX_IN). Similarly, if an on-pulse edge of the TSPWM signal (TSPWM_HV) occurs before (or simultaneously with) the pulse of the third pulse signal (S_PW) normally terminates and the pulse of the second pulse signal (M_PW) starts, the second pulse width (t M _ PW Pulse width (t) longer than ) b + t M _ PW A pulse having ) may appear in the fourth pulse signal (MS_PW) and the output signal (TX_IN). The pulse width (t) of the connected pulse a + t S_ PW or t b + t M _ PW ) is the first pulse width (t L _ PW If it is longer than ), the multi-signal decoder (140) described later incorrectly recognizes the edge timing of the TSPWM signal (TSPWM_LV) as the edge timing of the SCP signal (SCP_LV), thereby generating incorrect signals.

[0066] To prevent such malfunction, the multi-signal encoder (100b) can use an edge detection signal (ED) to clearly define the boundaries of the on-pulse and off-pulse intervals of the TSPWM signal (TSPWM_HV) in the fourth pulse signal (MS_PW) and the output signal (TX_IN). The multi-signal encoder (100b) can use the edge detection signal (ED) to mask the fourth pulse signal (MS_PW). For example, the fourth pulse signal (MS_PW) can be AND-gated with the edge detection signal (ED) and then input to a 2×1 MUX (264).

[0067] FIG. 6 is a schematic diagram showing the configuration of a multi-signal decoder according to a first embodiment of the present disclosure. FIG. 7 is a timing diagram showing the operation of a multi-signal decoder according to a first embodiment of the present disclosure.

[0068] As illustrated in FIG. 6, the multi-signal decoder (140a) may include all or part of a charge pump circuit (600), an analog-to-digital converter (ADC, 620), latches (640 and 660), and a pulse detection circuit (680).

[0069] The charge pump circuit (600) generates an analog signal (CP_OUT) whose potential varies according to the pulse width of the input signal (RX_OUT). For example, referring to FIG. 7, the longer the pulse width of an individual pulse within the input signal (RX_OUT), the higher the potential of the analog signal (CP_OUT). The structure of the charge pump circuit (600) may adopt the structure of a conventional charge pump circuit, and the present disclosure does not limit it to a specific structure.

[0070] The analog-to-digital converter (620) converts the analog signal (CP_OUT) output by the charge pump circuit (600) into multiple digital signals (SCP_Flag, TSPWM_On, TSPWM_Off, and RDY_Flag). The analog-to-digital converter (620) can generate multiple digital signals by comparing the analog signal (CP_OUT) with multiple reference voltages (VREF1, VREF2, and VREF3). A plurality of digital signals may include a first flag signal (SCP_Flag) indicating the edge timing (on-pulse or off-pulse edge timing) of the SCP signal (SCP_LV), a second flag signal (TSPWM_On) indicating the on-pulse edge timing of the TSPWM signal (TSPWM_LV), a third flag signal (TSPWM_Off) indicating the off-pulse edge timing of the TSPWM signal (TSPWM_LV), and a fourth flag signal (RDY_Flag) indicating both the on-pulse edge timing and the off-pulse edge timing of the TSPWM signal (TSPWM_LV). The first flag signal (SCP_Flag), the second flag signal (TSPWM_On), and the third flag signal (TSPWM_Off) may be represented by a one-hot code in which only one signal can have a logic high level in the same time interval.

[0071] FIG. 8 is a schematic diagram showing the configuration of an analog-to-digital converter according to one embodiment of the present disclosure.

[0072] Referring to FIG. 8, the analog-to-digital converter (620) may include a plurality of comparators (800, 802 and 804) and a masking circuit (820).

[0073] Comparators (800, 802, and 804) compare the analog signal (CP_OUT) with each reference voltage (VREF1, VREF2, and VREF3). For example, the first comparator (800) may compare the analog signal (CP_OUT) with the first reference voltage (VREF1), the second comparator (802) may compare the analog signal (CP_OUT) with the second reference voltage (VREF2), and the third comparator (804) may compare the analog signal (CP_OUT) with the third reference voltage (VREF3).

[0074] The first reference voltage (VREF1) is the first pulse width (t L _ PW It is set considering the length of ) and a predetermined margin, and the second reference voltage (VREF2) is the second pulse width (t M _ PW It is set considering the length of ) and a predetermined margin, and the third reference voltage (VREF3) is the third pulse width (t S_ PW It can be set considering the length of ) and a predetermined margin. For example, the first reference voltage (VREF1) may have the highest voltage, and the third reference voltage (VREF3) may have the lowest voltage.

[0075] The outputs (T1 to T3) of the comparators (800, 802 and 804) can be represented as thermometer codes. For example, when the analog signal (CP_OUT) has a voltage higher than the first reference voltage (VREF1), the outputs (T1 to T3) of the first to third comparators may all have a logic high level. For another example, when the analog signal (CP_OUT) has a voltage lower than the first reference voltage (VREF1) and higher than the second reference voltage (VREF2), the output (T1) of the first comparator may have a logic low level, and the outputs (T2 and T3) of the second and third comparators may all have a logic high level. As another example, if the analog signal (CP_OUT) has a voltage lower than the second reference voltage (VREF2) and higher than the third reference voltage (VREF3), the outputs (T1 and T2) of the first and second comparators may have a logic low level, and the output (T3) of the third comparator may have a logic high level. As another example, if the analog signal (CP_OUT) has a voltage lower than the third reference voltage (VREF3), the outputs (T1 to T3) of the first to third comparators may all have a logic low level. The comparators (800, 802 and 804) may be enabled on the falling edge of the input signal (RX_OUT). Each of the comparators (800, 802 and 804) may be reset by its output (T1 to T3).

[0076] The masking circuit (820) converts the outputs (T1 to T3) of the first to third comparators, which are represented by a 3-bit thermometer code, into the first to third flag signals (SCP_Flag, TSPWM_On, and TSPWM_Off), which are represented by a 3-bit one-hot code.

[0077] For example, the output (T1) of the first comparator can be used as is for the first flag signal (SCP_Flag), the second flag signal (TSPWM_On) is generated by NOR-gating the output (T1) of the first comparator, the inverted output (T2) of the second comparator, and the inverted output (T3) of the third comparator, and the third flag signal (TSPWM_Off) is generated by NOR-gating the output (T2) of the second comparator and the inverted output (T3) of the third comparator. Accordingly, as illustrated in FIG. 7, when a pulse with a pulse width longer than the first threshold pulse width appears in the input signal (RX_OUT), the first flag signal (SCP_Flag) has a logic high level, and when a pulse with a pulse width shorter than the first threshold pulse width and longer than the second threshold pulse width appears in the input signal (RX_OUT), the second flag signal (TSPWM_On) has a logic high level, and when a pulse with a pulse width shorter than the second threshold pulse width and longer than the third threshold pulse width appears in the input signal (RX_OUT), the third flag signal (TSPWM_Off) may have a logic high level. Here, the first to third threshold pulse widths may be values ​​determined according to the first to third reference voltages (VREF1, VREF2, and VREF3) and / or the step-up ratio of the charge pump circuit (600).

[0078] Meanwhile, the fourth flag signal (RDY_Flag) can be generated by OR-gating the second flag signal (TSPWM_On) and the third flag signal (TSPWM_Off). Accordingly, as shown in FIG. 7, when a pulse having a pulse width shorter than the first threshold pulse width and longer than the third threshold pulse width appears in the input signal (RX_OUT), the fourth flag signal (RDY_Flag) can have a logic high level.

[0079] Referring again to FIG. 6, each of the outputs of the analog-to-digital converter (620) can be input to any one of the first latch (640), the second latch (660), and the pulse detection circuit (680). For example, the first flag signal (SCP_Flag), corresponding to the most significant bit of the 3-bit one-hot codes generated by the masking circuit (820), can be input to the first latch (640), and the second flag signal (TSPWM_On) and the third flag signal (TSPWM_Off), corresponding to the remaining lower bits, can be input to the second latch (660). Additionally, the fourth flag signal (RDY_Flag), corresponding to the logical OR of the lower bits, can be input to the pulse detection circuit (680).

[0080] The first latch (640) can generate an SCP signal (SCP_LV) based on the timing indicated by the first flag signal (SCP_Flag). The first latch (640) may be an RS latch. The first latch (640) may receive the first flag signal (SCP_Flag) as a set input or a reset input. For example, referring to FIG. 7, the SCP signal (SCP_LV) may be set by the first flag signal (SCP_Flag) and reset by a reset signal (RESET) input from the outside.

[0081] The second latch (660) can generate a TSPWM signal (TSPWM_LV) based on timing indicated by the second flag signal (TSPWM_On) and the third flag signal (TSPWM_Off). The second latch (660) may be an RS latch. The second latch (660) may receive the second flag signal (TSPWM_On) and the third flag signal (TSPWM_Off) as a set input or a reset input, respectively. For example, referring to FIG. 7, the TSPWM signal (TSPWM_LV) may be set by the second flag signal (TSPWM_On) and reset by the third flag signal (TSPWM_Off). The TSPWM signal (TSPWM_LV) may be generated by AND gating the output signal of the second latch (660) and the RDY signal (RDY_LV).

[0082] The pulse detection circuit (680) can output an RDY signal (RDY_LV) having a logic low level if the fourth flag signal (RDY_Flag) is not applied for a period longer than a preset time.

[0083] FIG. 9 is a schematic diagram showing the configuration of a pulse detection circuit according to one embodiment of the present disclosure. FIG. 10 is a waveform diagram showing the operation of a pulse detection circuit according to one embodiment of the present disclosure.

[0084] Referring to FIG. 9, a pulse detection circuit (680) according to one embodiment of the present disclosure may include a switching element (SW), a capacitor (C), and a hysteresis comparator (900) in whole or in part. In normal conditions when the fourth flag signal (RDY_Flag) is not applied, the capacitor (C) is charged by a power source, and when the fourth flag signal (RDY_Flag) is applied, the capacitor (C) is discharged as the switching element (SW) is turned on. The hysteresis comparator (900) may output an RDY signal (RDY_LV) having a logic low level when the voltage (Vc) of the capacitor (C) increases above a predetermined threshold voltage. For example, referring to FIG. 10, when the fourth flag signal (RDY_Flag) is repeatedly applied at predetermined intervals, the capacitor (C) is repeatedly discharged so that the voltage (Vc) of the capacitor (C) can be maintained below the threshold voltage (Vth). On the other hand, if the fourth flag signal (RDY_Flag) is not applied for a longer period than the preset time (tc), the voltage (Vc) of the capacitor (C) may become greater than the threshold voltage (Vth).

[0085] FIG. 11 is a waveform diagram showing multiple input signals and multiple output signals of a signal isolation circuit according to a first embodiment of the present disclosure.

[0086] Referring to FIG. 11, assuming that the delay time caused by the operation of the transceiver (120) is negligibly small, the delay time (t) between the SCP signal (SCP_HV) of the first domain and the SCP signal (SCP_LV) of the second domain SCP ) is the first pulse width (t L _ PW Based on ), the delay time (t) between the on-pulse of the TSPWM signal (TSPWM_HV) of the first domain and the on-pulse of the TSPWM signal (TSPWM_LV) of the second domain TSPWM_On ) is the second pulse width (t M _PMBased on ), the delay time (t) between the off-pulse of the TSPWM signal (TSPWM_HV) of the first domain and the off-pulse of the TSPWM signal (TSPWM_LV) of the second domain TSPWM_Off ) is the third pulse width (t S_PM It can be confirmed that it is based on ).

[0087] Figures 12 and 13 are referenced drawings to illustrate the effects of power noise or power bounce.

[0088] In the process of encoding and decoding multiple signals by the signal isolation circuit (10), if noise is introduced into the supply power(s) or ground(s) or if a bounce occurs due to gate driving, the risk of the circuit malfunctioning may increase.

[0089] FIG. 12 illustrates an exemplary equivalent circuit of the driver section of a gate driver circuit providing an output current of several amperes (A). Parasitic inductance due to wire bonds or PCB patterns is inevitably present in the gate driver circuit. Wire bonds have a parasitic inductance of approximately 5 nH, and the parasitic inductance of PCB patterns can range from 2 nH to 20 nH depending on the design. FIG. 13 illustrates the supply bounce and ground bounce that may occur at the nodes (N1 and N2) of the circuit illustrated in FIG. 12.

[0090] Source current (I OUTH In the case of a P-type transistor (MP) providing ), it turns on when the input signal (IN) is high, and the source current (I OUTH ) flows from the power source (VDD2) to the output (OUTH). At this time, the source current (I OUTH Rate of change of ) over time (di outh / dt) is parasitic inductance (L par_VDD It causes voltage fluctuations in the power supply along with ). The amount of voltage fluctuation is L par_VDD ×diouth It can be expressed as / dt. Referring to FIG. 13, during the turn-off process of the P-type transistor (MP), the source current (I OUTH Rate of change of ) (di outh As / dt) increases rapidly, voltage fluctuations (i.e., power bounce) can become larger.

[0091] Similarly, sink current (I OUTL It is turned on when the input signal (IN) of the N-type transistor (MN) providing ) is low, and the sink current (I OUTL ) flows from the output (OUTL) to the ground (VEE2) side. At this time, the sink current (I OUTL Rate of change of ) over time (di outl / dt) is parasitic inductance (L par_VEE It causes voltage fluctuations at ground along with ). The amount of voltage fluctuation is L par_VEE ×di outl It can be expressed as / dt. Referring to FIG. 13, during the turn-off process of the N-type transistor (MN), the sink current (I OUTL Rate of change of ) (di outl As / dt) increases rapidly, voltage fluctuations (i.e., ground bounce) can become larger.

[0092] Due to such power bounce or ground bounce, incorrect pulses may occur during the encoding or decoding process of multiple signals. If these incorrectly generated pulses are not properly filtered, it may cause malfunction in the circuit receiving the multiple output signals (SCP_LV, TSPWM_LV, and RDY_LV). For example, the SCP signal (SCP_LV) in the second domain may have a logic high level even though the circuit is not actually short-circuited, or the RDY signal (RDY_LV) in the second domain may have a logic low level even though the power supply is normal. As another example, the TSPWM signal (TSPWM_HV) in the first domain may not be transmitted normally to the second domain.

[0093] In order to increase the reliability of the signal isolation circuit (10), encoding and / or decoding techniques that are robust against variations in power, such as noise or bounce, are required.

[0094] FIG. 14 is a schematic diagram showing the configuration of a multi-signal encoder according to a second embodiment of the present disclosure. FIG. 15 is a timing diagram showing the operation of a multi-signal encoder according to a second embodiment of the present disclosure.

[0095] Referring to FIG. 14, to ensure robustness against power fluctuations, the multi-signal encoder (100c) may include a third pulse train generator (132) instead of a pulse generator (200). Since the remaining components of the multi-signal encoder (100c), excluding the third pulse train generator (132) in FIG. 14, may be identical or corresponding to the components of the multi-signal encoder (100a or 100b) described above in FIG. 2 or FIG. 4, a redundant description thereof is omitted.

[0096] The third pulse train generator (132) can generate a first pulse signal (L_PW) based on the SCP signal (SCP_HV). The third pulse train generator (132) can be activated during a time interval in which the SCP signal (SCP_HV) has a first logic level (e.g., logic high). The first logic level may be, for example, a logic level output when a short circuit is detected. The number of pulses included in the first pulse signal (L_PW) may vary depending on the length of the time interval in which the SCP signal (SCP_HV) has the first logic level.

[0097] Referring to FIG. 15, the first pulse signal (L_PW) has a relatively long first pulse width (t) compared to other pulse signals (M_PW and S_PW). L_PW It can have ). The second pulse signal (M_PW) has an intermediate second pulse width (t M_PWWith ), the third pulse signal (S_PW) has a relatively short third pulse width (t) compared to the other pulse signals (L_PW and M_PW). S_PW Can have ).

[0098] That is, the multi-signal encoder (100a or 100b) illustrated in FIG. 2 or FIG. 4 generates a single pulse having a relatively long pulse width during the time interval when the SCP signal (SCP_HV) has a first logic level, whereas the multi-signal encoder (100c) illustrated in FIG. 14 can generate multiple pulses having a relatively long pulse width and repeating according to a certain period. Depending on the design specifications, the pulse widths (t) applied to the multi-signal encoder (100a or 100b) and the multi-signal encoder (100c) L_PW , t M_PW , and t S_PW ) can have different lengths.

[0099] Meanwhile, FIG. 14 illustrates an example in which a multi-signal encoder (100c) includes an edge detection circuit (400), but the present disclosure is not limited thereto. That is, depending on the embodiment, the edge detection circuit (400) in the multi-signal encoder (100c) may be omitted. In this case, the fourth pulse signal (MS_PW) may be input to a 2×1 MUX (264) without being AND-gated with the edge detection signal (ED).

[0100] FIG. 16 is a schematic diagram showing the configuration of a multi-signal decoder according to a second embodiment of the present disclosure. FIG. 17 is a timing diagram showing the operation of a multi-signal decoder according to a second embodiment of the present disclosure.

[0101] Referring to FIG. 16, to ensure robustness against power fluctuations, the multi-signal decoder (140b) may further include an N-pulse detection circuit (162). Since the remaining components of the multi-signal decoder (140b) excluding the N-pulse detection circuit (162) in FIG. 16 may be identical or corresponding to the components of the multi-signal decoder (140a) described in FIG. 6, a redundant description thereof is omitted.

[0102] The N-pulse detection circuit (162) can detect the Nth pulse (N is a natural number) in the digital signals (SCP_Flag, TSPWM_On, and TSPWM_Off) output by the analog-to-digital converter (620) and generate detection signals (SCP_DET, TSOn_DET, and TSOff_DET) that indicate the edge timing of multiple output signals (SCP_LV, TSPWM_LV, and RDY_LV). Here, N can be determined by an externally input selection signal (SEL).

[0103] The detection signals (SCP_DET, TSOn_DET and TSOff_DET) may include a first detection signal (SCP_DET) indicating the edge timing (on-pulse or off-pulse edge timing) of the SCP signal (SCP_LV), a second detection signal (TSOn_DET) indicating the on-pulse edge timing of the TSPWM signal (TSPWM_LV), and / or a third detection signal (TSOff_DET) indicating the off-pulse edge timing of the TSPWM signal (TSPWM_LV).

[0104] The detection signals (SCP_DET, TSOn_DET and TSOff_DET) can be input to the first latch (640) or the second latch (660). For example, the first detection signal (SCP_DET) can be input to the first latch (640), and the remaining second detection signal (TSOn_DET) and third detection signal (TSOff_DET) can be input to the second latch (660).

[0105] The first latch (640) can generate an SCP signal (SCP_LV) based on the timing indicated by the first detection signal (SCP_DET). The first latch (640) can receive the first detection signal (SCP_DET) as a set input or a reset input. For example, the SCP signal (SCP_LV) can be set by the first detection signal (SCP_DET) and reset by a reset signal (RESET) input from the outside.

[0106] The second latch (660) can generate a TSPWM signal (TSPWM_LV) based on the timing indicated by the second detection signal (TSOn_DET) and the third detection signal (TSOff_DET). The second latch (660) can receive the second detection signal (TSOn_DET) and the third detection signal (TSOff_DET) as a set input or a reset input, respectively. For example, the TSPWM signal (TSPWM_LV) can be set by the second detection signal (TSOn_DET) and reset by the third detection signal (TSOff_DET). The TSPWM signal (TSPWM_LV) can be generated by AND gating the output signal of the second latch (660) and the RDY signal (RDY_LV).

[0107] FIG. 17 shows examples of digital signals (SCP_Flag, TSPWM_On and TSPWM_Off) output by an analog-to-digital converter (620) when N is set to 2, detection signals (SCP_DET, TSOn_DET and TSOff_DET) output by an N-pulse detection circuit, and multiple output signals (SCP_LV, TSPWM_LV and RDY_LV) generated based thereon.

[0108] Referring to the first section (P171) of FIG. 17, the N-pulse detection circuit (162) can detect the second pulse of the first flag signal (SCP_Flag) and generate the first detection signal (SCP_DET). At the second pulse of the first flag signal (SCP_Flag), the first detection signal (SCP_DET) can transition to a logic high level, and accordingly, the SCP signal (SCP_LV) can be set.

[0109] Referring to the second section (P172), the N-pulse detection circuit (162) can detect the second pulse of the second flag signal (TSPWM_On) and generate a second detection signal (TSOn_DET). At the second pulse of the second flag signal (TSPWM_On), the second detection signal (TSOn_DET) can be transitioned to a logic high level, and accordingly, the TSPWM signal (TSPWM_LV) can be set.

[0110] Referring to the third section (P173), the N-pulse detection circuit (162) can detect the second pulse of the third flag signal (TSPWM_Off) and generate a third detection signal (TSOff_DET). At the second pulse of the third flag signal (TSPWM_Off), the third detection signal (TSOff_DET) can transition to a logic high level, and accordingly, the TSPWM signal (TSPWM_LV) can be reset.

[0111] That is, the multi-signal decoder (140a) illustrated in FIG. 6 sets or resets the multi-output signals (SCP_LV, TSPWM_LV, and RDY_LV) at the first pulse of the digital signals (SCP_Flag, TSPWM_On, and TSPWM_Off) output by the analog-to-digital converter (620), whereas the multi-signal decoder (140b) illustrated in FIG. 16 sets or resets the multi-output signals (SCP_LV, TSPWM_LV, and RDY_LV) at the Nth pulse of the digital signals (SCP_Flag, TSPWM_On, and TSPWM_Off). This prevents the multi-output signals (SCP_LV, TSPWM_LV, and RDY_LV) from being distorted due to glitches caused by noise or bounces in the digital signals (SCP_Flag, TSPWM_On, and TSPWM_Off). At this time, the number of pulses the N-pulse detection circuit (162) detects (i.e., the value of N) can be appropriately adjusted according to the level of power noise in the environment where the signal isolation circuit (10) is applied.

[0112] In some examples, a first pulse width (t) is given to the input signal (RX_OUT). L_PW To prevent the voltage level of the RDY signal (RDY_LV) from being incorrectly transitioned during the time interval in which pulse trains having ) appear, the output (T3) of the third comparator may be used as the fourth flag signal (RDY_Flag). That is, in all cases where a pulse with a pulse width longer than the third threshold pulse width appears in the input signal (RX_OUT), the fourth flag signal (RDY_Flag) may have a logic high level. In another example, if the threshold time (tc) of the pulse detection circuit (680) is designed to be sufficiently long, the structure of the analog-to-digital converter (620) shown in FIG. 8 may be applied as is to the multi-signal decoder (140b).

[0113] FIG. 18 is a schematic diagram showing the configuration of an N-pulse detection circuit according to one embodiment of the present disclosure. FIG. 19 is a timing diagram showing the operation of an N-pulse detection circuit according to one embodiment of the present disclosure.

[0114] FIG. 18 illustrates the configuration of an N-pulse detection circuit (162a) that detects the Nth pulse of a second flag signal (TSPWM_On) and generates a second detection signal (TSOn_DET).

[0115] The N-pulse detection circuit (162a) can be implemented as a serial-in to parallel-out shift register.

[0116] The N-pulse detection circuit (162a) may include M flip-flops (181–184) and an M×1 multiplexer (MUX) (185). The flip-flops (181–184) may be D-flip-flops. A power supply voltage (VDD), i.e., a logic high, is applied to the input (D) of the first flip-flop (181), and the output (D1–D2) of the preceding flip-flops (181–183) is applied to the input (D) of the remaining flip-flops (182–184), respectively. M-1 ) can be applied. The second flag signal (TSPWM_On) can be applied as the clock (CLK) of the flip-flops (181~184). The M×1 MUX (185) is the outputs (D1~D M One of the ) can be selectively read and output as a second detection signal (TSOn_DET). That is, by an externally input selection signal (SEL), the outputs (D1~D) of the flip-flops (181~184) M Any one of ) can be selected as the second detection signal (TSOn_DET).

[0117] The flip-flops (181–184) can be reset or cleared based on the second flag signal (TSPWM_On) and the TSPWM signal (TSPWM_LV) which is set by the second detection signal (TSOn_DET). For example, the output (CLRB_PRE) of the pulse detection circuit (186) for the second flag signal (TSPWM_On) and the signal obtained by inverting the TSPWM signal (TSPWM_LV) can be AND-gated and provided as a Clear Bar (CLRB) control signal for the flip-flops (181–184). The pulse detection circuit (186) may have the same or a corresponding structure as the pulse detection circuit (680) shown in FIG. 9, and the size of the capacitor (C) and the threshold voltage (V) have a threshold time suitable for the generation period of the second flag signal (TSPWM_On). th ) can be designed. The output (CLRB_PRE) of the pulse detection circuit (186) changes to a logic high level at the first pulse of the second flag signal (TSPWM_On), and the size of the capacitor (C) and the threshold voltage (V th If no pulse appears in the second flag signal (TSPWM_On) for a period longer than the threshold time determined by ), it may be changed to a logic low level.

[0118] Flip-flops (181–184) can synchronously transmit data based on the second flag signal (TSPWM_On). For every rising edge of the second flag signal (TSPWM_On), the input signal of the first flip-flop (181) (i.e., a fixed logic high value) can be moved serially along the flip-flops (181–184).

[0119] For example, at the first rising edge of the second flag signal (TSPWM_On), the reset of the flip-flops (181–184) is released, and subsequently, at the second rising edge, the output (D1) of the first flip-flop (181) can be changed to logic high. Subsequently, at the third rising edge of the second flag signal (TSPWM_On), the output (D1) of the first flip-flop (181) is transferred to the second flip-flop (182), and accordingly, the output (D2) of the second flip-flop (182) can be changed to logic high. Through this process, at the Nth rising edge, the logic high value is the output (D2) of the N-1th flip-flop. N-1 It reaches ), and accordingly, the second detection signal (TSOn_DET) can be changed to logic high. When the TSPWM signal (TSPWM_LV) is set by the second detection signal (TSOn_DET), the flip-flops (181~184) are switched back to the reset state, and accordingly, the outputs (D1~D) of all flip-flops (181~184) M ) can be changed to a logic row.

[0120] Meanwhile, if fewer than N pulses appear in the second flag signal (TSPWM_On) due to power supply noise or the like, the input of the first flip-flop (181) does not reach the N-1th flip-flop, so the second detection signal (TSOn_DET) can be maintained as logic low. The flip-flops (181–184) activated by this glitch signal are set to a pre-designed time (t) from the last pulse. th It can be switched to a reset state after ) has elapsed.

[0121] Meanwhile, although the above description has focused on an example in which the N-pulse detection circuit (162a) generates a second detection signal (TSOn_DET) based on a second flag signal (TSPWM_On), it will be clearly understood by a person skilled in the art that the same or corresponding technical concept can be applied to N-pulse detection circuits that generate a first detection signal (SCP_DET) or a third detection signal (TSOff_DET). For example, an N-pulse detection circuit that generates a first detection signal (SCP_DET) may receive a first flag signal (SCP_Flag) instead of a second flag signal (TSPWM_On) and may be reset based on an SCP signal (SCP_LV) instead of a TSPWM signal (TSPWM_LV). As another example, an N-pulse detection circuit that generates a third detection signal (TSOff_DET) receives the third flag signal (TSPWM_Off) instead of the second flag signal (TSPWM_On), and the uninverted TSPWM signal (TSPWM_LV) can be AND gated with the output (CLRB_PRE) of the pulse detection circuit (186). When an N-pulse detection circuit having the same circuit structure is used to generate the detection signals, the N-pulse detection circuit that generates the third detection signal (TSOff_DET) can receive an inverted TSPWM signal (not shown) instead of the TSPWM signal (TSPWM_LV).

[0122] FIG. 20 is a timing diagram showing multiple input signals and multiple output signals of a signal isolation circuit according to a second embodiment of the present disclosure.

[0123] FIG. 20 shows an example of multiple input signals (SCP_HV, TSPWM_HV and RDY_HV) input to a multiple signal encoder (100c), an encoded signal (TX_IN) output by the multiple signal encoder (100c), a demodulated signal (RX_OUT) input to a multiple signal decoder (140b), and multiple output signals (SCP_LV, TSPWM_LV and RDY_LV) output by the multiple signal decoder (140b).

[0124] The multi-signal encoder (100c) has different pulse widths (T) in time intervals determined by a combination of the logic level of the input SCP signal (SCP_HV) and the logic level of the input TSPWM signal (TSPWM_HV). L_PW , T M_PW , and T S_PW A pulse train having ) can be generated. For example, during the time interval when the SCP signal (SCP_HV) is logic high, a first pulse width (T) is given to the encoded signal (TX_IN). L_PW Pulse trains having ) may appear. Additionally or alternatively, during the time interval when the SCP signal (SCP_HV) is logic low and the TSPWM signal (TSPWM_HV) is logic high, a second pulse width (T) in the encoded signal (TX_IN) may appear. M_PW Pulse trains having ) may appear. Additionally or alternatively, during the time interval when the SCP signal (SCP_HV) is logic low and the TSPWM signal (TSPWM_HV) is logic low at the same time, a third pulse width (T) in the encoded signal (TX_IN) may appear. S_PW Pulse trains having ) may appear. The multi-signal encoder (100c) can adjust whether pulse trains occur in at least two of the aforementioned time intervals based on the RDY signal (RDY_HV). For example, when the RDY signal (RDY_HV) is logic low, the aforementioned second pulse width (T M_PW ) and / or the third pulse width (T S_PW The generation of pulse trains having ) can be disabled.

[0125] The multi-signal decoder (140d) can switch the logic level of the SCP signal (SCP_LV) and the logic level of the TSPWM signal (TSPWM_LV) based on the detection of a plurality of consecutive pulses having corresponding pulse widths in the demodulated signal (RX_OUT). For example, in the demodulated signal (RX_OUT), a first pulse width (T L_PWIf N consecutive pulses having ) are detected, the multi-signal decoder (140b) may output an SCP signal (SCP_LV) having a logic high level. Additionally or alternatively, a second pulse width (T) in the demodulated signal (RX_OUT) M_PW If N consecutive pulses having ) are detected, the multi-signal decoder (140d) can output a TSPWM signal (TSPWM_LV) having a logic high level. Additionally or alternatively, a third pulse width (T) in the demodulated signal (RX_OUT) S_PW When N consecutive pulses having ) are detected, the multi-signal decoder (140d) can output a TSPWM signal (TSPWM_LV) having a logic low level. The multi-signal decoder (140d) can switch the logic level of the RDY signal (RDY_LV) based on the time interval between the last detected pulse and the current time point among the pulses appearing in the demodulated signal (RX_OUT). For example, if a pre-designed threshold time (tc) has elapsed from the falling edge timing of the last pulse, the multi-signal decoder (140d) can output an RDY signal (RDY_LV) having a logic low level.

[0126] Meanwhile, assuming that the delay time caused by the operation of the transceiver (120) is negligibly small, the delay time (t) between the SCP signal (SCP_HV) of the first domain and the SCP signal (SCP_LV) of the second domain SCP ) is the pulse width (t) of the first pulse signal (L_PW). L_PW It can be based on ), period, and the number of times N to detect a pulse. The delay time (t) between the on-pulse of the TSPWM signal (TSPWM_HV) of the first domain and the on-pulse of the TSPWM signal (TSPWM_LV) of the second domain. TSPWM_On ) is the pulse width (t) of the second pulse signal (M_PW). M_PMIt can be based on ), period, and detection count N. The delay time (t) between the off-pulse of the TSPWM signal (TSPWM_HV) of the first domain and the off-pulse of the TSPWM signal (TSPWM_LV) of the second domain. TSPWM_Off ) is the pulse width (t) of the third pulse signal (S_PW). S_PM It can be based on ), period, and detection count N.

[0127] As described above, a multi-signal encoder (100a, 100b, or 100c) according to various embodiments of the present disclosure encodes an output signal (TX_IN) by assigning different pulse widths to the on-pulse of the SCP signal (SCP_HV), the TSPWM signal (TSPWM_HV), and the off-pulse of the TSPWM signal (TSPWM_HV), respectively, and a multi-signal decoder (140a or 140b) can decode the SCP signal (SCP_LV) and the TSPWM signal (TSPWM_LV) from the input signal (RX_OUT) based on the pulse widths of individual pulses of the input signal (RX_OUT). Additionally, the multi-signal encoder (100a, 100b, or 100c) may transmit a series of pulses (e.g., pulses having a pulse width specified for the on-pulse and off-pulse of the TSPWM signal (TSPWM_HV)) to the second domain side when the RDY signal of the first domain is at a first logic level (e.g., logic high), and may not transmit the corresponding pulse train to the second domain side when the RDY signal is at a second logic level (e.g., logic low). The multi-signal decoder (140a or 140b) may recognize whether the corresponding pulse trains are received and decode the RDY signal (RDY_LV).

[0128] Various embodiments of the systems and techniques described in this specification may be realized in analog electronic circuits, digital electronic circuits, integrated circuits, FPGAs (field programmable gate arrays), ASICs (application specific integrated circuits), and / or combinations thereof.

[0129] The above description is merely an illustrative explanation of the technical concept of the present embodiment, and a person skilled in the art to which the present embodiment belongs would be able to make various modifications and variations within the scope of the essential characteristics of the present embodiment. Accordingly, the present embodiments are intended to explain, not limit, the technical concept of the present embodiment, and the scope of the technical concept of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present embodiment.

[0130]

[0131] CROSS-REFERENCE TO RELATED APPLICATION

[0132] This patent application claims priority to Korean patent application No. 10-2025-0007307, filed on January 17, 2025, the entirety of which is incorporated herein by reference.

Claims

As a signal isolation circuit for transmitting multiple signals from a first domain to a second domain, A multi-signal encoder configured to encode a first signal, a second signal, and a third signal into a single fourth signal in the first domain, generate pulse trains having different pulse widths in time intervals determined by a combination of the logic level of the first signal in the first domain and the logic level of the second signal, and adjust whether the pulse trains are generated in at least two of the time intervals based on the third signal in the first domain; A transceiver configured to transmit the fourth signal from the first domain to the second domain; and A signal isolation circuit comprising a multi-signal decoder configured to decode the first signal, the second signal, and the third signal from the fourth signal in the second domain, and to switch the logic levels of the first signal and the second signal in the second domain based on the detection of a plurality of consecutive pulses having a corresponding pulse width in the fourth signal of the second domain, and to switch the logic level of the third signal in the second domain based on the time interval between the last pulse detected relative to the current time point among the pulses appearing in the fourth signal of the second domain and the current time point. In paragraph 1, The above multi-signal decoder is, A charge pump circuit that converts the fourth signal of the second domain into a signal having a potential corresponding to the pulse width; and An analog-to-digital converter that generates a plurality of one-hot encoded flag signals by comparing the potential of the converted signal with a plurality of reference potentials; A plurality of N-pulse detection circuits that detect a preset number of pulses from each of the plurality of flag signals and generate a plurality of detection signals; and A signal isolation circuit comprising a plurality of latches that generate a first signal of the second domain and a second signal based on the plurality of detection signals. In paragraph 2, Each of the above plurality of N-pulse detection circuits is, A shift register comprising a plurality of flip-flops and configured to synchronously transmit data based on an input flag signal; and A signal isolation circuit comprising a multiplexer that selects the output of any one of the plurality of flip-flops as a detection signal corresponding to the input flag signal based on a selection signal applied from the outside. In paragraph 3, Each of the above plurality of N-pulse detection circuits is, It further includes a pulse detection circuit configured to switch the logic level of the output based on the length of the time interval during which no pulse appears in the input flag signal, and The plurality of flip-flops are a signal isolation circuit that is reset based on a signal generated based on a first signal of the second domain and a selected detection signal among the second signals, and the output of the pulse detection circuit. In paragraph 2, The above analog-to-digital converter is, A first flag signal is generated based on the detection of a first pulse having a length longer than the first threshold pulse width in the fourth signal of the second domain, and A second flag signal is generated based on the detection of a second pulse having a length shorter than the first threshold pulse width and longer than the second threshold pulse width in the fourth signal of the second domain, and A signal isolation circuit configured to generate a third flag signal based on the detection of a third pulse having a length shorter than the second threshold pulse width and longer than the third threshold pulse width in the fourth signal of the second domain. In paragraph 5, The plurality of N-pulse detection circuits above generate a first detection signal, a second detection signal, and a third detection signal from each of the first flag signal, the second flag signal, and the third flag signal, respectively, and The above plurality of latches are, A first latch that receives the first detection signal as a set input or a reset input and generates a first signal of the second domain; and A second latch that receives the second detection signal and the third detection signal as either a set input or a reset input, respectively, and generates a second signal of the second domain. A signal isolation circuit including In paragraph 6, The second signal of the second domain is a signal isolation circuit generated based on a logical operation between the output of the second latch and the third signal of the second domain. In paragraph 2, The above analog-to-digital converter is, A plurality of comparators that generate a thermometer code by comparing the potential of the converted signal with the plurality of reference potentials, respectively; and It includes a masking circuit that converts the above thermometer code into a plurality of one-hot encoded flag signals, and The signal isolation circuit further comprises a pulse detection circuit configured to generate a third signal of the second domain based on the least significant bit (LSB) of the thermometer code. In paragraph 1, The above multi-signal encoder is, A first pulse train generator that generates a second pulse signal including a series of second pulses based on the second signal of the first domain having a first logic level, and is selectively deactivated based on the logic level of the third signal of the first domain; A second pulse train generator that generates a third pulse signal including a series of third pulses based on the fact that the second signal of the first domain has a second logic level different from the first logic level, and is selectively deactivated based on the logic level of the third signal of the first domain; A third pulse train generator that generates a first pulse signal including consecutive first pulses based on the first signal of the first domain having the first logic level; and A merging circuit that generates a fourth signal of the first domain by merging the first pulse signal, the second pulse signal, and the third pulse signal, wherein Each of the above consecutive second pulses has a second pulse width, Each of the above consecutive third pulses has a third pulse width different from the second pulse width. Each of the above consecutive first pulses is a signal isolation circuit having a first pulse width different from the second pulse width and the third pulse width. In Paragraph 9, The number of consecutive first pulses appearing in the fourth signal of the first domain is varied based on the length of the time interval in which the first signal of the first domain has the first logic level, and The number of consecutive second pulses appearing in the fourth signal of the first domain is varied based on the length of the time interval during which the first signal of the first domain has the second logic level and the second signal of the first domain has the first logic level, and A signal isolation circuit in which the number of consecutive third pulses appearing in the fourth signal of the first domain is varied based on the length of a time interval in which the first signal of the first domain has the second logic level and the second signal of the first domain has the second logic level. In Paragraph 9, The second pulse width is smaller than the first pulse width, and The above third pulse width is smaller than the above second pulse width, a signal isolation circuit. In Paragraph 9, The above-mentioned merger circuit is, A logic gate that merges the second pulse signal and the third pulse signal; and A multiplexer that outputs one of the first pulse signal and the merged signal as a fourth signal of the first domain based on the first pulse signal. A signal isolation circuit including In Paragraph 9, The multi-signal encoder further includes an edge detection circuit that detects the rising edge and falling edge of the second signal of the first domain and generates an edge detection signal. The above merged signal is a signal isolation circuit that is masked by the above edge detection signal. In paragraph 1, The first signal of the first domain is a short-circuit protection signal (SCP) output by a short-circuit protection circuit provided in the first domain, and The second signal of the first domain is a pulse-width modulated signal based on the temperature detected from an external switch element, module, or PCB, and A signal isolation circuit in which the third signal of the first domain is a Power Supply + Internal Temperature Sensing Signal (RDY) indicating whether the power supply and internal temperature of the first domain are in a normal state. As a multi-signal decoder that decodes a single input signal into multiple output signals, A charge pump circuit that converts the above input signal into a signal having a potential corresponding to the pulse width of each pulse appearing in the above input signal; and An analog-to-digital converter that generates a plurality of one-hot encoded flag signals by comparing the potential of the converted signal with a plurality of reference potentials; A plurality of N-pulse detection circuits that detect a preset number of pulses from each of the plurality of flag signals and generate a plurality of detection signals; and A plurality of latches that generate a first output signal and a second output signal based on the plurality of detection signals above; and A multi-signal decoder comprising a pulse detection circuit that generates a third output signal based on the length of the time interval during which no pulse appears in the input signal. In paragraph 15, Each of the above plurality of N-pulse detection circuits is, A shift register comprising a plurality of flip-flops and configured to synchronously transmit data based on an input flag signal; and A multiplexer comprising a multiplexer that selects the output of one of the plurality of flip-flops as a detection signal corresponding to the input flag signal based on an externally applied selection signal. In Paragraph 16, Each of the above plurality of N-pulse detection circuits is, It further includes a pulse detection circuit configured to switch the logic level of the output based on the length of the time interval during which no pulse appears in the input flag signal, and A multi-signal decoder in which the plurality of flip-flops are reset based on a signal generated based on a selected detection signal among a first output signal and a second output signal, and the output of the pulse detection circuit. In paragraph 15, The above analog-to-digital converter is, Based on the detection of a first pulse having a length longer than a first threshold pulse width in the above input signal, a first flag signal is generated, and Based on the detection of a second pulse having a length shorter than the first threshold pulse width and longer than the second threshold pulse width in the above input signal, a second flag signal is generated, and In the above input signal, it is configured to generate a third flag signal based on the detection of a third pulse having a length shorter than the second threshold pulse width and longer than the third threshold pulse width, and The plurality of N-pulse detection circuits above generate a first detection signal, a second detection signal, and a third detection signal from each of the first flag signal, the second flag signal, and the third flag signal, respectively, and The above plurality of latches are, A first latch that receives the first detection signal as a set input or a reset input and generates the first output signal; and A second latch that receives the second detection signal and the third detection signal as either a set input or a reset input, respectively, and generates the second output signal. A multi-signal decoder including As a multi-signal encoder that encodes multiple input signals into a single output signal, A first pulse train generator that generates a second pulse signal including a series of second pulses based on the second input signal having a first logic level, and is selectively deactivated based on the logic level of a third input signal; A second pulse train generator that generates a third pulse signal including a series of third pulses based on the fact that the second input signal has a second logic level different from the first logic level, and is selectively deactivated based on the logic level of the third input signal; A third pulse train generator that generates a first pulse signal including a series of first pulses based on the first input signal having the first logic level; and A merging circuit that generates the output signal by merging the first pulse signal, the second pulse signal, and the third pulse signal, wherein Each of the above consecutive second pulses has a second pulse width. Each of the above consecutive third pulses has a third pulse width different from the second pulse width, Each of the above consecutive first pulses is a multi-signal encoder having a first pulse width different from the second pulse width and the third pulse width. In Paragraph 19, The number of consecutive first pulses appearing in the output signal is varied based on the length of the time interval in which the first input signal has the first logic level, and The number of consecutive second pulses appearing in the output signal is varied based on the length of the time interval during which the first input signal has the second logic level and the second input signal has the first logic level, and A multi-signal encoder in which the number of consecutive third pulses appearing in the output signal is varied based on the length of a time interval in which the first input signal has the second logic level and the second input signal has the second logic level.

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