Method for detecting mounting failure of IC having pin arrangement structure for preventing SMT failure of probe card IC

Abstract

According to a method for detecting a mounting failure of an IC having a pin arrangement structure for preventing an SMT failure of a probe card IC, proposed in the present invention, it is possible to decrease a failure rate due to efficient pin arrangement of an IC (PMIC, switch IC) of a probe card bank system, and detect a short-circuit and an open mounting failure of the IC of the probe card bank system.

Description

Method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card

[0001] The present invention relates to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing Surface Mounted Technology (SMT) defects of an IC (Integrated Circuit) for a probe card, and more specifically, to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card that enables a reduction in the defect rate due to efficient pin arrangement of the IC (PMIC, switch IC) of a probe card bank system and the detection of mounting defects such as shorts and open circuits of the IC of the probe card bank system.

[0002] The content described in this section merely provides background information regarding an embodiment of the present invention and does not constitute prior art.

[0003]

[0004] Probe cards utilize various types of PMICs (Power Management ICs) and switch ICs. Recently, as the storage bits of NVM (Non-Volatile Memory) memory cells have increased, the voltage or current used increases as the storage size grows. Consequently, test equipment must also test with high voltage and high current depending on the NVM memory cell structure, and as microfabrication progresses, the number of DUTs (Device Under Test) is also steadily increasing.

[0005]

[0006] In addition, to configure a probe card that supports a large number of DUTs and high voltage and high current, hundreds of switch ICs and PMICs are typically mounted on the probe card PCB. Furthermore, since the number of interface signals used to control the numerous switch ICs and PMICs mounted on the probe card PCB is also large, these signals are often shared in bank units. At this time, if a defect occurs where an I / F signal shorts with another signal or power line during component mounting on the probe card PCB, widespread control failures occur, and there was a problem in detecting which component among the hundreds of switch ICs or PMICs had a mounting defect. Korean Patent Publication No. 10-2006-0094203 is disclosed as a prior art document.

[0007]

[0008] The aforementioned background technology is technical information that the inventor possessed for the derivation of the present invention or acquired during the process of deriving the present invention, and it cannot be considered as publicly known technology disclosed to the general public prior to the filing of the present invention.

[0009] The present invention is proposed to solve the aforementioned problems of previously proposed methods, and comprises a probe card bank system for electrical performance testing of Device Under Test (DUT) connected to a probe card, wherein ICs to which pin placement rules for power and communication interfaces (I / F) are applied to minimize defects such as open or short pins of input / output (I / O) or power pins are mounted on a probe card PCB, and a step of detecting a corresponding faulty IC by controlling the direction of the I / O pins of the ICs through a specific sequence after applying power to the ICs mounted on the probe card PCB of the probe card bank system, thereby enabling a reduction in the defect rate due to efficient pin placement of the ICs (PMIC, switch IC) of the probe card bank system and the detection of mounting defects such as shorts and open pins of the ICs of the probe card bank system. The purpose is to provide a method for detecting installation defects.

[0010]

[0011] In addition, another objective of the present invention is to provide a method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card, which reduces the failure rate due to efficient pin placement of the IC (PMIC, switch IC) of the probe card bank system and further improves the reliability of the probe card bank system by reducing the probability of power down of the probe card bank system by detecting mounting defects such as shorts and opens of the IC of the probe card bank system.

[0012]

[0013] In addition, another objective of the present invention is to provide a method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of a probe card IC, which enables the detection of a mounting defect IC (PMIC, switch IC) in a probe card bank system, thereby clearly identifying the defect location, reducing the number of times the defective IC is remounted and reducing the opportunity for defect transmission during the remounting process, and also enables the reduction of manufacturing time and cost, and thereby further improves the manufacturing efficiency of the probe card bank system.

[0014]

[0015] However, the technical problem that the present invention aims to solve is not limited to the technical problem described above, and other technical problems may exist.

[0016] A method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card according to the features of the present invention for achieving the above-mentioned purpose,

[0017] A method for detecting mounting defects of an IC having a pin placement structure for preventing Surface Mounted Technology (SMT) defects of an Integrated Circuit (IC) for a probe card,

[0018] (1) A probe card bank system for electrical performance testing of Device Under Test (DUT) connected to a probe card, wherein ICs are mounted on a probe card PCB with pin placement rules for power and communication interfaces (I / F) applied to minimize defects such as open or short pins of input / output (I / O) or power pins; and

[0019] (2) The mounting defect detection unit is characterized by the step of detecting the corresponding mounting defect IC (11) by controlling the direction of the input / output (I / O) pins of the ICs through a specific sequence after applying power to the ICs mounted on the probe card PCB of the probe card bank system through step (1).

[0020]

[0021] Preferably, in step (1),

[0022] ICs are mounted on a probe card PCB to which pin placement rules for power and communication interfaces (I / F) are applied to minimize defects such as open or short circuits in input / output (I / O) or power pins, and for each of the said ICs, according to the applied pin placement rules, the portion immediately adjacent to the power pin and the communication pin may be arranged as a channel pin to prevent system down in the event of a short circuit in the power pin or the communication pin.

[0023]

[0024] More preferably, each of the above ICs is,

[0025] The parts immediately adjacent to the power pin and the communication pin are arranged as channel pins so that even if adjacent pins are short-circuited, communication failure or the OCP (Over Current Protect) function of the utility power equipment does not occur.

[0026]

[0027] More preferably, each of the above ICs is,

[0028] Pin placement rules for power and communication interfaces (I / F) are applied to minimize defects caused by open or short circuits in the output (I / O), but the structure may be configured such that corner pins of the package are channel (CH) pins, which are not essential operation pins for communication or power, so that IC operation is not affected even if they are damaged by external shock or degradation.

[0029]

[0030] Preferably, in step (2),

[0031] (2-1) A step in which, in order for the mounting defect detection unit to detect the initial operation and mounting defects of ICs mounted on the probe card PCB of the probe card bank system, all pins of the communication pins and channel pins, excluding the power pin, are maintained in a High-Z state after power is applied;

[0032] (2-2) After step (2-1) above, a step of determining the state of an output pin among each pin by applying CLK to the CLK pin of the communication pin in a High-Z state for a set period of time; and

[0033] (2-3) After the above step (2-2), the process may include a step of detecting the point where a short circuit occurred by inputting a specific CMD (Command) to the IC while the channel pin state is High-Z state and arbitrarily changing the individual channel pin state of the IC belonging to the bank.

[0034]

[0035] More preferably, in step (2-3),

[0036] It is possible to control all ICs connected to the probe card bank system through a specific CMD, and it is also possible to function to change the state of each pin individually for each IC.

[0037]

[0038] Even more preferably, in the above step (2-3),

[0039] Among all ICs connected to the above probe card bank system, the process of detecting the IC with a mounting defect and re-mounting only the defective IC can be further performed.

[0040] According to the method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card proposed in the present invention, in a probe card bank system for electrical performance testing of DUTs (Device Under Test) connected to a probe card, the method comprises the steps of: mounting ICs on a probe card PCB to which pin placement rules for power and communication interfaces (I / F) are applied to minimize defects such as open or short pins of input / output (I / O) or power pins; and detecting a corresponding mounting defect IC by controlling the direction of the input / output (I / O) pins of the ICs through a specific sequence after applying power to the ICs mounted on the probe card PCB of the probe card bank system. By configuring the method, it is possible to reduce the defect rate due to efficient pin placement of ICs (PMIC, switch IC) in the probe card bank system and to detect mounting defects such as short and open pins of the ICs in the probe card bank system.

[0041]

[0042] In addition, according to the method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card according to the present invention, the failure rate is reduced due to the efficient pin placement of the IC (PMIC, switch IC) of the probe card bank system, and by detecting mounting defects such as short and open circuits of the IC of the probe card bank system, the reliability of the probe card bank system can be further improved by reducing the probability of power down of the probe card bank system.

[0043]

[0044] In addition, according to the method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card of the present invention, by enabling the detection of a mounting defect IC (PMIC, switch IC) in a probe card bank system, the defect location is clearly identified, thereby reducing the number of times the defective IC is remounted and reducing the opportunity for defect transmission during the remounting process, and also enabling a reduction in manufacturing time and cost, and thereby further improving the manufacturing efficiency of the probe card bank system.

[0045]

[0046] Furthermore, the various and beneficial advantages and effects of the present invention are not limited to those described above and may be more easily understood in the process of explaining specific embodiments of the present invention.

[0047] FIG. 1 is a diagram illustrating the schematic configuration of a probe card bank system applied to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention.

[0048] FIG. 2 is a diagram illustrating the configuration of a probe card bank system and a mounting defect detection unit applied to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention.

[0049] FIG. 3 is a diagram illustrating the pin arrangement configuration of a conventional switch IC of a probe card bank system applied to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention.

[0050] FIG. 4 is a drawing illustrating the pin arrangement configuration of an IC in a probe card bank system applied to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention.

[0051] FIG. 5 is a flowchart illustrating a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention.

[0052] FIG. 6 is a diagram illustrating the detailed flow of step S120 in a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention.

[0053] <Explanation of Symbols>

[0054] 10: Probe Card Bank System

[0055] 11: IC (Integrated Circuit)

[0056] 20: Installation defect detection unit

[0057] S110: A step in which ICs to which pin placement rules for power and communication interfaces are applied to minimize open or short circuits of input / output or power pins in a probe card bank system are mounted on a probe card PCB.

[0058] S120: A step of detecting a corresponding defective IC by applying power to ICs mounted on the probe card PCB of a probe card bank system and controlling the direction of the ICs' input / output pins through a specific sequence.

[0059] S121: A step of maintaining all communication pins and channel pins, excluding the power pin, in a High-Z state after power is applied.

[0060] S122: A step of determining the state of an output pin among each pin by applying CLK to the CLK pin of the communication pin for a set period of time while in a High-Z state.

[0061] S123: A step of detecting the point where a short circuit defect occurred by inputting a specific CMD to the IC while the channel pin state is High-Z and arbitrarily changing the state of the individual channel pin of the IC belonging to the bank.

[0062] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement the invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0063]

[0064] Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "indirectly connected" with other elements interposed between them. Furthermore, when a part is described as "including" a component, this means that, unless specifically stated otherwise, it does not exclude other components but rather allows for the inclusion of additional components; it should be understood that this does not preclude the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0065]

[0066] The following examples are detailed descriptions to aid in understanding the present invention and are not intended to limit the scope of the present invention. Accordingly, inventions within the same scope that perform the same function as the present invention will also fall within the scope of the present invention.

[0067]

[0068] In addition, each component, process, procedure, or method included in each embodiment of the present invention may be shared within a scope that is not technically contradictory to one another.

[0069]

[0070] FIG. 1 is a schematic diagram illustrating the configuration of a probe card bank system applied to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating the configuration of a probe card bank system and a mounting defect detection unit applied to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention. As shown in FIG. 1 and FIG. 2, respectively, the probe card bank system (10) has a power source line for power supply for the operation of an IC (PMIC, switch IC) (11) that performs a DUT test, and various voltages and high currents may be required depending on the type of test of the DUT. In addition, as the number of DUTs increases and the process develops, the bank configuration of the power source becomes more complex. In particular, if a short circuit occurs in the power line, the probe card bank system (10) may experience an overcurrent and the entire system may be shut down.

[0071]

[0072] In addition, the interface line requires various pins such as CLK and RESETB to control the IC (11), and if even one of the pins is shorted to a power or communication pin, there is a possibility that all ICs (11) connected to the bank will be unable to operate, and in this case, since all ICs (11) will not operate, it becomes very difficult to detect the fault point.

[0073]

[0074] FIG. 3 is a diagram illustrating the pin arrangement configuration of a conventional switch IC in a probe card bank system applied to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating the pin arrangement configuration of an IC in a probe card bank system applied to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention. As shown in FIG. 3, the pin arrangement configuration of the conventional switch IC includes power pins of ICs AVDD, VDDIO, AVSS, and VSSIO, communication pins of ICs RSTB, ID, CLK, and DATA, and CH pins which are channel pins of the IC. In this case, in the existing arrangement, the power pins and communication-related pins are all placed adjacently, so if a short circuit occurs in the power pin or communication pin, the OCP (Over Current Protection) function of the utility power equipment is activated, increasing the likelihood of the probe card bank system going down. In addition, as shown in FIG. 3, corner pins of packages such as A1, A5, E1, and E5 are vulnerable to external shock and deterioration, so an open circuit may occur. Accordingly, if an open circuit occurs because the power or communication pin is placed in the corner pin, the IC (11) may not operate, making verification very difficult.

[0075]

[0076] FIG. 4 shows the pin arrangement configuration of an IC in a probe card bank system applied to a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention, and illustrates an IC pin arrangement configuration that prevents system downtime in the event of an open circuit or short circuit. As shown in FIG. 4, the pin arrangement structure of the IC (11) is configured such that the parts immediately adjacent to the power pins and communication pins are arranged as channel pins to prevent system downtime in the event of a short circuit in the power pins or communication pins, so that even if adjacent pins short-circuit each other, communication failure or the OCP (Over Current Protect) function of the utility power equipment does not occur. In particular, even in the case of corner pins such as A1, A5, E1, and E5 in FIG. 4, essential operating pins of the IC (11), such as channel (CH) pins, are not arranged so that the operation of the IC (11) is not affected even if they are damaged by external shock or deterioration.

[0077]

[0078] FIG. 5 is a diagram illustrating the flow of a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention, and FIG. 6 is a diagram illustrating the detailed flow of step S120 in a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention. As shown in FIG. 5, a method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention may be implemented by including the step (S110) of mounting ICs on a probe card PCB to which pin arrangement rules for power and communication interfaces are applied to minimize defects such as open or short pins of input / output or power pins in a probe card bank system, and the step (S120) of detecting a corresponding mounting defect IC by controlling the direction of the input / output pins of the ICs through a specific sequence after applying power to the ICs mounted on the probe card PCB of the probe card bank system.

[0079]

[0080] In step S110, in a probe card bank system (10) for electrical performance testing of DUTs (Device Under Test) connected to a probe card, ICs (11) to which pin placement rules for power and communication interfaces (I / F) are applied to minimize failures of open or short pins of input / output (I / O) or power pins are mounted on the probe card PCB. In this step S110, ICs (11) are mounted on a probe card PCB to which pin placement rules for power and communication interfaces (I / F) are applied to minimize failures such as open or short pins of input / output (I / O) or power pins. Each IC (11) may be configured with a channel pin in the part immediately adjacent to the power pin and the communication pin, as shown in FIG. 4, according to the applied pin placement rules, to prevent system down when a short occurs in the power pin or the communication pin. Here, each IC (11) may be configured with a channel pin in the part immediately adjacent to the power pin and the communication pin so that even if adjacent pins are shorted, communication failure or the OCP (Over Current Protect) function of the utility power equipment does not occur. In other words, when a short circuit occurs at a power pin or communication pin, the OCP function of the utility power equipment is activated, which reduces the possibility of the system going down.

[0081]

[0082] Additionally, each IC (11) applies pin placement rules for power and communication interfaces (I / F) to minimize open or short failures of outputs (I / O), but the corner pins of the package may be structured such that channel (CH) pins, which are not essential operating pins for communication or power, are placed therein so that even if they are damaged by external shock or degradation as shown in FIG. 4, the IC operation is not affected. That is, by placing CH pins at the corner pins of the package, the impact on the overall operation of the IC can be minimized even if an open occurs due to external shock and degradation.

[0083]

[0084] In step S120, the mounting defect detection unit (20) applies power to the ICs (11) mounted on the probe card PCB of the probe card bank system (10) through step S110, and then controls the direction of the input / output (I / O) pins of the ICs (11) through a specific sequence to detect the corresponding mounting defect IC (11). As shown in FIG. 6, this step S120 may include a step (S121) of maintaining all pins of the communication pins and channel pins, excluding the power pin, in a High-Z state after applying power; a step (S122) of determining the state of the output pin among each pin by applying a CLK to the CLK pin of the communication pin for a set period of time while in the High-Z state; and a step (S123) of detecting the point where a short circuit defect occurred by inputting a specific CMD to the IC while the channel pin state is High-Z state to arbitrarily change the state of the individual channel pin of the IC belonging to the bank. Here, High-Z refers to a state where the pin or circuit is electrically disconnected from the outside and has high impedance.

[0085]

[0086] In step S121, the mounting defect detection unit (20) maintains all pins of the communication pins and channel pins, excluding the power pin, in a High-Z state after power is applied in order to detect the initial operation and mounting defects of the ICs (11) mounted on the probe card PCB of the probe card bank system (10). In this step S121, by maintaining all pins of the communication pins and channel pins, excluding the power pin, in a High-Z state after power is applied, it is possible to function to prevent the OCP situation of the utility power equipment in an unexpected short circuit situation and thus prevent the system down state.

[0087]

[0088] In step S122, after step S121, a CLK is applied to the CLK pin of the communication pin in a High-Z state for a set period of time to determine the state of the output pin among each pin. In this step S122, when the IC (11) does not operate while power is applied, the High-Z state can be maintained to detect a defective IC (11) or pin.

[0089]

[0090] In step S123, after step S122, when the channel pin state is High-Z, a specific CMD (Command) is input to the IC (11) to arbitrarily change the individual channel pin state of the IC (11) belonging to the bank, thereby detecting the point where a short circuit defect occurred. In this step S123, all ICs (11) connected to the probe card bank system (10) can be controlled through the specific CMD, and the function can be to change the pin state for each IC (11) individually.

[0091]

[0092] Additionally, in step S123, among all ICs (11) connected to the probe card bank system (10), the IC (11) that has a mounting defect can be detected, and the process of re-mounting only the defective IC (11) can be further performed. That is, after making the pins of all ICs (11) connected to the probe card bank system (10) into a High-Z state, the pin status of the IC (11) is individually checked to detect the IC (11) that has a mounting defect, and the process of re-mounting only the defective IC (11) can be performed to improve the probe card manufacturing efficiency.

[0093]

[0094] Thus, in a probe card bank system (10) for electrical performance testing of DUTs (Device Under Test) connected to a probe card, a method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card comprises: (1) a step of mounting ICs (11) on a probe card PCB to which pin placement rules for power and communication interfaces (I / F) are applied to minimize defects such as open or short pins of input / output (I / O) or power pins; and (2) a step in which a mounting defect detection unit (20) detects a corresponding mounting defect IC (11) by controlling the direction of the input / output (I / O) pins of the ICs (11) through a specific sequence after applying power to the ICs (11) mounted on the probe card PCB of the probe card bank system (10) through step (1). In addition to improving the reliability of the probe card system by reducing the failure rate due to the efficient pin placement of the switch IC and reducing the probability of power down in the probe card bank system, the manufacturing efficiency of the probe card system is improved through a method for detecting defective ICs (PMIC, switch IC), and by clearly identifying the defect point, it is possible to reduce the number of times defective ICs need to be remounted and reduce the opportunity for defect transmission during the remounting process, thereby enabling the reduction of manufacturing time and cost.

[0095]

[0096] As described above, a method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card according to an embodiment of the present invention comprises: a step of mounting ICs on a probe card PCB to which pin placement rules for power and communication interfaces (I / F) are applied to minimize defects such as open or short pins of input / output (I / O) or power pins in a probe card bank system for electrical performance testing of DUTs (Device Under Test) connected to a probe card; and a step of detecting a corresponding mounting defect IC by controlling the direction of the input / output (I / O) pins of the ICs through a specific sequence after applying power to the ICs mounted on the probe card PCB of the probe card bank system, thereby enabling a reduction in the defect rate due to efficient pin placement of ICs (PMIC, switch IC) in the probe card bank system and enabling the detection of mounting defects such as shorts and open pins of the ICs in the probe card bank system. In particular, by enabling the reduction of the failure rate due to the efficient pin placement of ICs (PMIC, switch IC) in the probe card bank system and the detection of mounting defects such as shorts and open circuits in the ICs of the probe card bank system, the reliability of the probe card bank system can be further improved by reducing the probability of power down in the probe card bank system. Additionally, by enabling the detection of mounting defect ICs (PMIC, switch IC) in the probe card bank system, the location of the defect can be clearly identified, thereby reducing the number of times defective ICs need to be remounted and reducing the opportunity for defect transmission during the remounting process. Furthermore, it is possible to shorten manufacturing time and reduce costs, and consequently, further improve the manufacturing efficiency of the probe card bank system.

[0097]

[0098] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0099]

[0100] The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present invention.

Claims

1. A method for detecting mounting defects of an IC having a pin arrangement structure for preventing Surface Mounted Technology (SMT) defects of an IC (Integrated Circuit) for a probe card, wherein (1) In a probe card bank system (10) for electrical performance testing of DUTs (Device Under Test) connected to a probe card, ICs (11) to which pin placement rules for power and communication interfaces (I / F) are applied to minimize failures of open or short pins of input / output (I / O) or power pins are mounted on a probe card PCB; and (2) A method for detecting mounting defects of an IC having a pin arrangement structure for preventing SMT defects of an IC for a probe card, characterized in that the mounting defect detection unit (20) applies power to the ICs (11) mounted on the probe card PCB of the probe card bank system (10) through step (1) and then controls the direction of the input / output (I / O) pins of the ICs (11) through a specific sequence to detect the corresponding mounting defect IC (11).

2. In paragraph 1, in step (1), A method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card, wherein ICs (11) are mounted on a probe card PCB to which pin placement rules for power and communication interfaces (I / F) are applied to minimize defects of open or short pins of input / output (I / O) or power pins, and each of the ICs (11) is configured such that, according to the applied pin placement rules, the portion immediately adjacent to the power pin and the communication pin is configured as a channel pin to prevent system down when a short occurs in the power pin or the communication pin.

3. In paragraph 2, each of the above ICs (11) is, A method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card, characterized in that the portion immediately adjacent to the power pin and the communication pin is arranged as a channel pin so that even if adjacent pins are short-circuited, communication failure or the OCP (Over Current Protect) function of the utility power equipment does not occur.

4. In paragraph 2, each of the above ICs (11) is, A method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card, characterized by applying pin placement rules for power and communication interfaces (I / F) to minimize open or short defects of output (I / O), wherein, in the case of corner pins of a package, channel (CH) pins are placed instead of essential operation pins for communication or power so as not to affect IC operation even if they are damaged by external shock or degradation.

5. In any one of paragraphs 1 to 4, in step (2), (2-1) A step in which the mounting defect detection unit (20) maintains all pins of the communication pins and channel pins, excluding the power pin, in a High-Z state after power is applied, so that the mounting defect detection unit (20) detects the initial operation and mounting defects of the ICs (11) mounted on the probe card PCB of the probe card bank system (10); (2-2) After step (2-1) above, a step of determining the state of an output pin among each pin by applying CLK to the CLK pin of the communication pin in a High-Z state for a set period of time; and (2-3) A method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card, characterized by including the step of detecting a point where a short circuit has occurred by inputting a specific CMD (Command) to the IC (11) in a High-Z state after the above step (2-2), thereby arbitrarily changing the individual channel pin state of the IC (11) belonging to the bank.

6. In paragraph 5, in step (2-3) above, A method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card, characterized by being able to control all ICs (11) connected to a probe card bank system (10) through a specific CMD and individually change the state of each pin for each IC (11).

7. In paragraph 6, in step (2-3) above, A method for detecting mounting defects of an IC having a pin placement structure for preventing SMT defects of an IC for a probe card, characterized by detecting an IC (11) that has a mounting defect among all ICs (11) connected to the probe card bank system (10) and further performing a process of re-mounting only the defective IC (11).

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