Display device and electronic device comprising same

Abstract

A display device according to one embodiment comprises: a display panel including a display area and a non-display area and including a plurality of pixels disposed in the display area; an emission driver, which applies emission control signals to the plurality of pixels and is disposed in the non-display area provided on a first side of the display area; and a scan driver, which applies scan signals to the display panel and is disposed in the non-display area provided on a second side facing the first side of the display area, wherein the respective pixels include a first sub-pixel for emitting light of a first wavelength and a second sub-pixel for emitting light of a second wavelength that is shorter than the first wavelength, and the emission driver can include a first emission driver for applying a first emission control signal to the first sub-pixel and a second emission driver for applying a second emission control signal to the second sub-pixel.

Description

Display device and electronic device including the same

[0001] Embodiments of the present invention relate to a display device and an electronic device including the same.

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. For example, display devices are integrated into various electronic devices and used as the display screens for these devices. In response to this, various types of display devices, including light-emitting displays, are being developed.

[0003] The problem that the present invention aims to solve is to provide a display device having a symmetrical non-display area and an electronic device including the same.

[0004] The problems of the present invention are not limited to the technical problems mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0005] A display device according to one embodiment includes a display panel comprising a display area and a non-display area and a plurality of pixels disposed in the display area, a light-emitting driving unit disposed in the non-display area of ​​the first side of the display area and applying light-emitting control signals to the plurality of pixels, and a scan driving unit disposed in the non-display area of ​​the second side facing the first side of the display area and applying scan signals to the display panel, wherein the plurality of pixels include a first sub-pixel emitting light of a first wavelength and a second sub-pixel emitting light of a second wavelength shorter than the first wavelength, and the light-emitting driving unit may include a first light-emitting driver that applies a first light-emitting control signal to the first sub-pixel and a second light-emitting driver that applies a second light-emitting control signal to the second sub-pixel.

[0006] The above scan driving unit may include a write scan signal driver, an initialization scan signal, a control scan signal driver, and a bias scan signal driver, each connected to a subpixel to apply a scan signal.

[0007] The above non-display area surrounds the above display area, and the first side and the second side may have a shape that is symmetrical to each other.

[0008] Among the above-mentioned write scan signal driver, initialization scan signal, control scan signal driver, and bias scan signal driver, they can be arranged in order of smallest size close to the display area.

[0009] The above-mentioned write scan signal driver, initialization scan signal, control scan signal driver, and bias scan signal driver can be arranged close to the display area in that order.

[0010] The light-emitting driving unit and the scan driving unit may be symmetrical to each other with respect to the display area.

[0011] The above display device may include a first light-emitting control line connecting the first light-emitting driver and the first subpixel to each other, and a second light-emitting control line connecting the second light-emitting driver and the second subpixel to each other.

[0012] The display device may further include a write scan line connecting the write scan signal driver and the first subpixel and the second subpixel, a control scan line connecting the initialization scan signal and control scan signal driver and the first subpixel and the second subpixel, an initialization scan line connecting the initialization scan signal and control scan signal driver and the first subpixel and the second subpixel, and a bias scan line connecting the bias scan signal driver and the first subpixel and the second subpixel.

[0013] The plurality of pixels further include a third subpixel that emits light of a third wavelength shorter than light of the first wavelength, and the second light-emitting driver can apply a second light-emitting control signal to the third subpixel.

[0014] The second light emission control line further connects the second light emission driver and the third subpixel, the write scan line further connects the write scan signal driver and the third subpixel, the control scan line further connects the initialization scan signal and the control scan signal driver and the third subpixel, the initialization scan line further connects the initialization scan signal and the control scan signal driver and the third subpixel, and the bias scan line further connects the bias scan signal driver and the third subpixel.

[0015] The above display area may be square or circular.

[0016] The first subpixel includes a first pixel circuit and a first light-emitting element electrically connected to the first pixel circuit, the second subpixel includes a second pixel circuit and a second light-emitting element electrically connected to the second pixel circuit, and the third subpixel may include a third pixel circuit and a third light-emitting element electrically connected to the third pixel circuit.

[0017] A display device according to another embodiment includes a display panel comprising a display area and a non-display area, and a first subpixel and a second subpixel disposed in the display area; a light-emitting driving unit comprising a first light-emitting driver that applies a first light-emitting control signal to the first subpixel and a second light-emitting driver that applies a second light-emitting control signal to the second subpixel; and a scan driving unit comprising a write scan signal driver, an initialization scan signal, a control scan signal driver, and a bias scan signal driver that are respectively connected to the first subpixel and the second subpixel to apply a scan signal, wherein the light-emitting driving unit and the scan driving unit may be disposed symmetrically in the non-display area centered on the display panel.

[0018] The above-mentioned write scan signal driver, initialization scan signal, control scan signal driver, and bias scan signal driver can be arranged close to the display area in that order.

[0019] The above display device may further include a first light-emitting control line connecting the first light-emitting driver and the first subpixel to each other, and a second light-emitting control line connecting the second light-emitting driver and the second subpixel to each other.

[0020] The display device may further include a write scan line connecting the write scan signal driver and the first subpixel and the second subpixel, a control scan line connecting the initialization scan signal and control scan signal driver and the first subpixel and the second subpixel, an initialization scan line connecting the initialization scan signal and control scan signal driver and the first subpixel and the second subpixel, and a bias scan line connecting the bias scan signal driver and the first subpixel and the second subpixel.

[0021] The first light emission control line extends in the first direction from the display area and is electrically connected to the first subpixel, and the second light emission control line extends in the first direction from the display area and can be electrically connected to the second subpixel.

[0022] The first subpixel above includes a first light-emitting element that emits light of a first wavelength, and the second subpixel above may include a second light-emitting element that emits light of a second wavelength shorter than the first wavelength.

[0023] An electronic device according to another embodiment may include a display device, a window disposed on the display device, and a lower cover disposed on the lower part of the display device.

[0024] The electronic device may further include a battery that supplies power to the display device and is disposed in the space of the lower cover, and a middle frame disposed between the window and the lower cover.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] According to a display device and an electronic device including the same according to one embodiment, a first light-emitting driver connected to a first subpixel and a second light-emitting driver connected to a second subpixel are placed on the first side of a non-display area, and a plurality of scan drivers are placed on the second side of a non-display area, thereby allowing non-display areas on the first side and the second side to be symmetrically formed.

[0027] Additionally, the display device according to the embodiments can reduce wiring resistance by placing a small-sized driver close to the display area.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification.

[0029] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0030] FIG. 2 is a plan view showing a display panel according to one embodiment.

[0031] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0032] Figure 4 is a graph showing the external quantum efficiency and current density range of a subpixel in one embodiment.

[0033] FIG. 5 is an equivalent circuit diagram showing a light emission control signal and a subpixel according to one embodiment.

[0034] FIG. 6 is a waveform diagram showing driving signals of a subpixel according to one embodiment.

[0035] FIG. 7 is an enlarged view of regions A and B of FIG. 2 according to one embodiment.

[0036] FIG. 8 is an enlarged view of regions A and B of FIG. 2 according to another embodiment.

[0037] FIG. 9 is an enlarged view of regions A and B of FIG. 2 according to another embodiment.

[0038] FIG. 10 is a plan view showing a display panel according to another embodiment.

[0039] FIG. 11 is an enlarged view of regions A', B', C', and D' of FIG. 10 according to one embodiment.

[0040] FIG. 12 is an enlarged view of regions A', B', C', and D' of FIG. 10 according to another embodiment.

[0041] FIG. 13 is a layout diagram showing a light-emitting element layer of a display panel according to one embodiment.

[0042] FIG. 14 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line X1-X1' of FIG. 13.

[0043] FIG. 15 is a cross-sectional view showing the A2 region of FIG. 14 in detail.

[0044] FIG. 16 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the X2-X2' line and the X3-X3' line of FIG. 13.

[0045] FIG. 17 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to the line X1-X1' of FIG. 13.

[0046] FIGS. 18 and 19 are exemplary drawings showing a smart watch including a display device according to one embodiment.

[0047] FIG. 20 is an exploded view of a smart watch including a display device according to one embodiment.

[0048] FIG. 21 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment.

[0049] FIG. 22 is an exemplary drawing showing a head-mounted display device including a display device according to one embodiment.

[0050] FIG. 23 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0051] FIG. 24 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0052] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0053] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and the invention is not limited to the depicted details.

[0054] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0055] Specific embodiments will be described below with reference to the attached drawings.

[0056] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0057] Referring to FIG. 1, the display device (10) is a device for displaying video or still images and can be used as a display screen in various electronic devices such as mobile phones, smartphones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, UMPCs (Ultra Mobile PCs), as well as in televisions, laptops, monitors, billboards, and Internet of Things (IOT) devices. Additionally, the display device (10) can be included in other electronic devices such as virtual reality (VR) devices or augmented reality (AR) devices and used to display images in said electronic devices. In one embodiment, the electronic device including the display device (10) may further include a display device housing in which the display device (10) is housed, and / or a case or cover for protecting said display device (10).

[0058] In one embodiment, the display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, the display device (10) has been described with a focus on being a micro light-emitting display device, but the present invention is not limited thereto. Meanwhile, for convenience of explanation, a micro light-emitting diode has been described as a light-emitting element below.

[0059] The display device (10) may include a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply circuit (500).

[0060] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded or at a right angle. The planar shape of the display panel (100) is not limited to a rectangular shape and may be formed in other polygonal shapes, circular shapes, or elliptical shapes. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved portions formed at the left and right ends that have a constant curvature or a changing curvature. In one embodiment, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0061] The display panel (100) may include a main area (MA) and a sub-area (SBA).

[0062] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) that is a surrounding area of ​​the display area (DA). The display area (DA) may include pixels that display an image. Each pixel may include a plurality of subpixels. For example, each pixel may include a first subpixel emitting light of a first color (or first light), a second subpixel emitting light of a second color (or second light), and a third subpixel emitting light of a third color (or third light), but the embodiments of the present specification are not limited thereto.

[0063] A sub-region (SBA) may protrude from one side of a main region (MA) in a second direction (DR2) (for example, the vertical direction of the display panel (100)). Although FIG. 1 illustrates a sub-region (SBA) unfolded, the sub-region (SBA) may be bent, in which case it may be placed on the lower surface of the display panel (100). When the sub-region (SBA) is bent, it may overlap with the main region (MA) in a third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be placed in the sub-region (SBA).

[0064] The display driving circuit (250) can generate signals and voltages to drive the display panel (100). The display driving circuit (250) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) may be attached to the circuit board (300) using a COF (chip on film) method.

[0065] A circuit board (300) can be attached to one end of a sub-region (SBA) of a display panel (100). As a result, the circuit board (300) can be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0066] The power supply circuit (500) can generate panel driving voltages according to the power voltage supplied from the outside. The power supply circuit (500) can be formed as an integrated circuit (IC) and attached to the circuit board (300) in a COF manner.

[0067] FIG. 2 is a plan view showing a display panel according to one embodiment. FIG. 2 illustrates a sub-region (SBA) that is unfolded without being bent.

[0068] Referring to FIGS. 1 and FIGS. 2, the display panel (100) may include a main area (MA) and a sub-area (SBA).

[0069] The main area (MA) may include a display area (DA) that displays images and a non-display area (NDA) that is the surrounding area of ​​the display area (DA). The display area (DA) may occupy most of the main area (MA). The display area (DA) may be positioned in the center of the main area (MA).

[0070] A display area (DA) includes pixels (PX) for displaying an image, and each pixel (PX) may include a plurality of subpixels (SPX). A pixel (PX) may be defined as a group of subpixels of the smallest unit capable of expressing a white gradation.

[0071] The non-display area (NDA) may be placed adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0072] The light-emitting driver (EDC) and the scan driver (SDC) may be placed in the non-display area (NDA). The light-emitting driver (EDC) may be placed on one side (e.g., the left side) of the display panel (100), and the scan driver (SDC) may be placed on the other side (e.g., the right side) of the display panel, but are not limited thereto. Each of the light-emitting driver (EDC) and the scan driver (SDC) may be electrically connected to the display driver circuit (250) through scan fan-out lines. The light-emitting driver (EDC) receives a drive control signal (ECS) from the display driver circuit (250), and the scan driver (SDC) receives a scan control signal from the display driver circuit (250), and may generate scan signals according to the scan control signal and output them to the scan lines. The configuration and operation of the light-emitting driver (EDC) and the scan driver (SDC) will be described in detail with reference to FIGS. 3 through 7.

[0073] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be shorter than the length of the first direction (DR1) of the main region (MA) or substantially equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent and positioned below the main region (MA). In this case, the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3).

[0074] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0075] The connection area (CA) is an area protruding in a second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0076] The pad area (PA) is an area where pads (PDs) and a display driving circuit (250) are placed. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area (PA) may be in contact with the bending area (BA).

[0077] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) may be positioned below the connecting area (CA) and below the main area (MA). The bending area (BA) may be positioned between the connecting area (CA) and the pad area (PA). One side of the bending area (BA) is in contact with the connecting area (CA), and the other side of the bending area (BA) may be in contact with the pad area (PA).

[0078] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0079] Referring to FIG. 3, pixels (PX) can be arranged in a first direction (DR1) and a second direction (DR2). For example, pixels (PX) can be arranged in a matrix form in the first direction (DR1) and the second direction (DR2). Scan lines (SL), first light emission control lines (EL1) and second light emission control lines (EL2) extend in the first direction (DR1) and can be arranged or positioned in the second direction (DR2). Data lines (DL) extend in the second direction (DR2) and can be arranged or positioned in the first direction (DR1). Scan lines (SL) may include write scan lines (GWL), initialization scan lines (GIL), control scan lines (GCL), and bias scan lines (GBL). The configuration or number of scan lines (SL) may vary depending on the structure or driving method of the pixels (PX).

[0080] Each of the pixels (PX) may include a plurality of subpixels (SPX). For example, each of the pixels (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). The first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may each emit light of a first color, light of a second color, and light of a third color. The light of the first color, the light of the second color, and the light of the third color may each be red light (for example, light in the red wavelength band with a main peak wavelength of approximately 600 nm to 750 nm), green light (for example, light in the green wavelength band with a main peak wavelength of approximately 480 nm to 560 nm), and blue light (for example, light in the blue wavelength band with a main peak wavelength of approximately 370 nm to 460 nm), but are not limited thereto. In one embodiment, the first subpixel (SPX1), second subpixel (SPX2), and third subpixel (SPX3) of each of the pixels (PX) may be arranged in a first direction (DR1). The number, type, arrangement structure, and / or emission wavelength of the subpixels (SPX) included in each of the pixels (PX) may be varied according to the embodiments.

[0081] Each of the plurality of subpixels (SPX) may be connected to any one of the write scan lines (GWL), any one of the initialization scan lines (GIL), any one of the control scan lines (GCL), any one of the bias scan lines (GBL), any one of the light emission control lines (EL1, EL2), and any one of the data lines (DL). In describing the embodiments, the term “connection” may include the meaning of “physical connection” and / or “electrical connection”.

[0082] Each of the plurality of subpixels (SPX) receives a data voltage of a data line (DL) according to a write scan signal of a write scan line (GWL), and can emit light from a light-emitting element according to said data voltage. The plurality of subpixels (SPX) included in each pixel (PX) can be connected to different data lines (DL). For example, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) can be connected to the first data line (DLr), the second data line (DLg), and the third data line (DLb), respectively. Accordingly, the luminous brightness of each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) can be controlled individually.

[0083] In one embodiment, each pixel (PX) is connected to two or more light emission control lines (EL), and the light emission period (or on-duty ratio) of at least two subpixels (SPX) among a plurality of subpixels (SPX) included in each pixel (PX) can be controlled independently and / or individually by different light emission control signals supplied to different light emission control lines (EL). For example, in each horizontal line (e.g., each pixel row) of a display area (DA), a first light emission control line (EL1) and a second light emission control line (EL2) connected to different subpixels (SPX) among the subpixels (SPX) included in the pixels (PX) placed on the corresponding horizontal line may be disposed. For example, a first light-emitting control line (EL1) may be connected to first subpixels (SPX1) of pixels (PX) arranged on the horizontal line, and a second light-emitting control line (EL2) may be connected to second subpixels (SPX2) and third subpixels (SPX3) included in pixels (PX) of the horizontal line.

[0084] In the non-display area (NDA), a light-emitting driver (EDC), a scan driver (SDC), and a display driver circuit (250) may be placed.

[0085] The light-emitting driver (EDC) receives a driving control signal (ECS) from the display driving circuit (250). The light-emitting driver (EDC) can output light-emitting control signals to the light-emitting control lines (EL) in response to the light-emitting control signal (ECS).

[0086] In one embodiment, the light-emitting driver (EDC) may include a first light-emitting driver (611) and a second light-emitting driver (612).

[0087] The first light-emitting driver (611) can be connected to the first light-emitting control line (EL1). The second light-emitting driver (612) can be connected to the second light-emitting control line (EL2).

[0088] The first subpixel (SPX1) can emit light during a first light emission period in response to a first light emission control signal supplied through the first light emission control line (EL1). The first light emission period may be a period during which a driving current can flow through the first subpixel (SPX1) by the first light emission control signal. The second subpixel (SPX2) and the third subpixel (SPX3) can emit light during a second light emission period in response to a second light emission control signal supplied through the second light emission control line (EL2). The second light emission period may be a period during which a driving current can flow through the second subpixel (SPX2) and the third subpixel (SPX3) by the second light emission control signal. The first light emission period and the second light emission period may be controlled independently or individually, and may or may not overlap in time.

[0089] In one embodiment, the duration of the first light emission period and the duration of the second light emission period may be different. For example, the duration of the first light emission period may correspond to an on-duty ratio adjusted so that the first subpixel (SPX1) emits light at a target brightness, in accordance with a driving current optimized for the light emission efficiency of the first subpixel (SPX1) (for example, a driving current that falls within the range in which the light-emitting element of the first subpixel (SPX1) exhibits optimal consumption efficiency).

[0090] The duration of the second light-emitting period can correspond to an on-duty ratio adjusted so that the second subpixel (SPX2) and the third subpixel (SPX3) emit light at a target brightness, in accordance with a driving current optimized for the light-emitting efficiency of the second subpixel (SPX2) and the third subpixel (SPX3) (for example, a driving current that falls within the range in which the light-emitting elements of the second subpixel (SPX2) and the third subpixel (SPX3) exhibit optimal consumption efficiency).

[0091] The scan driver (SDC) can be electrically connected to pixels (PX) through scan lines (SL). For example, the scan driver (SDC) can be electrically connected to the pixel circuits of subpixels (SPX) included in each pixel (PX) through write scan lines (GWL), initialization scan lines (GIL), control scan lines (GCL), and bias scan lines (GBL).

[0092] The scan drive unit (SDC) may include a write scan signal driver (621), an initial scan signal and control scan signal driver (622), and a bias scan signal driver (623). Each of the write scan signal driver (621), the initial scan signal and control scan signal driver (622), and the bias scan signal driver (623) may receive a scan timing control signal (SCS) from the timing control circuit (251).

[0093] The write scan signal driver (621) can generate write scan signals according to the scan timing control signal (SCS) and output them sequentially to the write scan lines (GWL).

[0094] The initialization scan signal and control scan signal driver (622) can generate initialization scan signals according to the scan timing control signal (SCS) and output them sequentially to the initialization scan lines (GIL). Additionally, the initialization scan signal and control scan signal driver (622) can generate control scan signals according to the scan timing control signal (SCS) and output them sequentially to the control scan lines (GCL).

[0095] The bias scan signal driver (623) can generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (GBL).

[0096] The display driving circuit (250) may include a timing control circuit (251) and a data driving circuit (252).

[0097] The data driving circuit (252) can be electrically connected to pixels (PX) through data lines (DL). For example, the data driving circuit (252) can be electrically connected to the pixel circuits of subpixels (SPX) included in each pixel (PX) through a first data line (DLr), a second data line (DLg), and a third data line (DLb).

[0098] The data driving circuit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (251). The data driving circuit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). In this case, subpixels (SPX) can be selected by the write scan signal of the scan driving unit (SDC), and the converted data can be supplied to the selected subpixels (SPX) through the data line (DL).

[0099] The timing control circuit (251) can receive digital video data (DATA) and timing signals from an external source. The timing control circuit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control circuit (251) can output the scan timing control signal (SCS) to the scan driving unit (SDC). The timing control circuit (251) can output the digital video data (DATA) and the data timing control signal (DCS) to the data driving circuit (252).

[0100] The power supply circuit (500) can generate panel driving voltages according to the power voltage supplied from the outside. For example, the power supply circuit (500) can generate and supply a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), a fourth driving voltage (VAINT), and a fifth driving voltage (VOBS) to the display panel (100). The first driving voltage (VDD), the second driving voltage (VSS), the third driving voltage (VINT), the fourth driving voltage (VAINT), and the fifth driving voltage (VOBS) can be supplied to the subpixels (SPX) through respective power lines connected between the power supply circuit (500) and the subpixels (SPX), and can be used to drive the subpixels (SPX). Depending on the structure or operation method of the subpixels (SPX), the number and / or type of panel driving voltages output from the power supply circuit (500) may be changed.

[0101] Figure 4 is a graph showing the external quantum efficiency and current density range of a subpixel in one embodiment.

[0102] Semiconductor light-emitting devices (hereinafter referred to as Micro LEDs) with a diameter or major axis length of several to several hundred micrometers tend to exhibit a lower External Quantum Efficiency (EQE) compared to relatively larger light-emitting devices. External Quantum Efficiency generally refers to the number of photons generated relative to the injected carriers. In particular, severe carrier leakage at low currents during the initial driving phase can lead to a decrease in the device's brightness.

[0103] Referring to FIG. 4, in particular, it can be seen that the external quantum efficiency of the red light-emitting element (R) is significantly lower compared to the blue light-emitting element (B) or the green light-emitting element (G). In addition, even in the optimal current density range that produces the optimal external quantum efficiency, it can be seen that the external quantum efficiency of the red light-emitting element (R) is significantly lower compared to the external quantum efficiency of the blue light-emitting element (B) or the green light-emitting element (G).

[0104] As such, generally, the on-duty ratio of a light-emitting element emitting a red wavelength is low, whereas the on-duty ratio of a light-emitting element emitting a blue or green wavelength may be relatively high. Nevertheless, if the on-duty ratios of the light-emitting element emitting a red wavelength and the light-emitting element emitting a blue or green wavelength are reflected equally, the light-emitting element emitting a red wavelength uses a low current density range, resulting in increased power consumption. Therefore, as in one embodiment, by applying a first light-emitting driver (611) and a second light-emitting driver (612), power consumption can be reduced by operating the light-emitting control signals that control the light-emitting element emitting a red wavelength and the light-emitting control signals that control the light-emitting element emitting a blue or green wavelength separately.

[0105] FIG. 5 is an equivalent circuit diagram showing a light emission control signal and a subpixel according to one embodiment. For example, FIG. 5 may be an equivalent circuit diagram showing a subpixel (SPX) of FIG. 2 and FIG. 3. In one embodiment, the circuit configuration of a plurality of subpixels (SPX) forming each pixel (PX) may be substantially identical to one another. For example, the equivalent circuit diagrams of the subpixels (SPX) of FIG. 5 may be identical to one another.

[0106] A first light emission control signal (EM_R) may be input to the first subpixel (SPX1), and a second light emission control signal (EM_GB) may be input to the second subpixel (SPX2) and the third subpixel (SPX3). In this way, by applying different light emission control signals to the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3), an optimal current density range for each subpixel (SPX) can be used.

[0107] FIG. 6 is a waveform diagram showing driving signals of a subpixel according to one embodiment. For example, FIG. 6 shows a first light emission control signal (EM_R), a write scan signal (GW), a control scan signal (GC), an initialization scan signal (GI), a bias scan signal (GB), and a second light emission control signal (EM_GB) supplied to the scan lines (SL) and light emission control line (EL) of FIG. 5.

[0108] Referring to FIGS. 5 and FIGS. 6 in addition to FIGS. 1 to 3, each of the subpixels (SPX) may include a pixel circuit (PXC) and a light-emitting element (LE) electrically connected to the pixel circuit (PXC).

[0109] A subpixel (SPX) can be connected to at least one scan driver through scan lines (SL) and a light emission control line (EL). For example, a first subpixel (SPX1) can be connected to a light emission driver (EDC) through a first light emission control line (EL1) and to a scan driver (SDC) through a write scan line (GWL), an initial scan line (GIL), a control scan line (GCL), and a bias scan line (GBL). Additionally, a second subpixel (SPX1) and a third subpixel (SPX2) can be connected to a light emission driver (EDC) through a second light emission control line (EL2) and to a scan driver (SDC) through a write scan line (GWL), an initial scan line (GIL), a control scan line (GCL), and a bias scan line (GBL).

[0110] The first light-emitting driver (611) can output a first light-emitting control signal (EM_R) to the first light-emitting control line (EL1).

[0111] The second light-emitting driver (612) can output a second light-emitting control signal (EM_GB) to the second light-emitting control line (EL2).

[0112] The scan drive unit (SDC) can output a write scan signal (GW), an initial scan signal (GI), a control scan signal (GC), and a bias scan signal (GB) to the write scan line (GWL), the initial scan line (GIL), the control scan line (GCL), and the bias scan line (GBL), respectively.

[0113] If the subpixel (SPX) is the first subpixel (SPX1), the subpixel (SPX) is connected to the first light emission control signal (EM_R) placed on the corresponding horizontal line and can receive the first light emission control signal (EM_R) from the first light emission control line (EL1). If the subpixel (SPX) is the second subpixel (SPX2) or the third subpixel (SPX3), the subpixel (SPX) is connected to the second light emission control line (EL2) placed on the corresponding horizontal line and can receive the second light emission control signal (EM_GB) from the second light emission control line (EL2).

[0114] The subpixel (SPX) can be connected to the data driving circuit (252) via the data line (DL). The data driving circuit (252) can output a data voltage (Vdata) corresponding to the image data of each frame via the data line (DL).

[0115] If the subpixel (SPX) is the first subpixel (SPX1), the subpixel (SPX) may be connected to the first data line (DLr) placed in the corresponding pixel column. If the subpixel (SPX) is the second subpixel (SPX2), the subpixel (SPX) may be connected to the second data line (DLg) placed in the corresponding pixel column. If the subpixel (SPX) is the third subpixel (SPX3), the subpixel (SPX) may be connected to the third data line (DLb) placed in the corresponding pixel column.

[0116] A subpixel (SPX) can be connected to a power supply circuit (500) through power lines (PL). For example, the subpixel (SPX) can be connected to the power supply circuit (500) through a first power line (VDL), a second power line (VSL), a third power line (VIL), a fourth power line (VAIL), and a fifth power line (VOBL). The power supply circuit (500) can supply a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), a fourth driving voltage (VAINT), and a fifth driving voltage (VOBS), respectively, to the first power line (VDL), the second power line (VSL), the third power line (VIL), the fourth power line (VAIL), and the fifth power line (VOBL). In one embodiment, the first driving voltage (VDD), the second driving voltage (VSS), the third driving voltage (VINT), the fourth driving voltage (VAINT), and the fifth driving voltage (VOBS) may each be a high-potential pixel voltage (e.g., anode voltage), a low-potential pixel voltage (e.g., cathode voltage or common voltage), a first initialization voltage (e.g., gate initialization voltage), a second initialization voltage (e.g., anode initialization voltage), and a bias voltage.

[0117] The pixel circuit (PXC) can control the driving current (Ids) supplied to the light-emitting element (LE) in response to driving signals supplied to the subpixel (SPX) (for example, a write scan signal (GW), an initialization scan signal (GI), a control scan signal (GC), a bias scan signal (GB), a first light emission control signal (EM_R), a second light emission control signal (EM_GB), and a data voltage (Vdata)). The pixel circuit (PXC) can control the light emission timing and brightness of the light-emitting element (LE).

[0118] The pixel circuit (PXC) may include pixel transistors (PXT) and a storage capacitor (Cst). In one embodiment, the pixel circuit (PXC) may further include a boosting capacitor (Cbst).

[0119] In one embodiment, the pixel transistors (PXT) may include first to eighth transistors (T1 to T8). The first transistor (T1) may be a driving transistor of a subpixel (SPX). The second to eighth transistors (T2 to T8) may be switching transistors of a subpixel (SPX).

[0120] In one embodiment, the subpixel (SPX) may include heterogeneous pixel transistors (PXT). For example, the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) may be P-type transistors (e.g., P-type polycrystalline silicon transistors including each active layer formed of polycrystalline silicon), and the third and fourth transistors (T3, T4) may be N-type transistors (e.g., N-type oxide transistors including each active layer formed of an oxide semiconductor). In one embodiment, the active layers of the P-type transistors (e.g., active layers formed of polycrystalline silicon) and the active layers of the N-type transistors (e.g., active layers formed of an oxide semiconductor) may be disposed on different layers within the display panel (100) (e.g., the backplane layer of the display panel (100)).

[0121] The first transistor (T1) can be connected between the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to the first power line (VDL) via the fifth transistor (T5) and to the light-emitting element (LE) via the sixth transistor (T6). The gate electrode of the first transistor (T1) can be connected to the first node (N1). The first transistor (T1) can control the driving current (Ids) flowing to the subpixel (SPX) according to the voltage of the first node (N1) applied to the gate electrode (for example, a voltage corresponding to the data voltage (Vdata)).

[0122] The second transistor (T2) may be connected between the data line (DL) and the first electrode of the first transistor (T1) (for example, the source electrode of the first transistor (T1) connected to the fifth transistor (T5)). The gate electrode of the second transistor (T2) may be connected to the write scan line (GWL). The second transistor (T2) may be turned on by a write scan signal (GW) of a gate-on voltage supplied from the write scan line (GWL) (for example, a low-level voltage at which the second transistor (T2) can be turned on). When the second transistor (T2) is turned on, a data voltage (Vdata) supplied from the data line (DL) may be delivered to the first electrode (for example, the source electrode) of the first transistor (T1).

[0123] The third transistor (T3) can be connected between the second electrode of the first transistor (T1) (for example, the drain electrode of the first transistor (T1) connected to the sixth transistor (T6)) and the first node (N1). The gate electrode of the third transistor (T3) can be connected to a control scan line (GCL). The third transistor (T3) can be turned on by a control scan signal (GC) of a gate-on voltage supplied from the control scan line (GCL) (for example, a high-level voltage at which the third transistor (T3) can be turned on) to connect the gate electrode of the first transistor (T1) and the second electrode. When the third transistor (T3) is turned on, the first transistor (T1) can be driven as a diode, and a voltage corresponding to a data voltage (Vdata) can be applied to the first node (N1).

[0124] The fourth transistor (T4) can be connected between the first node (N1) and the third power line (VIL). The gate electrode of the fourth transistor (T4) can be connected to the initialization scan line (GIL). The fourth transistor (T4) can be turned on by an initialization scan signal (GI) of a gate-on voltage supplied from the initialization scan line (GIL) (for example, a high-level voltage at which the fourth transistor (T4) can be turned on) to connect the first node (N1) to the third power line (VIL). When the fourth transistor (T4) is turned on, the voltage of the first node (N1) can be initialized to the third driving voltage (VINT) of the third power line (VIL).

[0125] The fifth transistor (T5) can be connected between the first power line (VDL) and the first electrode of the first transistor (T1). The gate electrode of the fifth transistor (T5) can be connected to the first light emission control line (EL1) or the second light emission control line (EL2) of FIG. 3. The fifth transistor (T5) can be turned on by a light emission control signal (EM_R, EM_GB) of a gate-on voltage supplied from the first light emission control line (EL1) or the second light emission control line (EL2) (for example, a low-level voltage at which the fifth transistor (T5) can be turned on), and the first electrode of the first transistor (T1) can be connected to the first power line (VDL). When the fifth transistor (T5) is turned on, the first power line (VDL) can be connected to the first electrode of the first transistor (T1).

[0126] The sixth transistor (T6) can be connected between the second electrode of the first transistor (T1) and the light-emitting element (LE). The gate electrode of the sixth transistor (T6) can be connected to light-emitting control lines (EL1, EL2). The sixth transistor (T6) can be turned on by a light-emitting control signal (EM) of a gate-on voltage supplied from the light-emitting control line (EL) (for example, a low-level voltage at which the sixth transistor (T6) can be turned on) to connect the second electrode of the first transistor (T1) to the light-emitting element (LE).

[0127] The seventh transistor (T7) can be connected between the first electrode of the light-emitting element (LE) (for example, the anode electrode connected to the sixth transistor (T6)) and the fourth power line (VAIL). The gate electrode of the fourth transistor (T4) can be connected to the bias scan line (GBL). The seventh transistor (T7) can be turned on by a bias scan signal (GB) of a gate-on voltage supplied from the bias scan line (GBL) (for example, a low-level voltage at which the seventh transistor (T7) can be turned on) to connect the first electrode of the light-emitting element (LE) to the fourth power line (VAIL). When the seventh transistor (T7) is turned on, the voltage of the first electrode of the light-emitting element (LE) can be initialized to the fourth driving voltage (VAINT) of the fourth power line (VAIL).

[0128] The eighth transistor (T8) can be connected between the fifth power line (VOBL) and the first electrode of the first transistor (T1). The gate electrode of the eighth transistor (T8) can be connected to the bias scan line (GBL). The eighth transistor (T8) can be turned on by a bias scan signal (GB) of a gate-on voltage supplied from the bias scan line (GBL) to connect the first electrode of the first transistor (T1) to the fifth power line (VOBL). When the eighth transistor (T8) is turned on, the voltage of the first electrode of the first transistor (T1) can be initialized to the fifth driving voltage (VOBS) of the fifth power line (VOBL). In one embodiment, the fifth driving voltage (VOBS) may be a bias voltage having a voltage level suitable for compensating for the hysteresis characteristics of the first transistor (T1).

[0129] A storage capacitor (Cst) can be connected between a first node (N1) and a first power line (VDL). The storage capacitor (Cst) can be charged to a voltage corresponding to a data voltage (Vdata) applied to the first node (N1).

[0130] A boosting capacitor (Cbst) can be connected between the first node (N1) and the write scan line (GWL). By stabilizing the voltage of the first node (N1) through the coupling action of the boosting capacitor (Cbst), the operation of the first transistor (T1) can be stabilized. The boosting capacitor (Cbst) may be formed by a parasitic capacitance formed between the first node (N1) and the write scan line (GWL), or it may be designed separately.

[0131] A subpixel (SPX) may emit light during a portion of the frame period corresponding to the on-duty ratio and may not emit light during the remainder of the frame period. The emission and non-emission periods of the subpixel (SPX) may be controlled by an emission control signal (EM). For example, the emission and non-emission periods of the first subpixel (SPX1) may be controlled by a first emission control signal (EM_R). The emission and non-emission periods of the second subpixel (SPX2) and the third subpixel (SPX3) may be controlled by a second emission control signal (EM_GB).

[0132] The period during which the fifth transistor (T5) and the sixth transistor (T6) are turned off (for example, the period during which a high-level light emission control signal (EM_R, EM_GB) is supplied to the subpixel (SPX)) may be a non-light emission period of the subpixel (SPX). For example, the period during which a high-level first light emission control signal (EM_R) is supplied to the first subpixel (SPX1) may be a non-light emission period of the first subpixel (SPX1). The period during which a high-level second light emission control signal (EM_GB) is supplied to the second subpixel (SPX2) or the third subpixel (SPX3) may be a non-light emission period of the second subpixel (SPX2) or the third subpixel (SPX3). The non-luminous period of the subpixel (SPX) may include an initialization period for initializing the voltage of a specific node of the subpixel (SPX) (e.g., a first node (N1)), and a data writing and storage period for charging a storage capacitor (Cst) with a voltage corresponding to the data voltage (Vdata). In one embodiment, an initialization scan signal (GI), a control scan signal (GC), a write scan signal (GW), and a bias scan signal (GB) of the gate-on voltage may be supplied during the non-luminous period of the subpixel (SPX). In one embodiment, the initialization scan signal (GI), the control scan signal (GC), and the bias scan signal (GB) of the gate-on voltage may be supplied sequentially during the non-luminous period of the subpixel (SPX). The periods during which the initialization scan signal (GI) and the control scan signal (GC) of the gate-on voltage are supplied may overlap, but are not limited thereto. The write scan signal (GW) of the gate-on voltage may be supplied during the period in which the control scan signal (GC) of the gate-on voltage is supplied.

[0133] The period during which the fifth transistor (T5) and the sixth transistor (T6) are turned on (for example, the period during which a low-level light emission control signal (EM_R, EM_GB) is supplied to the subpixel (SPX)) may be the light emission period of the subpixel (SPX). For example, the period during which a low-level first light emission control signal (EM_R) is supplied to the first subpixel (SPX1) may be the light emission period of the first subpixel (SPX1). The period during which a low-level second light emission control signal (EM_GB) is supplied to the second subpixel (SPX2) or the third subpixel (SPX3) may be the light emission period of the second subpixel (SPX2) or the third subpixel (SPX3). During the light emission period of the subpixel (SPX), the first transistor (T1) may supply a driving current (Ids) corresponding to the voltage of the first node (N1) to the light-emitting element (LE).

[0134] The light-emitting element (LE) can be connected between the pixel circuit (PXC) and the second power line (VSL). For example, the first electrode of the light-emitting element (LE) (e.g., an anode electrode or a pixel electrode) can be connected to a node between the sixth transistor (T6) and the seventh transistor (T7), and the second electrode of the light-emitting element (LE) (e.g., a cathode electrode or a common electrode) can be connected to the second power line (VSL). The light-emitting element (LE) can emit light in response to a driving current (Ids) supplied from the pixel circuit (PXC).

[0135] In one embodiment, the subpixel (SPX) may include a single light-emitting element (LE), but is not limited thereto. For example, the subpixel (SPX) may include at least two light-emitting elements (LE). The at least two light-emitting elements (LE) may be connected in a series, parallel, or series-parallel structure between the pixel circuit (PXC) and the second power line (VSL).

[0136] In one embodiment, the light-emitting element (LE) may be a micro light-emitting diode containing an inorganic compound such as a nitride-based or phosphide-based semiconductor material, but is not limited thereto. For example, the light-emitting element (LE) may be an organic light-emitting element, a quantum dot light-emitting element, or other types of light-emitting elements. Additionally, the size or shape of the light-emitting element (LE) may vary depending on the embodiments.

[0137] FIG. 7 is an enlarged view of regions A and B of FIG. 2 according to one embodiment.

[0138] Referring to FIG. 7 in addition to FIG. 1 to 3, the light-emitting driver (EDC) is positioned in a non-display area (NDA) on a first side (e.g., left side) and may include a plurality of first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) and a plurality of second light-emitting drivers (612_1, 612_2, 612_3, 612_4…). The plurality of first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) may be positioned further from the display area (DA) than the plurality of second light-emitting drivers (612_1, 612_2, 612_3, 612_4…). That is, a plurality of first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) can be positioned further outward than a plurality of second light-emitting drivers (612_1, 612_2, 612_3, 612_4…).

[0139] The scan drive unit (SDC) is positioned in a non-display area (NDA) on the second side (e.g., right) facing the first side, and may include a plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…), a plurality of initialization scan signal and control scan signal drivers (622_1, 622_2, 622_3, 622_4…), and a plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…). A plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…), a plurality of initialization scan signals and a plurality of control scan signal drivers (622_1, 622_2, 622_3, 622_4…), and a plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…) are arranged in order to be away from the display area (DA). Accordingly, a plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…) may be arranged at the outermost position, and a plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…) may be arranged at the innermost position.

[0140] The width (WEDC) of the first direction (DR1) of the area where the light-emitting driver (EDC) is placed is approximately 600 μm to 610 μm, and the width (WSDC) of the first direction (DR1) of the area where the scan driver (SDC) is placed is approximately 600 μm to 610 μm, which may be similar or identical. The light-emitting driver (EDC) and the scan driver (SDC) may be arranged symmetrically with respect to the display area (DA).

[0141] The number of multiple first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) may be the same as the number of multiple second light-emitting drivers (612_1, 612_2, 612_3, 612_4…). The size of the multiple first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) may be the same as the size of the multiple second light-emitting drivers (612_1, 612_2, 612_3, 612_4…). The area of ​​the multiple first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) may be the same as the area of ​​the multiple second light-emitting drivers (612_1, 612_2, 612_3, 612_4…). For example, the width (WE1) of the first direction (DR1) of each of the plurality of first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) may be about 215 μm to 225 μm, and the width (WE2) of the first direction (DR1) of each of the plurality of second light-emitting drivers (612_1, 612_2, 612_3, 612_4…) may be about 215 μm to 225 μm. In one embodiment, the width (WE1) of the first direction (DR1) of each of the first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) and the width (WE2) of the first direction (DR1) of each of the plurality of second light-emitting drivers (612_1, 612_2, 612_3, 612_4…) may be approximately 220 μm, and the width (WE3) of the first direction (DR1) of the power line placement area may be approximately 160 μm. Accordingly, the width (WEDC) of the first direction (DR1) of the light-emitting driver (EDC) may be approximately 600 μm.

[0142] The area of ​​the write scan signal driver (621) of the scan drive unit (SDC), the area of ​​the initialization scan signal and the plurality of control scan signal drivers (622), and the bias scan signal driver (623) can be increased in order.

[0143] The number of multiple write scan signal drivers (621_1, 621_2, 621_3, 621_4…), multiple initialization scan signals, and multiple control scan signal drivers (622_1, 622_2, 622_3, 622_4…) may be the same. The width (WS1) of the first direction (DR1) of each of the plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…) may be approximately 145 μm to 155 μm, the width (WS2) of the first direction (DR1) of each of the plurality of initialization scan signal and plurality of control scan signal drivers (622_1, 622_2, 622_3, 622_4…) may be approximately 195 μm to 205 μm, and the width (WS3) of the first direction (DR1) of each of the plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…) may be approximately 95 μm to 105 μm. The number of multiple bias scan signal drivers (623_1, 623_2, 623_3, 623_4…) may be less than the number of multiple write scan signal drivers (621_1, 621_2, 621_3, 621_4…), multiple initialization scan signals, and multiple control scan signal drivers (622_1, 622_2, 622_3, 622_4…). The width (WS1) of the first direction (DR1) of the write scan signal driver (621_1, 621_2, 621_3, 621_4…) may be approximately 150 μm, the width (WS2) of the first direction (DR1) of the plurality of initialization scan signals and the plurality of control scan signal drivers (622_1, 622_2, 622_3, 622_4…) may be approximately 200 μm, and the width (WS3) of the first direction (DR1) of each of the plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…) may be approximately 100 μm. The width (WS4) of the first direction (DR1) of the power line placement area may be approximately 155 μm. Accordingly, the width (WSDC) of the first direction (DR1) of the scan drive unit (SDC) may be approximately 605 μm.

[0144] FIG. 8 is an enlarged view of regions A and B of FIG. 2 according to another embodiment, and FIG. 9 is an enlarged view of regions A and B of FIG. 2 according to yet another embodiment.

[0145] FIGS. 8 and 9 differ from FIG. 7 in that the arrangement of drivers within the light-emitting driver unit (EDC) and the arrangement of drivers within the scan driver unit (SDC) are different. In FIGS. 8 and 9, the same description as in FIG. 7 is omitted, and the explanation focuses on the differences.

[0146] Referring to FIG. 8, a plurality of second light-emitting drivers (612) in the light-emitting driver unit (EDC) may be positioned further outward than a plurality of first light-emitting drivers (611).

[0147] In the scan drive unit (SDC), a plurality of initialization scan signals and a plurality of control scan signal drivers (622_1, 622_2, 622_3, 622_4…) may be positioned further inside than a plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…).

[0148] Referring to FIG. 9, a plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…), a plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…), a plurality of initialization scan signals, and a plurality of control scan signal drivers (622_1, 622_2, 622_3, 622_4…) may be sequentially arranged from the inside to the outside.

[0149] As can be seen by referring to FIGS. 7 to 9, drivers can be symmetrically placed in the non-display areas (NDA) on the left and right sides of the display area (DA). Accordingly, the non-display area (NDA) has a shape in which the first side and the second side are symmetrical with respect to the display area (DA).

[0150] The second light-emitting driver (612) and the first light-emitting driver (611) are positioned on the first side of the non-display area (NDA), and the second light-emitting driver (612) and the first light-emitting driver (611) are of the same size and there are no positional restrictions within the light-emitting driver (EDC). The first light-emitting driver (611) may be positioned close to the display area (DA), and the second light-emitting driver (612) may be positioned close to the display area (DA). A plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…), a plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…), a plurality of initialization scan signals, and a plurality of control scan signal drivers (622_1, 622_2, 622_3, 622_4…) are placed on the second side of the non-display area (NDA), and there may be no positional constraints between each driver. However, among the multiple bias scan signal drivers (623_1, 623_2, 623_3, 623_4…), multiple write scan signal drivers (621_1, 621_2, 621_3, 621_4…), multiple initialization scan signal drivers, and multiple control scan signal drivers (622_1, 622_2, 622_3, 622_4…), placing the smallest driver close to the display area (DA) is advantageous in terms of wiring resistance. This is because the connecting wiring connecting to the driver located outside the display area (DA) must bypass the driver located relatively inside.

[0151] FIG. 10 is a plan view showing a display panel according to another embodiment, FIG. 11 is an enlarged view of regions A', B', C', and D' of FIG. 10 according to one embodiment, and FIG. 12 is an enlarged view of regions A', B', C', and D' of FIG. 10 according to another embodiment.

[0152] Referring to FIG. 10, the display panel (100) may differ from the display panel (100) of FIG. 2 in that it is circular. In FIG. 10, the same description as in FIG. 2 is omitted, and the differences are explained mainly.

[0153] Referring to FIG. 10, the display panel (100) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a planar circular shape. The non-display area (NDA) may be placed around the display area (DA). The non-display area (NDA) may be a bezel area. The non-display area (NDA) may surround the display area (DA).

[0154] Referring to FIGS. 10 and 11, the non-display area (NDA) may include a region C' in the first quadrant, a region A' in the second quadrant, a region B' in the third quadrant, and a region D' in the fourth quadrant. An emitting driver (EDC) may be disposed in the region A' in the second quadrant and the region B' in the third quadrant of the non-display area (NDA), and a scanning driver (SDC) may be disposed in the region C' in the first quadrant and the region D' in the fourth quadrant.

[0155] The driver placement in area A' of the second quadrant of the non-display area (NDA) and the driver placement in area B' of the third quadrant may be the same. The driver placement in area C' of the first quadrant of the non-display area (NDA) and the driver placement in area D' of the fourth quadrant may be the same. Therefore, area A' of the second quadrant and area C' of the first quadrant will be described.

[0156] The light-emitting driving unit (EDC) of region A' of the second quadrant may include a plurality of first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) and a plurality of second light-emitting drivers (612_1, 612_2, 612_3, 612_4…).

[0157] The number of multiple first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) may be the same as the number of multiple second light-emitting drivers (612_1, 612_2, 612_3, 612_4…). The size of the multiple first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) may be the same as the size of the multiple second light-emitting drivers (612_1, 612_2, 612_3, 612_4…).

[0158] The scan drive unit (SDC) of the C' region of the first quadrant may include a plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…), a plurality of initialization scan signal and a plurality of control scan signal drivers (622_1, 622_2, 622_3, 622_4…), and a plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…). A plurality of first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) may be positioned further from the display area (DA) than a plurality of second light-emitting drivers (612_1, 612_2, 612_3, 612_4…). That is, a plurality of first light-emitting drivers (611_1, 611_2, 611_3, 611_4…) can be positioned further outward than a plurality of second light-emitting drivers (612_1, 612_2, 612_3, 612_4…).

[0159] A plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…), a plurality of initialization scan signals and a plurality of control scan signal drivers (622_1, 622_2, 622_3, 622_4…), and a plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…) are arranged in order to be away from the display area (DA). Accordingly, a plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…) may be arranged at the outermost position, and a plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…) may be arranged at the innermost position.

[0160] The number of multiple write scan signal drivers (621_1, 621_2, 621_3, 621_4…), multiple initialization scan signals, and multiple control scan signal drivers (622_1, 622_2, 622_3, 622_4…) may be the same.

[0161] Referring to FIGS. 10 and 12, a plurality of second light-emitting drivers (612) in the light-emitting driver unit (EDC) may be positioned further outward than a plurality of first light-emitting drivers (611).

[0162] A plurality of bias scan signal drivers (623_1, 623_2, 623_3, 623_4…), a plurality of write scan signal drivers (621_1, 621_2, 621_3, 621_4…), a plurality of initialization scan signals, and a plurality of control scan signal drivers (622_1, 622_2, 622_3, 622_4…) may be arranged sequentially from the inside to the outside.

[0163] The size of each driver exemplified in FIGS. 11 and FIGS. 12 is the same as the size of the corresponding driver described with reference to FIGS. 7, so no redundant description is provided.

[0164] As can be seen by referring to FIGS. 10 to 12, in a display panel (100) having a circular display area (DA), a first light-emitting driver (611) and a second light-emitting driver (612) may be placed on the first side (e.g., left) of the non-display area (NDA), and other write scan signal drivers (621), initialization scan signals and a plurality of control scan signal drivers (622) and bias scan signal drivers (623) may be symmetrically placed on the second side (e.g., right) of the non-display area (NDA).

[0165] FIG. 13 is a layout diagram showing a light-emitting element layer of a display panel according to one embodiment. For example, FIG. 13 shows light-emitting elements (LE), pixel electrodes (PXE), and a common electrode (CE) included in sub-pixels (SPX) of each pixel (PX) in a part of a display area (DA) in which two adjacent pixels (PX) are arranged in a second direction (DR2).

[0166] Referring to FIG. 13 in addition to FIG. 3 to 12, each of the subpixels (SPX) may include a pixel electrode (PXE) and a light-emitting element (LE) disposed in a light-emitting region (EA). In one embodiment, if the light-emitting element (LE) is a flip-chip type or lateral type micro LED, each of the subpixels (SPX) may further include a common electrode (CE) disposed on one side (e.g., a bottom surface or a top surface) of the light-emitting element (LE) together with the pixel electrode (PXE).

[0167] Although FIG. 13 illustrates that the size of the light-emitting regions (EA) of the subpixels (SPX) is the same, the embodiments are not limited thereto. For example, the size of the light-emitting regions (EA) of the subpixels (SPX) may be differentiated or optimized according to the light-emitting characteristics or target brightness of each light-emitting element (LE) and / or subpixel (SPX).

[0168] Additionally, although FIG. 13 illustrates that the pixel electrodes (PXE) are located only within each light-emitting region (EA), the embodiments are not limited thereto. For example, at least one portion of a pixel electrode (PXE) may be placed in a non-light-emitting region surrounding the light-emitting region (EA). For example, the size, shape, and / or placement direction of the pixel electrodes (PXE) may vary depending on the embodiments.

[0169] In one embodiment, the subpixels (SPX) of each pixel (PX) may be arranged in a first direction (DR1). Additionally, the subpixels (SPX) of each pixel (PX) may share a common electrode (CE). For example, the common electrode (CE) extends in the first direction (DR1) from each horizontal line of the display area (DA), and the subpixels (SPX) of the pixels (PX) arranged on the corresponding horizontal line may share a common electrode (CE).

[0170] The first subpixel (SPX1) may include a first pixel electrode (PXE1), a first light-emitting element (LE1), and a common electrode (CE) (or a part of the common electrode (CE)) disposed in a first light-emitting region (EA1). The first light-emitting region (EA1) may refer to the light-emitting region (EA) of the first subpixel (SPX1). The first light-emitting element (LE1) may refer to the light-emitting element (LE) of the first subpixel (SPX1).

[0171] The second subpixel (SPX2) may include a second pixel electrode (PXE2), a second light-emitting element (LE2), and a common electrode (CE) disposed in a second light-emitting region (EA2). The second light-emitting region (EA2) may refer to the light-emitting region (EA) of the second subpixel (SPX2). The second light-emitting element (LE2) may refer to the light-emitting element (LE) of the second subpixel (SPX2).

[0172] The third subpixel (SPX3) may include a third pixel electrode (PXE3), a third light-emitting element (LE3), and a common electrode (CE) disposed in a third light-emitting region (EA3). The third light-emitting region (EA3) may refer to the light-emitting region (EA) of the third subpixel (SPX3). The third light-emitting element (LE3) may refer to the light-emitting element (LE) of the third subpixel (SPX3).

[0173] In each pixel (PX), the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may be arranged in a first direction (DR1). The first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may be spaced apart from the common electrode (CE) in a second direction (DR2).

[0174] Pixel electrodes (PXE) can be electrically connected to each pixel circuit (PXC) through each anode contact hole (ANH). For example, a first pixel electrode (PXE1) can be electrically connected to a first pixel circuit (PXC1) through a first anode contact hole (ANH1). A second pixel electrode (PXE2) can be electrically connected to a second pixel circuit (PXC2) through a second anode contact hole (ANH2). A third pixel electrode (PXE3) can be electrically connected to a third pixel circuit (PXC3) through a third anode contact hole (ANH3).

[0175] Light-emitting elements (LE) may be placed between each pixel electrode (PXE) and a common electrode (CE). For example, a first light-emitting element (LE1) may be placed on the first pixel electrode (PXE1) and the common electrode (CE), with one part of the first light-emitting element (LE1) overlapping with the first pixel electrode (PXE1) and another part of the first light-emitting element (LE1) overlapping with the common electrode (CE). The first light-emitting element (LE1) may be electrically connected between the first pixel electrode (PXE1) and the common electrode (CE). A second light-emitting element (LE2) may be placed on the second pixel electrode (PXE2) and the common electrode (CE), with one part of the second light-emitting element (LE2) overlapping with the second pixel electrode (PXE2) and another part of the second light-emitting element (LE2) overlapping with the common electrode (CE). The second light-emitting element (LE2) may be electrically connected between the second pixel electrode (PXE2) and the common electrode (CE). The third light-emitting element (LE3) is positioned on the third pixel electrode (PXE3) and the common electrode (CE), and a portion of the third light-emitting element (LE3) may overlap with the third pixel electrode (PXE3) and another portion of the third light-emitting element (LE3) may overlap with the common electrode (CE). The third light-emitting element (LE3) may be electrically connected between the third pixel electrode (PXE3) and the common electrode (CE).

[0176] Each of the light-emitting elements (LE) can emit light of a specific color (e.g., red light, green light, blue light, or white light). In one embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can emit light of different colors. For example, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can each emit light of a first color (e.g., red light), light of a second color (e.g., green light), and light of a third color (e.g., blue light).

[0177] In one embodiment, the light-emitting elements (LE) of at least two subpixels (SPX) may have different sizes. For example, the size of the first light-emitting element (LE1) may be larger than the size of the second light-emitting element (LE2) and the third light-emitting element (LE3), respectively.

[0178] In one embodiment, the light-emitting elements (LE) may have a differentiated or optimized size depending on the light-emitting efficiency of the light-emitting elements (LE). For example, depending on the light-emitting efficiency of each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3), at least two of the light-emitting elements (LE) among the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may have different sizes. For example, based on the same size and shape, if the light-emitting efficiency of the first light-emitting element (LE1) is lower than the light-emitting efficiency of the second light-emitting element (LE2) and the third light-emitting element (LE3), the size of the first light-emitting element (LE1) may be larger than the size of the second light-emitting element (LE2) and the third light-emitting element (LE3). Accordingly, the light-emitting efficiency of the first light-emitting element (LE1) can be improved, and the difference in light-emitting efficiency between the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can be reduced or prevented.

[0179] In another embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may emit light of the same color. In this case, on at least one light-emitting element (LE) among the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3), at least one of a light conversion layer (e.g., a light conversion layer including wavelength conversion particles such as quantum dots) and a color filter may be disposed to convert the light emitted from the light-emitting element (LE) of the corresponding subpixel (SPX) into light corresponding to the light emission color of the corresponding subpixel (SPX). When the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) emit light of the same color, the sizes of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may be the same or different from each other. For example, depending on the light conversion efficiency of the light conversion layer, at least one of the size of the light-emitting elements (LE) of the subpixels (SPX) and the area of ​​the light-emitting regions (EA) of the subpixels (SPX) may be differentiated.

[0180] Meanwhile, FIG. 13 discloses an embodiment in which the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) each include a single light-emitting element (LE), but the embodiments are not limited thereto. For example, at least one of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may include a plurality of light-emitting elements (LE).

[0181] The common electrode (CE) may be electrically connected to the second power lines (VSL). For example, the common electrode (CE) may be electrically connected to the second power lines (VSL) through a cathode contact hole (CDH) inside the display area (DA), but is not limited thereto. A second driving voltage (VSS) may be applied to the common electrode (CE) and the second power lines (VSL).

[0182] The cathode contact hole (CDH) may be spaced apart from the light-emitting elements (LE) by a certain distance or more. For example, the distance (d) between the cathode contact hole (CDH) and the second light-emitting element (LE2) closest to the cathode contact hole (CDH) may be approximately 10 μm or more. In one embodiment, considering alignment errors that may occur during the manufacturing process of the display panel (100), the shortest distance (d) between the cathode contact hole (CDH) and the light-emitting elements (LE) may be set to approximately 11 μm.

[0183] By securing a separation distance between the cathode contact hole (CDH) and the light-emitting elements (LE), each light-emitting element (LE) can be placed more stably in the pixels (PX). For example, by controlling the separation distance between the cathode contact hole (CDH) and the light-emitting elements (LE) to 10 μm or more (e.g., 11 μm), the common electrode (CE) can be substantially flat in the area where the light-emitting elements (LE) are placed. Accordingly, the light-emitting elements (LE) can be stably placed or bonded on the common electrode (CE).

[0184] In one embodiment, the distance between the anode contact holes (ANH) and the light-emitting elements (LE) may be greater than the shortest distance (d) between the cathode contact hole (CDH) and the light-emitting elements (LE). Accordingly, the pixel electrodes (PXE) may be substantially flat in the area where the light-emitting elements (LE) are placed. Accordingly, the light-emitting elements (LE) can be placed or bonded more stably on the pixel electrodes (PXE) and the common electrode (CE).

[0185] In one embodiment, the common electrode (CE) may extend to a non-display area (NDA) around the display area (DA) and may be electrically connected to a power bus line placed in the non-display area (NDA) (for example, a bus line to which a second driving voltage (VSS) is applied). As the second power lines (VSL) are placed inside the backplane layer (BPL) in the display area (DA), the resistance of the wiring including the second power lines (VSL) may be reduced.

[0186] FIG. 14 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line X1-X1' of FIG. 13. For example, FIG. 14 shows an example of a cross-section of a display panel (100) corresponding to a part of a first subpixel (SPX1). In one embodiment, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) may have substantially the same or similar cross-sectional structures. For example, the corresponding circuit elements of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) (for example, the first transistors (T1) of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3)) are placed on substantially the same layer and may have substantially the same or similar cross-sectional structures.

[0187] FIG. 15 is a cross-sectional view showing the A2 region of FIG. 14 in detail.

[0188] In one embodiment, the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may have substantially the same or similar cross-sectional structures.

[0189] FIG. 16 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the X2-X2' line and the X3-X3' line of FIG. 13.

[0190] Referring to FIG. 14 through 16 in addition to FIG. 13, a display panel (100) may include a substrate (SUB) and a backplane layer (BPL) and an emitting element layer (EDL) disposed on the substrate (SUB). In one embodiment, the display panel (100) may further include a color filter layer (CFL) disposed on the emitting element layer (EDL). The backplane layer (BPL), the emitting element layer (EDL), and the color filter layer (CFL) may be sequentially disposed on the substrate (SUB) along a third direction (DR3).

[0191] The substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a stretchable flexible substrate. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0192] A substrate (SUB) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include pixel areas (PXA) where pixels (PX) are arranged. Each pixel area (PXA) may include light-emitting areas (EA) of sub-pixels (SPX).

[0193] The backplane layer (BPL) may include circuit elements included in the pixel circuits (PXC) of the subpixels (SPX) and wiring connected to the subpixels (SPX). In one embodiment, the backplane layer (BPL) may be formed entirely on one side of the substrate (SUB).

[0194] The backplane layer (BPL) may include at least one semiconductor layer, conductive layers, and insulating layers. In one embodiment, if the pixel circuits (PXC) include at least two types of pixel transistors (PXT) formed of different materials, the backplane layer (BPL) may include a plurality of semiconductor layers.

[0195] For example, the backplane layer (BPL) comprises a barrier layer (BR) (or buffer layer), a first semiconductor layer (SCL1) (e.g., a polycrystalline silicon semiconductor layer), a first insulating layer (INS1) (e.g., a first inorganic insulating layer), a first gate conductive layer (GCDL1) (or a first conductive layer), a second insulating layer (INS2) (e.g., a second inorganic insulating layer), a second gate conductive layer (GCDL2) (or a second conductive layer), a third insulating layer (INS3) (e.g., a third inorganic insulating layer), a second semiconductor layer (SCL2) (e.g., an oxide semiconductor layer), a fourth insulating layer (INS4) (e.g., a fourth inorganic insulating layer), a third gate conductive layer (GCDL3) (or a third conductive layer), a fifth insulating layer (INS5) (e.g., a fifth inorganic insulating layer), a first source-drain conductive layer (SCDL1) (or a fourth conductive layer), and a sixth It may include an insulating layer (INS6) (e.g., a first organic insulating layer), a second source-drain conductive layer (SCDL2) (or a fifth conductive layer) and a seventh insulating layer (INS7) (e.g., a second organic insulating layer).

[0196] A barrier layer (BR) may be disposed on a substrate (SUB). The barrier layer (BR) can protect circuit elements of the backplane layer (BPL) and light-emitting elements (LE) on the backplane layer (BPL) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability. In one embodiment, the barrier layer (BR) may be composed of a plurality of inorganic films.

[0197] Circuit elements of the backplane layer (BPL) may be disposed on the barrier layer (BR). For example, on the barrier layer (BR), pixel transistors (PXT), storage capacitors (Cst), and boosting capacitors (Cbst) of each pixel circuit (PXC) included in the corresponding pixel (PX) may be disposed in each pixel region (PXA). Additionally, wiring of the backplane layer (BPL) may be disposed on the barrier layer (BR). For example, a write scan line (GWL), an initialization scan line (GIL), a control scan line (GCL), a bias scan line (GBL), a first light emission control line (EL1), a second light emission control line (EL2), a first data line (DLr), a second data line (DLg), a third data line (DLb), a first power line (VDL), a second power line (VSL), a third power line (VIL), a fourth power line (VAIL), a fifth power line (VOBL), and a horizontal power line (HVDL) may be arranged on the barrier layer (BR).

[0198] In one embodiment, each pixel circuit (PXC) may include a first type of transistor and a second type of transistor. The first type of transistor and the second type of transistor may be placed on different layers within the backplane layer (BPL).

[0199] For example, each pixel circuit (PXC) may include first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) of P-type and third and fourth transistors (T3, T4) of N-type. The first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the third and fourth active layers (ACT3, ACT4) of the third and fourth transistors (T3, T4) may be disposed on different semiconductor layers included in the backplane layer (BPL). In one embodiment, the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the third and fourth active layers (ACT3, ACT4) of the third and fourth transistors (T3, T4) may include different semiconductor materials, but are not limited thereto. Additionally, the first, second, fifth, sixth, seventh, and eighth gate electrodes (GE1, GE2, GE5, GE6, GE7, GE8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8) and the third and fourth active layers (ACT3, ACT4) of the third and fourth transistors (T3, T4) may be placed on different conductive layers included in the backplane layer (BPL).

[0200] Specifically, a first semiconductor layer (SCL1) may be disposed on the barrier layer (BR). The first semiconductor layer (SCL1) may include an active layer for each of the first type of transistors. For example, the first semiconductor layer (SCL1) may include the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8). FIGS. 14 and 16 show only some of the pixel transistors (PXT) included in each pixel circuit (PXC), and FIGS. 14 and 16 show the first active layer (ACT1) and the sixth active layer (ACT6) among the active layers included in the first semiconductor layer (SCL1). In one embodiment, the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of each pixel circuit (PXC) may be integrally formed using the same semiconductor material. For example, as shown in FIGS. 13 to 16, the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8) of each of the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) may be formed as a single semiconductor pattern connected to each other.

[0201] Patterns of the first semiconductor layer (SCL1) (for example, the first, second, fifth, sixth, seventh, and eighth active layers (ACT1, ACT2, ACT5, ACT6, ACT7, ACT8)) may include a first semiconductor material. In one embodiment, the first semiconductor material may be polycrystalline silicon (for example, low-temperature polycrystalline silicon), but is not limited thereto. For example, the first semiconductor material may be an oxide semiconductor (for example, at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors) or single-crystal silicon.

[0202] A first insulating layer (INS1) may be disposed on the first semiconductor layer (SCL1). The first insulating layer (INS1) may comprise at least one insulating material (e.g., silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), titanium oxide (TiOx), aluminum oxide (AlOx), or other inorganic insulating material) and may be composed of a single layer or multiple layers.

[0203] A first gate conductive layer (GCDL1) may be disposed on the first insulating layer (INS1). The first gate conductive layer (GCDL1) may include the gate electrodes of each of the first type of transistors. For example, the first gate conductive layer (GCDL1) may include the first, second, fifth, sixth, seventh, and eighth gate electrodes (GE1, GE2, GE5, GE6, GE7, GE8) of the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, T8). The first gate conductive layer (GCDL1) may further include at least one conductive pattern and / or wiring. For example, the first gate conductive layer (GCDL1) may further include a first electrode (SCE1) of a storage capacitor (Cst), a first electrode (BCE1) of a boosting capacitor (Cbst), a write scan line (GWL), and a bias scan line (GBL). In FIGS. 14 and 16, among the patterns of the first gate conductive layer (GCDL1), the first gate electrode (GE1), the sixth gate electrode (GE6), the first electrode (SCE1) of the storage capacitor (Cst), the first electrode (BCE1) of the boosting capacitor (Cbst), and the write scan line (GWL) are shown.

[0204] In one embodiment, the first gate electrode (GE1) of each pixel circuit (PXC) and the first electrode (SCE1) of the storage capacitor (Cst) are formed integrally, and the second gate electrode (GE2), the first electrode (BCE1) of the boosting capacitor (Cbst), and the write scan line (GWL) (for example, the write scan line (GWL) connected to the subpixels (SPX) of the corresponding horizontal line) may be formed integrally. Additionally, the seventh gate electrode (GE7), the eighth gate electrode (GE8), and the bias scan line (GBL) (for example, the bias scan line (GBL) connected to the subpixels (SPX) of the corresponding horizontal line) may be formed integrally.

[0205] Patterns of the first gate conductive layer (GCDL1) (for example, first, second, fifth, sixth, seventh, and eighth gate electrodes (GE1, GE2, GE5, GE6, GE7, GE8), the first electrode (SCE1) of the storage capacitor (Cst), the first electrode (BCE1) of the boosting capacitor (Cbst), the write scan line (GWL) and the bias scan line (GBL)) may include the same conductive material.

[0206] A second insulating layer (INS2) may be disposed on the first gate conductive layer (GCDL1). The second insulating layer (INS2) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0207] A second gate conductive layer (GCDL2) may be disposed on the second insulating layer (INS2). The second gate conductive layer (GCDL2) may include a second electrode (SCE2) of a storage capacitor (Cst). The first electrode (SCE1) and the second electrode (SCE2) of the storage capacitor (Cst) may overlap with the first insulating layer (INS1) in between. The second electrode (SCE2) of the storage capacitor (Cst) may be open at the portion where the first electrode (SCE1) of the storage capacitor (Cst) is connected to the first connecting electrode (CNE1) (for example, the fourth contact hole (CH4) and its surroundings). The second gate conductive layer (GCDL2) may further include at least one conductive pattern and / or wiring. For example, the second gate conductive layer (GCDL2) may further include a first light-blocking pattern (LBP1), a second light-blocking pattern (LBP2), a horizontal power line (HVDL), and a fourth power line (VAIL). In FIGS. 19 and 21, among the patterns of the second gate conductive layer (GCDL2), the second electrode (SCE2) of the storage capacitor (Cst), the first light-blocking pattern (LBP1), the second light-blocking pattern (LBP2), and the fourth power line (VAIL) are illustrated.

[0208] In one embodiment, the first light-blocking patterns (LBP1) of the subpixels (SPX) arranged in each horizontal line may be formed integrally, and the second light-blocking patterns (LBP2) of the subpixels (SPX) arranged in each horizontal line may be formed integrally. Additionally, the second electrodes (SCE2) of the storage capacitors (Cst) of the subpixels (SPX) arranged in each horizontal line and the horizontal power line (HVDL) may be formed integrally.

[0209] Patterns of the second gate conductive layer (GCDL2) (for example, the second electrode (SCE2) of the storage capacitor (Cst), the first light-blocking pattern (LBP1), the second light-blocking pattern (LBP2), the horizontal power line (HVDL), and the fourth power line (VAIL)) may include the same conductive material.

[0210] A third insulating layer (INS3) may be disposed on the second gate conductive layer (GCDL2). The third insulating layer (INS3) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0211] A second semiconductor layer (SCL2) may be disposed on the third insulating layer (INS3). The second semiconductor layer (SCL2) may include the active layer of each of the second type of transistors. For example, the second semiconductor layer (SCL2) may include the third and fourth active layers (ACT3, ACT4) of the third and fourth transistors (T3, T4). In one embodiment, the third and fourth active layers (ACT3, ACT4) of each pixel circuit (PXC) may be integrally formed using the same semiconductor material.

[0212] Patterns of the second semiconductor layer (SCL2) (for example, the third and fourth active layers (ACT3, ACT4), the second electrode (BCE2) of the boosting capacitor (Cbst)) may include a second semiconductor material. In one embodiment, the second semiconductor material may be an oxide semiconductor, but is not limited thereto. For example, the second semiconductor material may be polycrystalline silicon or single-crystal silicon.

[0213] A fourth insulating layer (INS4) may be disposed on the second semiconductor layer (SCL2). The fourth insulating layer (INS4) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0214] A third gate conductive layer (GCDL3) may be disposed on the fourth insulating layer (INS4). The third gate conductive layer (GCDL3) may include the gate electrodes of each of the second type of transistors. For example, the third gate conductive layer (GCDL3) may include the third and fourth gate electrodes (GE3, GE4) of the third and fourth transistors (T3, T4). The third gate conductive layer (GCDL3) may further include at least one conductive pattern and / or wiring. For example, the third gate conductive layer (GCDL3) may further include an initialization scan line (GIL), a control scan line (GCL), and a fifth power line (VOBL). In FIGS. 19 and 21, the third gate electrode (GE3) and the fourth gate electrode (GE4) among the patterns of the third gate conductive layer (GCDL3) are illustrated.

[0215] In one embodiment, the third gate electrode (GE3) and the control scan line (GCL) (for example, the control scan line (GCL) connected to the subpixels (SPX) of the corresponding horizontal line) may be formed integrally. Additionally, the fourth gate electrode (GE4) and the initialization scan line (GIL) (for example, the initialization scan line (GIL) connected to the subpixels (SPX) of the corresponding horizontal line) may be formed integrally.

[0216] Patterns of the third gate conductive layer (GCDL3) (for example, third and fourth gate electrodes (GE3, GE4), initialization scan line (GIL), control scan line (GCL) and fifth power line (VOBL)) may include the same conductive material.

[0217] A fifth insulating layer (INS5) may be disposed on the third gate conductive layer (GCDL3). The fifth insulating layer (INS5) may comprise at least one insulating material (e.g., an inorganic insulating material) and may be composed of a single layer or multiple layers.

[0218] A first source-drain conductive layer (SCDL1) may be disposed on the fifth insulating layer (INS5). The first source-drain conductive layer (SCDL1) may include at least one electrode, a conductive pattern, and / or wiring. For example, the first source-drain conductive layer (SCDL1) may include source and drain electrodes (SE1, DE1) of the first transistor (T1), first, second, third, fourth, sixth, and seventh connecting electrodes (CNE1, CNE2, CNE3, CNE4, CNE6, CNE7), first and second light emission control lines (EL1, EL2), and a third power line (VIL). In FIGS. 19 and 21, the source and drain electrodes (SE1, DE1) of the first transistor (T1), the first and fourth connection electrodes (CNE1, CNE4), the first and second light emission control lines (EL1, EL2) and the third power line (VIL) are shown among the patterns of the first source-drain conductive layer (SCDL1).

[0219] Patterns of the first source-drain conductive layer (SCDL1) (for example, source and drain electrodes (SE1, DE1) of the first transistor (T1), first, second, third, fourth, sixth, and seventh connecting electrodes (CNE1, CNE2, CNE3, CNE4, CNE6, CNE7), first and second light emission control lines (EL1, EL2) and third power line (VIL)) may include the same conductive material.

[0220] A sixth insulating layer (INS6) may be disposed on the first source-drain conductive layer (SCDL1). The sixth insulating layer (INS6) may comprise at least one insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating material) and may be composed of a single layer or multiple layers.

[0221] A second source-drain conductive layer (SCDL2) may be disposed on the sixth insulating layer (INS6). The second source-drain conductive layer (SCDL2) may include at least one electrode, a conductive pattern, and / or wiring. For example, the second source-drain conductive layer (SCDL2) may include a fifth connection electrode (CNE5), first, second, and third data lines (DLr, DLg, DLb), and first and second power lines (VDL, VSL). In FIGS. 19 and 21, the fifth connection electrode (CNE5), the first power line (VDL), and the second power line (VSL) are shown among the patterns of the second source-drain conductive layer (SCDL2).

[0222] Patterns of the second source-drain conductive layer (SCDL2) (for example, the fifth connecting electrode (CNE5), the first, second, and third data lines (DLr, DLg, DLb), and the first and second power lines (VDL, VSL)) may include the same conductive material.

[0223] A seventh insulating layer (INS7) may be disposed on the second source-drain conductive layer (SCDL2). The seventh insulating layer (INS7) comprises at least one insulating material (e.g., an organic insulating material) and may be composed of a single layer or multiple layers.

[0224] Patterns included in each of the conductive layers of the backplane layer (BPL) may include at least one conductive material. For example, electrodes, conductive patterns, and / or wiring included in each of the first gate conductive layer (GCDL1), the second gate conductive layer (GCDL2), the third gate conductive layer (GCDL3), the first source-drain conductive layer (SCDL1), and the second source-drain conductive layer (SCDL2) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials. In one embodiment, electrodes, conductive patterns, and / or wiring disposed in the same conductive layer may be formed simultaneously using the same conductive material. At least two of the conductive layers of the backplane layer (BPL) may contain the same conductive material or different conductive materials.

[0225] In one embodiment, the patterns included in each of the conductive layers of the backplane layer (BPL) may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and / or wirings included in each of the first gate conductive layer (GCDL1), the second gate conductive layer (GCDL2), the third gate conductive layer (GCDL3), the first source-drain conductive layer (SCDL1), and the second source-drain conductive layer (SCDL2) may have a single-layer or multi-layer structure. At least two of the conductive layers of the backplane layer (BPL) may have the same cross-sectional structure or different cross-sectional structures.

[0226] In one embodiment, the patterns of the second source-drain conductive layer (SCDL2) may comprise a metal (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, or an alloy thereof) and may have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns, and / or wiring included in the second source-drain conductive layer (SCDL2) may be low-resistance patterns formed with a triple-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). Alternatively, the patterns of the second source-drain conductive layer (SCDL2) may comprise other low-resistance materials and / or structures. When the resistance of the patterns included in the second source-drain conductive layer (SCDL2) is reduced or minimized, the resistance of the first power line (VDL) and the second power line (VSL), through which the driving current (Ids) of each subpixel (SPX) flows, can be reduced or minimized. Accordingly, the image quality of the display device (10) can be standardized and power consumption improved.

[0227] A light-emitting element layer (EDL) may be disposed on the seventh insulating layer (INS7). The light-emitting element layer (EDL) may include pixel electrodes (PXE), light-emitting elements (LE), and a common electrode (CE) included in subpixels (SPX). Additionally, the light-emitting element layer (EDL) may further include insulating layers. In one embodiment, the insulating layers of the light-emitting element layer (EDL) may include eighth, ninth, and tenth insulating layers (INS8, INS9, INS10), a capping layer (CPL), and a first overcoat layer (OC1).

[0228] A pixel electrode layer including pixel electrodes (PXE) of subpixels (SPX) may be disposed on the seventh insulating layer (INS7). For example, the pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). In one embodiment, the light-emitting element (LE) may be a flip-chip type micro LED. A flip-chip type micro LED refers to an LED having first and second contact electrodes (CTE1, CTE2) formed on one side (e.g., the bottom side) of the light-emitting element (LE). When the light-emitting element (LE) is a flip-chip type micro LED, the pixel electrode layer may further include a common electrode (CE). For example, the pixel electrodes (PXE) of subpixels (SPX) and the common electrode (CE) may be disposed on the same layer and may be formed simultaneously using the same conductive material.

[0229] The first pixel electrode (PXE1) of the first subpixel (SPX1) can be electrically connected to the fifth connecting electrode (CNE5) of the first subpixel (SPX1) through a first anode contact hole (ANH1) (for example, a contact hole that penetrates the seventh insulating layer (INS7) and exposes the fifth connecting electrode (CNE5) of the first subpixel (SPX1). The second pixel electrode (PXE2) of the second subpixel (SPX2) can be electrically connected to the fifth connecting electrode (CNE5) of the second subpixel (SPX2) through a second anode contact hole (ANH2) (for example, a contact hole that penetrates the seventh insulating layer (INS7) and exposes the fifth connecting electrode (CNE5) of the second subpixel (SPX2). The third pixel electrode (PXE3) of the third subpixel (SPX3) can be electrically connected to the fifth connecting electrode (CNE5) of the third subpixel (SPX3) through a third anode contact hole (ANH3) (for example, a contact hole that penetrates the seventh insulating layer (INS7) to expose the fifth connecting electrode (CNE5) of the third subpixel (SPX3). Accordingly, the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) are electrically connected to the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3), respectively, and the first pixel circuit (PXC1), the second pixel circuit (PXC2), and the third pixel circuit (PXC3) can control the voltage applied to the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3).

[0230] A common electrode (CE) shared by the first, second, and third subpixels (SPX1, SPX2, SPX3) can be electrically connected to the second power line (VSL) of the backplane layer (BPL) through a cathode contact hole (CDH) (for example, a contact hole that penetrates the seventh insulating layer (INS7) to expose the second power line (VSL) of the backplane layer (BPL). Accordingly, a second driving voltage (VSS) applied to the second power line (VSL) can be transmitted to the common electrode (CE).

[0231] In one embodiment, the patterns of the pixel electrode layer (e.g., pixel electrodes (PXE) and common electrode (CE)) may include the same conductive material. In one embodiment, the patterns of the pixel electrode layer (e.g., pixel electrodes (PXE) and common electrode (CE)) may include the same conductive material. In one embodiment, the patterns of the pixel electrode layer may include a metal (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, or an alloy thereof) and may have a single-layer or multi-layer structure. For example, the patterns of the pixel electrode layer may be low-resistance patterns formed with a triple-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). Alternatively, the patterns of the pixel electrode layer may include other low-resistance materials (e.g., copper (Cu)) and / or structures. When the resistance of the patterns included in the pixel electrode layer is reduced or minimized, the first driving voltage (VDD) and the second driving voltage (VSS) can be stably transmitted to the light-emitting elements (LE) of the subpixels (SPX).

[0232] An eighth insulating layer (INS8) may be disposed on the pixel electrodes (PXE) and the common electrode (CE). The eighth insulating layer (INS8) serves to temporarily fix or adhere the light-emitting elements (LE) to prevent them from tilting or falling over during the process of transferring the light-emitting elements (LE) to the display panel (100). For example, the eighth insulating layer (INS8) may be a film for temporarily adhering the light-emitting elements (LE) to each pixel electrode (PXE) and the common electrode (CE). To facilitate temporary adhesion, the thickness of the eighth insulating layer (INS8) may be greater than the thickness of each pixel electrode (PXE) and the common electrode (CE), and greater than the thickness of each of the first and second contact electrodes (CTE1, CTE2) of the light-emitting elements (LE).

[0233] Although FIGS. 14 to 16 illustrate that the eighth insulating layer (INS8) is placed over the entire display area (DA), the embodiments are not limited thereto. For example, the eighth insulating layer (INS8) may be placed only on a portion of the pixel electrodes (PXE) and common electrode (CE) that overlap with the light-emitting elements (LE), and may expose other portions of the pixel electrodes (PXE) and common electrode (CE).

[0234] The eighth insulating layer (INS8) may include at least one insulating material, for example, an organic insulating material. For example, the eighth insulating layer (INS8) may be a photosensitive organic film such as a photoresist. Alternatively, the eighth insulating layer (INS8) may be formed from an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0235] Light-emitting elements (LE) may be disposed on the eighth insulating layer (INS8). For example, a first light-emitting element (LE1) may be disposed on the first pixel electrode (PXE1) and the common electrode (CE) of a first subpixel (SPX1). A second light-emitting element (LE2) may be disposed on the second pixel electrode (PXE2) and the common electrode (CE) of a second subpixel (SPX2). A third light-emitting element (LE3) may be disposed on the third pixel electrode (PXE3) and the common electrode (CE) of a third subpixel (SPX3).

[0236] In one embodiment, each of the light-emitting elements (LE) may be a micro LED comprising an inorganic material. For example, each of the light-emitting elements (LE) may be formed of an inorganic material such as gallium nitride (GaN), and the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of each of the light-emitting elements (LE) may each be several μm to several hundred μm. For example, the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of each of the light-emitting elements (LE) may each be approximately 100 μm or less.

[0237] Light-emitting elements (LE) can be formed by growing on a semiconductor substrate, such as a silicon substrate or a sapphire substrate. Light-emitting elements (LE) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE) and common electrode (CE) of the display panel (100). Alternatively, light-emitting elements (LE) can be transferred onto the pixel electrodes (PXE) and common electrode (CE) of the display panel (100) via an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material, such as PDMS or silicon, as a transfer substrate.

[0238] The light-emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), contact electrodes (CTE1, CTE2), and a protective film (PRL). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW) (e.g., a light-emitting layer), and a second semiconductor layer (SEM2) arranged sequentially in a third direction (DR3). In one embodiment, the semiconductor stack (STC) may further include a third semiconductor layer (SEM3) on the second semiconductor layer (SEM2).

[0239] A conductive layer (E1) may be disposed on the lower surface of the first semiconductor layer (SEM1). Although FIG. 15 illustrates the conductive layer (E1) covering the entire lower surface of the first semiconductor layer (SEM1), the embodiments of this specification are not limited thereto. As an example, the conductive layer (E1) may be disposed on a part of the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a transparent conductive material such as a metal oxide.

[0240] The first semiconductor layer (SEM1) can be placed on the conductive layer (E1). The first semiconductor layer (SEM1) may be made of a semiconductor material layer doped with a first conductive type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc., for example, gallium nitride (GaN).

[0241] An active layer (MQW) may be disposed on a first semiconductor layer (SEM1). The active layer (MQW) may include the same semiconductor material as the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). For example, if the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2) include gallium nitride (GaN), the active layer (MQW) may also include gallium nitride (GaN). For example, the active layer (MQW) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The active layer (MQW) may emit light by the recombination of electron-hole pairs according to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0242] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different Group 3 to Group 5 semiconductor materials depending on the wavelength of the emitted light.

[0243] When the active layer (MQW) contains indium gallium nitride (InGaN), the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer shifts to a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer shifts to a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of a light-emitting device (LE) that emits a third color of light (blue light) may be approximately 10 wt% to 20 wt%.

[0244] The second semiconductor layer (SEM2) can be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductivity type dopant, such as silicon (Si), germanium (Ge), tin (Sn), etc., for example, gallium nitride (GaN).

[0245] A third semiconductor layer (SEM3) may be disposed on a second semiconductor layer (SEM2). The third semiconductor layer (SEM3) is a semiconductor material layer in which the n-type dopant is lower than a predetermined threshold value and may be referred to as an un-doped semiconductor layer. For example, the third semiconductor layer (SEM3) may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN), in which the n-type dopant is lower than a predetermined threshold value.

[0246] An electron blocking layer may be placed between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer designed to suppress or prevent too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0247] A superlattice layer may be disposed between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0248] A protective film (PRL) may be disposed on the side of the first semiconductor layer (SEM1), the side of the active layer (MQW), and the side of the second semiconductor layer (SEM2). The protective film (PRL) may be a film for protecting the side of the light-emitting element (LE). The protective film (PRL) may be formed of an inorganic material, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), titanium oxide (TiOx), aluminum oxide (AlOx), or other inorganic insulating material.

[0249] FIG. 15 illustrates that a protective film (PRL) is disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), and the sides of the second semiconductor layer (SEM2) of the semiconductor stack (STC), but is not disposed on the sides of the third semiconductor layer (SEM3), but embodiments are not limited thereto. In one example, the protective film (PRL) may be disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), the sides of the second semiconductor layer (SEM2), and the sides of the third semiconductor layer (SEM3) of the semiconductor stack (STC).

[0250] A hole (LEH) may be formed that penetrates the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light-emitting element (LE) to expose the second semiconductor layer (SEM2). The hole (LEH) may have a circular planar shape, but the embodiments of this specification are not limited thereto. As an example, the hole (LEH) may have a polygonal planar shape such as an ellipse or a square.

[0251] A protective film (PRL) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective film (PRL) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Accordingly, the second semiconductor layer (SEM2) may be exposed without being covered by the protective film (PRL).

[0252] The first contact electrode (CTE1) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side of the conductive layer (E1) and on the lower surface. The first contact electrode (CTE1) may be disposed on the lower surface of the conductive layer (E1) that is exposed and not covered by a protective film (PRL). Therefore, the first contact electrode (CTE1) may be electrically connected to the conductive layer (E1).

[0253] The second contact electrode (CTE2) may be disposed on at least one side of the semiconductor stack (STC), at least one side of the conductive layer (E1), and on the lower surface. In this case, while the first contact electrode (CTE1) is disposed on the first side of the semiconductor stack (STC) and the first side of the conductive layer (E1), the second contact electrode (CTE2) may be disposed on the second side of the semiconductor stack (STC) and the second side of the conductive layer (E1).

[0254] The second contact electrode (CTE2) can be placed on a protective film (PRL) placed in the hole (LEH) and on a second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the protective film (PRL). Therefore, the second contact electrode (CTE2) can be electrically connected to the second semiconductor layer (SEM2) in the hole (LEH).

[0255] FIGS. 14 and 15 illustrate that the first contact electrode (CTE1) and the second contact electrode (CTE2) of each of the light-emitting elements (LE) are disposed on the eighth insulating layer (INS8), but the embodiments of this specification are not limited thereto. As an example, the eighth insulating layer (INS8) may be disposed on the lower surface and part of the side of the first contact electrode (CTE1) of each of the light-emitting elements (LE) and on the lower surface and part of the side of the second contact electrode (CTE2). Alternatively, the eighth insulating layer (INS8) may be disposed on the sides of the conductive layer (E1) of each of the light-emitting elements (LE). Alternatively, the eighth insulating layer (INS8) may be disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), and the sides of the second semiconductor layer (SEM2) of each of the light-emitting elements (LE). In this case, the eighth insulating layer (INS8) may be disposed on a part of each of the sides of the second semiconductor layer (SEM2).

[0256] Each of the first contact electrode (CTE1) and the second contact electrode (CTE2) may be placed on three sides of the semiconductor stack (STC). For example, if the semiconductor stack (STC) includes first to fourth sides, the first contact electrode (CTE1) may be placed on the first side, the second side, and the third side, and the second contact electrode (CTE2) may be placed on the second side, the third side, and the fourth side.

[0257] Each of the first contact electrode (CTE1) and the second contact electrode (CTE2) may include at least one conductive material, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). In one embodiment, the first contact electrode (CTE1) and the second contact electrode (CTE2) may be formed with a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of ITO (Indium Tin Oxide), silver (Ag), and ITO (Indium Tin Oxide) to increase reflectivity.

[0258] When the first contact electrode (CTE1) and the second contact electrode (CTE2) are each formed of a metal with high reflectivity, light emitted from the active layer (MQW) of the light-emitting element (LE) that travels in the lateral direction of the light-emitting element (LE) can be reflected by the first contact electrode (CTE1) and the second contact electrode (CTE2) and emitted to the upper surface of the light-emitting element (LE). Therefore, since the loss of light from the light-emitting element (LE) can be reduced, the light efficiency of the light-emitting element (LE) can be increased. To increase the light efficiency of the light-emitting element (LE), the first contact electrode (CTE1) and the second contact electrode (CTE2) can be arranged to cover most of the side of the semiconductor stack (STC).

[0259] The first bridge electrode (BE1) (or the eighth connecting electrode) connects the first contact electrode (CTE1) of the light-emitting element (LE) to each pixel electrode (PXE). For example, the first bridge electrode (BE1) of the first subpixel (SPX1) can connect the first contact electrode (CTE1) of the first light-emitting element (LE1) to the first pixel electrode (PXE1). Similarly, the first bridge electrode (BE1) of the second subpixel (SPX2) can connect the first contact electrode (CTE1) of the second light-emitting element (LE2) to the second pixel electrode (PXE2), and the first bridge electrode (BE1) of the third subpixel (SPX3) can connect the first contact electrode (CTE1) of the third light-emitting element (LE3) to the third pixel electrode (PXE3).

[0260] The first bridge electrode (BE1) can be connected to each exposed pixel electrode (PXE) through a first connection hole (BH1) penetrating the eighth insulating layer (INS8). Additionally, the first bridge electrode (BE1) can be placed on the upper surface of the eighth insulating layer (INS8) and on the first contact electrode (CTE1) of the light-emitting element (LE). In another embodiment, if the eighth insulating layer (INS8) is placed only on a portion of the pixel electrode (PXE) that overlaps with the light-emitting element (LE), the first connection hole (BH1) may be unnecessary. For example, the first bridge electrode (BE1) may be placed directly on the pixel electrode (PXE) exposed around the light-emitting element (LE).

[0261] The second bridge electrode (BE2) (or the ninth connecting electrode) connects the second contact electrode (CTE2) of the light-emitting element (LE) to the common electrode (CE). For example, the second bridge electrode (BE2) of the first subpixel (SPX1) can connect the second contact electrode (CTE2) of the first light-emitting element (LE1) to the common electrode (CE). Similarly, the second bridge electrode (BE2) of the second subpixel (SPX2) can connect the second contact electrode (CTE2) of the second light-emitting element (LE2) to the common electrode (CE), and the second bridge electrode (BE2) of the third subpixel (SPX3) can connect the second contact electrode (CTE2) of the third light-emitting element (LE3) to the common electrode (CE). In another embodiment, if the eighth insulating layer (INS8) is placed only on a portion of the common electrode (CE) that overlaps with the light-emitting element (LE), the second connecting hole (BH2) may be unnecessary. For example, the second bridge electrode (BE2) may be placed directly on the common electrode (CE) exposed around the light-emitting element (LE).

[0262] The second bridge electrode (BE2) can be connected to a common electrode (CE) exposed through a second connection hole (BH2) penetrating the eighth insulating layer (INS8). Additionally, the second bridge electrode (BE2) can be placed on the upper surface of the eighth insulating layer (INS8) and on the second contact electrode (CTE2).

[0263] Each of the first bridge electrode (BE1) and the second bridge electrode (BE2) may comprise at least one conductive material, for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the first bridge electrode (BE1) and the second bridge electrode (BE2) may be made of a transparent conductive material such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) (for example, Transparent Conductive Oxide (TCO)).

[0264] When the first bridge electrode (BE1) and the second bridge electrode (BE2) are each made of a highly reflective metallic material such as aluminum (Al), light emitted from the active layer (MQW) of the light-emitting element (LE) that travels in the lateral direction of the light-emitting element (LE) can be reflected by the connecting electrodes (BE) and travel in the upper direction of the light-emitting element (LE). Accordingly, the loss of light from the light-emitting element (LE) can be reduced, thereby increasing the light efficiency of the light-emitting element (LE).

[0265] As shown in FIGS. 14 and 15, the conductive layer (E1) of the light-emitting element (LE) can be electrically connected to each pixel electrode (PXE) through a first contact electrode (CTE1) and a first bridge electrode (BE1). Additionally, the second semiconductor layer (SEM2) of the light-emitting element (LE) can be electrically connected to a common electrode (CE) through a second contact electrode (CTE2) and a second bridge electrode (BE2) formed in a hole (LEH). Meanwhile, the pixel electrodes (PXE) may be referred to as the anode electrode or the first electrode, and the common electrode (CE) may also be referred to as the cathode electrode or the second electrode.

[0266] The ninth insulating layer (INS9) may be disposed on the eighth insulating layer (INS8). The ninth insulating layer (INS9) may be disposed to cover a portion of the side of the light-emitting elements (LE). Additionally, the ninth insulating layer (INS9) may be disposed to cover the first and second bridge electrodes (BE1, BE2), but at least a portion of the first and second bridge electrodes (BE1, BE2) may be exposed and not covered by the ninth insulating layer (INS9).

[0267] The 10th insulating layer (INS10) may be disposed on the 9th insulating layer (INS9). The 10th insulating layer (INS10) may be disposed to cover a portion of the side of each of the light-emitting elements (LE). The 10th insulating layer (INS10) may be disposed on at least a portion of the first and second bridge electrodes (BE1, BE2) that are exposed and not covered by the 9th insulating layer (INS9). The upper surface of each of the light-emitting elements (LE) may be exposed and not covered by the 10th insulating layer (INS10).

[0268] The ninth insulating layer (INS9) and the tenth insulating layer (INS10) may include at least one insulating material, for example, an organic insulating material. For example, each of the ninth insulating layer (INS9) and the tenth insulating layer (INS10) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0269] The ninth insulating layer (INS9) and the tenth insulating layer (INS10) can flatten the step difference caused by the light-emitting elements (LE). If the height of the ninth insulating layer (INS9) is positioned to cover most of the side of each of the light-emitting elements (LE), the tenth insulating layer (INS10) may be omitted.

[0270] A capping layer (CPL) may be disposed on light-emitting elements (LE), a ninth insulating layer (INS9), and a tenth insulating layer (INS10). The capping layer (CPL) may comprise at least one insulating material, for example, an inorganic insulating material.

[0271] In one embodiment, when the light-emitting element (LE) of each subpixel (SPX) emits light of a color corresponding (e.g., matching) to the light-emitting color (or light-emitting wavelength) of the corresponding subpixel (SPX), the display panel (100) may not include a light conversion layer. For example, a first overcoat layer (OC1) may be placed directly on the capping layer (CPL).

[0272] When subpixels (SPX) include light-emitting elements (LE) that emit light corresponding to each light-emitting color, the light emitted from the light-emitting elements (LE) can be utilized more efficiently. For example, the degradation of light efficiency of the subpixels (SPX) due to light conversion can be prevented. In addition, the color purity of the light emitted from the subpixels (SPX) can be increased, and the color reproduction rate of the subpixels (SPX) can be improved.

[0273] In another embodiment, if a light-emitting element (LE) of at least one subpixel (SPX) emits light of a color different from the light-emitting color (or light-emitting wavelength) of the subpixel (SPX), a light-converting layer may be further disposed on top of the light-emitting element (LE). For example, if the first light-emitting element (LE1) emits blue light and the first subpixel (SPX1) is a red subpixel that emits red light, a light-converting layer covering the first light-emitting element (LE1) may be disposed on the capping layer (CPL). The light-converting layer may include light-converting particles (e.g., red quantum dots) that convert blue light incident from the first light-emitting element (LE1) into red light. If the subpixels (SPX) include light-emitting elements (LE) that emit light of the same color, the manufacturing efficiency of the light-emitting element layer (EDL) and the display panel (100) including it can be increased and the manufacturing cost reduced.

[0274] The first overcoat layer (OC1) may be disposed on a capping layer (CPL) (or light conversion layer). The first overcoat layer (OC1) may be an organic film comprising an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin), and the upper surface of the first overcoat layer (OC1) may be substantially flat. However, the embodiments are not limited thereto. For example, the first overcoat layer (OC1) may be an inorganic film comprising an inorganic insulating material, and the first overcoat layer (OC1) may be formed with a sufficient thickness to include a substantially flat upper surface or may be flattened through a separate flattening process. Accordingly, the upper surface of the first overcoat layer (OC1) may be substantially flat.

[0275] A color filter layer (CFL) may be disposed on the first overcoat layer (OC1). The color filter layer (CFL) may further include color filters (CF) disposed in the light-emitting regions (EA) of the subpixels (SPX), and a second overcoat layer (OC2) covering the color filters (CF).

[0276] The color filter layer (CFL) may include color filters (CF) that selectively transmit light corresponding to the emission color (or emission wavelength) of each subpixel (SPX). For example, if the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) are subpixels (SPX) that emit red light, green light, and blue light, respectively, a red color filter, a green color filter, and a blue color filter may be disposed in the first emission region (EA1) of the first subpixel (SPX1), the second emission region (EA2) of the second subpixel (SPX2), and the third emission region (EA3) of the third subpixel (SPX3), respectively. In one embodiment, the color filters (CF) of the subpixels (SPX) may overlap each other in a non-emission region surrounding the emission regions (EA) of the subpixels (SPX) to form a light-blocking pattern.

[0277] The second overcoat layer (OC2) may be disposed on the color filters (CF). The second overcoat layer (OC2) may be an organic film containing an organic insulating material, and the upper surface of the second overcoat layer (OC2) may be substantially flat. However, the embodiments are not limited thereto. For example, the second overcoat layer (OC2) may be an inorganic film containing an inorganic insulating material, and the second overcoat layer (OC2) may be formed with a sufficient thickness to include a substantially flat upper surface or may be flattened through a separate flattening process. Accordingly, the upper surface of the second overcoat layer (OC2) may be substantially flat.

[0278] FIG. 17 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to the line X1-X1' of FIG. 13. For example, FIG. 17 shows an embodiment of a cross-section of a display panel (100) corresponding to a portion of a first subpixel (SPX1). Compared to FIG. 14, FIG. 17 shows an embodiment in which the display panel (100) further includes a lower conductive layer (BCDL).

[0279] Referring to FIG. 17, the display panel (100) may further include a lower conductive layer (BCDL) disposed on a substrate (SUB). For example, the backplane layer (BPL) may include a lower conductive layer (BCDL) disposed between the substrate (SUB) and the barrier layer (BR).

[0280] The lower conductive layer (BCDL) may include a lower pattern (BML) disposed below the first transistor (T1). The lower pattern (BML) may cover the lower surface of the first active layer (ACT1) wholly or partially. For example, the lower pattern (BML) may be disposed below the first active layer (ACT1) to overlap with the channel region of the first active layer (ACT1) (for example, a part of the first active layer (ACT1) that overlaps with the first gate electrode (GE1)).

[0281] In one embodiment, the lower conductive layer (BCDL) may include a light-blocking material. For example, the lower conductive layer (BCDL) may include a metal, and the lower pattern (BML) may be formed as a lower metal pattern. In one embodiment, the lower pattern (BML) may be electrically connected to a power line to which a positive voltage is applied (for example, a first power line (VDL)). In one embodiment, the lower pattern (BML) may be formed in the display area (DA) as a pattern that extends or connects along at least one of the first direction (DR1) and the second direction (DR2) when viewed on a plane defined by the first direction (DR1) and the second direction (DR2), but is not limited thereto.

[0282] The lower pattern (BML) can block external light from being incident on the channel region of the first active layer (ACT1) or the lower part of the first transistor (T1). Additionally, the lower pattern (BML) can disperse charges that accumulate around the first transistor (T1). Accordingly, the operating characteristics of the first transistor (T1) can be stabilized.

[0283] FIGS. 18 and 19 are exemplary drawings showing a smart watch including a display device according to one embodiment.

[0284] Referring to FIGS. 18 and 19, a display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of the smart devices.

[0285] The planar shape of the display device (10_1) may be square or circular, but is not limited thereto and can be varied in various ways, such as elliptical.

[0286] FIG. 20 is an exploded view of a smart watch including a display device according to one embodiment.

[0287] Referring to FIG. 20, the smart watch (1000_1) may include a main body unit (BP) and a wearable part (BD).

[0288] The main body unit (BP) may include a display panel (100) on which an image is displayed, a cover window (CW) placed on the display panel (100), a lower cover (BC) placed below the display panel (100), a middle frame (MF) placed between the cover window (CW) and the lower cover (BC), and a battery (BR) placed between the middle frame (MF) and the lower cover (BC). In addition, in addition to the battery (BR), a circuit board on which a main processor controlling the smart watch (1000_1), a communication chipset communicating with the outside via wired or wireless communication, and memory are mounted may be additionally placed between the middle frame (MF) and the lower cover (BC).

[0289] The main body unit (BP) may have a lower cover (BC), a battery (BR), a middle frame (MF), a display panel (100), and a cover window (CW) arranged sequentially.

[0290] A cover window (CW) is positioned on the upper part of a display panel (10) to protect the display panel (10) and to transmit light emitted from the display panel (10). As described above, the cover window (CW) may include a light-blocking portion to block a portion of the light emitted from the display panel (10). The cover window (CW) may be made of a transparent plastic material, a glass material, or a reinforced glass material.

[0291] A cover window (CW) may be positioned to overlap the display panel (10) and cover the front of the display panel (10). The cover window (CW) generally has a shape similar to the display panel (10) in planar form, but its size may be larger than that of the display panel (10). For example, the cover window (CW) may protrude outward from the display panel (10). The planar shape of the cover window (CW) may be the same as the planar shape of the main body unit (BP). For example, the planar shape of the cover window (CW) may generally be circular, but is not limited thereto and may have various shapes, such as a polygon (e.g., square) or an ellipse.

[0292] The middle frame (MF) is positioned between the cover window (CW) and the lower cover (BC) as a connecting member for joining the cover window (CW) and the lower cover (BC). For example, the middle frame (MF) may include a bracket.

[0293] The lower cover (BC) is a housing placed at the bottom of the display panel (10).

[0294] The lower cover (BC) may include a central cover portion (BCP) and a peripheral portion (BS) positioned around the central cover portion (BCP).

[0295] The central cover portion (BCP) is located in the center of the lower cover (BC) and can be generally flat.

[0296] The periphery (BS) may be positioned to surround the central cover portion (BCP). The periphery (BS) may be a bent portion formed by being folded from the central cover portion (BCP). The periphery (BS) may be folded from the edge of the central portion (CP). In some embodiments, the periphery (BS) may include a curved surface having a certain curvature in part, and a flat part in other parts. The degree (or angle) at which the periphery (BS) is folded from the central cover portion (BCP) may be obtuse, but is not limited thereto, and may be right or acute.

[0297] A storage space (BC-S) can be formed by the central cover portion (BCP) and the peripheral portion (BS). A battery (BR) can be placed in the storage space (BC-S).

[0298] The battery (BR) can be connected to a circuit board on which the main processor, etc. is mounted. The display device (10_1) is electrically connected to the circuit board and can receive digital video signals, timing signals, power, etc.

[0299] The lower cover (BC) is positioned on the outermost rear surface of the electronic device and comprises at least one material among plastic, metal, and glass, and may include a color coating layer. For example, the lower cover (BC) according to one example may be a flat glass having a transparent, translucent, or opaque color coating layer.

[0300] According to another example, the lower cover (BC) may include a glass material having the same shape as the cover window (CW) and a color coating layer. For example, according to another example, the lower cover (BC) may have a structure symmetrical to the cover window (CW) with the middle frame (MF) in between and may include a transparent, translucent, or opaque color coating layer.

[0301] The wearing part (BD) is a part for securing the main body unit (BP) to the user's wrist, etc., and may be, for example, any one of a strap, a chain, and a bracelet.

[0302] FIG. 21 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment.

[0303] Referring to FIG. 21, a head-mounted display device (1000_2) according to one embodiment may include a display module that emits a display image and a reflector that reflects the emitted display screen to provide it to the user's eyes, thereby providing a virtual reality or augmented reality screen to the user.

[0304] FIG. 22 is an example drawing showing a virtual reality device including a display device according to another embodiment. FIG. 22 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0305] Referring to FIG. 22, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. A virtual reality device (1000_3) according to one embodiment may have a display device (10_4), a left eye lens (10a), a right eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device housing (50).

[0306] FIG. 22 illustrates a virtual reality device (1000_3) that is an eyeglass-type display device including eyeglass frame temples (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that shown in FIG. 22 and can be applied in various forms in various other electronic devices.

[0307] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user can view the virtual reality image displayed on the display device (10_4) through their right eye.

[0308] FIG. 22 illustrates that the display device housing (50) is positioned at the right end of the support frame (20), but the embodiments of this specification are not limited thereto. For example, the display device housing (50) may be positioned at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user can view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be positioned at both the left end and the right end of the support frame (20), in which case the user can view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0309] FIG. 23 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment. FIG. 22 shows an automobile with display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment applied.

[0310] Referring to FIG. 23, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to an instrument panel of a vehicle, to a center fascia of a vehicle, or to a Center Information Display (CID) placed on the dashboard of a vehicle. Additionally, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0311] FIG. 24 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0312] Referring to FIG. 24, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. Therefore, a user located in front of the transparent display device can not only view the image (IM) displayed on the display device (10_5), but also see an object (RS) or background located on the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) may include a light-transmitting portion capable of transmitting light, or be formed of a material capable of transmitting light.

[0313] FIGS. 18 to 24 illustrate examples of electronic devices that may include display devices (10, 10_1, 10_2, 10_3, 10_4, 10_5, 10_a, 10_b, 10_c, 10_d, 10_e) according to embodiments, such as a smart watch (1000_1), a head-mounted display device (1000_2, 1000_3), an automobile instrument panel and center fascia, and a transparent display device, but the embodiments are not limited thereto. For example, a display device (10) according to at least one of the embodiments described above may be included in an electronic device of a different type or structure in addition to the electronic devices shown in FIGS. 18 to 24.

[0314] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

A display panel comprising a display area and a non-display area, and a plurality of pixels disposed in the display area; A light-emitting driving unit that applies light-emitting control signals to the plurality of pixels and is disposed in a non-display area on the first side of the display area; and A scan driving unit that applies scan signals to the above-mentioned display panel and is disposed in a non-display area on the second side facing the first side of the above-mentioned display area. Includes, The plurality of pixels above include a first subpixel that emits light of a first wavelength and a second subpixel that emits light of a second wavelength shorter than the first wavelength. The light-emitting driving unit comprises a first light-emitting driver that applies a first light-emitting control signal to the first subpixel and a second light-emitting driver that applies a second light-emitting control signal to the second subpixel. In paragraph 1, The above-described scan driving unit is a display device comprising a write scan signal driver, an initialization scan signal, a control scan signal driver, and a bias scan signal driver, each connected to a subpixel to apply a scan signal. In paragraph 2, A display device in which the above-mentioned non-display area surrounds the above-mentioned display area, and the above-mentioned first side and the above-mentioned second side have a shape that is symmetrical to each other. In paragraph 2, A display device positioned close to the display area in order of smallest size among the above-mentioned write scan signal driver, initialization scan signal, control scan signal driver, and bias scan signal driver. In paragraph 4, A display device positioned close to the display area in the order of the above-mentioned entry scan signal driver, initialization scan signal, control scan signal driver, and bias scan signal driver. In paragraph 1, A display device in which the light-emitting driving unit and the scan driving unit are symmetrical to each other with respect to the display area. In paragraph 4, A first light-emitting control line connecting the first light-emitting driver and the first subpixel to each other; and A display device comprising a second light-emitting control line connecting the second light-emitting driver and the second subpixel. In paragraph 2, A write scan line connecting the above write scan signal driver and the first subpixel and the second subpixel; A control scan line connecting the initialization scan signal and control scan signal driver and the first subpixel and the second subpixel; An initialization scan line connecting the initialization scan signal and control scan signal driver and the first subpixel and the second subpixel; and A display device further comprising a bias scan line connecting the bias scan signal driver, the first subpixel, and the second subpixel. In paragraph 2, The plurality of pixels further include a third subpixel that emits light of a third wavelength shorter than the light of the first wavelength, and The above second light-emitting driver is a display device that applies a second light-emitting control signal to the above third subpixel. In Paragraph 9, The above second light emission control line further connects the second light emission driver and the third subpixel, and The above-mentioned write scan line further connects the above-mentioned write scan signal driver and the above-mentioned third subpixel, and The above control scan line further connects the initialization scan signal and the control scan signal driver with the third subpixel, and The above initialization scan line further connects the initialization scan signal and control scan signal driver with the third subpixel, and The above bias scan line is a display device that further connects the above bias scan signal driver and the above third subpixel. In paragraph 3, The above display area is a rectangular or circular display device. In Paragraph 9, The first subpixel above includes a first pixel circuit and a first light-emitting element electrically connected to the first pixel circuit, and The second subpixel above includes a second pixel circuit and a second light-emitting element electrically connected to the second pixel circuit, and The above third subpixel is a display device comprising a third pixel circuit and a third light-emitting element electrically connected to the third pixel circuit. A display panel including a display area and a non-display area, and including a first subpixel and a second subpixel disposed in the display area; A light-emitting driving unit comprising a first light-emitting driver that applies a first light-emitting control signal to the first subpixel and a second light-emitting driver that applies a second light-emitting control signal to the second subpixel; and A scan driving unit comprising a write scan signal driver, an initialization scan signal, a control scan signal driver, and a bias scan signal driver, each connected to the first subpixel and the second subpixel to apply a scan signal. Includes, A display device in which the light-emitting driving unit and the scan driving unit are symmetrically arranged in the non-display area centered on the display panel. In Paragraph 13, A display device positioned close to the display area in the order of the above-mentioned entry scan signal driver, initialization scan signal, control scan signal driver, and bias scan signal driver. In Paragraph 13, A first light-emitting control line connecting the first light-emitting driver and the first subpixel to each other; and A display device further comprising a second light-emitting control line connecting the second light-emitting driver and the second subpixel. In Paragraph 13, A write scan line connecting the above write scan signal driver and the first subpixel and the second subpixel; A control scan line connecting the initialization scan signal and control scan signal driver and the first subpixel and the second subpixel; An initialization scan line connecting the initialization scan signal and control scan signal driver and the first subpixel and the second subpixel; and A display device further comprising a bias scan line connecting the bias scan signal driver, the first subpixel, and the second subpixel. In paragraph 15, The first light-emitting control line extends in the first direction from the display area and is electrically connected to the first subpixel, and A display device in which the second light-emitting control line extends in the first direction from the display area and is electrically connected to the second subpixel. In Paragraph 13, The first subpixel above includes a first light-emitting element that emits light of a first wavelength, and The above second subpixel is a display device comprising a second light-emitting element that emits light of a second wavelength shorter than the first wavelength. As an electronic device, Display device; A window disposed on the above-mentioned display device; and It includes a lower cover positioned at the bottom of the above-mentioned display device, and The above display device is, A display panel comprising a display area and a non-display area, and a plurality of pixels disposed in the display area; A light-emitting driving unit that outputs light-emitting control signals to the above-mentioned display panel and is disposed in a non-display area on the second side facing the first side of the above-mentioned display area; and A scan driving unit that outputs scan signals to the above-mentioned display panel and is disposed in a non-display area on the first side of the above-mentioned display area Includes, The plurality of pixels above include a first subpixel that emits light of a first wavelength and a second subpixel that emits light of a second wavelength shorter than the first wavelength. The above-described light-emitting driving unit is an electronic device comprising a first light-emitting driver that applies a first light-emitting control signal to the first subpixel and a second light-emitting driver that applies a second light-emitting control signal to the second subpixel. In Paragraph 19, A battery disposed in the space of the lower cover and supplying power to the display device; and An electronic device further comprising a middle frame disposed between the above window and the above lower cover.

Images