Apparatus and method for converting analog signal into digital signal in two-step flash analog to digital converter

Abstract

One embodiment of the present invention may reduce power consumption by converting an analog signal into a digital signal through a two-step flash ADC including a plurality of complementary amplifiers. An apparatus according to one embodiment of the present invention comprises: a capacitive digital-to-analog converter which samples and holds an input voltage to generate a sampled-and-held input voltage, outputs the sampled-and-held input voltage to an upper analog-to-digital converter, receives upper data from the upper analog-to-digital converter, generates a residual voltage on the basis of the sampled-and-held input voltage and the upper data, samples and holds the residual voltage to generate a sampled-and-held residual voltage, and outputs the sampled-and-held residual voltage to a lower analog-to-digital converter; the upper analog-to-digital converter which is composed of a plurality of complementary dynamic amplifiers and one time domain interpolation unit, and generates the upper data on the basis of a reference voltage and the sampled-and-held input voltage; the lower analog-to-digital converter which is composed of a plurality of complementary dynamic amplifiers and one time domain interpolation unit, and generates the lower data on the basis of the sampled-and-held residual voltage; and a digital encoder which generates output data by encoding the upper data and the lower data.

Description

Device and method for converting an analog signal to a digital signal in a two-stage flash analog-to-digital converter

[0001] The present invention relates to a two-stage flash analog-to-digital converter, and more specifically, to an apparatus and method for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter.

[0002] A two-step flash Analog to Digital Converter (hereinafter referred to as 'ADC') is an ADC capable of increasing bit resolution at the expense of lowering the high-speed sampling rate. A two-step flash ADC includes a higher ADC (CADC, also used interchangeably with coarse ADC), a lower ADC (FADC, also used interchangeably with fine ADC), and a Digital to Analog Converter (hereinafter referred to as 'DAC'). Here, both the higher ADC and the lower ADC are flash ADCs. Assuming the resolution of the two-step flash ADC is N bits (hereinafter referred to as 'Nbit'), the higher ADC has a resolution of the upper C bit (hereinafter referred to as 'Cbit'), and the lower ADC has a resolution of the lower F bit (hereinafter referred to as 'Fbit'). Here, N is set to be less than or equal to 'C+F'.

[0003] In a two-stage flash ADC, the upper ADC converts the input voltage, which is an analog signal, into upper data, and the DAC converts the upper data into an upper analog voltage. The lower ADC converts the difference between the input analog voltage and the upper analog voltage into lower data. The digital encoder combines the upper data and the lower data to generate the final output data, which is a digital signal.

[0004] Meanwhile, when the resolution of a conventional 2-stage flash ADC is 7 bits, the upper ADC is composed of 6 comparators and the lower ADC is composed of 5 dynamic amplifiers, which had the problem of high power consumption.

[0005] Therefore, measures are needed to resolve these problems.

[0006] [Prior Art Literature]

[0007] [Patent Literature]

[0008] Republic of Korea Registered Patent Publication No. 10-2199016

[0009] The objective of the present invention to solve the above-mentioned problems is to convert an analog signal into a digital signal through a two-stage flash ADC comprising multiple complementary amplifiers instead of multiple comparators and multiple dynamic amplifiers.

[0010] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the present invention belongs from the description below.

[0011] The device of the present invention for achieving the above-mentioned purpose comprises: a capacitive digital-to-analog converter that samples and holds an input voltage to generate a sample and hold input voltage, outputs the sample and hold input voltage to an upper analog-to-digital converter, receives upper data from the upper analog-to-digital converter, generates a residual voltage based on the sample and hold input voltage and the upper data, samples and holds to generate a sample and hold residual voltage, and outputs the sample and hold residual voltage to a lower analog-to-digital converter; the upper analog-to-digital converter, which is composed of a plurality of complementary dynamic amplifiers and a time domain interpolation unit, and generates the upper data based on a reference voltage and the sample and hold input voltage; the lower analog-to-digital converter, which is composed of a plurality of complementary dynamic amplifiers and a time domain interpolation unit, and generates the lower data based on the sample and hold residual voltage; and a digital encoder that encodes the upper data and the lower data to generate output data.

[0012] A method of the present invention for achieving the above-mentioned purpose comprises: a capacitive digital-to-analog converter generating a sample-and-hold input voltage by sampling and holding an input voltage; an upper analog-to-digital converter generating upper data based on a reference voltage and the sample-and-hold input voltage through a plurality of complementary dynamic amplifiers and a time domain interpolation unit; the capacitive digital-to-analog converter generating a residual voltage based on the upper data and the sample-and-hold input voltage and generating a sample-and-hold residual voltage by sampling and holding; a lower analog-to-digital converter generating lower data based on the sample-and-hold residual voltage through a plurality of complementary dynamic amplifiers and a time domain interpolation unit; and a digital encoder encoding the upper data and the lower data to generate output data.

[0013] The effect of the present invention according to the above configuration is to reduce power consumption by converting an analog signal into a digital signal through a two-stage flash ADC including a plurality of complementary amplifiers.

[0014] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the configuration of the invention described in the detailed description of the invention or the claims.

[0015] Figure 1 is a diagram illustrating the configuration of a two-stage flash ADC according to general technology.

[0016] Figure 2 is a diagram illustrating the configuration of a two-stage flash ADC with a resolution of 7 bits according to general technology.

[0017] FIG. 3 is a diagram illustrating the configuration of a two-stage flash ADC according to one embodiment of the present invention.

[0018] FIG. 4 is a diagram illustrating the configuration of a two-stage flash ADC with 7-bit resolution according to one embodiment of the present invention.

[0019] FIG. 5 is a diagram illustrating the structure of a complementary dynamic amplifier according to one embodiment of the present invention.

[0020] FIG. 6 is a flowchart for converting an analog signal into a digital signal in a two-stage flash ADC according to one embodiment of the present invention.

[0021] The present invention will be described below with reference to the attached drawings. However, the present invention may be implemented in various different forms and is therefore not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been given similar reference numerals.

[0022] Throughout the specification, when it is stated that a part is "connected (connected, in contact, combined)" with another part, this includes not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other members interposed between them. Furthermore, when it is stated that a part "includes" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but rather allows for the inclusion of additional components.

[0023] The terms used in this specification are used merely to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprising" or "having" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0024] The present invention will be described in detail below with reference to the attached drawings.

[0025]

[0026] Figure 1 is a diagram illustrating the configuration of a two-stage flash ADC according to general technology.

[0027] Referring to FIG. 1, the two-stage flash ADC includes a resistor string (101), a capacitive digital to analog converter (hereinafter referred to as 'Cap-DAC'), a CADC (105), an FADC (107), and a digital encoder (109).

[0028] Looking at each component, the resistor string (101) is connected to the CADC (105), and 2 c It consists of two identical resistors. The resistor string (101) is 2 between the upper and lower voltages. c Divide equally into 2 cbit -1 reference voltage (V CR [n]) is generated, and the generated reference voltage is output to the CADC (105). For example, between the upper and lower terminal voltages, the upper voltage (V RP ) and lower voltage (V RN It can show the difference between ).

[0029] The CADC (105) is connected to the Cap-DAC (103) and the digital encoder (109), and 2 cbit It consists of one comparator. The CADC (105) obtains a reference voltage (V) from the resistor string (101). CR [n]) is received as input, and the input voltage (V) sampled and held from the Cap-DAC (103) is received. B [n]) is received as input. For example, the sample-and-hold input voltage is based on the reference voltage, and the input voltage (V IN It can be generated by sample-and-holding ). And the CADC (105) uses the sample-and-hold input voltage to generate upper data (C o [n]) is generated, and the generated upper data is output to the digital encoder (109) and Cap-DAC (103). For example, the upper data may be a thermometer code.

[0030] Cap-DAC (103) includes a capacitor array composed of a plurality of capacitors and a switch cell array composed of a plurality of switch cells, the lower part of the capacitor array is connected to the switch cell array and CADC (105), and the upper part of the capacitor array is connected to FADC (107).

[0031] The Cap-DAC (103) receives the input voltage, upper reference voltage, and lower reference voltage through the switch cell array. The Cap-DAC (103) samples and holds the input voltage to generate the sampled and held input voltage and outputs the sampled and held input voltage to the CADC (105). The Cap-DAC (103) receives upper data from the CADC (105) and, based on the upper data received through the switch cell array, applies the upper and lower reference voltages to the lower portion of at least one capacitor in the capacitor array to generate a Digital-to-Analog Conversion (hereinafter referred to as 'DAC voltage'). At this time, since the input voltage is charged in the capacitor, a residual voltage representing the difference between the input voltage and the DAC voltage is generated at the upper portion of the capacitor. The Cap-DAC (103) samples and holds the residual voltage to generate the sampled and held residual voltage (V RES It generates ) and outputs the sample-and-hold residual voltage to the FADC (107).

[0032] FADC (107) is connected to Cap-DAC (103) and consists of a plurality of voltage-to-time converters and a time-domain interpolation unit (hereinafter referred to as 'IP'). For example, the voltage-to-time converters may be dynamic amplifiers. For example, the time-domain interpolation unit may include a TDI array and an SR latch array, and may perform an 8x time-domain interpolation technique through the TDI array and the SR latch array. FADC (107) receives a sample-and-hold residual voltage from Cap-DAC (103), generates sub-data based on the difference between the built-in reference voltage and the sample-and-hold residual voltage, and outputs the generated sub-data to a digital encoder (109). For example, the built-in reference voltage may represent a reference voltage provided by FADC (107) itself. For example, the sub-data may be a thermometer code.

[0033] The digital encoder (109) is connected to the CADC (105) and FADC (107). The digital encoder (109) receives upper data from the CADC (105) and lower data from the FADC (107), and encodes the upper data and lower data to generate digital data. For example, if both the upper and lower data are thermometer codes, the digital encoder (150) can compress them into a binary form to generate N bits of digital data corresponding to the resolution of a 2-stage flash ADC.

[0034] In general technology, two sub-ADCs share a single sample-and-hold, thereby resolving mismatch between the two sub-ADCs and facilitating wideband input sampling.

[0035]

[0036] Figure 2 is a diagram illustrating the configuration of a two-stage flash ADC with a resolution of 7 bits according to general technology.

[0037] Referring to FIG. 2, in a 7-bit 2-stage flash ADC, the CADC (201) is composed of 6 comparators. The CADC (201) receives a reference voltage (V) from a resistor string (101). CR [6]) is received as input, and the input voltage (V sample-and-hold) from the Cap-DAC (103) is received. B [6]) is received as input. And CADC (201) uses the sample-and-hold input voltage to obtain upper data (C o [6]) is generated, and the generated upper data is output to the digital encoder (109) and Cap-DAC (103).

[0038] FADC (203) is connected to Cap-DAC (103) and consists of five dynamic amplifiers and one IP. FADC (203) receives the sample-and-hold residual voltage from Cap-DAC (103), generates sub-data (F0

[0033] ) based on the difference between the built-in reference voltage and the sample-and-hold residual voltage, and outputs the generated sub-data to the digital encoder (109).

[0039] That is, in general technology, multiple comparators and multiple voltage-time converters are required for each of the CADC (201) and FADC (203). In particular, to achieve 7-bit resolution, 6 comparators and 5 voltage-time converters are required for each of the CADC (201) and FADC (203). However, the use of these multiple comparators and multiple voltage-time converters had the problem of increasing the power consumption of the 2-stage flash ADC.

[0040] Therefore, one embodiment of the present invention proposes a solution to solve these problems.

[0041]

[0042] FIG. 3 is a diagram illustrating the configuration of a two-stage flash ADC according to one embodiment of the present invention.

[0043] Referring to FIG. 3, the two-stage flash ADC includes a resistor string (301), a Cap-DAC (303), a CADC (305), an FADC (307), and a digital encoder (309).

[0044] Since the resistor string (301), Cap-DAC (303), and digital encoder (309) shown in FIG. 3 correspond to the resistor string (101) and digital encoder (109) shown in FIG. 1, the description of the resistor string (301) and digital encoder (309) is omitted.

[0045] The CADC (305) is connected to the Cap-DAC (303) and the digital encoder (309) and consists of (N-1) / 2 complementary dynamic amplifiers and one IP. For example, N bits can represent the resolution of a 2-stage flash ADC. Meanwhile, the complementary dynamic amplifier consists of a first dynamic amplifier that amplifies a negative voltage and a second dynamic amplifier that amplifies a positive voltage. In one embodiment of the present invention, the CADC (305) is implemented as the first dynamic amplifier that amplifies the negative voltage of the complementary dynamic amplifier.

[0046] The CADC (305) obtains a reference voltage (V) from the resistor string (301). CR [n]) is received as input, and the input voltage (V) sampled and held (input voltage (V) from the Cap-DAC (303) is received. B [n]) is received as input. Then, the CADC (305) uses the sample-and-hold input voltage to obtain upper data (C o [6n-1]) is generated, and the generated upper data is output to the digital encoder (309) and Cap-DAC (303).

[0047] Cap-DAC (303) includes a capacitor array composed of multiple capacitors and a switch cell array composed of multiple switch cells, the lower part of the capacitor array is connected to the switch cell array and CADC (305), and the upper part of the capacitor array is connected to FADC (307).

[0048] Cap-DAC (303) receives input voltage, upper reference voltage, and lower reference voltage through a switch cell array. Cap-DAC (303) samples and holds the input voltage to generate a sampled and held input voltage and outputs the sampled and held input voltage to CADC (305). Cap-DAC (303) receives upper data from CADC (305) and generates a DAC voltage by applying the upper and lower reference voltages to the lower part of at least one capacitor in the capacitor array based on the upper data received through the switch cell array. At this time, since the input voltage is charged in the capacitor, a residual voltage representing the difference between the input voltage and the DAC voltage is generated at the upper part of the capacitor. Cap-DAC (303) samples and holds the residual voltage to generate a sampled and held residual voltage and outputs the sampled and held residual voltage to FADC (307).

[0049] FADC (307) is connected to Cap-DAC (303) and consists of (N-1) / 2 multiple complementary dynamic amplifiers and one IP. According to one embodiment of the present invention, FADC (307) is implemented as a second dynamic amplifier that amplifies the positive voltage of the complementary dynamic amplifier. That is, since CADC (305) uses a first dynamic amplifier and FACD (307) uses a second dynamic amplifier, CADC (305) and FACD (307) share multiple complementary dynamic amplifiers. Also, since the output of the first dynamic amplifier of CADC (305) is input to the IP and the output of the second dynamic amplifier of FACD (307) is input to the same IP, CADC (305) and FACD (307) also share the IP.

[0050] FADC (307) receives the sample-and-hold residual voltage from Cap-DAC (303), generates sub-data (F0[6n-1]) based on the difference between the built-in reference voltage and the sample-and-hold residual voltage, and outputs the generated sub-data to the digital encoder (309).

[0051]

[0052] FIG. 4 is a diagram illustrating the configuration of a two-stage flash ADC with 7-bit resolution according to one embodiment of the present invention.

[0053] Referring to FIG. 4, in a 7-bit 2-stage flash ADC, the CADC (401) is composed of three complementary dynamic amplifiers and one IP. The CADC (301) receives a reference voltage (V) from a resistor string (301). CR [3]) is received as input, and the input voltage (V sample-and-hold) from the Cap-DAC (303) is received. B [3]) receives input. And CADC (401) uses the sample-and-hold input voltage to receive upper data (C o

[0017] ) is generated, and the generated upper data is output to the digital encoder (309) and Cap-DAC (303).

[0054] FADC (403) is connected to Cap-DAC (303) and consists of three complementary dynamic amplifiers and one IP. FADC (403) receives a sample-and-hold residual voltage from Cap-DAC (303), generates sub-data (F0

[0017] ) based on the difference between the built-in reference voltage and the sample-and-hold residual voltage, and outputs the generated sub-data to a digital encoder (309). For example, the size of the sub-data may be the same as the size of the upper data.

[0055] Meanwhile, in the complementary dynamic amplifier (405), a first dynamic amplifier that amplifies negative voltage receives the sample-and-hold input voltage of the CADC (401), and a second dynamic amplifier that amplifies positive voltage receives the sample-and-hold residual voltage of the FADC (403). Therefore, since the CADC (401) and FADC (403) can share the complementary dynamic amplifier, the CADC (401) and FADC (403) in a 7-bit 2-stage flash ADC can be implemented with three complementary dynamic amplifiers and one IP. The total ADC (hereinafter referred to as 'TADC') (407) can be formed by including both the CADC (401) and FADC (403).

[0056] As such, since the CADC (401) is implemented with a plurality of complementary dynamic amplifiers and a single IP, the CADC (401) can perform time-domain signal conversion like the FADC (403), and thus a time-domain interpolation technique can be applied to improve power efficiency. Therefore, one embodiment of the present invention can perform data conversion of the CADC (401) by recycling the current used in the FADC (403). Furthermore, one embodiment of the present invention can reduce the number of comparators required in the CADC (201), thereby improving power efficiency, area, and input bandwidth.

[0057] Through this configuration, one embodiment of the present invention can reduce power consumption by converting an analog signal into a digital signal through a two-stage flash ADC including a plurality of complementary dynamic amplifiers.

[0058]

[0059] FIG. 5 is a diagram illustrating the structure of a complementary dynamic amplifier according to one embodiment of the present invention.

[0060] Looking at the structure (501) of the complementary dynamic amplifier shown in FIG. 5, the complementary dynamic amplifier is composed of three NPN type transistors, three PNP type transistors, and two inverting amplifiers.

[0061] If we look at the timing chart (503) of this complementary dynamic amplifier, the reference signal (Φ c When ) is Low, the first node (S P It can be confirmed that voltage is applied linearly to ). And when the reference signal is High, the second node (S M It can be confirmed that voltage is applied linearly to ).

[0062]

[0063] FIG. 6 is a flowchart for converting an analog signal into a digital signal in a two-stage flash ADC according to one embodiment of the present invention.

[0064] Referring to FIG. 6, the Cap-DAC (303) samples and holds the input voltage in step 601 to generate the sample and hold input voltage, and outputs the sample and hold input voltage to the CADC (305).

[0065] In step 603, the CADC (305) generates upper data based on a reference voltage and a sample-and-hold input voltage through a plurality of complementary dynamic amplifiers and one IP, and outputs the generated upper data to the Cap-DAC (303) and digital encoder (309).

[0066] In step 605, the Cap-DAC (303) generates a residual voltage based on the upper data and the sample-and-hold input voltage. Then, the Cap-DAC (303) samples and holds the generated residual voltage to produce a sample-and-hold residual voltage and outputs the sample-and-hold residual voltage to the FADC (307).

[0067] In step 607, the FADC (307) generates sub-data using a sample-and-hold residual voltage through a plurality of complementary dynamic amplifiers and one IP, and outputs the generated sub-data to a digital encoder (309).

[0068] In step 609, the digital encoder (309) encodes the upper data and lower data to produce output data, which is digital data.

[0069] Meanwhile, in the complementary dynamic amplifier, a first dynamic amplifier that amplifies negative voltage receives the sample-and-hold input voltage of the CADC (305), and a second dynamic amplifier that amplifies positive voltage receives the sample-and-hold residual voltage of the FADC (307). Therefore, the CADC (305) and the FADC (307) share a single IP with multiple complementary dynamic amplifiers.

[0070] Through this process, one embodiment of the present invention can reduce power consumption by converting an analog signal into a digital signal through a two-stage flash ADC including a plurality of complementary dynamic amplifiers.

[0071] This achievement is the result of research conducted with funding from the government (Ministry of Science and ICT) and supported by the National Research Foundation of Korea (RS-2023-00274028).

[0072]

[0073] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0074] The scope of the present invention is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present invention.

Claims

1. A capacitive digital-to-analog converter that samples and holds an input voltage to generate a sample and hold input voltage, outputs the sample and hold input voltage to an upper analog-to-digital converter, receives upper data from the upper analog-to-digital converter, generates a residual voltage based on the sample and hold input voltage and the upper data, samples and holds to generate a sample and hold residual voltage, and outputs the sample and hold residual voltage to a lower analog-to-digital converter; The upper analog-to-digital converter, which is composed of a plurality of complementary dynamic amplifiers and a time domain interpolation unit and generates the upper data based on a reference voltage and the sampled input voltage; The lower analog-to-digital converter, which is composed of a plurality of complementary dynamic amplifiers and a time domain interpolation unit and generates the lower data based on the sample-and-hold residual voltage; and A device for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter comprising a digital encoder that encodes the upper data and the lower data to generate output data.

2. In Paragraph 1, A device for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter, characterized in that the upper analog-to-digital converter and the lower analog-to-digital converter share the complementary dynamic amplifiers and the time domain interpolation unit.

3. In Paragraph 2, A device for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter, characterized in that among the above complementary dynamic amplifiers, a plurality of first dynamic amplifiers that amplify a positive voltage are used in the lower analog-to-digital converter, and a plurality of second dynamic amplifiers that amplify a negative voltage are used in the upper analog-to-digital converter.

4. In Paragraph 1, A device for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter, characterized in that the upper analog-to-digital converter applies a time domain interpolation technique through the complementary dynamic amplifiers and the time domain interpolation unit.

5. In Paragraph 1, A device for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter, characterized in that the size of the lower data is the same as the size of the upper data.

6. A process in which a capacitive digital-to-analog converter samples and holds an input voltage to generate a sample-and-held input voltage, A process in which an upper analog-to-digital converter generates upper data based on a reference voltage and the sampled input voltage through a plurality of complementary dynamic amplifiers and a time domain interpolation unit, The above capacitive digital-to-analog converter generates a residual voltage based on the above upper data and the above sample-and-hold input voltage, and the process of generating a sample-and-hold residual voltage, A process in which a lower analog-to-digital converter generates lower data based on the sampled residual voltage through a plurality of complementary dynamic amplifiers and a time domain interpolator, and A method for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter, comprising a process in which a digital encoder encodes the upper data and the lower data to generate output data.

7. In Paragraph 6, A method for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter, characterized in that the upper analog-to-digital converter and the lower analog-to-digital converter share the complementary dynamic amplifiers and the time domain interpolation unit.

8. In Paragraph 7, A method for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter, characterized in that among the above complementary dynamic amplifiers, a plurality of first dynamic amplifiers that amplify a positive voltage are used in the lower analog-to-digital converter, and a plurality of second dynamic amplifiers that amplify a negative voltage are used in the upper analog-to-digital converter.

9. In Paragraph 6, A method for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter, characterized in that the upper analog-to-digital converter applies a time domain interpolation technique through the complementary dynamic amplifiers and the time domain interpolation unit.

10. In Paragraph 6, A method for converting an analog signal into a digital signal in a two-stage flash analog-to-digital converter, characterized in that the size of the lower data is the same as the size of the upper data.

Images