Photodetector assembly having three-dimensional inductor

The three-dimensional inductor structure in photodetector assemblies addresses parasitic capacitance issues by integrating on-chip, reducing footprint and maintaining high bandwidth performance.

WO2026155691A1PCT designated stage Publication Date: 2026-07-23GLOBALFOUNDRIES SINGAPORE PTE LTD
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
GLOBALFOUNDRIES SINGAPORE PTE LTD
Filing Date
2025-01-15
Publication Date
2026-07-23

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Abstract

A photodetector assembly comprises: a stacked structure having a cladding layer, a buried oxide layer, a semiconductor substrate, wherein the cladding layer includes a first side and a second opposed side which abuts a first side of the buried oxide layer, wherein the semiconductor substrate includes a first side which abuts a second opposed side of the buried oxide layer and further includes a second opposed side; a photodetector device embedded in the stacked structure; an inductor operably coupled to the photodetector device, wherein the inductor is arranged on the first side of the cladding structure and at least partially traverses the stacked structure; a signal electrode operably coupled to the photodetector device by using the inductor; and at least one ground electrode operably coupled to the photodetector device, wherein the signal electrode and the ground electrode are arranged on the first side of the cladding layer.
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Description

[0001] PHOTODETECTOR ASSEMBLY HAVING THREE-DIMENSIONAL INDUCTOR

[0002] FIELD OF THE INVENTION

[0003]

[0001] The present invention relates to optoelectronic devices, and more particularly to high-speed photodetectors having on-chip inductors which are three-dimensional structures to achieve low inductor footprint.

[0004] BACKGROUND

[0005]

[0002] Recently, driven by the new technologies such as cloud computing and artificial intelligence (Al), the amount of data generated every day grows exponentially, bringing significant challenges to current optical interconnect systems. Besides, data communication in long-haul telecommunication and data centres also requires high-speed interconnects. To increase the interconnect capacity, highspeed photodetectors are thus in high demand as the key component of the highspeed interconnect systems. Additionally, high-speed photodetectors find applications in heterodyne and homodyne coherent detection, and for millimetrewave signal generation.

[0006]

[0003] A photodetector typically converts a received optical signal into an output electrical signal. Besides, a high-speed photodetector can detect the fast-changing optical signal.

[0007]

[0004] A photodetector device typically includes various components such as device layer, optical absorption layers, optical coupling structures, metal connection layers, electrodes and passivation layers. The device components are positioned close to one another for operation of the photodetector. The positioning and proximity of these components inevitably result in undesired capacitance between the components, known as parasitic capacitance. Parasitic capacitance typically exists in a junction of two or more components or between electrodes. Such capacitance impacts overall performance of the photodetector, such as limiting the speed of operation of the photodetectors.

[0008]

[0005] To address the above issue, on-chip inductors have been developed in which an inductor may be connected to the electrodes of the photodetector to offset part of parasitic capacitance and improve bandwidth of the photodetector by impedance peaking. However, on-chip inductors significantly increase the footprint of impedance peaked photodetectors and thus limit their applications.SUMMARY

[0009]

[0006] According to an aspect, a photodetector assembly comprises:

[0010] a stacked structure having a cladding layer, a buried oxide layer, a semiconductor substrate, wherein the cladding layer includes a first side and a second opposed side which abuts a first side of the buried oxide layer, wherein the semiconductor substrate includes a first side which abuts a second opposed side of the buried oxide layer and further includes a second opposed side;

[0011] a photodetector device embedded in the stacked structure;

[0012] an inductor operably coupled to the photodetector device, wherein the inductor is arranged on the first side of the cladding structure and at least partially traverses the stacked structure;

[0013] a signal electrode operably coupled to the photodetector device by using the inductor; and

[0014] at least one ground electrode operably coupled to the photodetector device, wherein the signal electrode and the ground electrode are arranged on the first side of the cladding layer.

[0015]

[0007] In some embodiments, the inductor includes:

[0016] a plurality of first conductive layers embedded in the stacked structure;

[0017] a plurality of second conductive layers arranged on the first side of the cladding layer; and

[0018] a plurality of vias traversing the stacked structure and respectively interconnecting the first conductive layers and the second conductive layers.

[0019]

[0008] In some embodiments, the first conductive layers are embedded in the cladding layer and arranged on the first side of the buried oxide layer, wherein the vias at least partially traverse the cladding layer. A height of the second vias may be between 1 pm to 10 pm.

[0020]

[0009] In some embodiments, the first conductive layers are embedded in the buried oxide layer, wherein the vias fully traverse the cladding layer and at least partiallytraverse the buried oxide layer. A height of the second vias may be between 2 gm to 20 pm.

[0021]

[0010] In some embodiments, the first conductive layers are arranged on the second side of the semiconductor substrate, wherein the vias fully traverse the cladding layer, the buried oxide layer, and the semiconductor substrate. A height of the second vias may be between 100 pm to 1000 pm.

[0022]

[0011] In some embodiments, the inductor includes a coil-like arrangement, wherein an axis of the coil-like arrangement is parallel to planar directions of the cladding layer, the buried oxide layer, and the semiconductor substrate.

[0023]

[0012] In some embodiments, the coil-like arrangement includes a square or rectangle cross-section profile along a plane traversing the cladding layer, the buried oxide layer, and the semiconductor substrate.

[0024]

[0013] In some embodiments, the photodetector is embedded in the cladding layer or arranged on the first side of the semiconductor substrate.

[0025]

[0014] In some embodiments, the at least one ground electrode includes two or more ground electrodes which are arranged on the first side of the cladding layer, are operably coupled to the photodetector device.

[0026] BRIEF DESCRIPTION OF THE DRAWINGS

[0027]

[0015] Figure 1A shows a top see-through view of a high-speed photodetector assembly in accordance with an embodiment;

[0028]

[0016] Figure 1B shows a cross-section view taken along arrow 1B-1B indicated in Figure 1A;

[0029]

[0017] Figure 2A shows a top see-through view of a high-speed photodetector assembly in accordance with an embodiment;

[0030]

[0018] Figure 2B shows a cross-section view taken along arrow 2B-2B indicated in Figure 2A;

[0031]

[0019] Figure 3A shows a top see-through view of a high-speed photodetector assembly in accordance with an embodiment;

[0032]

[0020] Figure 3B shows a cross-section view taken along arrow 3B-3B indicated in Figure 3A;

[0033]

[0021] Figure 4A shows a top see-through view of a high-speed photodetector assembly in accordance with an embodiment;

[0022] Figure 4B shows a cross-section view taken along arrow 4B-4B indicated in Figure 4A;

[0034]

[0023] Figure 5A shows a top see-through view of a high-speed photodetector assembly in accordance with an embodiment;

[0035]

[0024] Figure 5B shows a cross-section view taken along arrow 5B-5B indicated in Figure 5A;

[0036]

[0025] Figure 6A shows a top see-through view of a high-speed photodetector assembly in accordance with an embodiment;

[0037]

[0026] Figure 6B shows a cross-section view taken along arrow 6B-6B indicated in Figure 6A;

[0038]

[0027] Figure 7 shows a conventional planar inductor; and

[0039]

[0028] Figure 8 shows a top see-through view of a three-dimensional inductor in accordance with at least some embodiments.

[0040]

[0029] It should be understood that the appended drawings are not necessarily to scale, presenting a somewhat simplified representation of various features illustrative of the basic principles of the invention. The specific design features of the photodetector assembly as disclosed here, including, for example, the specific dimensions of the inductors, buried oxide layer, electrodes will be determined in part by the particular intended application and use environment. Certain features of the illustrated embodiments have been enlarged or distorted relative to others to help provide clear understanding. In particular, thin features may be thickened, for example, for clarity of illustration. All references to direction and position, unless otherwise indicated, refer to the orientation illustrated in the drawings.

[0041] DETAILED DESCRIPTION

[0042]

[0030] In the following description, numerous specific details are set forth in order to provide a thorough understanding of various illustrative and non-limiting embodiments. It will be understood, however, to one skilled in the art, that embodiments of the invention may be practiced without some or all of these specific details. It is understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the invention. In the drawings, like reference labels or numerals refer to same or similar functionalities or features throughout the several views.

[0031] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and / or combinations and / or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0043]

[0032] It should be understood that the articles "a", "an" and "the" as used with regard to a feature or element include a reference to one or more of the features or elements. The term "and / or" includes any and all combinations of one or more of the associated feature or element. The terms "comprising", "including", "having", and any of their related terms, as used in description and claims, are intended to be open-ended and mean that there may be additional features or elements other than the listed ones. Identifiers such as "first", "second", "third", and so on, are used merely as labels, and are not intended to impose numerical requirements on their objects, nor construed in a manner imposing any relative position or time sequence between limitations. The term “to” may include a reference to “configured to”, "adapted to", and "constructed and arranged to" which may be used interchangeably.

[0044]

[0033] The term “coupled” and the phrase “operably coupled” may be used to include a reference to operational sense and may also include, but not necessarily limited to, a physical, optical, and / or electrical connection or coupling which may be direct or indirect. Thus, for example, two devices may be coupled or connected directly, or indirectly via one or more intermediary devices. Based on the present disclosure, a person of ordinary skill in the art will appreciate a variety of ways in which coupling exists in accordance with the aforementioned definition. The terms “coupled” and “connected” may be used interchangeably. The term “operably” includes a reference to the term “operatively”.

[0045]

[0034] The term “abut” and its associated term may include a reference to “arranged on” or “arranged in contact with” which may be used interchangeably.

[0046]

[0035] Embodiments provide high-speed photodetector assemblies, each having an on-chip three-dimensional inductor which is capable of reducing photodetector assembly and inductor footprint while introducing inductance to offset parasitic capacitance of photodiode by impedance peaking and to enhance bandwidth.

[0036] In embodiments, a photodetector assembly comprises a stacked structure; a photodetector device which is embedded in the stacked structure; an inductor operably coupled to the inductor, wherein the inductor is arranged on the stacked structure and at least partially traverses the stacked structure to provide a three-dimensional inductor structure; a signal electrode operably coupled to the photodetector device by using the inductor and arranged on the stacked structure; and at least one ground electrode operably coupled to the photodetector and arranged on the stacked structure. The signal electrode, the ground electrode(s), and at least part of the inductor are arranged on the same side of the stacked structure. The stacked structure may include a Silicon-on-lnsulator (SOI) structure.

[0047]

[0037] Reference is made to Figures 1A and 1B showing a photodetector assembly 100 in accordance with an embodiment. In this embodiment, a signal electrode 103 and two ground electrodes 104 are provided; the inductor 120 at least partially traverses the stacked structure 105, e g., the inductor 120 partially traverses a cladding layer 106 without traversing into a buried oxide layer 110 or a semiconductor substrate 114.

[0048]

[0038] The photodetector assembly 100 comprises a stacked structure 105; a photodetector device 102; a three-dimensional inductor 120; and signal and ground electrodes 103, 104.

[0049]

[0039] The stacked structure 105 includes a SOI structure which includes a cladding layer 106, a buried oxide layer 110, and a semiconductor substrate 114, and which may be fabricated by Complementary Metal Oxide Semiconductor (CMOS) processes. The cladding layer 106 includes a first side 107 and a second opposed side 108. The first side 107 of the cladding layer 106 is provided with signal and ground electrodes 103, 104 while the second side 108 of the cladding layer 106 abuts a buried oxide layer 110. The cladding layer 106 may include silicon dioxide. The buried oxide layer 110 includes a first side 111 and a second opposed side 112. The first side 111 of the buried oxide layer 110 abuts the second side 108 of the cladding layer 106 while the second side 112 of the buried oxide layer 110 abuts a semiconductor substrate 114. The buried oxide layer 110 may include silicon oxide. The semiconductor substrate 114 includes a first side 115 and a second opposed side 116. The first side 115 of the semiconductor substrate 114 abuts the second side 112 of the buried oxide layer 110. The semiconductor substrate 114 may include silicon. The stacked structure 105 includes a first side which is analogous to the first side 107 of the cladding layer106, and further includes a second opposed side which is analogous to the second side 116 of the semiconductor substrate 114.

[0050]

[0040] The photodetector device 102 is embedded in the stacked structure 105, e.g., the photodetector device 102 is embedded in the cladding layer 106 and abuts the first side 111 of the buried oxide layer 110. The photodetector device 102 is operable to convert a received optical signal or electromagnetic radiation in predetermined bands into an output electrical or current signal, and may include arrangements, e.g., semiconductor device layers for implementing p-n or p-i-n junction, which are known to persons skilled in the art and hence not shown.

[0051]

[0041] The inductor 120 is a three-dimensional structure having a length, a width, and a height, which are taken in mutually transverse directions. The length and the width provide the inductor 120 with planar dimensions on the first side 107 of the stacked structure 105 or cladding layer 106, while the height provides the inductor 120 with height or depth dimension that extends at least partially into the stacked structure 105, e.g., traverses a cladding layer 106, or both the cladding layer 106 and the buried oxide layer 110, or all of the cladding layer 106, the buried oxide layer 110, and the semiconductor substrate 114. The height or depth dimension is therefore transverse to a plane defined by the length and the width. The height or depth dimension may be substantially similar to, greater or substantially greater than the length and / or width dimensions. The inductor 120 is operatively coupled to the photodetector device 102 directly or indirectly, such as by using a first via 117 which traverses the stacked structure 105, e.g., cladding layer 106, and interconnects the photodetector device 102 and the inductor 120.

[0052]

[0042] The inductor 120 includes a plurality of first conductive layers 121 embedded in the stacked structure 105 while being arranged on the first side 111 of the buried oxide layer 110, a plurality of second conductive layers 122 arranged on the first side 107 of the stacked structure 105 or cladding layer 106, and a plurality of second vias 123 traversing the stacked structure 105, e.g., cladding layer 106, and respectively interconnecting the first conductive layers 121 and the second conductive layers 122. The first conductive layers 121 and the second conductive layers 122 may include the same or different material, such as but not limited to metal and / or conductive material. The first conductive layers 121 and the second conductive layers 122 may have same or different thickness. The first via 117 and the second vias 123 may include the same or different material, such as but not limited to metal and / or conductive material. Thefirst conductive layers 121 and the second conductive layers 122, and the vias 117, 123 may include the same or different material, such as but not limited to metal and / or conductive material.

[0053]

[0043] The signal and ground electrodes 103, 104 are arranged on the first side 107 of the stacked structure 105 or cladding layer 106. The signal electrode 103 is operably coupled to the photodetector device 102 by using the inductor 120, i.e., the inductor 120 interconnects the signal electrode 103 and the photodetector device 102. The ground electrode(s) 104 are operably coupled to the photodetector device 102 such as by using via(s), e.g., third via(s) which are not shown.

[0054]

[0044] In the embodiment of Figures 1A and 1B, the first conductive layers 121 are embedded in the cladding layer 106. In particular, most of the embedded first conductive layers 121 abut or are arranged on the first side 111 of the buried oxide layer 110. Accordingly, the second vias 123 at least partially traverse the cladding layer 106. A distance between most of the first conductive layers 121 and most of the second conductive layers 122 may be denoted by ti which is analogous to a height of the second vias 123. This distance ti generally applies to most first conductive layers 121 and second conductive layers 122 which are interconnected by the second vias 123. However, at least one of the first conductive layers 121 which interconnects the first via 117 and a corresponding second via 123 may not be arranged on the first side 111 of the buried oxide layer 110, i.e., it may be embedded within the cladding layer 106 while being spaced apart from the first side 111 of the buried oxide layer 110, hence a distance between this conductor layer and a corresponding second layer is less than ti (see rightmost first conductive layer 121 in Figure 1B). Such first conductive layer 121 may be arranged at one end of the length of the inductor 120 which is most proximate to the photodetector device 102, i.e., most proximately coupled to the photodetector device 102. Furthermore, in the embodiment of Figures 1A and 1B, the ground electrodes 104 include two ground electrodes.

[0055]

[0045] Reference is made to Figures 2A and 2B showing a photodetector assembly 200 in accordance with an embodiment. This embodiment is similar to the embodiment of Figures 1A and 1B, except that this embodiment includes a signal electrode 103 and a ground electrode 104. For the sake of brevity, a description of these similar features would not be repeated. Accordingly, an inductor 220, first conductive layers 221 , second conductive layers 222, a first via 217, and second vias 223 of Figures 2A and 2B are analogous to the inductor 120, the first conductive layers 121 , the secondconductive layers 122, the first via 117, and the second vias 123 of Figures 1A and 1B.

[0056]

[0046] Reference is made to Figures 3A and 3B showing a photodetector assembly 300 in accordance with an embodiment. In this embodiment, a signal electrode 103 and two ground electrodes 104 are provided; the inductor 320 fully traverses a cladding layer 106 and at least partially traverses the buried oxide layer 106 without traversing a chip substrate 114.

[0057]

[0047] The photodetector assembly 300 comprises a stacked structure 105; a photodetector device 102; an inductor 320; and signal and ground electrodes 103, 104. The stacked structure 105, the photodetector device 102, and the signal and ground electrodes 103, 104 are similar to the embodiment of Figures 1A and 1B and hence a description of these similar features would not be repeated for the sake of brevity. Accordingly, an inductor 320, first conductive layers 321 , second conductive layers 322, a first via 317, and second vias 323 of Figures 3A and 3B are analogous to the inductor 120, the first conductive layers 121, the second conductive layers 122, the first via 117, and the second vias 123 of Figures 1A and 1B.

[0058]

[0048] The inductor 320 is mostly similar to the inductor 120 of the embodiment of Figures 1 A and 1 B, except that most of the first conductive layers 321 of inductor 320 of Figures 3A and 3B are embedded in the buried oxide layer 110. Accordingly, most of the second vias 323 fully traverse the cladding layer and at least partially traverse the buried oxide layer 110. A distance between most of the first conductive layers 321 and most of the second conductive layers 322 may be denoted by t? which is analogous to a height of the second vias 323. This distance t2 generally applies to most first conductive layers 321 and second conductive layers 322 which are interconnected by the second vias 323. However, at least one of the first conductive layers 321 which interconnects the first via 317 and a corresponding second via 323 may not be embedded in the buried oxide layer 110, i.e. , it may be embedded within the cladding layer 106 while being spaced apart from the first side 111 of the buried oxide layer 110, hence a distance between this conductor layer and a corresponding second layer is less than t (see rightmost first conductive layer 321 in Figure 3B). Such first conductive layer 321 may be arranged at one end of the length of the inductor 320 which is most proximate to the photodetector device 102, i.e., most proximately coupled to the photodetector device 102.

[0049] Reference is made to Figures 4A and 4B showing a photodetector assembly 400 in accordance with an embodiment. This embodiment is similar to the embodiment of Figures 3A and 3B, except that this embodiment includes a signal electrode 103 and a ground electrode 104. For the sake of brevity, a description of these similar features would not be repeated. Accordingly, an inductor 420, first conductive layers 421 , second conductive layers 422, a first via 417, and second vias 423 of Figures 4A and 4B are analogous to the inductor 120, the first conductive layers 121 , the second conductive layers 122, the first via 117, and the second vias 123 of Figures 1A and 1B.

[0059]

[0050] Reference is made to Figures 5A and 5B showing a photodetector assembly 500 in accordance with an embodiment. In this embodiment, a signal electrode 103 and two ground electrodes 104 are provided; the inductor 520 fully traverses through the stacked structure 105, i.e. , the cladding layer 106, the buried oxide layer 110, and the semiconductor substrate 114.

[0060]

[0051] The photodetector assembly 500 comprises a stacked structure 105; a photodetector device 102; an inductor 520; and signal and ground electrodes 103, 104. The stacked structure 105, the photodetector device 102, and the signal and ground electrodes 103, 104 are similar to the embodiment of Figures 1A and 1B and hence a description of these similar features would not be repeated for the sake of brevity. Accordingly, an inductor 520, first conductive layers 521 , second conductive layers 522, a first via 517, and second vias 523 of Figures 5A and 5B are analogous to the inductor 120, the first conductive layers 121, the second conductive layers 122, the first via 117, and the second vias 123 of Figures 1A and 1B.

[0061]

[0052] The inductor 520 is mostly similar to the inductor 120 of the embodiment of Figures 1 A and 1 B, except that most of the first conductive layers 521 of inductor 520 of Figures 5A and 5B are arranged on the second side 116 of the semiconductor substrate 114. In other words, most of the first conductive layers 521 of inductor 520 are non-embedded in the stacked structure 105. Accordingly, most of the second vias 523 fully traverse through the stacked structure 105, i.e., the cladding layer 106, the buried oxide layer 110, and the semiconductor substrate 114. A distance between most of the first conductive layers 521 and most of the second conductive layers 522 may be denoted by ts which is analogous to a height of the second vias 523. This distance ts generally applies to those first conductive layers 521 and second conductive layers 522 which are interconnected by the second vias 523. However, atleast one of the first conductive layers 521 which interconnects the first via 517 and a corresponding second via 523 may not be arranged on the second side 116 of the semiconductor substrate 116, i.e., it is non-embedded in the stacked structure 105 but is embedded within the cladding layer 106 while being spaced apart from the first side 111 of the buried oxide layer 110, hence a distance between this conductor layer and a corresponding second layer is less than ts (see rightmost first conductive layer 521 in Figure 5B). Such first conductive layer 521 may be arranged at one end of the length of the inductor 520 which is most proximate to the photodetector device 102, i.e., most proximately coupled to the photodetector device 102

[0062]

[0053] Reference is made to Figures 6A and 6B showing a photodetector assembly 600 in accordance with an embodiment. This embodiment is similar to the embodiment of Figures 5A and 5B, except that this embodiment includes a signal electrode 103 and a ground electrode 104. For the sake of brevity, a description of these similar features would not be repeated. Accordingly, an inductor 620, first conductive layers 621 , second conductive layers 622, a first via 617, and second vias 623 of Figures 6A and 6B are analogous to the inductor 120, the first conductive layers 121 , the second conductive layers 122, the first via 117, and the second vias 123 of Figures 1A and 1B.

[0063]

[0054] In the illustrated embodiments, the photodetector device 102 is embedded in the cladding layer and arranged on the first side of the buried oxide layer 110. In certain other embodiments (not shown), the photodetector device 102 may be embedded in the buried oxide layer 110 and arranged on the first side 115 of the semiconductor substrate 114.

[0064]

[0055] In certain other embodiments (not shown), the first conductive layers and / or the second conductive layers may include one or more passivation layers. Passivation layer typically provides electrical isolation and may additionally protect the conductive layers from erosion and degradation.

[0065]

[0056] In the illustrated embodiments, the inductor includes first conductive layers and second conductive layers. In certain other embodiments (not shown), the inductor may additionally include a plurality of subsequent conductive layers, e g., third conductive layers arranged between the first conductive layers and the second conductive layers, etc.

[0066]

[0057] In some embodiments, the photodetector device is operational in the visible or optical communication band. A photodetector device operable in the opticalcommunication band, in an example, is a germanium or silicon-based photodetector device while a photodetector device operable in the visible range is a silicon photodetector device. In some embodiments, the photodetector device may be operational in the optical communication band in the range of 1260 nanometres (nm) to 1625 nm.

[0067]

[0058] In some embodiments, the SOI structure may include a top silicon layer of thickness which ranges between 150 nm and 400 nm. The buried oxide layer may have a thickness which ranges between 100 nm and 4000 nm. The cladding layer may include silicon dioxide or a passivation material having a thickness which ranges between 1000 nm and 10000 nm. The first conductive layers and the second conductive layers may have same or different thickness which, in some examples, may range between 100 nm and 3000 nm. Passivation layers which may be on the first conductive layers and / or the second conductive layers may each have a thickness of between 100 nm and 1000 nm. The size of the signal and ground electrodes, e.g., electrical probe pads, may range between 10 micrometres (pm) and 1000 pm. Pitch of the electrical probe pads, e g., centre-to-centre distance between the pads, may range between 10 pm and 1000 pm. These dimensions are illustrative of non-limiting examples only.

[0068]

[0059] In the embodiments of Figures 1 A, 1B, 2A, 2B, the distance between the first conductive layers and the second conductive layers which is denoted by ti may range between 1 pm and 10 pm. In the embodiments of Figures 3A, 3B, 4A, 4B, the distance between the first conductive layers and the second conductive layers which may be denoted by t2 may range between 2 pm and 20 pm. In the embodiments of Figures 5A, 5B, 6A, 6B, a distance between the first conductive layers and the second conductive layers which may be denoted by ts may range between 100 pm and 1000pm. These dimensions are illustrative of non-limiting examples only.

[0069]

[0060] With three-dimensional on-chip inductor, embodiments of high-speed photodetector assembly are capable of achieving a substantially reduced footprint as compared to a high-speed photodetector assembly having a conventional two-dimensional or planar inductor, while maintaining bandwidth performance. The reduced footprint of a high-speed photodetector assembly according to embodiments is therefore comparable to a footprint of a normal photodetector assembly. A comparison of footprints is described with reference to Figures 7 and 8.

[0061] Figure 7 is a schematic view of a conventional planar inductor 700. As shown in Figure 7, the planar inductor is a square inductor having a coil member 702 which is arranged as a plurality of turns in a spiral arrangement. The planar inductor 700 includes the following parameters: number of turns n, turn width w, turn width spacing s, outer diameter dout, inner diameter din, average diameter davg, and fill ratio p. As thickness of a conventional planar inductor has a very minor effect on inductance, it will not be considered.

[0070]

[0062] Modified Wheeler Formula may be used to ascertain an inductance of a planar inductor, as follows:

[0071]

[0072] where

[0073] Ki is a coefficient, e.g., Ki - 2.34;

[0074] K2 is a coefficient, e.g., K.2 = 2.75;

[0075] po is a coefficient, e.g., po = TT X 10'7H / m.

[0076] Here, da

[0077] p — (dout

[0078]

[0079]

[0063] In an example planar inductor 700 of Figure 7, values of the above parameters may be provided as follows:

[0080] w = s = 10 pm;

[0081] din = 40 pm;

[0082] dout = 100 pm;

[0083] n = 2;

[0084] L = 0.378 nH.

[0085] Based on the above parameter values, the footprint of the conventional planar inductor 700 of Figure 7, as defined by the spiral-like area having diameter dout, is 10000 pm2.

[0086]

[0064] Figure 8 is a schematic view of a three-dimensional inductor 120, 220, 320, 420, 520, 620 employed in embodiments, e.g., Figures 1A to 6B. The inductor 120, 220, 320, 420, 520, 620 includes first conductive layers, second conductive layers, and second vias, wherein each second via interconnects an end of a first conductive layer and an end of a second conductive layer which is spaced above the particular first conductive layer. Accordingly, the inductor 120, 220, 320, 420, 520, 620 may have a coil-like arrangement which may include a square, rectangle, or circular cross-section profile along a plane traversing the stacked structure, i.e. , the cladding layer, the buried oxide layer, and the semiconductor substrate. An axis of the coil-like arrangement is parallel to or along planar directions of the cladding layer 106, the buried oxide layer 110, and the semiconductor substrate 114. The three-dimensional inductor structure includes the following parameters: length / , width w, and height or depth t, wherein the planar dimensions of length I and width w define a footprint of the inductor (see Figure 8).

[0087]

[0065] The inductor 800, e.g., 120, 220, 320, 420, 520, 620, has an inductance which may be determined based on Wheeler’s Continuous Inductance formula, as follows:

[0088]

[0089] where

[0090] n is number of turns, e.g., n = 17;

[0091] I is length of the inductor, e.g., / = 70.7 m;

[0092] L is inductance of the inductor, e.g., L = 0.378 nH which is assumed to be the same as the planar inductor of Figure 7 for comparison purpose;

[0093] x - 2(w / f / n0-5, e.g., x - 10 pm, which is a derived variable from t and w, and is a tool to back calculate w.

[0094]

[0066] In an example of a three-dimensional inductor having a square cross-section, e.g., embodiment of Figures 1A and 1 B, or 2A and 2B, if ti = 2.4 pm, then w = 32.7 pm in view of the above parameter values. Accordingly, the footprint of the inductor is 2312 pm2which represents 76.9 % reduction as compared to the footprint of the conventional planar inductor of Figure 7.

[0095]

[0067] In another example of a three-dimensional inductor having a square crosssection, e.g., embodiment of Figures 3A and 3B, or 4A and 4B, if t = 5.4 pm, then w - 14.5 pm in view of the above parameter values. Accordingly, the footprint of the inductor is 1028 pm2which represents 89.7 % reduction as compared to the footprint of the conventional planar inductor of Figure 7.

[0096]

[0068] In another example of a three-dimensional inductor having a square crosssection, e.g., embodiment of Figures 5A and 5B, or 6A and 6B, if ts = 730 pm, n = 2, 1 - 16 pm, x - 66.4 pm, w - 4.7 pm, L = 0.378 nH, the footprint of the inductor is 75.2 pm2which represents 99.3 % reduction in the footprint as compared to the conventional planar inductor of Figure 7.

[0069] In view of the foregoing, photodetector assemblies according to embodiments of Figures 5A and 5B, or 6A and 6B, achieves maximum or improved reduction in the footprint of the inductor as compared to photodetector assemblies according to embodiments of Figures 1 A and 1 B, 2A and 2B, 3A and 3B, 4A and 4B, or 5A and 5B.

[0097]

[0070] As the three-dimensional inductor is fabricated on-chip, i.e. , integrated with the photodetector device, fabrication of the photodetector assemblies with three-dimensional inductors according to embodiments are compatible with CMOS technologies, including but not limited to processes of photolithography, ion implantation, etching, chemical vapor deposition, physical vapor deposition, rapid thermal anneal, and / or chemical-mechanical polishing. This obviates the need for off-chip inductor, additional off-chip processing, and associated coupling of off-chip inductor with photodetector device.

[0098]

[0071] It is to be understood that the embodiments and features described above should be considered exemplary and not restrictive. Many other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the invention. Furthermore, certain terminology has been used for the purposes of descriptive clarity, and not to limit the disclosed embodiments of the invention.

Claims

CLAIMS1. A photodetector assembly comprising:a stacked structure having a cladding layer, a buried oxide layer, a semiconductor substrate, wherein the cladding layer includes a first side and a second opposed side which abuts a first side of the buried oxide layer, wherein the semiconductor substrate includes a first side which abuts a second opposed side of the buried oxide layer and further includes a second opposed side;a photodetector device embedded in the stacked structure;an inductor operably coupled to the photodetector device, wherein the inductor is arranged on the first side of the cladding structure and at least partially traverses the stacked structure;a signal electrode operably coupled to the photodetector device by using the inductor; andat least one ground electrode operably coupled to the photodetector device, wherein the signal electrode and the ground electrode are arranged on the first side of the cladding layer.

2. The photodetector assembly of claim 1 wherein the inductor includes:a plurality of first conductive layers embedded in the stacked structure; a plurality of second conductive layers arranged on the first side of the cladding layer; anda plurality of vias traversing the stacked structure and respectively interconnecting the first conductive layers and the second conductive layers.

3. The photodetector assembly of claim 2, wherein the first conductive layers are embedded in the cladding layer and arranged on the first side of the buried oxide layer, wherein the vias at least partially traverse the cladding layer.

4. The photodetector assembly of claim 3, wherein a height of the second vias is between 1 pm to 10 pm.

5. The photodetector assembly of claim 2, wherein the first conductive layers are embedded in the buried oxide layer, wherein the vias fully traverse the cladding layer and at least partially traverse the buried oxide layer.

6. The photodetector assembly of claim 5, wherein a height of the second vias is between 2 pm to 20 pm.

7. The photodetector assembly of claim 2, wherein the first conductive layers are arranged on the second side of the semiconductor substrate, wherein the vias fully traverse the cladding layer, the buried oxide layer, and the semiconductor substrate.

8. The photodetector assembly of claim 7, wherein a height of the second vias is between 100 pm to 1000 pm.

9. The photodetector assembly of any one of claim 1 to claim 8, wherein the inductor includes a coil-like arrangement, wherein an axis of the coil-like arrangement is parallel to planar directions of the cladding layer, the buried oxide layer, and the semiconductor substrate.

10. The photodetector assembly of claim 9, wherein the coil-like arrangement includes a square or rectangle cross-section profile along a plane traversing the cladding layer, the buried oxide layer, and the semiconductor substrate.

11. The photodetector assembly of any one of claim 1 to claim 10, wherein the photodetector is embedded in the cladding layer or arranged on the first side of the semiconductor substrate.

12. The photodetector assembly of any one of claim 1 to claim 11 , wherein the at least one ground electrode includes two or more ground electrodes which are arranged on the first side of the cladding layer, are operably coupled to the photodetector device.