Hardware-assisted parameterized circuit execution of quantum computing tasks

Abstract

A method, a system, and a non-transitory computer-readable storage medium are provided. The method includes receiving, from a host computer, a compilation of a plurality of quantum circuit templates that are structurally different from one another. The method includes storing, by a quantum computing controller, a plurality of lists respectively associated with the plurality of quantum circuit templates. Each list includes a plurality of parameters of one or more quantum circuit instances of a plurality of quantum circuit instances. The method includes reconstructing, at digital circuit of the quantum computing controller, the plurality of quantum circuit instances based on the plurality of quantum circuit templates and the plurality of lists. The method includes executing, by the quantum computing controller, a quantum computing task using the plurality of quantum circuit instances.

Description

Attorney Docket No.: 2024-074-02 HARDWARE-ASSISTED PARAMETERIZED CIRCUIT EXECUTION OF QUANTUM COMPUTING TASKSInventors: Abhi Rajagopala, Neelay Fruitwala, Akel Hashim, Kasra NowrouziCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U. S. Provisional Patent Application No.63 / 651,049, filed on May 23, 2024, the content of which is incorporated herein by reference.STATEMENT OF GOVERNMENT RIGHTS

[0002] This invention was made with government support, under Contract No. DE-AC02-05CH11231 awarded by the U.S. Department of Energy. The government has certain rights in the invention.TECHNICAL FIELD

[0003] The present disclosure relates generally to quantum computing, and more particularly, to hardware-assisted parameterized circuit execution of quantum computing tasks.BACKGROUND

[0004] Quantum computing is a rapidly evolving technology with the potential of solving many complex problems that are difficult for traditional computers. Quantum computing tasks (e.g., algorithms or protocols) are executed in quantum circuits, which typically include gates with fixed parameters, such as Hadamard, controlled NOT (CNOT or CX), swap, and Pauli X, Y, and Z gates, and gates with flexible parameters, such as virtual Z (virtual-Z) gates. A virtual-Z gate having a phase of φ is often denoted as Z(φ).BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The described implementations and the advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings. These drawings in no way limit any changes in form and detail that may be made to the described implementations by one skilled in the art without departing from the spirit and scope of the described implementations.Attorney Docket No.: 2024-074-02

[0006] FIG. 1A is a diagram of an example quantum computing system based on hardware- assisted parameterized circuit execution (PCE), according to some implementations.

[0007] FIG. IB is a diagram of an example quantum computing controller in the quantum computing system of FIG. 1A, according to some implementations.

[0008] FIG. 2 illustrates an example procedure of compiling quantum circuit instances based on a read-identify-peel (RIP) algorithm for PCE, according to some implementations.

[0009] FIG. 3 illustrates the function signature of PCE for defining a program module, according to some implementations.

[0010] FIG. 4 illustrates example instructions for fetching parameters from a stitch module on a digital circuit for PCE, according to some implementations.

[0011] FIG. 5 illustrates performance improvement on various quantum computing tasks due to PCE, according to some implementations.

[0012] FIG. 6 is a flow diagram depicting an example method, according to some implementations.

[0013] FIG. 7 is a block diagram of an example computing device that performs one or more of the operations described herein, according to some implementations.DETAILED DESCRIPTION

[0014] In quantum computing, quantum circuits are usually designed in quantum programming languages on classical (e.g., non-quantum) computers. Instances of the quantum circuits are then compiled by compiling tools, which transform the quantum circuit designs into one or more formats that, provide abstraction of the circuit, structure and interconnections. Compilation of the quantum circuits may then be loaded to quantum computing platforms for performing various quantum computing tasks. Quantum compilers typically decompose single-bit quantum gates (e.g., logic gates with a single quantum bit (qubit) input) in terms of discrete physical Xπ / 2 pulses (e.g., implemented via resonant Rabi-driven pulses) and arbitrary virtual-Z phase gates by, e.g., changing the phase of the subsequent physical pulse. Accordingly, a single-bit quantum gate is often a U3 gate that may be parameterized by three distinct phases, φ, θ, and λ, as shown in equation (1). ThisAttorney Docket No.: 2024-074-02 manner of decomposition, often referred to as ZXZXZ-decomposition, parameterizes all single-qubit gates by three phases, such that, implementing different single-qubit gates can be achieved by changing the phases of the physical pulses without changing the physical parameters of the Xπ / 2 pulses.U3 <p, 0, A) “ Z^>-wl2Xn / 2Zw—6Xjt / 2ZA-jt / 2 (1)

[0015] Many classes of quantum circuits have structural equivalency, e.g., the same structure of physical pulses, although the virtual phases in the single-qubit gates of the quantum circuits may differ. The equivalent circuit structure may implement the same or different logical operations. Existing compilation techniques compile each quantum circuit instance independently (e.g., without regarding the structural equivalency), load the compiled quantum circuit instances on the control hardware, and make measurements on a quantum computing unit (QPU). When the number of quantum circuit instances becomes large (e.g., ranging from 100 to 10,000), the compilation and loading become time-consuming, creating large overheads for execution of quantum computing tasks. The overheads may be more noticeable when active resets are used to reduce passive quantum reset delays. Therefore, it is desirable to reduce the compilation time, especially for large-scale quantum circuits.

[0016] In view of the above challenges, implementations of this disclosure provide techniques that utilize structural equivalencies among quantum circuit instances to reduce compilation time. As described below, implementations of this disclosure provide a PCE mechanism based on a RIP module that identifies unique structures from quantum circuit instances while separating the parameters associated with quantum circuit instances.According to an aspect, a host computer generates a compilation of a plurality of quantum circuit templates that are structurally different from one another. The host computer obtains a plurality of lists respectively associated with the plurality of quantum circuit templates, wherein each list includes a plurality of parameters of one or more quantum circuit instances of a plurality of quantum circuit instances. A quantum computing controller is configured to store the plurality of lists in a memory of the digital circuit. The quantum computing controller is configured to reconstruct the plurality of quantum circuit instances based on the plurality of quantum circuit templates and the plurality of lists. The quantum computing controller is configured to execute a quantum computing task using the plurality of quantum circuit instances. With one or more features described below; the compilation time may beAttorney Docket No.: 2024-074-02 reduced because only the unique structures are compiled. The reduction of compilation time thus improves the processing efficiency of quantum computing.

[0017] FIG. 1A is a diagram of an example quantum computing system 100 based on hardware-assisted PCE, according to some implementations. As illustrated, system 100 includes host computer 110, which may be a general -purpose classical computer, and quantum computing controller 120, which may include or be implemented on a radio frequency system-on-a-chip (RFSoC) having processor 121 (e.g., an embedded ARM processor) and digital circuit 125 (e.g., an FPGA circuit, an application specific integrated circuit (ASIC), a cryoCMOS circuit, or circuits using other digital technologies).

[0018] Host computer 110 includes software code that describes quantum circuit instances 111 in a quantum programming language, such as OPENQASM3, QISKIT, TRUE-Q, or PYGSTI. These quantum circuit instances 111, after compilation, may be implemented on hardware to perform one or more quantum computing tasks. Host computer 110 also includes software code that implements RIP module 113.

[0019] In some implementations, host computer 110 is configured to generate a quantum circuit abstraction corresponding to quantum circuit instances 111, e.g., by transpiling quantum circuit instances 111 from the quantum programming language to a format suitable for a quantum control system. As an example, host computer 110 may transpile quantum circuit instances 111 to an abstraction in the format of QUBIC, which is an open source, FPGA-based, quantum control system with the capability of generating arbitrary waveforms for control and read measurements on superconducting quantum devices.

[0020] RIP module 113 reads the transpiled quantum circuit instances 111, identifies structural equivalencies among quantum circuit instances 111, and peels (e.g., extracts) parameters 142, such as the phases of the virtual-Z gates in each circuit instance, from quantum circuit instances 111. For example, RIP module 113 constructs a directed acyclic graph (DAG) for each circuit instance to represent the sequence of gates applied to each qubit in the circuit instance. Each node in the graph corresponds to a gate operation, and the edges indicate the temporal order of the gate execution. By comparing these graphs, RIP module 113 identifies circuit instances with equivalent (e.g., identical) structures and generate a plurality of quantum circuit templates 141 to respectively represent the unique structures using a sequence of single-bit and multi-bit gates, with each quantum circuit template beingAttorney Docket No.: 2024-074-02 unique from other quantum circuit templates. A circuit template or circuit structure is considered unique if the corresponding graph structure and metadata (without parameter values) are distinct from other circuit templates or circuit structures. In other words, the plurality of quantum circuit templates are structurally different from one another.Accordingly, for each identified quantum circuit template, there may be one or more corresponding circuit instances that are structurally equivalent. Host computer 110 may generate a file for each quantum circuit template to list all corresponding structurally equivalent circuit instances. In some implementations, RIP module 113 is configured to switch between generating quantum circuit templates for out-of-order circuit instances or for in-order circuit instances. Quantum circuit templates 141 may be compiled in the format of instructions that are readable by a quantum controller, such as a QUBIC controller.

[0021] For each unique quantum circuit template, RIP module 113 also obtains parameters of the circuit instances having equivalent structures. For instance, assuming two instances are structurally equivalent to a given quantum circuit template, RIP module 113 extracts parameters of each of the two instances and obtains a list of parameters for each circuit instance. The parameters in each list may be organized in accordance with the indices of the circuit instances corresponding to the quantum circuit template.

[0022] In some implementations, after compiling quantum circuit templates 141 and extracting parameters 142, host computer 110 is configured to modify the compilation of quantum circuit templates 141. For example, the modification replaces each virtual -Z instruction in a compiled circuit template, from which parameters have been extracted, with an alu_fproc instruction from the QUBIC instruction set. With the modified compilation, the QUBIC controller, which operates along with a stitch module (described later), is able to locate the corresponding parameters when reconstructing the quantum circuit instances corresponding to the circuit template during execution of a quantum computing task.

[0023] Host computer 110 then transmits, e.g., via a remote procedure call (RPC), modified compilation of circuit templates 141 and parameters 142 to quantum computing controller 120, which is configured to execute the quantum computing task and provide results 180 back to host computer 110. Because circuit templates 141 are structurally unique from one another, the compiler of host computer 110 only needs to compile one copy for multiple structurally equivalent circuit instances, thereby reducing compilation time.Attorney Docket No.: 2024-074-02

[0024] FIG. IB is a diagram of quantum computing controller 120 in quantum computing system 100 of FIG. 1A, according to some implementations. Referring to FIGs. 1 and IB, processor 121 of quantum computing controller 120 is configured to implement software code for deft scheduler 122. In addition, digital circuit 125 of quantum computing controller 120 is configured to implement circuitry of stitch module 124 communicatively coupled to memory 126 and control processor and signal generator 123. Memory 126 may be implemented using a block random access memory (BRAM) having a 32-kilobit block size, although other types of memories are possible depending on the underlying digital technology. Memory 126 may have a true dual-port (TDP) design, e.g., with one port interfacing memory controller 127 and another port interfacing stitch module 124. This dual¬ port configuration enables efficient concurrent access for both writing and reading of the parameters.

[0025] Deft scheduler 122 is a software module configured to orchestrate the execution of the quantum computing task by coordinating the interaction between RIP module 113, stitch module 124, and other quantum computing control processes implemented by processor 121. In some implementations, deft scheduler 122 is implemented in PYTHON to interface with existing QUBIC control software, e.g., to generate the control signals (e.g., pulses) applied to qubits involved in the quantum computing task. Deft scheduler 122 is also communicatively coupled to digital circuit 125, e.g., via AXI buses, to provide parameters 142 and quantum circuit templates 141 for parameterized circuit execution of the quantum computing task.

[0026] During circuit execution of the quantum computing task, deft scheduler 122 receives, from host computer 110 via an RPC, lists of parameters 142, which may be organized as one or more binarized parameter dictionaries. Deft scheduler 122 also receives, from host computer 110 via the RPC, a compilation of circuit templates 141. Deft scheduler 122 may then de-binarizes the parameter dictionaries and use the indices associated with circuit templates 141 to extract the order of circuit instances. Based on the order and the indices associated with the parameters, deft scheduler 122 fetches the parameters from the parameter dictionaries and matches each circuit instance with associated parameter values. Deft scheduler 122 may then instruct memory controller 127 to load (e.g,, store) the parameters in memory 126 in the order that matches the circuit instances.

[0027] Digital circuit 125 executes the quantum computing task by processing qubits with a sequence of circuit instances in the order as extracted by deft scheduler 122. For example,Attorney Docket No.: 2024-074-02 control processor and signal generator 123 may obtain, from deft scheduler 122, one circuit instance per clock cycle. Control processor and signal generator 123 may then transmit the obtained circuit instance to stitch module 124 along with a control signal for instantiation on hardware. Meanwhile, because the parameters are stored in memory 126 in the order that matches the order of circuit instances 143, stitch module 124 fetches the parameters associated with the obtained circuit instance and assigns the values of the fetched parameters to the gates (e.g., virtual -Z gates) of the obtained circuit instance. Accordingly, stitch module 124 reconstructs the obtained circuit instance with parameters that were previously peeled off by RIP module 113 during compilation. The reconstructed circuit instance may then process the qubits as part of executing the quantum computing task. After all circuit instances have been reconstructed and finished executing the respective part of the quantum computing task, control processor and signal generator 123 sends results 180 to processor 121, which in turn provides results 180 to host computer 110.

[0028] In some implementations, stitch module 124 employs a prefetch mechanism that anticipates future parameter requests and fetches the anticipated parameters in advance, reducing latency and achieving a parameter request completion within two clock cycles (e.g., 4 nanoseconds). Since quantum circuits are typically executed multiple times (shots) with the same set of parameters, stitch module 124 may track the number of parameters in each circuit instance and automatically repeat the parameter delivery for the specified number of shots. Moreover, stitch module 124 may repeat a partial set of parameters or switch to a different set based on control codes provided by deft scheduler 122 before circuit execution. This flexibility enables dynamic parameter adjustments during circuit execution.

[0029] In some implementations, stitch module 124 preserves the existing mid-circuit measurement and feed-forward functionality of the QUBIC system, which allows for conditional execution of gates based on measurement outcomes. Stitch module 124 may distinguish between parameter requests and mid-circuit measurement requests from control processor and signal generator 123, e.g., using a core_id parameter in an fproc interface. For instance, core id values between 0 and 7 may indicate mid-circuit measurement requests for the corresponding qubits, while the value of 10 may indicate a parameter request. These core id values may be encoded by RIP module 113 during the modification of compiled quantum circuit templates.Attorney Docket No.: 2024-074-02

[0030] As described above with reference to FIGs. 1A and IB, RIP module 113 reduces compilation time by compiling only quantum circuit templates 141 that are structurally unique to one another, while peeling off the parameters from circuit instances that may be structurally equivalent. Meanwhile, stitch module 124 ensures accurate circuit execution by reconstructing the circuit instances on hardware such that parameter variations among structurally equivalent circuit instances are recovered.

[0031] FIG. 2 illustrates an example procedure 200 of compiling quantum circuit instances 210 based on a RIP algorithm for PCE, according to some implementations. Procedure 200 may correspond to one or more operations performed on host computer 110 of FIG. 1A.

[0032] As illustrated, quantum circuit instances 210 are a collection of circuit instances 210a, 210b,... 21 On, which may be described in a quantum programming language and stored on a host computer. Each of quantum circuit instances 210 has a plurality of gates, denoted by symbols such as “H” and “CX,” connected to process one or more qubits.

[0033] Quantum circuit instances 210 are converted to abstraction 220, which describes the gates in each of quantum circuit instances 210. In the illustrated example, the abstraction is in the format of QUBIC instructions and represents each gate using at least one of: a name field, a qubit field, and a phase field. For example, a line {‘name’: ‘virtual ’, ‘qubit.’:[‘Q0’], ‘phase’: -0.0} in the abstraction may correspond to a virtual-Z gate configured to apply a -0.0 degree phase shift operation on qubit Q0. Similarly, a line {‘name’: ‘CZ’, ‘qubit’: [‘Q0’, ‘QI’]} in the abstraction may correspond to a CZ gate operation on qubits Q0 and QI. In some implementations, the host computer first converts each of quantum circuit instances 210 to ZXZXZ-decompositions according to equation (1) before generating abstraction 220.

[0034] Abstraction 220 is then processed by RIP module 230 to obtain parameters 240 and quantum circuit templates 250. As described above, parameters 240 may be arranged as a plurality of lists respectively corresponding to quantum circuit instances 210, with each list including parameter values (e.g., phases of virtual-Z gates) arranged in order. In addition, circuit templates 250 are structurally different from one another, with each template corresponding to one or more circuit instances that are structurally equivalent.

[0035] FIG. 3 illustrates function signature for defining program module 300 for PCE, according to some implementations. Program module 300 may be implemented as part ofAttorney Docket No.: 2024-074-02 RIP module 113 of FIG. 1A or RIP module 230 of FIG. IB to identify structurally equivalent circuit instances.

[0036] As illustrated, program module 300 has three arguments. The “circuits” argument is a list of circuit instances before the RIP process. In some implementations, the “circuit” argument corresponds to the abstraction that a host computer generates by transpiling the circuit instances from a quantum programming language to QUBIC instructions. The “qubits” argument indicates the indices, which may be integers, of qubits to be processed by the circuit instances identified by the “circuit” argument. The “chanmap” argument describes the physical mapping of qubits from the control system to the quantum processor.

[0037] A method based on program module 300 may return one or more lists of parameters, such as parameters 240 of FIG. 2, and one or more lists of unique circuit templates, such as quantum circuit templates 250 of FIG. 2. As discussed previously, the parameters, denoted as a return (e.g., output) with the name “Diet,” are organized as one or more binarized parameter dictionaries, which may be loaded to the memory of an FPGA circuit and accessed by a stitch module. Also, the unique circuit templates, denoted as a return with the name “List,” are generated by the host computer and modified by the RIP module for the stitch module to match with the corresponding parameters during execution. The generation of the returns based on the arguments may be similar to one or more operations described above with reference to FIGs. 1A-1B and 2.

[0038] FIG. 4 illustrates example instructions 400 for fetching parameters from a stitch module on an FPGA circuit for PCE, according to some implementations. Instructions 400 may be generated by an RIP module by modifying the compilation of quantum circuit templates. Instructions 400 may then be provided to a QUBIC controller, which coordinates with the stitch module on the FPGA circuit to reconstruct quantum circuit instances.

[0039] In particular, line number 8 of instructions 400 is an alu_fproc instruction (circled), which instructs a distributed processor (e.g., control processor and signal generator 123 of FIG. IB) to request data from the stitch module and store the data in a variable. Line number 10 addresses the processing delay for the stitch module to align with the circuit execution.

[0040] The variable, which represents a value of a phase parameter for a virtual-Z gate, is created (e.g., declared) by the instruction at line number 2 to have a name of “varname” and a type of “phase.” Line number 4 deploys a bind_phase instruction to bind (e.g., associate) theGAttorney Docket No.: 2024-074-02 variable with a qubit frequency (e.g., the frequency at which the qubits are processed), and line number 6 sets the initial value of the variable to 0.

[0041] The code, abstraction, compilation, and instructions illustrated above in FIGs. 2-4 are merely examples in the context of QUBIC. One of ordinary skill in the art would readily appreciate that other formats and representations are possible to implement the system illustrated in FIGs. 1A and IB.

[0042] FIG. 5 is a table 500 that illustrates performance improvement on various quantum computing tasks due to PCE, according to some implementations. The example tasks in table 500 include tasks according to quantum characterization, verification, and validation (QCVV) algorithms and tasks according to time-evolution algorithms. The algorithms, listed in the “Algorithms” column of table 500, include: randomized compiling with N=20 (RC20), fully randomized compiling (FRC), cycle benchmarking (CB), randomized benchmarking (RB), gate set tomography (GST), transverse-field Ising model XY with 50 circuits (TFXY50), transverse-field Ising model XY with 500 circuits (TFXY 500), Heisenberg spin model with 50 circuits, and Heisenberg spin model with 500 circuits. The “Circuit” and “No. Unique Circuits” columns indicate the number of quantum circuit instances and the number of unique quantum circuit templates, respectively, for executing the corresponding quantum computing algorithms. The “Parameters” column indicates the numbers of parameters extracted by an RIP module from the quantum circuit instances when generating the unique quantum circuit templates.

[0043] The performance improvement is quantitatively shown in the “Compilation Speedup,” “Classical Time Reduction,” and “Classical Speedup” columns, the calculations of which may follow equations (2)-(5).(Software Compile Time + Software Assemble Time) Compilation Speedup = (PCE Compile Time + PCE Assemble Time)Classical Time Reduction (%)(Software Classical Time ■■■■ PCE Classical Time)100 (Software Classical Time)Attorney Docket No.: 2024-074-02Classical Time = Total execution time — Quantum circuit runtime(4)Software Classical Time Classical Speedup = -: — TSX-. - PCE Classical T me(5)

[0044] Using RC20 as an example, table 500 shows that the RIP module generates 77 unique quantum circuit templates from a total of 1,540 quantum circuit instances. The RIP module also obtains a total of 1,180,200 parameters from the quantum circuit instances. Under PCE, because the host computer only needs to compile the 77 circuit templates that are structurally different from one another, instead of compiling all the 1,540 quantum circuit instances under conventional software compilation, compilation efficiency and classical processing speed on the host computer may be greatly improved.

[0045] FIG. 6 is a flow diagram depicting an example method 600, according to some implementations. Method 600 may be performed by a quantum computing controller, such as quantum computing controller 120 of FIG. 1A.

[0046] At 602, method 600 involves receiving a compilation of a plurality of quantum circuit templates that are structurally different from one another. The compilation may be received from a host computer, such as host computer 110 of FIG. 1A.

[0047] At 604, method 600 involves storing a plurality of lists respectively associated with the plurality of quantum circuit templates, with each list including a plurality of parameters of one or more quantum circuit instances. The parameters and the quantum circuit templates may be outputs of an RIP module, such as RIP module 113 of FIG. 1A. The quantum computing controller may obtain the parameters and the quantum circuit templates from the host computer via an RPC.

[0048] At 606, method 600 involves reconstructing, at a digital circuit of the quantum computing controller, a plurality of quantum circuit instances based on the plurality of quantum circuit templates and the plurality of lists. The reconstruction may involve a stitchAttorney Docket No.: 2024-074-02 module, such as stitch module 124 of FIG. 1B, and a deft scheduler, such as deft scheduler 122 of FIG. 1B.

[0049] At 608, method 600 involves executing, by the quantum computing controller, a quantum computing task using the plurality of quantum circuit instances. The quantum computing controller may provide the results of the quantum computing task back to the host computer.

[0050] FIG. 7 is a block diagram of an example computing device 700 that performs one or more of the operations described herein, according to some implementations. Computing device 700 may be implemented as or within a classical computer, e.g., host computer 110 of FIG. 1A, and may be connected to other computing devices in a LAN, an intranet, an extranet, and / or the Internet. The computing device may operate in the capacity of a server machine in client-server network environment or in the capacity of a client in a peer-to-peer network environment. The computing device may be provided by a personal computer (PC), a set-top box (STB), a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single computing device is illustrated, the term “computing device” shall also be taken to include any collection of computing devices that individually or jointly execute a set (or multiple sets) of instructions to perform the methods discussed herein.

[0051] The example computing device 700 may include a processing device (e.g., a general-purpose processor, a PLD, etc.) 702, a main memory 704 (e.g., synchronous dynamic random-access memory (DRAM), read-only memory (ROM)), a static memory 706 e.g., flash memory and a data storage device 718), which may communicate with each other via a bus 730.

[0052] Processing device 702 may be provided by one or more general -purpose processing devices such as a microprocessor, central processing unit, or the like. In an illustrative example, processing device 702 may include a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very' long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. Processing device 702 may also include one or more special-purpose processing devices such as an application specificAttorney Docket No.: 2024-074-02 integrated circuit (ASIC), an FPGA, a digital signal processor (DSP), network processor, or the like. The processing device 702 may be configured to execute the operations described herein, in accordance with one or more aspects of the present disclosure, for performing the operations and steps discussed herein.

[0053] Computing device 700 may further include a network interface device 708 which may communicate with a communication network 720. The computing device 700 also may include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g, a mouse) and an acoustic signal generation device 716 (e.g, a speaker). In one embodiment, video display unit 710, alphanumeric input device 712, and cursor control device 714 may be combined into a single component or device (e.g, an LCD touch screen).

[0054] Data storage device 718 may include a computer-readable storage medium 728 on which may be stored one or more sets of instructions 725 that may include instructions for one or more components, agents, and / or applications 742 for carrying out the operations described herein, in accordance with one or more aspects of the present disclosure. For example, instructions 725 may include program 765 corresponding to an RIP module.Instructions 725 may also reside, completely or at least partially, within main memory 704 and / or within processing device 702 during execution thereof by computing device 700, main memory' 704 and processing device 702 also constituting computer-readable media. The instructions 725 may further be transmitted or received over a communication network 720 via network interface device 708.

[0055] While computer-readable storage medium 728 is shown in an illustrative example to be a single medium, the term “computer-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store the one or more sets of instructions. The term “computer-readable storage medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the machine and that cause the machine to perform the methods described herein. The term “computer- readable storage medium” shall accordingly be taken to include, but not be limited to, solid¬ state memories, optical media and magnetic media.Attorney Docket No.: 2024-074-02

[0056] Unless specifically stated otherwise, terms such as “converting,” “calculating,” “generating,” “multiplying,” “sending,” “determining,” “concatenating,” “identifying,” “partitioning,” “mapping,” or the like, refer to actions and processes performed or implemented by computing devices that manipulates and transforms data represented as physical (electronic) quantities within the computing device’s registers and memories into other data similarly represented as physical quantities within the computing device memories or registers or other such information storage, transmission or display devices. Also, the terms "first," "second," "third," "fourth," etc., as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation.

[0057] The methods and illustrative examples described herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used in accordance with the teachings described herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear as set forth in the description above.

[0058] The above description is intended to be illustrative, and not restrictive. Although the present disclosure has been described with references to specific illustrative examples, it will be recognized that the present disclosure is not limited to the examples described. The scope of the disclosure should be determined with reference to the following claims, along with the full scope of equivalents to which the claims are entitled.

[0059] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes”, and / or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Therefore, the terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting.

[0060] It should also be noted that in some alternative implementations, the functions / acts noted may occur out of the order noted in the figures. For example, two figures shown inAttorney Docket No.: 2024-074-02 succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality / acts involved,

[0061] Although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or the described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing.

[0062] Various units, circuits, or other components may be described or claimed as “configured to” or “configurable to” perform a task or tasks. In such contexts, the phrase “configured to” or “configurable to” is used to connote structure by indicating that the units / circuits / components include structure (e.g., circuitry) that performs the task or tasks during operation. As such, the unit / circuit / component can be said to be configured to perform the task, or configurable to perform the task, even when the specified unit / circuit / component is not currently operational (e.g., is not on). The units / circuits / components used with the “configured to” or “configurable to” language include hardware— for example, circuits, memory storing program instructions executable to implement the operation, etc. Reciting that a unit / circuit / component is “configured to” perform one or more tasks, oris “configurable to” perform one or more tasks, is expressly intended not to invoke 35 U. S. C. §112, sixth paragraph, for that unit / circuit / component. Additionally, “configured to” or “configurable to” can include generic structure (e.g., generic circuitry') that is manipulated by software and / or firmware (e.g., an FPGA or a general- purpose processor executing software) to operate in manner that is capable of performing the task(s) at issue. “Configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks. “Configurable to” is expressly intended not to apply to blank media, an unprogrammed processor or unprogrammed generic computer, or an unprogrammed programmable logic device, programmable gate array, or other unprogrammed device, unless accompanied by programmed media that confers the ability to the unprogrammed device to be configured to perform the disclosed function(s).

[0063] The foregoing description, for the purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed.Attorney Docket No.: 2024-074-02 Many modifications and variations are possible in view of the above teachings. The implementations were chosen and described to best explain the principles of the implementations and its practical applications, to thereby enable others skilled in the art to best utilize the implementations and various modifications as may be suited to the particular use contemplated. Accordingly, the present implementations are to be considered as illustrative and not restrictive, and the present disclosure is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

Attorney Docket No.: 2024-074-02CLAIMS WHAT IS CLAIMED IS:

1. A method comprising:receiving, from a host computer, a compilation of a plurality of quantum circuit templates that are structurally different from one another;storing, by a quantum computing controller, a plurality of lists respectively associated with the plurality of quantum circuit templates, wherein each list comprises a plurality of parameters of one or more quantum circuit instances of a plurality of quantum circuit instances,reconstructing, at a digital circuit of the quantum computing controller, the plurality of quantum circuit instances based on the plurality of quantum circuit templates and the plurality of lists; andexecuting, by the quantum computing controller, a quantum computing task using the plurality of quantum circuit instances.

2. The method of claim 1, wherein, within each list, the one or more quantum circuit instances are structurally equivalent.

3. The method of claim 1, wherein, within each list, the plurality of parameters comprise a phase value of a virtual-Z gate of the one or more quantum circuit instances.

4. The method of claim 3, wherein executing the quantum computing task comprises generating a quantum control signal based on the phase value.

5. The method of claim 1, wherein reconstructing the plurality of quantum circuit instances comprises:assigning the plurality of parameters in each list to the one or more quantum circuit instances according to a quantum circuit template associated with that list.

6. The method of claim 1, further comprising providing a result of the quantum computing task to the host computer.

7. A system comprising:a host computer, to:Attorney Docket No.: 2024-074-02 generate a compilation of a plurality of quantum circuit templates that are structurally different from one another; andobtain a plurality of lists respectively associated with the plurality of quantum circuit templates, wherein each list comprises a plurality of parameters of one or more quantum circuit instances; anda quantum computing controller operatively coupled to the host computer and comprising a processor and a digital circuit, to:store the plurality of lists in a memory of the digital circuit;reconstruct, at the digital circuit, a plurality of quantum circuit instances based on the plurality of quantum circuit templates and the plurality of lists; andexecute, by the processor, a quantum computing task using the plurality of quantum circuit instances.

8. The system of claim 7, wherein, to generate the compilation of the plurality of quantum circuit templates, the host computer is to:generate a quantum circuit abstraction corresponding to a plurality of quantum circuit instances; andidentify, from the quantum circuit abstraction, structural equivalencies among the plurality of quantum circuit instances.

9. The system of claim 8, wherein, to obtain the plurality of lists, the host computer is to extract the plurality of parameters based on one or more gates of the plurality of quantum circuit instances.

10. The system of claim 8, wherein, to identify the structural equivalencies among the plurality of quantum circuit instances, the host computer is to:generate a plurality of directed acyclic graphs representing a sequence of gates in the plurality of quantum circuit instances; andcompare the plurality of directed acyclic graphs with one another.

11. The system of claim 8, wherein the quantum circuit abstraction comprises a U3 gate.

12. The system of claim 7, wherein, within each list, the one or more quantum circuit instances are structurally equivalent.Attorney Docket No.: 2024-074-02 13. The system of claim 7, wherein, within each list, the plurality of parameters comprise a phase value of a virtual-Z gate of the one or more quantum circuit instances.

14. The system of claim 13, wherein, to execute the quantum computing task, the quantum computing controller is to generate a quantum control signal based on the phase value.

15. The system of claim 7, wherein, to reconstruct the plurality of quantum circuit instances, the quantum computing controller is to assign the plurality of parameters in each list to the one or more quantum circuit instances according to a quantum circuit template associated with that list.

16. The system of claim 7, wherein the quantum computing controller is to access the host computer via a remote procedure call (RPC).

17. The system of claim 7, wherein the quantum computing controller is further to provide a result of the quantum computing task to the host computer.

18. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to:generate a compilation of a plurality of quantum circuit templates that are structurally different from one another;obtain a plurality of lists respectively associated with the plurality of quantum circuit templates, wherein each list comprises a plurality of parameters of one or more quantum circuit instances; andprovide the compilation and the plurality of lists to a digital circuit.

19. The non-transitory computer-readable storage medium of claim 18, wherein, to generate the compilation of the plurality of quantum circuit templates, the instructions cause the processor to:generate a quantum circuit abstraction corresponding to a plurality of quantum circuit instances; andidentify, from the quantum circuit abstraction, structural equivalencies among the plurality of quantum circuit instances.Attorney Docket No.: 2024-074-02 20. The non-transitory computer-readable storage medium of claim 18, wherein, to obtain the plurality of lists, the instructions cause the processor to extract the plurality of parameters based on one or more gates of the one or more quantum circuit instances.

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