Spatial varying laser technique for wafer shape and overlay correction

Abstract

Provided herein are methods and related apparatus for deposition and laser treatment of films on semiconductor substrates. In some embodiments, a film may be annealed by laser treatment. In some embodiments, internal stress of films may be controlled on a local or whole wafer scale by laser treatment. In some embodiments, a wafer may be etched by laser treatment.

Description

Docket No. LAM1P088WOSPATIAL VARYING LASER TECHNIQUE FOR WAFER SHAPE AND OVERLAY CORRECTIONCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.BACKGROUND

[0002] Materials may interact with light by transmission, reflection, and absorption. Controlling the wavelength of light may affect how the light interacts with the material. For semiconductor manufacturing, light may be used for lithography to pattern materials. Other applications are possible.SUMMARY

[0003] Disclosed herein are methods and systems of processing wafers using a laser treatment. In one aspect of the embodiments herein, a method is provided, the method including: receiving a substrate having a frontside and a backside, wherein the substrate has a wafer bow from one or more frontside layers on the frontside and a backside layer; and exposing one or more portions of a backside layer to laser beams to modify the internal stress of the one or more portions.

[0004] In some embodiments, exposing one or more portions of the backside layer to laser beams includes annealing the one or more portions. In some embodiments, further including depositing the backside layer. In some embodiments, the one or more portions is the entire backside layer. In some embodiments, the backside layer mitigates wafer bow from the one or more frontside layers. In some embodiments, the one or more portions have an elliptical shape. In some embodiments, the one or more portions have a rectangular shape. In some embodiments, the backside layer reduces in-plane distortion of the substrate caused by the one or more frontside layers. In some embodiments, further including depositing an additional backside layer and exposing one or more portions of the additional backside layer to laser beams to modify one or more properties of the one or more exposed portions of the additional backside layer. A method of reducing bow in a substrate, the method including: receiving aDocket No. LAM1P088WOsubstrate having a frontside and a backside, wherein the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction of the substrate, wherein the substrate has a backside layer on the backside of the substrate, wherein the backside layer compensates the first bow more than it compensates the second bow; and exposing one or more portions of a backside layer to laser beams to modify the internal stress of the one or more portions, wherein after exposure the backside layer further compensates the second bow. In some embodiments, the received substrate has a saddle-shaped bow.

[0005] In another aspect of the embodiments herein, a method of reducing bow in a substrate is provided, the method including: receiving a substrate having a frontside and a backside, wherein the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction of the substrate, wherein the substrate has a backside layer on the backside of the substrate, wherein the backside layer compensates the first bow more than it compensates the second bow; and etching one or more portions of the backside layer using laser beams, wherein after etching the backside layer better compensates the second bow. In some embodiments, the backside layer before etching increases the second bow.

[0006] In some embodiments, the method further includes depositing an additional backside layer, wherein the additional backside layer backfills the etched one or more portions of the backside layer. In some embodiments, the additional backside layer compensates the second bow more than it compensates the first bow. In some embodiments, a pitch between the one or more portions of the backside layer is between about 0.1 pm and about 10 pm.

[0007] In another aspect of the embodiments herein, a method of reducing bow in a substrate is provided, the method including: receiving a substrate having a frontside and a backside; exposing the backside of the substrate to laser beams to cause a tensile internal stress in the backside of the substrate; and depositing a backside layer on the backside of the substrate having a tensile internal stress. In some embodiments, tensile internal stress of the substrate and the backside layer causes a wafer bow of at least about 1 mm.

[0008] In another aspect of the embodiments herein, a method of reducing bow in a substrate is provided, the method including: receiving a substrate having a frontside and a backside; etching one or more portions of the substrate using laser beams to create features; and depositing a backside layer on the backside of the substrate, wherein the backside layer fills the features and forms a uniform layer.

[0009] In some embodiments, the method further includes planarizing the backside layer.Docket No. LAM1P088WO

[0010] In another aspect of the embodiments herein, a method of etching features in a substrate is provided, the method including: receiving a substrate including one or more layers; modifying one or more layers in the substrate using laser beams; and depositing a backside layer on the backside of the substrate, wherein the backside layer fills the features and forms a uniform layer.

[0011] In another aspect of the embodiments herein, a method for depositing material is provided, the method including: receiving a substrate in a process chamber; and depositing material on the substrate using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process, wherein during depositing one or more portions of the substrate are exposed to laser beams.

[0012] In some embodiments, the laser beams heat the one or more portions of the substrate to a temperature of at least about 400 °C. In some embodiments, material substantially deposits only on the one or more portions of the substrate exposed to laser beams. In some embodiments, the CVD and ALD process each include flowing a species into the process chamber, and the laser beams cause a photochemical reaction of the species flowed into the process chamber. In some embodiments, the substrate has one or more features that correspond to the one or more portions of the substrate exposed to laser beams. In some embodiments, the one or more portions have a critical dimension of at least 1 pm.

[0013] In another aspect of the embodiments herein, a method of etching is provided, including: receiving a substrate in a process chamber; and etching material on the substrate by: exposing one or more portions of the substrate to laser beams; and exposing the substrate to a chemical species to react with the one or more exposed portions.

[0014] In some embodiments, exposing one or more portions of the substrate to laser beams occurs simultaneously with exposing the substrate to a chemical species. In some embodiments, exposing one or more portions of the substrate to laser beams occurs prior to exposing the substrate to a chemical species. In some embodiments, the one or more portions have a critical dimension of at least 1 pm.

[0015] In another aspect of the embodiments herein, a substrate is provided, including: a laser absorption layer; and an annealing layer, wherein one or more properties of the annealing layer changes under annealing conditions of at least about 600 °C.

[0016] In some embodiments, the laser absorption layer is the outermost layer. In some embodiments, the laser absorption layer includes one or more compositions from the group consisting of: amorphous silicon, silicon nitride, metal oxides, silicon oxide, carbon, metal, aluminum oxide, aluminum nitride, aluminum oxynitride, boron nitride, tungsten nitride,Docket No. LAM1P088WOtungsten carbide, and tungsten carbide-nitride. In some embodiments, the laser absorption layer is a sacrificial layer. In some embodiments, the substrate further includes a thermal insulation layer. In some embodiments, the thermal insulation layer includes one or more compositions from the group consisting of silicon oxide, silicon nitride, and low-k dielectric materials. In some embodiments, the substrate further includes a laser reflection and / or absorption layer. In some embodiments, the laser reflection and / or absorption layer includes tungsten, titanium nitride, or both.

[0017] In another aspect of the embodiments herein, a system for laser treatment of substrates is provided, including: a process chamber, wherein the process chamber includes: a laser; a substrate support; wherein the substrate support and the laser are movable with respect to each other; and a controller configured for performing any one of the methods above. In some embodiments, the laser includes a fixed laser head, a galvo scanner, a beam shaper, a beam splitter, or any combinations thereof. In some embodiments, substrate support and laser are movable along x- and y-dimensions relative to each other. In some embodiments, substrate support and laser are movable along radial and azimuthal dimensions relative to each other. In some embodiments, the laser is a pulsed laser. In some embodiments, the laser includes a pilot laser, wherein the pilot laser determines a distance between the laser and a substrate surface. In some embodiments, further including an inbound load lock, an outbound load lock, an atmospheric port, a wafer handling system, one or more other process chambers, or any combinations thereof, wherein the process chamber is located in one element selected from the group consisting of: the inbound load lock, the outbound load lock, or the atmospheric port. In some embodiments, the process chamber is configured to receive substrates from the wafer handling system.

[0018] In another aspect of the embodiments herein, a method is provided including: receiving a substrate having a frontside and a backside, wherein the substrate has a wafer distortion from one or more frontside layers on the frontside and a backside layer; and exposing one or more portions of a backside layer to laser beams to modify an internal stress of the one or more portions.

[0019] In some embodiments, exposing one or more portions of the backside layer to laser beams includes annealing the one or more portions, wherein annealing of the one or more portions causes chemical reactions to occur within the one or more portions, recrystallization of the one or more portions, or both. In some embodiments, the one or more portions have an elliptical or rectangular shape. In some embodiments, the substrate has in-plane distortion caused by the one or more frontside layers, wherein after exposure of the one or more portionsDocket No. LAM1P088WOof the backside layer to laser beams the backside layer reduces in-plane distortion (IPD) of the substrate. In some embodiments, the method further includes determining IPD of the substrate prior to exposing one or more portions, wherein exposing one or more portions of the backside layer to laser beams is based on the IPD of the substrate. In some embodiments, the method further includes depositing an additional backside layer and exposing one or more portions of the additional backside layer to laser beams to modify one or more properties of the one or more exposed portions of the additional backside layer. In some embodiments, the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction of the substrate, wherein the backside layer compensates the first bow more than it compensates the second bow; and wherein after exposing the one or more portions of the backside layer, the backside layer compensates more of the second bow. In some embodiments, the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction of the substrate, wherein the backside layer compensates the first bow more than it compensates the second bow; and wherein exposing one or more portions of the backside layer to laser beams includes etching the one or more portions of the backside layer, wherein after the etching the backside layer compensates the second bow more than before the etching. In some embodiments, the method further includes depositing an additional backside layer, wherein the additional backside layer backfills the etched one or more portions of the backside layer. In some embodiments, the additional backside layer compensates the second bow more than it compensates the first bow. In some embodiments, exposing portions of the backside layer to laser beams causes a tensile internal stress in the backside of the substrate; and depositing an additional backside layer on the backside of the substrate having a tensile internal stress. In some embodiments, exposing one or more portions of the backside layer to laser beams includes etching one or more portions of the substrate to create features; and wherein the method further includes depositing a backside layer on the backside of the substrate, wherein the backside layer fills the features and forms a uniform layer. In some embodiments, the method further includes etching the one or more portions of the backside layer exposed to laser beams, wherein unexposed portions of the backside layer are etched less than exposed portions. In some embodiments, the substrate includes one or more additional backside layers, wherein the one or more of additional backside layers include one or more layers selected from the group consisting of: a laser absorption layer; a thermal insulation layer; and a laser reflection. In some embodiments, the laser absorption layer includes one or more compositions from the group consisting of: amorphous silicon, silicon nitride, metal oxides, silicon oxide, carbon, metal, aluminum oxide, aluminumDocket No. LAM1P088WOnitride, aluminum oxynitride, boron nitride, tungsten nitride, tungsten carbide, and tungsten carbide-nitride. In some embodiments, the thermal insulation layer includes one or more compositions from the group consisting of silicon oxide, silicon nitride, and low-k dielectric materials. In some embodiments, the laser reflection layer, laser absorption layer, or both include tungsten, titanium nitride, or both.

[0020] In another aspect of the embodiments herein, a method is provided including: receiving a substrate in a process chamber; and exposing the substrate to a process gas including a reactive species; and exposing one or more portions of the substrate to laser beams.

[0021] In some embodiments, a material deposits on the one or more portions of the substrate exposed to laser beams and does not deposit on unexposed portions of the substrate. In some embodiments, the substrate is etched at the one or more portions of the substrate exposed to laser beams and is not etched at unexposed portions of the substrate.

[0022] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings.BRIEF DESCRIPTION OF DRAWINGS

[0023] Figures 1A-1C present illustrations of layer modification by laser treatment according to various embodiments herein.

[0024] Figure 2A shows example isometric views of various wafer bow shapes.

[0025] Figures 2B-2C show examples of in-plane distortion.

[0026] Figures 3A-3C illustrate schematic diagrams of modifying internal stress of layers according to various embodiments herein.

[0027] Figures 4A-4C present process flow diagrams for laser treatment layers according to various embodiments herein.

[0028] Figure 5 presents a comparison of complementary profile films and laser treated films according to various embodiments herein.

[0029] Figure 6A and 6B illustrate a top-down and isometric view of a wafer having parallel features laser etched into a layer.

[0030] Figures 7A and 7B illustrate two side views of thermal stress in layers according to various embodiments herein.

[0031] Figures 8A-8C present illustrations of high bow inducement according to various embodiments herein.

[0032] Figures 9A and 9B present process flow diagrams for laser treatments with chemical species according to various embodiments herein.Docket No. LAM1P088WO

[0033] Figures 10A-10F illustrate various films stacks according to various embodiments herein.

[0034] Figures 11A and 11B illustrate temperature as a function of film depth / thickness for silicon oxide and silicon films.

[0035] Figure 12 presents a schematic illustration of a laser according to various embodiments herein.

[0036] Figures 13A and 13B illustrate spot patterns according to various embodiments herein.

[0037] Figure 13C and 13D present intensity profiles for different beam shapes according to various embodiments herein.

[0038] Figures 14A-B and 15 presents a schematic diagram of an example process chamber for performing methods in accordance with disclosed embodiments.

[0039] Figures 16-21 present schematic diagrams of examples of wafer and laser control schemes according to various embodiments herein.

[0040] Figure 22 presents a schematic diagram of examples of multi-station tools for performing methods in accordance with disclosed embodiments.DETAILED DESCRIPTIONTerminology

[0041] The following terms are used throughout the instant specification:

[0042] The terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate” and “partially fabricated integrated circuit” may be used interchangeably. Those of ordinary skill in the art understand that the term “partially fabricated integrated circuit” can refer to a semiconductor wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. Examples of wafer materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe). Besides semiconductor wafers, other workpieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components such as backplanes for pixelated display devices, flat panel displays, micro-mechanical devices and the like. The workpiece may be of various shapes, sizes, and materials.

[0043] A “semiconductor device fabrication operation” as used herein is an operation performed during fabrication of semiconductor devices. Typically, the overall fabrication process includes multiple semiconductor device fabrication operations, each performed in itsDocket No. LAM1P088WOown semiconductor fabrication tool such as a plasma reactor, an electroplating cell, a chemical mechanical planarization tool, a wet etch tool, and the like. Categories of semiconductor device fabrication operations include subtractive processes, such as etch processes and planarization processes, and material additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etch processes, a substrate etch process includes processes that etch a mask layer or, more generally, processes that etch any layer of material previously deposited on and / or otherwise residing on a substrate surface. Such an etch process may etch a stack of layers in the substrate.

[0044] “Manufacturing equipment” refers to equipment in which a manufacturing process takes place. Manufacturing equipment often has a process chamber in which the workpiece resides during processing. Typically, when in use, manufacturing equipment performs one or more semiconductor device fabrication operations. Examples of manufacturing equipment for semiconductor device fabrication include deposition reactors such as electroplating cells, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive process reactors such as dry etch reactors (e.g., chemical and / or physical etch reactors), wet etch reactors, and ashers.

[0045] ‘ ‘Laser” as used herein refers to a device that emits a laser beam. A laser beam is a collection of photons that may be monochromatic, coherent, and collimated. An ideal laser beam is perfectly monochromatic, coherent, and collimated, though in practice these properties may be defined by density functions. Lasers may be defined based on their gain medium, e.g., gas, solid-state, diodes, etc. In some embodiments, lasers may also defined based on their mode of operation: continuous or pulsed. Continuous wave lasers emit a continuous output of laser beams, where the properties of the laser beam are substantially constant. Pulsed lasers have one or more properties that vary over time based on a frequency. Lor example, a pulsed laser may alternate between a pulse of laser beams having a high power and no or low power. Generally, the laser beams of a pulsed laser have a higher energy than the laser beams of a continuous wave laser, but due to the pulsing may have a similar power as a continuous wave laser.

[0046] Lasers have various additional characteristics that may be modified or controlled for use in semiconductor processing. The wavelength of the photons affects absorption and penetration for a specific composition, and is generally based on the gain medium. Power density may be defined by the power and spot size of the laser beam and defines the energy delivered per unit area and time. Lor pulsed lasers, energy density or fluence represents theDocket No. LAM1P088WOenergy transferred per unit area by a single pulse. Pulses may vary in duration, from femtoseconds to nanoseconds.

[0047] Lasers may also move relative to a substrate, either by movement or the laser itself or the substrate. Scanning speed refers to the velocity of motion between the laser and the substrate.

[0048] Lasers may also have various laser beam profiles. A laser beam profile is the intensity distribution of a laser beam at a particular point in space, e.g., a substrate surface. Profiles may include gaussian, rectangular, elliptical, etc. In some embodiments, laser beam profiles may be used with a beam splitter to cause a repeating pattern, such as a grid of dots or parallel, rectangular intensities.

[0049] Lasers for methods and apparatus described herein may include gas lasers, excimer lasers, and / or solid-state lasers. In some embodiments, a laser may emit laser beams having wavelengths between about 200 nm and about 1100 nm. In some embodiments, lasers may emit laser beams having wavelengths between about 200 nm and about 300 nm. In some embodiments, lasers may emit laser beams having wavelengths between about 8 microns and about 11 microns. In some embodiments, a laser may emit laser beams having a wavelength between about 200nm and about 10 pm. In some embodiments, a laser may be a DUV (deep-UV), which generally refers to use of 248nm or 193nm excimer laser sources.

[0050] In some embodiments, lasers described herein may have a power up to about 100 watts or between about 10W and about 50 W. In some embodiments, a laser may have a fluence between about 0 and about 10 joules / cm2or between about 0.5 and about 1 joules / cm2.

[0051] ‘ ‘Wafer distortion” as used herein may refer to a deformation of a wafer, including out-of-plane distortion, e.g., wafer bow, and in-plane distortion. The deformation may have radial and / or azimuthal components. In some embodiments, wafer distortion may be described by wafer bow. In some embodiments, wafer distortion may be described by in-plane distortion.

[0052] “Overlay error” refers to a misalignment between two features on a substrate. Overlay error may quantify how far the measured positions of features deviate from intended positions. In some embodiments, overlay error may be expressed as X and Y displacement in, e.g., nanometers. Overlay error may be caused by lithography tool misalignment, wafer distortion, thermal or process-induced stress, and optical aberrations. Overlay error may impact device yield and performance, as misalignment between, e.g., interconnects, contacts, and patterns from different layers may cause device failure. In some embodiments, overlay error may be used to determine distortion of a wafer.

[0053] ‘ ‘Wafer bow” refers to deformation of a wafer out of a reference plane defined by aDocket No. LAM1P088WOfrontside of the wafer and coincident with the frontside of the wafer in the absence of any wafer bow. Examples of types of wafer bow include dome shapes, bowl shapes, and saddle shapes. Wafer bow may occur during fabrication, for example, as a result of stress to the wafer during deposition of materials on an active surface of a wafer. Wafer bow may occur during various types of fabrication, such as when large stacks of materials are deposited. Wafer bow may cause complications in subsequent processing steps. For example, the wafer may fail to chuck correctly if an amount of bowing is too large, which may subject the wafer to nonuniform heating and / or other process conditions. Moreover, some processing steps (e.g., photolithography) may produce poor results if performed on a wafer that is excessively bowed.

[0054] In some embodiments, wafer bow may be measured as a deviation of the mean or median distance of the surface of the wafer to a reference plane. In some embodiments, the point of the median surface of the wafer may be the center point (e.g., in the case of concave or domed bowing), or an edge point of the wafer and / or an average edge point of the wafer (e.g., in the case of warping or convex bowing). In some embodiments wafer bow may be measured from a reference plane such that when an edge point of the wafer is below the reference plane the edge point is considered to have a negative bow, and when the edge point of the wafer is above the reference plane the edge point is considered to have a positive bow. In some embodiments, positive or negative bow may be measured along a z axis perpendicular to the reference plane.

[0055] In some embodiments, wafer bow may vary between the two principal planar directions of a substrate, which are referred to as the x and y directions. For example, wafer bow along the x direction may be in a positive z direction while wafer bow along the y direction may be in a negative z direction (the z axis being perpendicular to a plane formed by the planar x and y directions). Figure 2A illustrates 8 shapes that may be formed based on bowing in x and y directions. When bowing is positive along the x and y directions, a bowl shape is formed, while when bowing is negative in the x and y directions, an umbrella or dome shape is formed. Other shapes include a “half pipe” or “taco” shape when there is substantially no wafer bow in one direction while a positive or negative bow in the planar perpendicular direction. When wafer bow is positive in one direction and negative in another direction, a “saddle” or “potato chip” shape is formed.

[0056] Wafer bowing may be characterized by x-bow and y-bow values. A positive x-bow value corresponds to bowing of the wafer in a positive z-direction at a coordinate of the wafer having a large x- value and a small or zero y- value, e.g., an x- value greater than about 100 mm or of about 150 mm (for a 300 mm wafer) and a y-value of about 0 mm (where the referenceDocket No. LAM1P088WOpoint is at a center of the wafer). A negative x-bow value similarly corresponds to bowing of the wafer in a negative z-direction at a coordinate of the wafer having a large x- value and a small or zero y- value. Conversely, a positive y-bow and negative y-bow correspond to bowing of the wafer in positive or negative z-directions, respectively, at a coordinate of the wafer having a large y- value and a small or zero x-value.

[0057] In some embodiments, wafer bow may be characterized by a single value. In some embodiments, wafer bow may be described as a “delta bow.” When referring to wafer bow of saddle-shaped wafers, the wafer delta bow may be expressed in terms of a difference between the negative-bow in one direction (such as along the x-axis) and positive-bow in another direction (such as along the y-axis). For example, a wafer bow of 200 pm may result from an x-bow of -25 pm and a y-bow of +175 pm. For wafers having a taco, bowl, or dome-shaped wafer bow, wafer bow may refer to a difference between the maximum bow and a reference plane as described above.

[0058] Wafer bow is related to internal stresses of the substrate and various layers on the substrate, including frontside and backside layers. Internal stress may be measured in Pascals: positive values indicate a tensile stress and negative values indicate a compressive stress. In view of Figure 2A, assuming a layer is deposited on top of the wafer shown, a “bowl” shape would result from a layer having a tensile internal stress. Conversely, an “umbrella” shape would result from a layer having a compressive internal stress. Generally, when comparing stresses, a “more tensile” stress may be referred to as having a greater number, e.g., larger if positive or closer to zero if negative. Similarly, a “more compressive” stress may be referred to as having a lower number, e.g., smaller is positive or further from zero if negative. “Mitigating” or “compensating” internal stress may be referred to as reducing the magnitude of internal stress regardless of whether the internal stress is tensile or compressive. Mitigating may refer to a combined internal stress, e.g., backside layers mitigating internal stress from frontside layers to reduce wafer bow. Mitigating may also refer to the stress of a single film. In various embodiments herein, a film may be treated to mitigate internal stress of portions of the film, i.e., reduce the magnitude of internal stress, regardless of whether the internal stress is tensile or compressive.

[0059] ‘ ‘In-plane distortion (IPD)” refers to distortion of a substrate within a reference plane of the surface of the substrate, e.g., a frontside surface, caused by internal stresses of a substrate and frontside / backside layers. For example, if a rubber band was marked with two dots and stretched, the dots would move apart. Even if the ends of the rubber band are held fixed, if various portions of the rubber band are strained (i.e., stressed), the dots may still move withDocket No. LAM1P088WOrespect to each other. This movement from an original position may be measured as IPD and is generally undesirable. It can cause problems with overlay for lithographic processes, as the lithography process must measure and account for any IPD that occurs to ensure the pattern is properly transferred to a photoresist. IPD may be present even if a wafer is clamped flat to, e.g., reduce and / or eliminate wafer bow.

[0060] Figures 2B and 2C are wafer maps of substantially flat wafers each comprising a plurality of semiconductor devices 202 (it should be understood that the spacing and shapes have been simplified). Figure 2B represents a wafer having zero IPD, where each device 202 has a square shape and is evenly distributed across the surface of the wafer.

[0061] Figure 2C, by contrast, has significant IPD across the wafer surface. The IPD may cause some devices to be appear smaller, such as device 206, while other devices may appear larger or misshapen, such as device 204. IPD presents a significant problem for semiconductor processing as photolithography processes must correct for IPD, which may manifest as overlay error, to properly align semiconductor processes. Furthermore, IPD may vary across the surface of the wafer in a non-linear manner. The non-linear nature of IPD makes it difficult to correct using one or more backside layers having uniform internal stress. Furthermore, the IPD may remain even after clamping the wafer to a pedestal, which may reduce wafer bow to near- zero across the surface of the wafer but does not correct IPD. Notably, IPD as shown in Figure 2B may be present even if a wafer is substantially flat, e.g., a delta bow of the wafer is less than about 400 pm.

[0062] In some embodiments, IPD may be measured as a vector, e.g., a vector map, indicating distortion of a point on a wafer surface within a reference plane of the wafer surface. The vector may represent a magnitude and direction of the distortion. In some embodiments, the magnitude may be an absolute value of distortion, e.g., nm or mm. In some embodiments, the magnitude may be represented by a scaling unit, such as stretch per mm of the surface, e.g., a 20 ppm magnification in the X direction for a 300 mm wafer indicates a shift of 6 pm. A vector map may include IPD vectors for a plurality of points on a wafer surface.

[0063] Internal stress of a wafer, including internal stress of portions of a wafer, may be determined by various methods. In some embodiments, stress may be derived from wafer shape data, including OPD or IPD. OPD may include wafer bow measurements as described above. In some embodiments, OPD may be measured using various metrology techniques, including laser interferometry, low-power laser beam triangulation, or direct surface contact.

[0064] In some embodiments, OPD, e.g., wafer bow, may be correlated with internal stress, particularly aggregate internal stress of an entire substrate. In some embodiments, the firstDocket No. LAM1P088WOderivative of OPD may describe in-plane distortion (IPD) of a wafer, and the second derivative of OPD data (and thus first derivative of IPD data) may describe internal stress of a wafer. In some embodiments, the internal stress determined using derivatives of OPD or IPD may describe internal stress of various portions of a substrate.

[0065] In some embodiments, IPD may be measured using OPD, image-based overlay (IBO) methods, or diffraction-based overlay (DBO) methods. IPD and overlay error are related. In some embodiments, IPD may be caused by internal stress of a wafer, which may vary non-linearly across the surface of the wafer. IPD may be measured as an in-plane displacement of a point or portion of a wafer from an ideal, no-stress position. In some embodiments, overlay error describes an offset between features in a single layer or two layers, which may be caused by IPD or by other causes, e.g., scanner misalignment. In some embodiments, overlay error may be measured as an additional difference in position between two features, e.g., two features may be measured as having a relative position to each other of a pre-determined offset + any overlay error. In some embodiments, overlay error may be used to determine IPD, particularly if other sources of overlay error are controlled.

[0066] IBO methods may capture one or more optical images of a substrate and analyze features in the images to determine a displacement between two features. In some embodiments, the features may be between two layers and the displacement may be measured in X and Y directions. The displacement may then be used to determine an overlay error between the two layers. The overlay error may then be used to determine IPD. This process may be repeated for images across the surface of a wafer to determine IPD at various portions of the wafer.

[0067] DBO methods rely on spectroscopic scatterometry techniques to determine a displacement between features. In some embodiments, a set of features are patterned on a substrate with a known distance between each feature. In some embodiments, two sets of features may be patterned, with each set on an overlying / underlying layer of the other set and one set of features offset from the other set of features by a known distance. In some embodiments, a plurality of supersets of features may be patterned, where each superset includes two sets of features as described above and each superset has a different offset between the two sets of features. In some embodiments, a first superset and second superset may have equal and opposite offsets. In some embodiments, a third superset may have an offset different from the first superset and second superset.

[0068] A laser beam is then directed to the set(s) of features perpendicular to the substrate surface and the reflected signal may be measured and analyzed. In some embodiments, theDocket No. LAM1P088WOreflected signal is modeled to determine an overlay error based on the measured reflected signal compared to an expected reflected signal if no overlay error is present. In some embodiments, the reflected signal from different features may be compared. For example, reflected signals from supersets having equal and opposite offsets should cancel out if no overlay error is present. Any difference in the reflected signals may be correlated with overlay error. In some embodiments, a signal-to-noise ratio (SNR) of a difference spectra obtained from two signals may be correlated with overlay error, where greater SNR means a greater overlay error. In some embodiments, multiple supersets may be used with different offsets to empirically determine the relationship between SNR and overlay error. In some embodiments, the methods described above determine an overlay error in a first direction corresponding to the direction of the offset. The methods may be repeated with features in a second direction perpendicular to the first direction to determine X and Y overlay error. The overlay error may then be used to determine IPD. In some embodiments, the above method may be repeated at various positions of a wafer to determine IPD at the various positions of the wafer.Introduction

[0069] Materials may interact with light by transmission, reflection, and absorption. For a given material, various ranges of wavelengths may be transmitted, reflected, and / or absorbed. Controlling the wavelength, power, fluence, scanning speed, beam profile, etc., of a laser beam may affect how the photons of light interact with the material. In this disclosure, laser beams may be used to etch or modify materials on a surface of a substrate. By control of the properties of the laser beam and interaction of the laser beam with films, the properties of the films may be modified. In some embodiments, portions of a film may be exposed to laser beams, causing modified regions in the film to form. Modified regions may have a similar composition as the surrounding film, e.g., silicon nitride, but have different properties. For example, crystallinity, hydrogen content, internal stress, or other properties may be modified in modified regions compared to unmodified regions.

[0070] Figures 1A-1C present three different examples of using laser beams 108a-c to modify and / or etch one or more layers on a substrate. In Figure 1A, a substrate 102a having a layer 104a is exposed to laser beam 108a to generate a modified region 106a. The modification may include thermal annealing, e.g., heating of modified region 106a, as well as chemical changes, e.g., cross -linking. In some embodiments, the material phase or other material properties of layer 104a may be modified in modified region 106a.

[0071] Figure IB presents a substrate 102b treated with laser beam 108b, having a layer 104b and a modified region 106b that includes portions of layer 104b and substrate 102b. In someDocket No. LAM1P088WOembodiments, the laser treatment may interact with multiple layers, including a substrate layer that may be, e.g., crystalline silicon. In some embodiments, it is desirable to modify portions of substrate 102b, while in other embodiments substrate 102b may be modified as a side-effect of modifying layer 104b.

[0072] Figure 1C presents a substrate 102c having a layer 104c. Layer 104c has been partially etched by laser beam 108c to generate feature 107c as well as modified region 106c. In some embodiments, etching may occur by an ablation process that vaporizes material in layer 104c. In some embodiments, the portion of layer 104c near the ablated region is modified, e.g., thermally annealed, as shown by modified region 106c. In other embodiments, such a modified region does not exist as the ablated material does not heat the surrounding material.

[0073] While a single area of exposure is shown in Figures 1A-1C, in some embodiments the entire surface of a substrate or only portions of the surface of a substrate are exposed to laser treatment. Furthermore, while only two layers are shown, multiple layers may be present and have various interactions with a laser treatment. Described herein are various applications of laser treatments to modify and / or etch portions of layers on semiconductor substrates.

[0074] In some embodiments, laser treatments disclosed herein are applied to backside layers or the backside of a substrate. Semiconductor devices are developed on the frontside of a substrate by a series of layers formed by deposition and etch operations. Backside layers, by contrast, are not integrated into semiconductor devices but may be present on a chip. In some embodiments, backside layers may be used to correct wafer bow caused by frontside layers.

[0075] In some embodiments, laser treatments disclosed herein are applied to frontside layers or the frontside of a substrate. Semiconductor fabrication processes often include dielectric gap fill using chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) methods to fill features. Described herein are methods of filling features with dielectric material including but not limited to silicon-containing films such as silicon oxide or silicon nitride, and related systems and apparatuses. The methods described herein can be used to fill vertically oriented features formed in a substrate. In some embodiments, ALD process described herein may be “thermal ALD” processes or “non-plasma ALD” processes, which refer to ALD processes that are performed at elevated temperatures without striking a plasma. While a non-plasma ALD process is described herein, in some embodiments ALD processes described herein may be combined with plasma ALD processes where a plasma is ignited for one or more steps of an ALD process. In some embodiments, laser treatments disclosed herein may be combined with CVD or ALD methods to fill features of at least 1 pm in size.Docket No. LAM1P088WODistorted Wafers

[0076] One application for laser treatment is to mitigate distorted wafers, including bowed wafers. Semiconductor device fabrication often involves deposition of a stack of layers or films on a wafer. Typically, most deposition and other processing to form the devices occurs on one side of the wafer, often referred to as the front face or frontside of a wafer. As the deposited layers build up, they can introduce stress in the wafer. A large net tensile or compressive stress can cause out-of-plane distortion (OPD), e.g., wafer bow (and potentially cause cracks in cases of excessive tensile stress), which is undesirable. IPD may similarly be caused by internal stress from one or more frontside and one or more backside layers. Tensile or compressive stress from deposited layers may cause increased stress at various portions of a wafer surface, which may cause those portions to distort in-plane compared to other portions, e.g., IPD.

[0077] Distortion is especially likely to occur where large stacks of materials are deposited, for example, in the context of 3D-NAND devices, or where a thick frontside layer is deposited. Where distortion is significant, it can deleteriously affect subsequent processing steps. For instance, the wafer may fail to chuck correctly if the bowing is too great. Figure 2A shows various types of bowing. When a wafer is substantially flat for purposes of a particular process operation, e.g., having a bow of about 100 pm or less, the wafer may be properly clamped, securing the wafer for subsequent processing steps. Wafer bowing may result from frontside layers having a compressive internal stress, causing a dome shape. Frontside layers having a tensile internal stress may cause a wafer to bow in the opposite manner, having a bowl shape.

[0078] When the distortion is significant, various manufacturing problems may arise. In some instances, the wafer may fail to secure properly on the electrostatic chuck. This may cause various nonuniformity issues — for example, the wafer may not be heated uniformly, the process gases may not be applied to the wafer uniformly across the wafer, and / or the distance between the wafer and the showerhead and / or showerhead pedestal may not be maintained evenly in parallel (i.e., parallelism may be disrupted). Wafer bow may cause other problems. For example, certain processing steps (e.g., photolithography) are very precise and produce poor results if the wafer is not substantially flat. The problem may be manifest as lithography defocus or overlay error. Figure 2C shows an example of IPD, where distortion of the wafer surface may cause overlay error. When overlay error is below a threshold value, a semiconductor processing tool, such as a lithographic exposure tool, may compensate for the overlay error. Cracking may also occur, which can introduce additional defects, reducing yield.

[0079] One example stack that may cause these problems is a stack having alternating layers of oxide and nitride (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.).Docket No. LAM1P088WOAnother example of a type of stack likely to cause bowing includes alternating layers of oxide and polysilicon (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of stack materials that may be problematic include, but are not limited to, tungsten and titanium nitride.

[0080] The materials in the stacks may be deposited through chemical vapor deposition (CVD) techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or plasma enhanced atomic layer deposition (PEALD), or through direct metal deposition (DMD), etc. These examples are not intended to be limiting. Certain disclosed embodiments may be useful whenever wafer stress and / or bowing are induced due to material present on the frontside of the wafer.

[0081] The frontside stacks may be deposited to any number of layers and thicknesses. In an example, the stack may include about 20 or more layers, and have a total thickness of about 2 pm to about 4 pm. In some cases, multiple-layer stacks may include about one hundred or more layers. In some embodiments, multiple-layer stacks may have about five hundred or more layers. In some embodiments, the multiple-layer stacks may have about one thousand or more layers. Such stacks may have a thickness of about 4 pm to 12 pm, for example.

[0082] The stress induced in the wafer by the stack or other frontside deposition may be about -500 MPa to about +500 MPa. In some embodiments, the resulting in a bow is about 150 pm or greater, e.g., about 300 pm and above, about 400 pm and above, or about 200 pm to about 400 pm (for a 300 mm wafer).

[0083] Another cause of wafer distortion may be frontside processing which uses thick hardmasks with limited etch selectivity. In these embodiments, at least one of the one or more frontside layers is a hardmask. The thick hardmasks may have an internal stress similar to those described above, e.g., have a magnitude of 0 MPa to about 500 MPa. The stress caused by the hardmask may be tensile stress or compressive stress. The thick hardmasks may cause wafers to have a significant wafer bow, e.g., about 150 pm or more.

[0084] Various techniques have been devised for combatting bowing. When bowing is severe, deposition processes may be tuned to reduce or counteract internal stresses in deposited layers. However, any such tuning should not interfere with process requirements for fabricating devices. One commonly used technique to counteract bowing deposits layers on the backside of the wafer.

[0085] Backside deposition may form a high-stress film on the backside of the wafer intentionally to control overall stress and bowing of the wafer. If the backside layer has theDocket No. LAM1P088WOsame type of internal stress (tensile or compressive) and of comparable magnitude to the internal stress created on the frontside of the wafer, the backside film effectively counteracts and reduces the bow of the wafer.

[0086] Examples of backside films used to counteract bow include the following: amorphous silicon, silicon oxide, silicon nitride, and silicon oxynitride. Variations of these films may be used, such as doped amorphous silicon, doped silicon oxide, doped silicon nitride, and doped silicon oxynitride; and these films may be formed under different deposition conditions to tune and optimize their material properties. Also, other types of films that may be introduced during the semiconductor process may be used in conjunction with, and / or instead of, these exemplary films. Current backside films have high internal stress and can mitigate the stresses imparted on the wafer from the frontside layers to reduce or eliminate the wafer bow. Although not required, generally, backside layers are made of films with high stress when deposited on the silicon wafer. High-stress films may be preferred because a high-stress films may compensate the wafer bow more efficiently for a given thickness of film.

[0087] In some embodiments, backside films are relatively uniform because the bow caused by depositing material on the frontside is relatively symmetrical, forming a bowl or dome shape based on an isotropic internal stress. Thus, depositing a uniform film, either with tensile or compressive internal stress, could mitigate the stress imparted on a wafer from the frontside layers as the backside film would impart an opposite wafer bow that is similarly symmetrical. However, certain frontside deposition techniques may cause anisotropic stress, such that the internal stress on the frontside of the wafer, and hence the resultant bowing, varies in one principal planar direction compared to another principal planar direction, e.g., x and y directions. In such embodiments a wafer may have x-bow and y-bow that are different in magnitude as well as direction (or sign). A uniform backside layer may insufficiently address such saddle-shaped wafer bow. Similarly, anisotropic stress may cause IPD that a uniform backside layer may insufficiently address.

[0088] Figure 2A illustrates 8 different shapes that may form based on different combinations of positive or negative bowing along x and y axes or directions. A bowl, umbrella, half pipe, or saddle shape may be formed depending on whether wafer bow along the x and y directions is positive, negative, or substantially non-existent. When a wafer bow shape is a bowl or umbrella, a film having an isotropic tensile or compressive internal stress may properly mitigate the stress imparted on the wafer from frontside layers. However, when the wafer bow shape is a different shape, e.g., a saddle or half pipe shape, an isotropic internal stress would either over or under compensate wafer bow along the x or y direction, or potentially exaggerateDocket No. LAM1P088WOwafer bow. For example, an isotropic tensile backside film deposited on a wafer having a negative x-bow and positive y-bow (i.e., saddle shape) would mitigate wafer bow along the y direction, but would increase wafer bow along the x direction.Internal Stress Control

[0089] Disclosed herein are techniques to mitigate internal stress by laser treatment of backside films. In some embodiments, laser treatment may be used for annealing films. Laser annealing operates by exposing a substrate to laser beams that are absorbed by a layer on the substrate. The absorbed energy may then heat the layer absorbing it or heat a nearby layer, annealing one or more films. This technique presents advantages over other anneal processes as the annealing may be localized to a particular film in a film stack or even portions of a film in a film stack. By not heating adjacent or nearby layers, a single layer may be annealed without negatively affecting other layers that may be undesirably modified if annealed. Furthermore, a single film may be deposited and the internal stress of the film may be locally modified to generate, e.g., a compressive stress in one direction and a neutral or tensile stress in a different direction. Alternatively, the film may be etched along lines or patterns to remove portions of a film, reducing internal stress based on the etched portions to create anisotropic internal stress.

[0090] Furthermore, laser annealing may be used to reduce in-plane distortion (IPD) of the substrate. IPD refers to distortion from reference points on a substrate. For example, if a rubber band was marked with two dots and stretched, the dots would move apart. Even if the ends of the rubber band are held fixed, if various portions of the rubber band are stretched, the dots may still move with respect to each other. This movement from an original position may be measured as IPD and is generally undesirable. It can cause problems with overlay for lithographic processes, as the lithography process must measure and account for any IPD that occurs to ensure the pattern is properly transferred to a photoresist.

[0091] Wafer bow and internal stress contribute to IPD. While wafer bow may be considered an out of plane distortion, e.g., bowing along a z-axis, wafer bow causes strain in the x and y directions that may be measured as IPD. Furthermore, backside films deposited to mitigate wafer bow may have internal stresses that do not match the internal stresses of the frontside films. Thus, when the internal stresses are super-imposed, the wafer may have a non-flat shape that causes IPD.

[0092] Laser annealed films as described herein may reduce IPD by local annealing of films. In particular, deposited films may undergo a stress shift during a laser anneal operation that persists after the operation. In some embodiments, a film may have a stress shift that causes the film to have a more compressive or more tensile internal stress. A laser treatment may beDocket No. LAM1P088WOused to cause local stress shifts by local annealing.

[0093] Stress shift may occur under annealing conditions, e.g., temperatures greater than about 600°C. A stress shift is the change in internal stress of a film, typically after annealing. This stress shift may result from unreacted species in the film, such as hydrogen and nitrogen, which may be present in Si-H or N-H bonds from precursors and reactants such as silanes and NH3 (For, e.g., a silicon nitride film). Under annealing conditions these bonds may react and the hydrogen and / or nitrogen may diffuse to the surface, leaving the film and changing the internal stress. Alternative annealing mechanisms may include recrystallization or melting to relax internal stresses.

[0094] In some embodiments, laser treatments as disclosed herein may anneal films to a higher temperature than used in conventional furnaces. For example, whole-substrate annealing may typically be performed at temperatures up to about 900 °C, which may be limited by various layers already present on the wafer that may undergo undesirable modifications at higher temperatures. Laser annealing, by contrast, may heat a layer to at least about 1200°C or at least about 1500°C, which may enable faster annealing and / or different process mechanisms, without heating underlying layers to such temperatures. This may be advantageous as some films may recrystallize or melt at higher temperatures than a furnace can use, or above temperatures that other films would undesirably be modified at. In some embodiments, laser treatment may heat a wafer to cause ablation, which is the vaporization of material and may occur at temperatures greater than about 2000 °C depending on the particular material.

[0095] Laser annealing may be used to heat a portion of a film by controlling the interaction of laser beams with the film. By exposing a portion of a film to laser beams, that portion may be heated and annealed. In some embodiments, portions of the film not exposed to laser beams may still be heated by conduction, but to a lesser extent such that unexposed portions of the film do not anneal or anneal to a lesser extent.

[0096] Figures 3A-3C illustrate three different mechanisms for local laser treatment of backside films. Figure 3A illustrates an operation 310a having exposed portions 306a and unexposed portions 304a. Width describes the width of an exposed portion, while pitch describes the center-to-center distance between exposed portions (shown here on the left edge for clarity). In Figure 3A, exposed portions 306a are exposed to a laser treatment and thus have a different internal stress than unexposed portions 304a. In some embodiments, the internal stress of the exposed portions is more tensile than the internal stress of the unexposed portions. In some embodiments, the internal stress of the exposed portions is more compressive than the internal stress of the unexposed portions.Docket No. LAM1P088WO

[0097] Figure 3B illustrates etching of a wafer by laser treatment. Laser etching, or ablation, may occur by vaporizing material in exposed regions, as shown in Figure 1C. In operation 310b, exposed regions 308b have been etched, while unexposed regions 304b are not etched. In operation 312b, a new material 309b is then deposited within exposed regions. In some embodiments, new material 309b is deposited in the exposed regions as well as over the unexposed regions to form a uniform layer over the exposed and unexposed regions. In other embodiments, new material is only deposited within exposed regions to fill etched features. In some embodiments, new material 309b may also be planarized to form a uniform thickness layer.

[0098] Figure 3C illustrates an exposure and development for removal of material. In operation 310c, exposed regions 305c are modified by exposure to laser beams. This modification may include breaking / forming chemical bonds. In operation 312c, the exposed regions 305c are developed to remove the modified material. This may be a wet or dry development / etch process. In operation 314c, new material 309c is deposited in the exposed regions as well as over the unexposed regions to form a uniform layer over the exposed and unexposed regions. In other embodiments, new material is only deposited within exposed regions to fill etched features. In some embodiments, new material 309c may also be planarized to form a uniform thickness layer.

[0099] Figures 4A-4C provide process flows for fabrication processes according to various embodiments herein. Figures 4A-4C may correspond with Figures 3A-3C, above, as well as other operations and processes described herein. In some embodiments, various operations disclosed herein may be performed in different process chambers, for example deposition of a backside film and exposure to laser treatment may be performed in separate process chamber. The process of Figure 4A starts with measuring and / or identifying distortion of a wafer (402). The wafer may have one or more frontside layers deposited thereon, and one or more backside layers deposited thereon, that cause distortion of the wafer. Measuring and / or identifying the wafer distortion may include measuring or determining the shape of the wafer, which dimension has a larger bow, and any IPD. In some embodiments, measuring and / or identifying the wafer distortion may include measuring and / or identifying x-bow and y-bow values. In some embodiments, measuring and / or identifying wafer distortion may include measuring and / or identifying a map of wafer deflection across the wafer surface. In some embodiments, measuring and / or identifying wafer distortion may include measuring and / or identifying a map of overlay error across the wafer surface.

[0100] After measuring and / or identifying wafer distortion, the wafer is received into a processDocket No. LAM1P088WOchamber (404). In some embodiments, measuring and / or identifying wafer distortion may be performed as part of receiving the wafer into the process chamber or after receiving the wafer into the process chamber.

[0101] A backside layer having an internal stress is deposited (406a). The internal stress may be either compressive or tensile. The type of internal stress of the film may be based upon the wafer bow. For example, a substantially +X / +Y wafer bow may be mitigated a tensile internal stress backside layer. In some embodiments, the backside layer exhibits a stress shift under annealing conditions.

[0102] Generally, a tensile film pulls a positive bow to a more planar shape, while a compressive film would push a negative bow to a more planar shape. Thus, based on the x-bow and y-bow of the incoming wafer, a backside layer capable of a stress shift may be deposited to properly address the x-bow and y-bow. Depending on which wafer bow is addressed by the internal stress of the backside layer, the backside layer may be laser annealed to cause a stress shift to address the other wafer bow (i.e., x-bow or y-bow).

[0103] Portions of the backside layer are then exposed to a laser treatment to modify internal stress of the exposed portions (408a). In some embodiments, portions of the backside layer are exposed based on the wafer distortion measured and / or identified in operation 402. In some embodiments, the exposed portions of the backside layer represent a subset of a set of portions of the backside layer. Laser treatment may be performed with a continuous wave or pulsed laser. In some embodiments, the laser treatment modifies the exposed backside layer as well as an underlying backside layer. For example, a first backside layer may be a sacrificial layer to absorb laser beams, while a second, underlying backside layer is heated by conduction and anneals. The first backside layer may then be removed in a later processing step.

[0104] In some embodiments, after exposing portions of the backside layer, distortion of the wafer is reduced. As noted above, wafer distortion may include out-of-plane distortion and / or in-plane distortion, measured as wafer bow and / or one or more IPD vectors, respectively. In some embodiments, operation 408a may be performed based on the distortion of the wafer. After performing operation 408a, wafer distortion may be reduced, e.g., a lesser magnitude of wafer bow and / or IPD.

[0105] In some embodiments, operations 406a and 408a may be repeated one or more times. These operations may be repeated to deposit a layer stack, such as one shown in Figure 8B. In some embodiments, each laser treated film may have a thickness less than about 1 pm, where a stack of laser treated films may have a total thickness greater than about 1pm, greater than about 2 pm, greater than about 3 pm, or between about 1 pm and about 3 pm. In someDocket No. LAM1P088WOembodiments, additional laser treated layers may undergo different laser treatment in operation 408a. For example, a first backside layer may be deposited and laser treated based on a first combination of width and pitch, and a second backside layer may be deposited and laser annealed based on a second combination of width and pitch. A stack of films may generally decrease throughput compared to a single film. However, a stack of laser treated films may have improved material properties, including cracking margin, thermal stability, adhesion, substrate surface protection, and film uniformity.

[0106] Optionally, in some embodiments additional backside layers are deposited (411a). In some embodiments, the laser treated backside layer may equalize the x-bow and y-bow, however some bowing may still be present. In such embodiments, the wafer may have a bowl or umbrella shape. Thus, depositing a film having an isotropic internal stress may help further reduce the wafer bow. In some embodiments, an isotropic internal stress film is deposited, e.g., a tensile film or compressive film, to further mitigate wafer bow. The type of internal stress and the magnitude of the internal stress may be based upon the wafer bow. A positive wafer bow, or bowl shape, may be mitigated with a tensile film, while a negative wafer bow, or dome / umbrella shape, may be mitigated with a compressive film.

[0107] Figure 4B illustrates a process for depositing and etching a backside layer by laser treatment. The process of Figure 4B starts with measuring and / or identifying distortion of a wafer (402). The wafer may have one or more frontside layers deposited thereon, and one or more backside layers deposited thereon, that cause bowing of the wafer. Measuring and / or identifying the wafer distortion may include measuring or determining the shape of the wafer as well as which dimension has a larger bow. In some embodiments, measuring and / or identifying the wafer distortion may include measuring and / or identifying x-bow and y-bow values. In some embodiments, measuring and / or identifying wafer distortion may include measuring and / or identifying a map of wafer deflection across the wafer surface. In some embodiments, measuring and / or identifying wafer distortion may include measuring and / or identifying a map of overlay error across the wafer surface.

[0108] After measuring and / or identifying wafer distortion, the wafer is received into a process chamber (404). In some embodiments, measuring and / or identifying wafer distortion may be performed as part of receiving the wafer into the process chamber or after receiving the wafer into the process chamber.

[0109] A backside layer having an internal stress is deposited (406b). The internal stress may be either compressive or tensile. The type of internal stress of the film may be based upon the wafer bow. For example, a substantially +X / +Y wafer bow may be mitigated a tensile internalDocket No. LAM1P088WOstress backside layer. In some embodiments, the backside layer exhibits a stress shift under annealing conditions. In other embodiments, the backside layer does not exhibit a stress shift under annealing conditions.

[0110] Portions of the backside layer are then exposed to a laser treatment to remove the exposed portions (408b). In some embodiments, portions of the backside layer are exposed based on the wafer distortion measured and / or identified in operation 402. In some embodiments, the exposed portions of the backside layer represent a subset of a set of portions of the backside layer. Laser treatment may be performed with a continuous wave or pulsed laser. In some embodiments, the laser treatment ablates material from the exposed portions of the backside layer.

[0111] In some embodiments, after exposing portions of the backside layer, distortion of the wafer is reduced. As noted above, wafer distortion may include out-of-plane distortion and / or in-plane distortion, measured as wafer bow and / or one or more IPD vectors, respectively. In some embodiments, operation 408b may be performed based on the distortion of the wafer. After performing operation 408b, wafer distortion may be reduced, e.g., a lesser magnitude of wafer bow and / or IPD.

[0112] Optionally, in some embodiments additional backside layers are deposited (411b). In some embodiments, the additional backside layers may backfill etched portions of the backside layer. In some embodiments, the laser treated backside layer may equalize the x-bow and y-bow, however some bowing may still be present. In such embodiments, the wafer may have a bowl or umbrella shape. Thus, depositing a film having an isotropic internal stress may help further reduce the wafer bow. In some embodiments, an isotropic internal stress film is deposited, e.g., a tensile film or compressive film, to further mitigate wafer bow. The type of internal stress and the magnitude of the internal stress may be based upon the wafer bow. A positive wafer bow, or bowl shape, may be mitigated with a tensile film, while a negative wafer bow, or dome / umbrella shape, may be mitigated with a compressive film.

[0113] Figure 4C illustrates a process for depositing and etching a backside layer by laser treatment and a wet or dry development process. The process of Figure 4B starts with measuring and / or identifying distortion of a wafer (402). The wafer may have one or more frontside layers deposited thereon, and one or more backside layers deposited thereon, that cause distortion of the wafer. Measuring and / or identifying the wafer distortion may include measuring or determining the shape of the wafer as well as which dimension has a larger bow. In some embodiments, measuring and / or identifying the wafer distortion may include measuring and / or identifying x-bow and y-bow values. In some embodiments, measuringDocket No. LAM1P088WOand / or identifying wafer distortion may include measuring and / or identifying a map of wafer deflection across the wafer surface. In some embodiments, measuring and / or identifying wafer distortion may include measuring and / or identifying a map of overlay error across the wafer surface.

[0114] After measuring and / or identifying wafer bowing, the wafer is received into a process chamber (404). In some embodiments, measuring and / or identifying wafer bow may be performed as part of receiving the wafer into the process chamber or after receiving the wafer into the process chamber. A backside layer is deposited (406c). In some embodiments, the backside layer has a composition that may be changed by exposure to a laser treatment. In some embodiments, the backside layer is a photoresist.

[0115] Portions of the backside layer are then exposed to a laser treatment to modify the exposed portions (408c). In some embodiments, portions of the backside layer are exposed based on the wafer distortion measured and / or identified in operation 402. In some embodiments, the exposed portions of the backside layer represent a subset of a set of portions of the backside layer. Laser treatment may be performed with a continuous wave or pulsed laser. In some embodiments, the laser treatment physically and / or chemically modifies the exposed portions of the backside layer. After modifying the exposed portions of the backside layer, the exposed portions are etched using wet or dry development techniques (409c).

[0116] In some embodiments, after exposing and / or etching portions of the backside layer, distortion of the wafer is reduced. As noted above, wafer distortion may include out-of-plane distortion and / or in-plane distortion, measured as wafer bow and / or one or more IPD vectors, respectively. In some embodiments, operations 408c and 409 may be performed based on the distortion of the wafer. After performing operation 408c and 409, wafer distortion may be reduced, e.g., a lesser magnitude of wafer bow and / or IPD.

[0117] Optionally, in some embodiments additional backside layers are deposited (411c). In some embodiments, the additional backside layers may backfill etched portions of the backside layer. In some embodiments, the laser treated backside layer may equalize the x-bow and y-bow, however some bowing may still be present. In such embodiments, the wafer may have a bowl or umbrella shape. Thus, depositing a film having an isotropic internal stress may help further reduce the wafer bow. In some embodiments, an isotropic internal stress film is deposited, e.g., a tensile film or compressive film, to further mitigate wafer bow. The type of internal stress and the magnitude of the internal stress may be based upon the wafer bow. A positive wafer bow, or bowl shape, may be mitigated with a tensile film, while a negative wafer bow, or dome / umbrella shape, may be mitigated with a compressive film.Docket No. LAM1P088WO

[0118] Laser treatment operations described herein may be performed using a laser device that emits laser beams towards a substrate. Lasers may be operated in a continuous wave or pulsed mode, depending in part on the gain medium of the laser. In some embodiments, laser treatment may be performed on the entire wafer using a whole wafer exposure, i.e., a laser beam having a spot size of about 300 mm diameter. In other embodiments, a laser beam may have a smaller spot size that is scanned across the wafer surface. In some embodiments, a laser beam has a singular spot or multiple spots as discussed below in relation to Figures 11A-11B and 12. In some embodiments, a singular spot or grid of spots may be scanned across a wafer surface based on a pitch between spots. In some embodiments, the pitch may be smaller than the dot width, i.e., a continuous scan. In some embodiments, the pitch may be larger than the spot width, creating a grid pattern based on the spot width and pitch. In some embodiments, the spot size may vary between about 0.05pm to about 1000pm, and the pitch may vary between 0 and about 2 mm. In some embodiments, laser treatment may exposed portions of a layer, wherein the exposed portions represent a subset of a set of portions of the layer.

[0119] In some embodiments, flux and / or fluence of a laser treatment may be controlled during laser treatment operations described herein. Flux describes the time rate of flow of energy across a surface, while fluence describes the total energy absorbed per unit area. Generally, decreasing scan speed may increase fluence without affecting flux, while increasing laser power may increase flux and fluence. In some embodiments, the scan speed may be adjusted based on the desired modification of the exposed layer. A slower scan speed may increase fluence, increasing heating of the layer and / or ablating material.

[0120] In some embodiments, multiple passes may be performed for a laser treatment described herein. For example, a substrate may be exposed to a laser treatment in a first pass and then metrology may be performed. Based on the metrology, a second pass may be performed. In some embodiments, one or more process conditions may be changed in the second pass based on the obtained metrology. In some embodiments, in situ metrology may be used. In situ metrology may include metrology data produced by performing reflectometry, dome scatterometry, angle-resolved scatterometry, small-angle X-ray scatterometry, ellipsometry, interferometry, or any combinations thereof on a substrate.

[0121] The backside layers may be deposited using CVD, PECVD, ALD, epitaxy, PVD, or other deposition process. The backside layers may be deposited using a special purpose backside deposition apparatus. In some embodiments, the wafer switches chambers between operations 406, 408, 409, 410, or 411. The backside deposition apparatus may be a different deposition apparatus then the apparatus used to deposit the one or more frontside layers. TheDocket No. LAM1P088WObackside deposition apparatus may be a different apparatus than the apparatus used for laser treatment of backside layers.

[0122] The distortion induced by multiple backside layers may be the sum of the individual induced distortion. In some embodiments, the IPD of any combined backside layers may be about the same as the IPD of the one or more frontside layers. In some embodiments, backside layers may be used to reduce wafer bow. In some embodiments, bow magnitude of any combined backside layers may be about the same as the bow magnitude of the one or more frontside layers. In some embodiments, the x-bow and y-bow magnitude of the combined backside layers may be about the same as the x-bow and y-bow magnitude of the one or more frontside layers. In some embodiments, the bow contributions of all frontside and backside layers may combine so that the total bow of the wafer is minimal (i.e., less than about 100 pm). In some embodiments, after performing the method of Figures 4A-4C, the wafer may be substantially flat, e.g., the wafer has a bow of about 200 pm or less, about 150 pm or less, about 100 pm or less, about 50 pm or less, or about 30 pm or less. The degree of flatness may depend on the particular downstream operations to be performed. For example, deposition or etch operations may be within tolerance with a wafer bow of about 200 pm or less, about 150 pm or less, about 100 pm or less. Lithography operations, however, may have a stricter tolerance and substantially flat may be about 50 pm or less, or about 30 pm or less.

[0123] Note that references to bow values induced or caused by individual backside layers assume that the bow is uncompensated by other layers. For example, when referring to the magnitude of a bow caused by a first backside layer, we assume that is the bow that would be produced on the substrate if no other layers were present, e.g., no frontside layers. The magnitude of a bow induced by a layer depends on both the internal stress of the material in the layer and the thickness of the layer.

[0124] Compensation by backside layers refers to bow contributions of backside layers that may combine with bow contributions of frontside layers to reduce or equalize wafer bow, including x-bow and y-bow. As noted above, bow contributions of all frontside and backside layers may be combined. A positive bow cause by frontside layers, forming a bowl shape, may be reduced by a backside layer having a tensile internal stress that causes a negative bow. The negative bow caused by the backside layer compensates the positive bow caused by the frontside layers, resulting in a total bow of the wafer that is smaller and / or more uniform than without the backside layers. Laser treated films may compensate x-bow and / or y-bow. In some embodiments, compensation may include partially mitigating wafer bow. As noted above, a backside layer may partially compensate wafer bow, and an additional backside layer,Docket No. LAM1P088WOor any more numbers of layers, may be deposited to compensate any remaining wafer bow. In other embodiments, a laser treated backside layer may fully compensate wafer bow, e.g., reduce wafer bow to less than about 100 pm or less than about 30 pm.

[0125] In certain embodiments, backside layers disclosed herein comprise a material having an intrinsic internal stress, which has a magnitude of at least about 100 MPa or about 100 to about 2000 MPa. These values may be for tensile or compressive internal stress, as the case may be for the type and properties of backside material needed to counteract bow caused by the frontside layer(s). The above-recited internal stress values may apply to any one or more backside layers in a multilayer backside stack. Any two backside layers may have the same or different values of internal stress.

[0126] Example materials used to make backside layers having tensile internal stress include silicon nitrides (SiN), silicon oxynitrides, and polymer layers. As examples, tensile films can be deposited using CVD or PECVD techniques. To combat wafer bow caused by a frontside layer with a compressive internal force, a compressive film may be used for the bulk backside layers. Compressive films may be formed using specific materials and / or processing conditions. Example materials used to make compressive films include silicon oxides (SiOx), silicon nitrides, aluminum oxides, aluminum nitrides, and polysilicon. Compressive films can be deposited using CVD or PECVD techniques. The above-recited materials and deposition techniques may apply to any one or more backside layers in a multilayer backside stack. Any two backside layers may be formed by the same or different techniques.

[0127] Deposition by PECVD may proceed by flowing a reactant into a process chamber, and optionally with a co-reactant, while exposing the bowed semiconductor substrate to plasma. The plasma may drive a gas phase reaction that results in deposition of film. The PECVD reactions may generally involve delivering reactant(s) to the semiconductor substrate continuously while the semiconductor substrate is exposed to plasma. In some embodiments, depositing a nitride film on the backside of the substrate includes exposing the backside of the flat and / or bowed semiconductor substrate to a silicon-containing precursor and a nitrogencontaining reactant, and exposing the backside of the semiconductor substrate to plasma to drive a reaction between the silicon-containing precursor and the nitrogen-containing reactant to deposit the nitride film. To protect the frontside of the semiconductor substrate on which circuits, transistors, and other device components are patterned during the backside processes, the frontside is protected from being exposed to plasma and / or reactant or process gases, for example, by keeping the gap between the frontside of the semiconductor substrate and the showerhead to less than plasma sheath and / or by flowing inert gas(es) onto the frontside of theDocket No. LAM1P088WOsemiconductor substrate. By depositing on the backside of the semiconductor substrate, the nitride film avoids being deposited on circuits, transistors, and other device components on the frontside of the bowed semiconductor substrate.Anisotropic Stress Control

[0128] One aspect of the embodiments herein also related to managing saddle-shaped wafer bow, or anisotropic wafer distortion. As noted above, frontside layers may have features that vary in x and y dimensions, which cause frontside internal stresses that also vary in the x and y dimensions. This can lead to a wafer bow that is saddle shaped or half pipe shape, as shown in Figure 2 A. In some embodiments, techniques for mitigating saddle-shaped wafer bow may be performed using the processes described in Figures 4A-4C, modified as discussed below to mitigate anisotropic wafer bow.

[0129] Mitigating anisotropic wafer bow is difficult as backside films typically have an isotropic internal stress. For example, depositing a silicon nitride film having a tensile internal stress on a blank wafer would cause a bowl or dome shape, which may mitigate saddle shaped bowing in one dimension while increasing wafer bow in a different dimension. A stack of complementary profile films may mitigate saddle-shaped wafer bow better than an isotropic internal stress film. Complementary profile films include a combination of a curved bar profile and a curved channel profile film. These films may be deposited to individually have a non-uniform thickness profile that, when combined, the combination has a substantially uniform thickness. Complementary profile films may mitigate anisotropic wafer bow better than a single isotropic internal stress film, however the wafer bow and IPD profile of a stack of complementary profile films may be limited by the hardware configuration, limiting the mitigation enabled by such techniques.

[0130] Techniques for mitigating anisotropic wafer distortion may also be used to mitigate IPD. IPD may be difficult to mitigate for similar reasons as anisotropic wafer bow; backside films typically have an isotropic internal stress that does not address IPD. For example, returning to Figure 3C, a backside film having an isotropic internal stress may reduce IPD in one portion of a substrate surface but increase it in another portion.

[0131] Laser treatment, by contrast, may be used to modify and / or etch backside films to cause anisotropic internal stress. For example, a laser treatment may be used to cause a stress shift in one dimension for a backside film, causing anisotropic internal stress. Alternatively, a backside film may be etched to remove portions of a backside film that are parallel to, e.g., a y-dimension, mitigating internal stress in an orthogonal x-dimension. In some embodiments, laser treatment may expose one or more portions of a backside layer, wherein the exposedDocket No. LAM1P088WOportions of the backside layer represent a subset of a set of portions of the backside layer. In some embodiments, the exposed portions may correspond to an anisotropic stress or IPD of the wafer.

[0132] Figure 5 presents a film that has been laser treated to have anisotropic internal stress. A laser treated film is shown by film 502b, which has rectangular portions oriented with a long dimension in a y-dimension. After laser treatment, the laser treated film has a reduced internal stress in an x-dimension. View 504b shows an image of wafer bow for the laser treated film. View 506b shows an IPD map for a laser treated film. Views 504b and 506b correspond to the charts of wafer bow and linear IPD res, respectively.

[0133] One advantage of a laser treated film is that the wafer bow may be described by lower order polynomial functions. Looking at the charts of wafer bow, the laser treated film has a wafer bow that may be described by a 2ndorder polynomial, i.e. a parabola. A complementary profile films, by contrast, may have a wafer bow that is best fit by a 3rdor 4thorder polynomial. A laser treated film described herein may have a linear IPD residual of about 20 nm in the y dimension and about 6 nm in the x-dimension, a five-fold improvement over a complementary profile film. In some embodiments, laser treatments described herein may be used to reduce IPD by treating a backside layer according to a polynomial function corresponding to the IPD of the wafer.

[0134] Figure 6A and 6B show different views of a substrate 600 that has been etched to generate anisotropic internal stress. Figure 6A illustrates a top-down view of a substrate 600 and Figure 6B illustrates a perspective view. Substrate 600 may have an underlying layer 602 and laser etched features 604. The laser etched features have an individual width and a pitch between features. By etching features 604, the internal stress along the x-dimension is reduced more than the stress along the y-dimension, causing an anisotropic bow of substrate 600. In some embodiments, features 604 may have a width between about 1 pm and about 100 pm. In some embodiments, features 604 may have a pitch between about 1 pm and about 500 pm.

[0135] Figures 7A and 7B illustrate two methods for inducing stress in layers by laser treatment according to various embodiments herein. Figure 7A illustrates induced thermal stress in a silicon substrate 702a as well as a layer 704. In some embodiments, the modified region 706a includes both silicon substrate 702a and layer 704. It should be understood that modified regions 706a include material of both substrate 702a and layer 704a. Modified regions 706a refers to the region exposed to laser treatment, and does not imply a particular composition or a homogenous composition of modified regions 706a. Furthermore, while Figure 7A illustrates modified regions 706a and layers 704a and substrate 702a as having distinct boundaries, inDocket No. LAM1P088WOsome embodiments there is a temperature gradient between modified regions 706a and layer 704a and substrate 702a. In some embodiments, the boundary of modified regions 706a may be based on a boundary at which layer 704a and / or substrate 702a may melt, recrystallize, undergo a chemical reaction, etch, etc., that causes a significant change in the material.

[0136] In Figure 7A, modified regions 706a may have a depth of at least about 10 pm, or between about 5pm and about 15 pm. Modified regions 706a may have a width of about 50 pm, or between about 10 and about 100 pm. In some embodiments, modified regions 706a may have a pitch between about 10 pm and about 500 pm. In some embodiments, layer 704a has a thickness between about 0.01 pm to about 1 pm. In some embodiments, layer 704a may act as a thermal insulator to inhibit lateral heating in substrate 702a. In some embodiments, layer 704a does not contribute to wafer bow mitigation. In some embodiments, layer 704a may be a sacrificial layer that is removed after operations to induce stress in substrate 702a. In some embodiments, the non-uniform heating of substrate 702a and layer 704a may induce internal stress in the wafer, as the modified region 706a is annealed. In some embodiments, modified regions 706a may be generated by using a continuous wave laser to continuously heat layer 704a and substrate 702a.

[0137] Figure 7B illustrates induced thermal stress in a layer 704b deposited on a substrate 702b. In contrast to Figure 7A, in Figure 7B modified region 706b is only within layer 704b, and substrate 702b is unaffected. This may be advantageous to avoid modifying substrate 702b. In some embodiments, thermal stress in substrate 702a, such as shown in Figure 7A, may be reduced after a whole wafer annealing operation, as the entire substrate 702a may be heated and relax thermal stresses induced by operations described herein. This may be undesirable as the thermal stress in the substrate was partially compensating for wafer bow, and thus by relaxing such internal stress the wafer bow is less compensated, which is undesirable.

[0138] Thus, in some embodiments, only layer 704b is modified. In some embodiments, the width of modified regions 706b are about 5 pm, or between about 2 pm and about 8 pm. In some embodiments, the depth of modified regions 706b are about 1 pm, or about the depth of layer 704b. In some embodiments, layer 704b may be between about 0.1 pm and about 10 pm. In some embodiments, the pitch between modified regions 706b is between about 0.1 pm and about 10 pm. In some embodiments, modified regions 706b may be generated by a pulsed laser to inhibit heating of underlying layers.

[0139] In some embodiments, modified regions 706a of Figure 7A may be formed by a continuous wave type laser, while modified regions 706b of Figure 7B may be formed by a pulsed type laser. One advantage of a pulsed laser is that each pulse may have a higher fluxDocket No. LAM1P088WOthan a continuous wave laser, which may impart more thermal energy into a layer without heating of underlying or adjacent portions of a substrate. A continuous wave laser, by contrast, has a lower flux but continuous operation. Thus, while a continuous wave laser and a pulsed laser may have a similar average power, the continuous wave laser may cause more heating of adjacent portions through conduction.Bow Inducement

[0140] In another aspect of the embodiments herein, methods and apparatuses are disclosed for forming high tensile stress wafer bow. In some embodiments, frontside films may cause a wafer bow of up to about 1 mm, which may be correlated with tensile internal stress of frontside films. Thus, to compensate for this stress, a similar high tensile internal stress may be induced on the backside of the wafer. However, it is difficult to induce large amounts of wafer bow. Wafer bow may result from the combination of internal stress and thickness of a film. Thus, a thick film having a large tensile internal stress may be necessary to mitigate 1 mm of bow. However, such films are prone to cracking as the thickness is increased. In some embodiments, a high tensile bow is a bow of at least about 600 pm, at least about 700 pm, or at least about 800pm having a tensile internal stress. One or more layers may contribute to compensate for a high tensile bow.

[0141] Disclosed herein are methods of imparting a high tensile wafer bow on the backside of a substrate. Figure 8A-8C illustrate three different techniques. In Figure 8A, a thermal stress in the silicon substrate may be induced. Similar to Figure 7A, a substrate 802a may be modified by laser exposure to generate modified regions 806a, which have a larger tensile stress. In some embodiments, modified regions 806a may have widths and pitch similar to Figure 7A. In other embodiments, modified regions 806a may be a singular region. In some embodiments, laser treatment of substrate 802a may induce a wafer bow in the substrate of at least about 300 pm, at least about 350 pm, at least about 400 pm, or between about 300 and about 450 pm. A layer 804a may then be deposited on the backside of the substrate having a tensile internal stress. Layer 804a may induce a wafer bow of at least about 500 pm, at least about 600 pm, or between about 500 and about 800 pm. Thus, combining the wafer bow of the substrate 802a and layer 804a may cause a total wafer bow of at least about 800 pm, or between about 800pm and about 1200 pm. This is greater than the total wafer bow possible with layer 804a alone, which in some embodiments may crack when inducing a wafer bow greater than about 800 pm.

[0142] Figure 8B illustrates another technique to induce a high tensile bow using multiple layers. A layer 804b- 1 is deposited on a substrate 802b. Layer 804b- 1 may be exposed to laser treatment to generate modified layer 806b- 1. A second layer 804b-2 may then be deposited onDocket No. LAM1P088WOtop of layer 806b- 1. Layer 804b-2 may then be exposed to laser treatment to generate layer 806b-2. Each layer may be deposited and exposed to laser treatment to modify properties of the layer, e.g., internal stress of the layer to become more tensile. By depositing multiple layers, each layer has an individually lower chance of cracking than a single, thicker layer. In some embodiments, this may result from laser treatment not modifying the entire layer, such that a boundary layer at the bottom of each layer is less modified or unmodified. The boundary layer may help inhibit cracking between and / or within a layer, allowing for a cumulatively thicker layer without cracking than a singular layer.

[0143] Figure 8C illustrates another technique to induce a high tensile bow using multiple layers. In Figure 8C, a substrate 802c has been etched to have features 803c, which are then backfilled with a layer 804c. Eayer 804c may have a tensile internal stress, while substrate 802c has minimal internal stress. In some embodiments, the features 803c may be etched to increase the surface area between substrate 802c and layer 804c. By increasing the surface area, layer 804c can impart additional strain on substrate 802c, increasing wafer bow.Frontside Layer Modification

[0144] In some embodiments, laser treatments disclosed herein may be used to modify one or more frontside layers. Frontside layers may include various layers, including layers that are integrated into semiconductor devices, such as ONON stacks in 3D NAND memory, sacrificial mask layers such as carbon hardmasks that are used for etching ONON stacks, and photoresist layers that are used to pattern carbon hardmasks prior to etching ONON stacks. In some embodiments, methods disclosed herein for modifying, etching, or annealing backside films may be applied to frontside films.

[0145] Easer treatments disclosed herein may be used for modification of one or more properties of one or more frontside layers. In some embodiments, laser treatment may be used to etch features in an ONON stack by ablating materials. In some embodiments, laser etching may be used with oxide metal oxide metal stacks (OMOM), which may comprise alternating layers of oxide material and metal material. In some embodiments, laser etching may be used to etch features having an aspect ratio between about 3:1 and about 50:1 and a critical dimension of about 1 pm.

[0146] In some embodiments, laser treatments disclosed herein may be used for micromachining lattice or network structures into films. Micromachine features may have a critical dimension of about 1pm or at least 1pm. In some embodiments, micromachining may be used to modify the mechanical properties of a film, including toughness, modulus, or stress. In some embodiments, the mechanical properties may be anisotropically altered, i.e., having aDocket No. LAM1P088WOhigher modulus in an x-dimension than a y-dimension. This may be particularly advantageous for, e.g., semiconductor device layouts that cause greater stress in one dimension than a perpendicular dimension. In some embodiments, micromachining does not alter the electrical properties of films or create discrete semiconductor devices but only alters the mechanical properties of films. In some embodiments, micromachining may be used to create structures including voids, lattices, or meshes.

[0147] In some embodiments, backside processes discussed herein for annealing backside films may be used with frontside films. In some embodiments, laser treatment may be used to anneal carbon hardmask films to reduce internal stress of such films. In some embodiments, laser treatment may be used to reduce the hydrogen content of carbon-containing or silicon-containing films, including silicon oxide and silicon nitride films. In some embodiments, laser treatment may be used to crystalize amorphous silicon films into polycrystalline silicon films. In some embodiments, laser treatment may be used to crystalize films to modify the thermal conductivity or other properties of such films. In some embodiments, laser treatment may have an annealing effect by heating portions of a film. In other embodiments, laser treatments may facilitate a photochemical reaction, such as breaking Si-H bonds.

[0148] In some embodiments, laser treatments disclosed herein may be used with frontside films having compositions including silicon-containing films, carbon-containing films, boronnitride films, metal-containing films, or any combinations thereof. Laser treatments disclosed herein may be used to expose regions of frontside layers. In some embodiments, regions have a width of at least about 1pm. In some embodiments, regions may have a rectangular or elliptical shape, wherein a shortest dimension of the shape is at least about 1 pm, and a longest dimension of the shape may be up to about the width of the wafer, e.g., 300 mm.

[0149] One advantage of laser treatments for frontside films is limiting heating to an exposed layer or underlying layer without heating an entire substrate. For example, as discussed above regarding backside films, laser treatment may be used to heat a frontside film without heating an underlying layer. This may be advantageous to inhibit any undesirable effects from heating an underlying layer, such as diffusion of dopants or materials. Thus, in some embodiments, laser treatment methods disclosed herein may be used to heat an exposed frontside film or immediately underlying film.Deposition and Etching with Laser Treatment

[0150] In another aspect of the embodiments herein, laser treatment may be used during processes for deposition or etch of frontside or backside layers. In some embodiments, laser treatment as described herein may be performed while exposing a substrate to a process gasDocket No. LAM1P088WOhaving reactive species that may deposit or etch material on the substrate. In some embodiments for deposition processes, a material deposits on portions exposed to laser beams and material does not deposit on portions not exposed to laser beams. In some embodiments for etch processes, the substrate is etched at the portions exposed to laser beams and is not etched at portions not exposed to laser beams. Reactive species may include any species that react with material on the surface of a substrate, including species used during deposition and etch processes.

[0151] ALD or CVD are processes for frontside or backside layer deposition. In some embodiments, laser treatments disclosed herein are applied to frontside layers or the frontside of a substrate. Semiconductor fabrication processes often include dielectric gap fill using chemical CVD or ALD methods to fill features. Described herein are methods of depositing material, including filling features with dielectric material including but not limited to silicon-containing films such as silicon oxide or silicon nitride, and related systems and apparatuses. The methods described herein can be used to deposit material to form or fill features in a substrate. In some embodiments, ALD process described herein may be “thermal ALD” processes or “non-plasma ALD” processes, which refer to ALD processes that are performed at elevated temperatures without striking a plasma. While a non-plasma ALD process is described herein, in some embodiments ALD processes described herein may be combined with plasma ALD processes where a plasma is ignited for one or more steps of an ALD process. In some embodiments, laser treatments disclosed herein may be combined with CVD or ALD methods to fill features of at least 1 pm in size.

[0152] In some embodiments, laser treatments may be used during deposition or etch operations. In some embodiments, laser treatment may be used for thermal control, e.g., heating the surface of a wafer. In some embodiments, laser treatment may be used for spatial control by exposing one or more portions of a wafer. In some embodiments, a laser may be used for temporal control by, e.g., activating the laser based on a duty cycle. In some embodiments, a laser may be used for selective deposition or etching by thermal or photochemical processes. In some embodiments, a laser may be used to heat only the surface of a wafer. This may be particularly helpful to avoid heating other layers that would undesirably anneal or diffuse at elevated temperatures, e.g., temperatures greater than about 600°C. In some embodiments, laser treatment may also reduce the time for heating and cooling a substrate. Heating and cooling a substrate using a pedestal heater may require minutes to hours as the wafer moves from ambient temperature to operating temperature. A laser treatment, by contrast, may heat a wafer surface to an operation temperature in seconds or less than a second. Furthermore, theDocket No. LAM1P088WOwafer may cool to ambient temperature in less than a minute or less than 10 seconds. This may increase throughput by decreasing the time required for heating or cooling.

[0153] Techniques described herein may involve thermal atomic layer deposition (ALD). That is, in various embodiments, the reaction between a precursor and a reactant is performed without igniting a plasma. In some embodiments, a silane, including an aminosilane or halosilane, and a nitrogen-containing reactant to form silicon nitride is performed without igniting a plasma. ALD is a technique that deposits thin layers of material using sequential self-limiting reactions. Typically, an ALD cycle includes operations to deliver and adsorb at least one reactant to the substrate surface, and then react the adsorbed reactant with one or more reactants to form the partial layer of film. As another example, a silicon nitride deposition cycle may include the following operations: (i) delivery / adsorption of a silicon-containing precursor, (ii) purging of the silicon-containing precursor from the chamber, (iii) delivery of a nitrogen-containing gas, and (iv) purging of the nitrogen-containing gas and other byproducts from the chamber.

[0154] Unlike a chemical vapor deposition (CVD) technique, ALD processes use surface mediated deposition reactions to deposit films on a layer-by-layer basis. In one example of an ALD process, a substrate surface that includes a population of surface active sites is exposed to a gas phase distribution of a first precursor, such as a silicon-containing precursor, in a dose provided to a chamber housing a substrate. Molecules of this first precursor are adsorbed onto the substrate surface, including chemisorbed species and / or physiosorbed molecules of the first precursor. It should be understood that when the compound is adsorbed onto the substrate surface as described herein, the adsorbed layer may include the compound as well as derivatives of the compound. For example, an adsorbed layer of a silicon-containing precursor may include the silicon-containing precursor as well as derivatives of the silicon-containing precursor. After a first precursor dose, the chamber is then evacuated to remove most or all of the silicon-containing precursor remaining in gas phase so that mostly or only the adsorbed species remain. In some implementations, the chamber may not be fully evacuated. For example, the chamber may be evacuated such that the partial pressure of the first precursor in gas phase is sufficiently low to mitigate a reaction. A second reactant, such as a nitrogencontaining reactant, is introduced to the chamber so that some of these molecules react with the silicon-containing precursor adsorbed on the surface. In some processes, the second reactant reacts immediately with the adsorbed silicon-containing precursor. The chamber may then be evacuated again to remove unbound nitrogen-containing reactant molecules. As described above, in some embodiments the chamber may not be completely evacuated.Docket No. LAM1P088WOAdditional ALD cycles may be used to build film thickness.

[0155] In certain embodiments, an ALD first precursor dose partially saturates the substrate surface. In some embodiments, the dose phase of an ALD cycle concludes before the precursor contacts the substrate to evenly saturate the surface. Typically, the precursor flow is turned off or diverted at this point, and only purge gas flows. By operating in this sub saturation regime, the ALD process reduces the cycle time and increases throughput. However, because precursor adsorption is not saturation limited, the adsorbed precursor concentration may vary slightly across the substrate surface. Examples of ALD processes operating in the sub-saturation regime are provided in U.S. Patent Application No. 14 / 061,587 (now U.S. Patent No.9,355,839), filed October 23, 2013, titled “SUB -SATURATED ATOMIC LAYER DEPOSITION AND CONFORMAL FILM DEPOSITION,” which is incorporated herein by reference in its entirety.

[0156] In some embodiments, deposition may depend on the temperature of the precursor species, reactants, wafer surface, or any combination thereof. For example, silicon nitride precursors and reactants may be highly temperature sensitive in regard to deposition, such that deposition may not occur at temperatures below about 150°C or below about 200°C. In some embodiments, the temperature of a substrate during deposition of silicon nitride may be at least about 400°C, at least about 500°C, or at least about 600°C.

[0157] In some embodiments, the feature(s) may have an aspect ratio of at least about 1:1, at least about 2:1, at least about 4:1, at least about 6:1, at least about 10:1, or at least about 20:1, or at least about 50:1, or at least about 100:1, or at least about 150:1, or at least about 200:1, or higher. The feature(s) may also have a dimension near the opening, e.g., an opening diameter or line width of between about 1 pm to about 100 pm, for example between about 1 pm and about 10 pm. Disclosed methods may be performed on substrates with feature(s) having an opening grater than about 1 pm. A via, trench or other recessed feature may be referred to as an unfilled feature or a feature. According to various embodiments, the feature profile may widen gradually at the feature opening.

[0158] In some embodiments, the substrate may be partially fabricated for forming a memory device. In some embodiments, exposed regions of the substrate include silicon-containing surfaces, including but not limited to low-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbide. In some embodiments, exposed regions of the substrate include silicon oxynitride.

[0159] In some embodiments, laser treatment may be combined with deposition processes described herein to heat the surface of a substrate and / or gaseous species above the substrate.Docket No. LAM1P088WOFor example, in some embodiments, laser treatment may be performed during a silicon nitride deposition to heat one or more portions of the wafer to at least about 400°C to enable deposition of silicon nitride. In some embodiments, a whole-wafer laser treatment may be performed to uniformly heat the wafer of the surface and deposit a continuous layer of silicon nitride or other layers as described herein.

[0160] In some embodiments, a laser treatment disclosed herein may be combined with a CVD or ALD process to selectively deposit material. In some embodiments, a laser may be used to expose one or more portions of the substrate surface, heating such portions and enabling deposition of material on the heated portions. In such embodiments, material may not deposit on the unexposed portions as the surface and / or species do not have sufficient thermal energy to deposit. In some embodiments, deposition may still occur on unexposed portions but to a lesser extent than exposed portions. In such embodiments, an etch operation may be used to etch back material deposited on unexposed portions of the substrate.

[0161] Figure 9A presents a flowchart of depositing material using an ALD or CVD process in combination with a laser treatment. A wafer is received into a process chamber (902). Material is then deposited onto the wafer using an ALD or CVD process in combination with a laser treatment as described herein (904). In some embodiments, a laser treatment is performed during deposition, such as a CVD deposition. In some embodiments, a laser treatment may be performed continuously during a deposition process. In some embodiments, laser treatment may be performed with a pulsed or continuous wave laser. In some embodiments, a pulsed laser may be preferred to facilitate higher surface temperatures without heating underlying layers. In some embodiments, laser treatment may be performed for one or more steps of an ALD cycle. As noted above, an ALD cycle may include (1) exposing a substrate to a precursor species, (2) purging the precursor species, (3) exposing the substrate to a reactant, and (4) purging the reactant. In some embodiments, laser treatment may be performed during steps (1), (2), (3), (4), or any combinations thereof. In some embodiments, laser treatment may be performed during steps (1) and / or (3) to facilitate conversion of adsorbed precursor species into a growing film.

[0162] In some embodiments, deposition with laser treatment may be thermal, photochemical, or both. In a thermal deposition process, a laser may be used to heat the wafer surface, gaseous species, or both, to facilitate deposition at elevated temperatures. In a photochemical deposition process, a laser may be used for dissociation of species by electronic excitation, which may then react or deposit on a wafer surface. Thermal deposition may be used with any laser that can heat the wafer surface, including in combination with an underlying absorption layer.Docket No. LAM1P088WOPhotochemical deposition may be performed with lasers having wavelengths selected for a specific species. In some embodiments, photochemical or thermal deposition with laser treatment may be used with silicon-containing or metal-containing precursors. In some embodiments, laser treatment combined with CVD and / or ALD deposition processes may be used with silicon-containing precursors, carbon-containing precursors, halogen-containing precursors, and / or metal-containing precursors, such as WFe.

[0163] In some embodiments, laser treatment may be used to etch material. Etching may be distinguished from ablation. Ablation refers to vaporization of material, which may be performed using a laser according to various embodiments herein. Etching, by contrast, may include a chemical species that may react with material on a wafer to form a gaseous species that may be evacuated from a process chamber. In some embodiments, etching with laser treatment may be thermal, photochemical, or both. In a thermal etch process, a laser may be used to heat the wafer surface, gaseous species, or both, to facilitate etching at elevated temperatures. In a photochemical etching process, a laser may be used for dissociation of bonds of a material on a wafer surface or a gaseous species, which may then react to form vapor phase products that may be evacuated. Thermal etching may be used with any laser that can heat the wafer surface, including in combination with an underlying absorption layer. Photochemical etching may be performed with lasers having wavelengths selected for a specific species. In some embodiments, photochemical etching may be performed in multiple steps, such as steps shown in Figure 4C. During a first step, a substrate may be exposed to laser treatment to alter one or more portions of the wafer surface. In a second step, a chemical species may react with the exposed or unexposed portions of the wafer surface to etch material.

[0164] Figure 9B presents a flow chart for etching a material on a substrate using chemical species combined with a laser treatment. A wafer is received into a process chamber (912). Then, material is etched using a chemical process in combination with laser treatment (914). In some embodiments, laser treatment may be performed prior to the chemical process. In some embodiments, the chemical process may be a wet or dry development process. In some embodiments, the laser treatment may be used concurrently with exposure of the wafer to a dry development chemistry.Film Stack

[0165] Figures 10A-10F illustrate various film stacks that may be used in various embodiments herein. A film stack for laser treatment may include a laser absorption layer 1002, an annealed layer 1004, a laser reflection layer 1006, a thermal insulation layer 1007, other layers 1008, and a wafer 1000 (e.g., a crystalline silicon layer). Figure 10A illustrates a wafer 1000 havingDocket No. LAM1P088WOan annealed layer 1004 deposited thereon. Figure 10B illustrates a wafer 1000 having an annealed layer 1004 deposited thereon and a laser absorption layer 1002 on top of annealed layer 1004. Figure 10C illustrates a wafer 1000, annealed layer 1004, and laser absorption layer 1002, where annealed layer 1004 is on top of laser absorption layer 1002, rather than underneath it. Figure 10D illustrates a wafer 1000 having a thermal insulation layer 1007 and an annealed layer 1004 on top of the thermal insulation layer. Figure 10E illustrates a wafer 1000 having deposited thereon a thermal insulation layer 1007, an annealed layer 1004, and a laser absorption layer 1002 on top. Figure 10F illustrates a wafer 1000 having other layers 1008, a thermal insulation layer 1007, a laser reflection layer 1006, an annealed layer 1004, and a laser absorption layer 1002. While Figures 9A-9F present six different combinations of layers, it should be understood that other combinations may be used. A film stack may include an annealed layer and a thermal insulation layer 1007, a laser reflection layer 1006, a laser absorption layer 1002, other layers 1008, or any combinations thereof. In some embodiments, a substrate may have a backside layer that is an annealed layer 1004 and one or more additional backside layers selected from the layers disclosed herein, including a laser absorption layer, a thermal insulation layer, a laser reflection layer, and any combinations thereof.

[0166] In various embodiments herein, one or more layers may be deposited on a substrate. Generally, for any two layers, a first layer may be underlying a second layer. The first layer may be referred to as an underlying layer or an “inner” layer. The second layer, deposited on the first layer, may be referred to as an overlying or “outer” layer. Thus, regardless of the orientation of a substrate, an “underlying” layer may refer to a layer that is closer to the substrate than another layer in the film stack.

[0167] Annealed layer 1004 may be a layer that is to be modified by a laser treatment as described herein. In some embodiments, annealed layer 1004 is a layer to be annealed, i.e., heated to a set temperature for a set duration. In other embodiments, annealed layer 1004 may be a layer to be ablated, i.e., heated until vaporization occurs for, e.g., etching operations. In some embodiments, annealed layer 1004 is a backside layer. In some embodiments, annealed layer 1004 is a frontside layer. In some embodiments, annealed layer 1004 undergoes a stress shift under annealing conditions. In some embodiments, annealed layer 1004 has an internal stress that may be compressive or tensile. In some embodiments, annealed layer 1004 may be between about 0.1 and about 1pm thick.

[0168] Annealed layer 1004 may be any film that modifies its material properties on annealing. For example, a-Si, SiN, and a-C may have a significant internal stress shift on annealing. In some embodiments, the film to be annealed may be used to control wafer bow by counteractingDocket No. LAM1P088WOinternal stress of one or more frontside films. Thus, it may be desirable to modify the internal stress of annealed layer 1004 after one or more frontside semiconductor processing operations to counteract any stress changes caused by the frontside semiconductor processing operations.

[0169] Laser absorption layer 1002 may be a layer having a high absorption coefficient for a particular laser. In some embodiments, laser absorption layer 1002 may absorb photons and then heat an adjacent layer, such as annealed layer 1004. This may be advantageous when annealed layer 1004 has a low absorption coefficient, as laser absorption layer 1002 may absorb photons and convert them into heat, which may then heat nearby portions of annealed layer 1004. This may heat annealed layer 1004 more than directly exposing annealed layer 1004 to laser beams. In some embodiments, laser absorption layer 1002 may be between about 0.1 and about 0.5pm thick.

[0170] In some embodiments, laser absorption layer 1002 may include amorphous silicon, silicon nitride, metal oxides, silicon oxide, carbon, metal, aluminum oxide, aluminum nitride, aluminum oxynitride, boron nitride, tungsten nitride, tungsten carbide, tungsten carbidenitride, titanium nitride, or any combinations thereof. In some embodiments, laser absorption layer 1002 may include one or more dopants, including N-type dopants and / or P-type dopants. In some embodiments, laser absorption layer 1002 may include dopants of Boron (B), Arsenic (As), Phosphorus (P), Antimony (Sb), Indium (In), Aluminum (Al), Gallium (Ga), antimony (Sb), or any combinations thereof.

[0171] In some embodiments, laser absorption layer 1002 may be a sacrificial layer. Absorption layer 1002 may deform or be partially ablated by laser treatment processes described herein. Thus, in some embodiments, laser absorption layer 1002 may be removed following laser treatment operations described herein. In some embodiments, laser absorption layer 1002 may be a carbon-containing layer that can be removed by an ashing operation.

[0172] Thermal insulation layer 1007 may be any layer having a low thermal conductivity. In some embodiments, this layer may include silicon oxide, silicon nitride, or low-k dielectrics. A thermal insulation layer 1007 may be used to inhibit heating of other layers, including thermal insulation layer 1007. In some embodiments, it is undesirable to heat adjacent layers, as this may undesirably modify internal stress or other properties. Alternatively, it may be desirable to limit cooling of annealed layer 1004 by conduction of thermal energy to adjacent layers. A thermal insulation layer 1007 may thus be used to limit diffusion of heat from an annealed layer or a laser absorption layer. In some embodiments, thermal insulation layer 1007 may be between about 0.1 and about 3pm thick. In some embodiments, the temperature of annealed layer 1004 may be controlled based on the thickness and / or thermal conductivity ofDocket No. LAM1P088WOthermal insulation layer 1007, e.g., a thinner layer and / or higher thermal conductivity may dissipate more heat from an annealed layer or a laser absorption layer, reducing the temperature of such layers.

[0173] Laser reflection layer 1006 may be used to reflect photons that are not absorbed by other layers, e.g., a laser absorption layer or an annealed layer. In some embodiments, a laser reflection layer may reflect photons and / or absorb photons. In some embodiments, a laser reflection layer inhibits the transmission of photons to underlying layers, such as other layers 1008, where photons may be absorbed and undesirably heat such underlying layers. In some embodiments, a laser reflection layer may include tungsten, titanium nitride, or both. In some embodiments, laser reflection layer 1006 may be between about 0.1 and about 1pm thick.

[0174] In some embodiments, the choice of materials for each layer may depend on the absorption bands for the material to be annealed and / or ablated. For example, silicon nitride absorbs between blue light between about 400 nm and about 500 nm, which may be adjusted by changing the ratio of silicon to nitrogen in the film, where a higher ratio increases absorption. Thus, in some embodiments, annealing a silicon nitride film with a blue laser may not require a laser absorption layer.

[0175] Figures 11 A and 1 IB are charts of temperature as a function of film thickness. In Figure 11 A, maximum surface temperature is plotted as a function of film thickness for a silicon oxide film, with three different scanning speeds of a laser. In Figure 11B, temperature is plotted as a function of film depth, with 0 indicating the surface and a silicon oxide layer 3pm thick. Figure 11 A demonstrates that, for a fixed scan speed, as thickness increases the maximum temperature also increases. This may result from the low thermal conductivity of silicon oxide. For lower thickness films, heat may diffuse into the silicon substrate, which may act as a heat sink that does not substantially change temperature. As the thickness of the silicon oxide layer increases, heat transfer into the substrate decreases, remaining in the silicon oxide layer and causing a higher maximum temperature. This concept is similarly demonstrated in Figure 1 IB, where the wafer is substantially at room temperature while the substrate reaches a maximum temperature of about 2100K. As the thickness of the silicon oxide film increases, the maximum possible temperature also increases due to the low thermal conductivity of silicon oxide. Thus, in some embodiments, silicon oxide may be used as a thermal insulation layer to inhibit heating of a substrate. By controlling the thickness of a silicon oxide film the substrate temperature may remain relatively constant despite heating of the silicon oxide layer or another layer on top of the silicon oxide layer. Thus, in some embodiments, the thickness of a silicon oxide film, or other thermal insulation layers, may be used to control heating of the substrate or other layers.Docket No. LAM1P088WOApparatus

[0176] Figure 12 depicts a sample laser 1200 that may be used in various embodiments herein. Laser 1200 may include a laser medium 1202, a beam splitter 1204, a focusing lens 1206, and a spot distribution 1208 having spots with a width and pitch. Laser medium 1202 may be one of various laser technologies, including gas lasers, excimer lasers, or solid state laser. Beam splitter 1204 may modify a laser beam into one of various patterns, and focusing lens 1206 that changes the path of the laser beams, converging or diverging as designed. A square dot grid distribution 1208 is shown in Figure 12 and other arrangements may be used. Figure 13A shows a hexagonal dot grid. Figure 13B illustrates parallel rectangular spots. In some embodiments, a laser beam may have a spot pattern that includes multiple spots or a single spot. In some embodiments, a spot / laser beam may have various shapes, including elliptical or rectangular shapes, including circular or square shapes.

[0177] In addition to the spot shape and distribution, the energy distribution within a spot may vary. Figure 13C illustrates a gaussian distribution, where energy intensity is highest in the center and tapers to towards the edges. Figure 13D illustrates a “top-hat” distribution, where energy intensity has a square flat-top profile. A top-hat distribution may be desirable to control the fluence on the surface of a layer exposed to a laser beam. With a gaussian distribution, fluence would also be highest in the center, which could cause undesirable over-heating or ablation. A top-hat distribution, by contrast, may have a constant fluence, leading to uniform heating of a layer.

[0178] Figure 14A is a block diagram that illustrates a substrate processing system 1432 used to perform processing on a wafer 1402, according to some embodiments. As shown, the substrate processing system may include a processing chamber (or a chamber) 1434. A laser 1400 may be configured to direct laser beams at the wafer 1402 according to various embodiments disclosed herein. A showerhead 1436 may be disposed over the wafer 1402. In some embodiments, system 1432 may be used for backside or frontside fabrication operations, including laser treatments disclosed herein.

[0179] In some embodiments, the laser 1406 may be electrically coupled to laser power supply 1439. The laser power supply 1439 may be controlled by a controller module 1442, e.g., a controller. In some embodiments, power may be provided to the laser 1406 instead of the showerhead 1436, or power may be provided to both the laser 1406 and the showerhead 1436. The controller module 1442 may be configured to operate the substrate processing system 1432 by executing process input and control for specific process recipes. The controller module 1442 may set various operational inputs for a process recipe, such as power levels, timingDocket No. LAM1P088WOparameters, process gasses, mechanical movement of a wafer 1402, and / or the height of the wafer 1402 relative to the laser 1406 (and the distance between the wafer 1402 and the showerhead 1436).

[0180] In some embodiments, the substrate processing system 1432 may further include a first gas manifold 1446 that is connected to first gas sources 1448, e.g., gas chemistry supplies from a facility and / or inert gases. Depending on the purposes and processing being performed over a top surface of the wafer 1402, the controller module 1442 may controls the delivery of first gas sources 1448 via the first gas manifold 1446. The chosen gases may then be flown into the showerhead 1436 and distributed in a space volume defined between a face of the showerhead 1436 that faces that wafer 1402. In some embodiments, inert gases may be flowed during laser treatment operations described herein to inhibit interaction of any particles from the backside layers with frontside layers.

[0181] In some embodiments, a carrier ring 1454 may encircle an outer region. The top surface of the carrier ring 1454 is generally coplanar with the top surface of the wafer 1402. The carrier ring 1454 may include an outer edge side of its disk structure, e.g., outer radius, and a wafer edge side of its disk structure, e.g., inner radius, that is closest to where the wafer 1402 sits. The carrier ring 1454 may be associated with an inner diameter (ID). The inner diameter may extend to an inner perimeter of the carrier ring and generally surround a substrate (e.g., wafer 1402) in a processing chamber. The wafer edge side of the carrier ring 1454 may also include a plurality of contact support structures or “tabs” which may be configured to lift the wafer 1402 when the carrier ring 1454 is held by spacers. The carrier ring 1454 may include a plurality of tabs with a quantity selected from a range to support the wafer 1402 during processing. In some embodiments, a wafer may be placed directly upon, or supported directly by, spacers or other similar substrate support features without a carrier ring.

[0182] In some embodiments, spider forks 1456 may be used to lift and maintain the carrier ring 1454 in its process height, e.g., to allow laser treatment of the backside of the wafer 1402. The carrier ring 1454 may therefore be lifted along with the wafer 1402. In some implementations, the carrier ring 1454 may be rotated to another station, e.g., in a multi-station system. In some embodiments, a spider forks or any other transfer mechanism may be used to lift or move the wafer directly without a carrier ring. While a spider fork is shown in Figure 14A, in some embodiments a different lift mechanism may be used, including, e.g., lift pins.

[0183] Broadly speaking, the embodiments disclosed herein are for a system to laser treat films on the selective side of the wafer (front and / or back) with dynamic control. In some embodiments, the system may have a wafer lift mechanism that tightly controls parallelism ofDocket No. LAM1P088WOthe substrates against the laser, such as spider forks 1456. In one example, this may be achieved by setting up the lift mechanism perpendicular to the laser and controlling manufacturing tolerances, e.g., spindle or lift pins mechanisms. In another example, the lift may be achieved by raising the wafer lift parts. This option may not allow dynamic control of the side that gets laser treated.

[0184] In some configurations, the lift mechanism may allow dynamically controlling the substrate position during processing to control the side of the laser treatment, profile of the laser treatment, and laser treated film properties. In another embodiment, dynamic gap control using wafer lift mechanism enables: (a) control of the distance from the laser; and (b) the lift mechanism to control the distance dynamically during the process.

[0185] In some embodiments, the wafer, spider forks 1456 may move within x, y, and z dimensions to move the wafer with a 3-dimensional space. In some embodiments, the wafer may be moved within the x and y dimensions to change where the laser beams meet the surface of the wafer. In some embodiments, the wafer may be moved within the z dimension to change the focal distance between the laser and the surface of the wafer. In some embodiments, laser 1406 and / or wafer 1402 may be moved with respect to each other to perform various laser treatment processes described herein.

[0186] While Figure 14A illustrates a laser 1406 underneath a wafer 1402, in some embodiments the laser may be oriented above the wafer or the wafer and laser may be rotated 90 degrees from the orientation shown in Figure 14A. In such embodiments, showerhead 1436 may be oriented to flow purge gas over the frontside of the wafer to inhibit any ablated particles from depositing on the frontside of the wafer.

[0187] While one laser 1406 is shown in Figure 14A, in some embodiments multiple lasers may be used. In some embodiments, multiple lasers may be used to have different gain mediums / wavelengths. In some embodiments, multiple lasers may be used having different power for different operations or to increase a cumulative power by combining the output of multiple lasers. In some embodiments, multiple lasers having different beam shapes may be used. In some embodiments, a laser may be integrated with a showerhead disclosed herein. In other embodiments, a laser may be oriented to the side of a showerhead (not shown). In such embodiments, mirrors and lenses may be used to shape the laser beam to focus on various portions of a wafer during processing operations described herein.

[0188] Variations of Figure 14A may be used to facilitate laser treatment operations disclosed herein. Figure 14B presents a block diagram that illustrates another version of substrate processing system 1432 used to perform processing on a wafer 1402 according to variousDocket No. LAM1P088WOembodiments herein. A center column may be configured to support a pedestal for when a top surface (or a frontside) of the wafer 1402 is being processed, e.g., a film is being formed on the top surface of the wafer 1402, or on the backside of the wafer 1402. The pedestal, in accordance with some embodiments disclosed herein, may be referred to as a showerhead pedestal (“ShoPed”) 1437. A showerhead 1436 may be disposed over the ShoPed 1437.

[0189] In some embodiments, a laser 1406 may be integrated with shoped 1437 or may be separate from shoped 1437, showerhead 1436, or both. In some embodiments, a laser may be used to heat wafer 1402 and / or induce photochemical reactions in a gaseous phase or on the surface of the wafer 1402. In some embodiments, a laser may be configured to expose the entire wafer surface to laser beams or only portions of the surface. Various beam shapes and spot sizes may be used as disclosed herein.

[0190] In some embodiments, the showerhead 1436 may be electrically coupled to power supply 1438 via a match network 1440. The power supply 1438 may be controlled by a controller module 1442, e.g., a controller. In some embodiments, power may be provided to the ShoPed 1437instead of the showerhead 1436, or power may be provided to both the ShoPed 1437and the showerhead 1436. The controller module 1442 may be configured to operate the substrate processing system 1432 by executing process input and control for specific process recipes. Depending on whether the top surface of the wafer 1402 is receiving a deposited layer or layer stack or the bottom surface of the wafer 1402 is receiving a deposited layer or layer stack, the controller module 1442 may set various operational inputs for a process recipe, such as power levels, timing parameters, process gasses, mechanical movement of a wafer 1402, and / or the height of the wafer 1402 relative to the ShoPed 1437 (and the distance between the wafer 1402 and the showerhead 1436).

[0191] In some embodiments, the substrate processing system 1432 may further include a second gas manifold 1450 that is connected to second gas sources 1452, e.g., gas chemistry supplies from a facility and / or inert gases. Depending on the processing being performed over a bottom surface of the wafer 1402, the controller module 1442 may control the delivery of second gas sources 1452 via the second gas manifold 1450. The chosen gases may then be flown into the showerhead 1436 and distributed in a space volume defined between a face of the ShoPed 1437that faces an under surface or under side (e.g., backside) of the wafer 1402 when the wafer is resting over the ShoPed 1437and / or spacers 1444. The spacers 1444 may provide for a separation that optimizes deposition to the under surface of the wafer 1402, while reducing deposition over the top surface of the wafer 1402. In some embodiments, while deposition is targeted for the under surface of the wafer 1402, an inert gas may be flown overDocket No. LAM1P088WOthe top surface of the wafer 1402 via the showerhead 1436, which may push reactant gases away from the top surface and enable reactant gases provided from the ShoPed 1437 to be directed to the under surface of the wafer 1402. Spacers 1444 and / or other similar substrate support features may be used to provide controlled separation between the wafer and the ShoPed and the showerhead. Spacers 1444 and / or other similar substrate support features may be connected or supported by the ShoPed such that the wafer (or its reference plane, when the wafer is bowed) may maintain an even and / or parallel distance from the top surface of the ShoPed, even when there is an unwanted movement or oscillation at the system or chamber level.

[0192] Further, the gases may be premixed or not. Appropriate valving and mass flow control mechanisms may be employed to ensure that the correct gases are delivered during the deposition and plasma treatment phases of the process. Process gases may exit the chamber 1434 via one or more exhausts or outlets. A vacuum pump (e.g., a one or two stage mechanical dry pump and / or a turbomolecular pump) may draw process gases out and maintains a suitably low pressure within the reactor by a close loop-controlled flow restriction device, such as a throttle valve or a pendulum valve.

[0193] Figure 15 schematically shows an embodiment of a process station 1500 that may be used to deposit material using atomic layer deposition (ALD) and / or chemical vapor deposition (CVD), either of which may be plasma enhanced. For simplicity, the process station 1500 is depicted as a standalone process station having a process chamber body 1502 for maintaining a low-pressure environment. However, it will be appreciated that a plurality of process stations 1500 may be included in a common process tool environment. Further, it will be appreciated that, in some embodiments, one or more hardware parameters of process station 1500, including those discussed in detail below, may be adjusted programmatically by one or more computer controllers.

[0194] Process station 1500 fluidly communicates with reactant delivery system 1501 for delivering process gases to a showerhead 1506. Reactant delivery system 1501 includes a mixing vessel 1504 for blending and / or conditioning process gases for delivery to showerhead 1506. One or more mixing vessel inlet valves 1520 may control introduction of process gases to mixing vessel 1504. Similarly, a showerhead inlet valve 1505 may control introduction of process gasses to the showerhead 1506.

[0195] Some reactants, like BTBAS, may be stored in liquid form prior to vaporization at and subsequent delivery to the process station. For example, the embodiment of FIG. 15 includes a vaporization point 1503 for vaporizing liquid reactant to be supplied to mixing vessel 1504.Docket No. LAM1P088WOIn some embodiments, vaporization point 1503 may be a heated vaporizer. The reactant vapor produced from such vaporizers may condense in downstream delivery piping. Exposure of incompatible gases to the condensed reactant may create small particles. These small particles may clog piping, impede valve operation, contaminate substrates, etc. Some approaches to addressing these issues involve sweeping and / or evacuating the delivery piping to remove residual reactant. However, sweeping the delivery piping may increase process station cycle time, degrading process station throughput. Thus, in some embodiments, delivery piping downstream of vaporization point 1503 may be heat traced. In some examples, mixing vessel 1504 may also be heat traced. In one non-limiting example, piping downstream of vaporization point 1503 has an increasing temperature profile extending from approximately 100°C to approximately 150°C at mixing vessel 1504.

[0196] In some embodiments, reactant liquid may be vaporized at a liquid injector. For example, a liquid injector may inject pulses of a liquid reactant into a carrier gas stream upstream of the mixing vessel. In one scenario, a liquid injector may vaporize reactant by flashing the liquid from a higher pressure to a lower pressure. In another scenario, a liquid injector may atomize the liquid into dispersed microdroplets that are subsequently vaporized in a heated delivery pipe. It will be appreciated that smaller droplets may vaporize faster than larger droplets, reducing a delay between liquid injection and complete vaporization. Faster vaporization may reduce a length of piping downstream from vaporization point 1503. In one scenario, a liquid injector may be mounted directly to mixing vessel 1504. In another scenario, a liquid injector may be mounted directly to showerhead 1506.

[0197] In some embodiments, a liquid flow controller upstream of vaporization point 1503 may be provided for controlling a mass flow of liquid for vaporization and delivery to process station 1500. For example, the liquid flow controller (EFC) may include a thermal mass flow meter (MFM) located downstream of the EFC. A plunger valve of the EFC may then be adjusted responsive to feedback control signals provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM. However, it may take one second or more to stabilize liquid flow using feedback control. This may extend a time for dosing a liquid reactant. Thus, in some embodiments, the EFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, the EFC may be dynamically switched from a feedback control mode to a direct control mode by disabling a sense tube of the EFC and the PID controller.

[0198] Showerhead 1506 distributes process gases toward substrate 1512. In the embodiment shown in Figure 15, substrate 1512 is located beneath showerhead 1506, and is shown restingDocket No. LAM1P088WOon a pedestal 1508. It will be appreciated that showerhead 1506 may have any suitable shape, and may have any suitable number and arrangement of ports for distributing processes gases to substrate 1512.

[0199] In some embodiments, a laser 1513 may be present according to various embodiments herein. Laser 1513 may be integrated with or separate from showerhead 1506. A laser beam 1515 is shown encompassing substrate 1512. In some embodiments, the laser may emit laser beams having a spot size that covers the entire wafer or most of the wafer. In other embodiments, laser 1513 may operate according to other embodiments disclosed herein, including a scanning spot or spot grid. In some embodiments, a laser may be used during CVD, ALD, etch, or thermal treatment operations as disclosed herein.

[0200] Optionally, pedestal 1508 may be lowered and / or raised during portions the deposition process to modulate process pressure, reactant concentration, etc., within microvolume 1507. In one scenario where process chamber body 1502 remains at a base pressure during the deposition process, lowering pedestal 1508 may allow microvolume 1507 to be evacuated. Example ratios of microvolume to process chamber volume include, but are not limited to, volume ratios between 1:100 and 1:10. It will be appreciated that, in some embodiments, pedestal height may be adjusted programmatically by a suitable computer controller.

[0201] In another scenario, adjusting a height of pedestal 1508 may allow a plasma density to be varied during plasma activation and / or treatment cycles included in the deposition process. At the conclusion of the deposition process phase, pedestal 1508 may be lowered during another substrate transfer phase to allow removal of substrate 1512 from pedestal 1508.

[0202] While the example microvolume variations described herein refer to a height-adjustable pedestal, it will be appreciated that, in some embodiments, a position of showerhead 1506 may be adjusted relative to pedestal 1508 to vary a volume of microvolume 1507. Further, it will be appreciated that a vertical position of pedestal 1508 and / or showerhead 1506 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, pedestal 1508 may include a rotational axis for rotating an orientation of substrate 1512. It will be appreciated that, in some embodiments, one or more of these example adjustments may be performed programmatically by one or more suitable computer controllers.

[0203] Returning to the embodiment shown in Figure 15, showerhead 1506 and pedestal 1508 electrically communicate with RF power supply 1514 and matching network 1516 for powering a plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of a process station pressure, a gas concentration, an RF source power, an RF source frequency, and a plasma power pulse timing. For example, RF power supply 1514 andDocket No. LAM1P088WOmatching network 1516 may be operated at any suitable power to form a plasma having a desired composition of radical species. Examples of suitable powers are included above. Likewise, RF power supply 1514 may provide RF power of any suitable frequency. In some embodiments, RF power supply 1514 may be configured to control high- and low-frequency RF power sources independently of one another. Example low-frequency RF frequencies may include, but are not limited to, frequencies between 50 kHz and 1500 kHz. Example high-frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz. It will be appreciated that any suitable parameters may be modulated discretely or continuously to provide plasma energy for the surface reactions. In one non-limiting example, the plasma power may be intermittently pulsed to reduce ion bombardment with the substrate surface relative to continuously powered plasmas.

[0204] In some embodiments, the plasma may be monitored in-situ by one or more plasma monitors. In one scenario, plasma power may be monitored by one or more voltage, current sensors (e.g., VI probes). In another scenario, plasma density and / or process gas concentration may be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters may be programmatically adjusted based on measurements from such in-situ plasma monitors. For example, an OES sensor may be used in a feedback loop for providing programmatic control of plasma power. It will be appreciated that, in some embodiments, other monitors may be used to monitor the plasma and other process characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

[0205] In some embodiments, the plasma may be controlled via input / output control (IOC) sequencing instructions. In one example, the instructions for setting plasma conditions for a plasma process phase may be included in a corresponding plasma activation recipe phase of a deposition process recipe. In some cases, process recipe phases may be sequentially arranged, so that all instructions for a deposition process phase are executed concurrently with that process phase. In some embodiments, instructions for setting one or more plasma parameters may be included in a recipe phase preceding a plasma process phase. For example, a first recipe phase may include instructions for setting a flow rate of an inert and / or a reactant gas, instructions for setting a plasma generator to a power set point, and time delay instructions for the first recipe phase. A second, subsequent recipe phase may include instructions for enabling the plasma generator and time delay instructions for the second recipe phase. A third recipe phase may include instructions for disabling the plasma generator and time delay instructionsDocket No. LAM1P088WOfor the third recipe phase. It will be appreciated that these recipe phases may be further subdivided and / or iterated in any suitable way within the scope of the present disclosure.

[0206] In some deposition processes, plasma strikes last on the order of a few seconds or more in duration. In certain implementations, much shorter plasma strikes may be used. These may be on the order of 10 ms to 1 second, typically, about 20 to 80 ms, with 50 ms being a specific example. Such very short RF plasma strikes require extremely quick stabilization of the plasma. To accomplish this, the plasma generator may be configured such that the impedance match is set preset to a particular voltage, while the frequency is allowed to float. Conventionally, high-frequency plasmas are generated at an RF frequency at about 13.56 MHz. In various embodiments disclosed herein, the frequency is allowed to float to a value that is different from this standard value. By permitting the frequency to float while fixing the impedance match to a predetermined voltage, the plasma can stabilize much more quickly, a result which may be important when using the very short plasma strikes associated with some types of deposition cycles.

[0207] In some embodiments, pedestal 1508 may be temperature controlled via heater 1510. In some embodiments, the temperature of the wafer may be controlled by laser 1513. Further, in some embodiments, pressure control for deposition process station 1500 may be provided by butterfly valve 1518. As shown in the embodiment of Figure 15, butterfly valve 1518 throttles a vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of process station 1500 may also be adjusted by varying a flow rate of one or more gases introduced to process station 1500.

[0208] Figures 16-21 present various schematics of control schemes for a wafer and / or laser to perform laser treatment operations described herein. Figure 16 illustrates an embodiment of a polar control scheme of a wafer. A laser 1600 may direct laser beams towards a substrate 1602. Two positional schemes may be used, a rotational scheme that may rotate the wafer 360°, and a translational scheme that may move a wafer along a radius, e.g., 150mm. Based on the radius and angle of the wafer, the laser may treat all locations of the wafer. In some embodiments, the wafer moves in radial and azimuthal directions. In some embodiments, the laser may move in radial and azimuthal directions. In some embodiments, the wafer may move in an azimuthal direction and the laser may move in a radial direction, or vice versa. One advantage of a radial and azimuthal movement scheme is that the translational movement of the wafer is only up to the radius of the wafer. In some embodiments, the wafer may be fixed and the laser moves relative to the wafer. In some embodiments, the laser is fixed, and the wafer may move relative to the laser.Docket No. LAM1P088WO

[0209] Figure 17 illustrates an embodiment of a planar translational control scheme along x and y dimensions. A laser 1700 may direct laser beams towards a substrate 1702 that may move along axes 1704 and 1706. Axes 1704 and 1706 may be perpendicular and capable of moving the wafer a distance of at least about the full diameter of the wafer. In some embodiments, the laser may move instead of the wafer. In such embodiments, the wafer is stationary and the laser may move along perpendicular axes in a plane parallel to the surface of the wafer.

[0210] Figure 18 presents a schematic view of an indirect laser treatment apparatus. In Figure 16 a wafer 1802 may translate along axes 1804 and 1806. A laser 1800 may emit laser beams that pass through a first lens 1816, a patterning screen 1814, and second lens 1812. The patterning screen may implement a beam splitter or beam shaping pattern.

[0211] In some embodiments, a patterning screen may reflect, absorb, or transmit laser beams that, in combination with other optical devices, causes a particular pattern of laser beams to interact with a surface, such as patterns disclosed herein. In some embodiments a patterning screen may be static, e.g., a mask having a coating of reflective / absorptive material that absorbs / reflects light and slits or holes in the mask through which light may pass. In some embodiments, a patterning screen may be dynamic, e.g., an LCD or e-ink mask. A dynamic mask may be modified during or between laser treatments to selectively block or transmit light by, e.g., modification of the pixels of the mask. In some embodiments, laser beam patterns disclosed herein may be caused by one or more static or dynamic patterning screens. In some embodiments, a set of patterning screens may be included in a laser treatment apparatus, and one or more patterning screens of the set may be used during laser treatment operations to cause laser beam patterns described herein.

[0212] Figure 19 presents a schematic view of another indirect laser treatment apparatus. In Figure 19, a laser 1900 may direct a laser beam through a galvo 1910 that may redirect the laser beam through a series of lens, including a lens 1912, such that the laser beam meets a wafer 1902. In such embodiments, the wafer 1902 may only need to move along one axis 1906, as the galvo scanner and lens 1912 may be used to direct a laser beam along a perpendicular axis. In some embodiments, no translational movement of the wafer is required. A galvo may operate by using one or more mirrors that may be rotated to control reflections of laser beams. In some embodiments, mirrors and / or lens may be used to control the scanning of laser beams across a wafer.

[0213] In some embodiments, an indirect laser treatment apparatus may use a digital micromirror device (DMD). A DMD may have a plurality of mirrors that may be individually controllable to reflect light in a controlled pattern. A DMD may be used with a laser to transmitDocket No. LAM1P088WOlaser beams according to a determined pattern, including any patterns described herein. In some embodiments, a DMD may be used similar to a mask or patterning screen to selectively reflect light onto a wafer. In some embodiments, a DMD may be programmed according to a pattern so that each mirror reflects light onto a wafer according to the pattern. In some embodiments, no movement of the wafer is required for patterning with a DMD. In some embodiments, a DMD may be used with additional mirrors and / or lens to control the scanning of laser beams across a wafer.

[0214] In some embodiments, the focal distance, i.e., the distance between a lens associated with a laser and the wafer, may change as a result of wafer bow. For example, for a wafer having a 1mm wafer bow, the focal distance between the lens and the wafer may change by up to 1mm across the wafer surface. This may de-focus the laser beams, which is undesirable. Thus, in some embodiments, the laser, wafer, or both may be adjusted in a z-direction to control a focal distance between the laser and the wafer. In some embodiments, a laser may emit a Bessel beam or other highly collimated laser beam that has a depth of focus equal to or greater than the maximum wafer bow of the wafer. In some embodiments, a laser beam may have a depth of field of about 300 pm, such that if the focal distance is within this depth of field a z-axis adjustment is not required. In some embodiments, the z-axis distance between the wafer surface and the laser is not adjusted unless the focal distance changes by at least a threshold value. In some embodiments, that threshold value is about 300 pm.

[0215] In some embodiments, the wafer shape may be measured prior to laser treatment and used to determine a z-axis adjustment during laser treatment. This may be performed quickly as the wafer bow across the surface of the wafer may be quickly determined, increasing throughput. However, the wafer bow may change during laser treatment, which may undesirably disrupt the focal distance and reduce the effectiveness of laser treatment.

[0216] In some embodiments, a pilot laser may be used concurrently with the laser used for laser treatment to dynamically determine focal distance during laser treatment operations and adjust the z-axis of the laser and / or wafer. This may dramatically increase control of focal distance as the pilot laser may account for any instantaneous changes in wafer bow, but may also decrease throughput as the z-axis must be adjusted without over-exposing any portions of the wafer to laser treatment.

[0217] Figure 20 presents a schematic view of a pilot laser apparatus, which may include a pilot laser 2020, a z-axis adjustment 2016, and a pilot laser beam 2014. The pilot laser beam may scan the wafer ahead of a laser used for laser treatment to determine focal distance in situDocket No. LAM1P088WOand dynamically adjust the distance between the wafer 2002 and the laser. The wafer may also move along axes 2006 and 2004.

[0218] Figure 21 presents another schematic view of an apparatus for laser treatment. A stress measurement device 2120 may be used to dynamically measure wafer distortion using a laser beam 2114 and adjust one or more control values for a laser, including a z-axis adjustment 2116. In some embodiments, the measured stress may be used to affect the laser treatment to, e.g., increase or decrease the proportion of the wafer 2102 being laser treated or affect which portions of the wafer surface are laser treated. This may be particularly advantageous to measure and correct IPD by measuring IPD based on overlay error and / or wafer bow and adjusting laser treatment to reduce wafer bow / IPD. In some embodiments, laser parameters may be adjusted based on measured stress, including power, scanning speed, shape, width, pitch, etc. The wafer may also move along axes 2106 and 2104.

[0219] In some embodiments, wafer bow may be measured for a portion of the wafer, the focal distance adjusted for that portion, and then the measurement may be repeated for an additional portion until the entire wafer is laser treated. This may be faster than a pilot laser and more accurate than measuring the entire wafer. In some embodiments, the area of the portion to be scanned may vary between about 10 mm by 10 mm to about 50 mm by 50 mm. Larger areas may increase throughput at the expense of accuracy, as wafer bow may change more during laser treatment for larger areas.

[0220] As described above, one or more process stations may be included in a multi-station processing tool. Figure 22 shows a schematic view of an embodiment of a multi-station processing tool 2200 with an inbound load lock 2202 and an outbound load lock 2204, either or both of which may comprise a remote plasma source. A robot 2206, at atmospheric pressure, is configured to move substrates or wafers from a cassette loaded through a pod 2208 into inbound load lock 2202 via an atmospheric port 2210. A substrate is placed by the robot 2206 on a pedestal 2212 in the inbound load lock 2202, the atmospheric port 2210 is closed, and the load lock is pumped down. Where the inbound load lock 2202 comprises a remote plasma source, the substrate may be exposed to a remote plasma treatment in the load lock prior to being introduced into a processing chamber 2214. Further, the substrate also may be heated in the inbound load lock 2202 as well, for example, to remove moisture and adsorbed gases. Next, a chamber transport port 2216 to processing chamber 2214 is opened, and another robot (not shown) places the substrate into the reactor on a pedestal of a first station shown in the reactor for processing. While the embodiment depicted in Figure 22 includes load locks, it will be appreciated that, in some embodiments, direct entry of a substrate into a process station mayDocket No. LAM1P088WObe provided. In various embodiments, the soak gas is introduced to the station when the substrate is placed by the robot 2206 on the pedestal 2212.

[0221] The depicted processing chamber 2214 comprises four process stations, numbered from 1 to 4 in the embodiment shown in Figure 22. Each station has a heated pedestal (shown at 2218 for station 1), and gas line inlets. It will be appreciated that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between an ALD and PEALD process mode. Additionally or alternatively, in some embodiments, processing chamber 2214 may include one or more matched pairs of ALD and plasma-enhanced ALD process stations. While the depicted processing chamber 2214 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments a processing chamber may have three or fewer stations. In some embodiments, a processing chamber may be an SSM tool available from Lam Research.

[0222] Figure 22 depicts an embodiment of a wafer handling system 2290 for transferring substrates within processing chamber 2214. In some embodiments, wafer handling system 2290 may transfer substrates between various process stations and / or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. Figure 22 also depicts an embodiment of a system controller 2250 employed to control process conditions and hardware states of process tool 2200. System controller 2250 may include one or more memory devices 2256, one or more mass storage devices 2254, and one or more processors 2252. Processor 2252 may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc. In some embodiments, system controller 2250 includes machine-readable instructions for performing operations such as those described herein.

[0223] In some embodiments, a laser treatment chamber may be integrated into a multi-station processing tool at various locations. Each of letters A-E indicate a potential location for a laser treatment chamber, including a foup loader, as a process chamber connected to wafer handling system 2290, as a process chamber connected to inbound load lock 2202, as a process chamber connected to robot 2206, or integrated into load lock 2202. In some embodiments, a laser treatment chamber may be part of a standalone tool.

[0224] In some embodiments, system controller 2250 controls the activities of process tool 2200. System controller 2250 executes system control software 2258 stored in mass storageDocket No. LAM1P088WOdevice 2254, loaded into memory device 2256, and executed on processor 2252. Alternatively, the control logic may be hard coded in the system controller 2250. Applications Specific Integrated Circuits, Programmable Logic Devices (e.g., field-programmable gate arrays, or FPGAs) and the like may be used for these purposes. In the following discussion, wherever “software” or “code” is used, functionally comparable hard coded logic may be used in its place. System control software 2258 may include instructions for controlling the timing, mixture of gases, amount of gas flow, chamber and / or station pressure, chamber and / or station temperature, substrate temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by process tool 2200. System control software 2258 may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components used to carry out various process tool processes. System control software 2258 may be coded in any suitable computer readable programming language.

[0225] In some embodiments, system control software 2258 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored on mass storage device 2254 and / or memory device 2256 associated with system controller 2250 may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0226] In some implementations, a controller 2250 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller 2250, depending on the processing requirements and / or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and otherDocket No. LAM1P088WOtransfer tools and / or load locks connected to or interfaced with a specific system.

[0227] Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0228] The controller, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits locatedDocket No. LAM1P088WOremotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0229] Without limitation, example systems may include a laser treatment chamber, plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0230] As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0231] A substrate positioning program may include program code for process tool components that are used to load the substrate onto pedestal 2218 and to control the spacing between the substrate and other parts of process tool 2200.

[0232] A process gas control program may include code for controlling gas composition (e.g., first precursor gas, soak gas, second reactant gas, and purge gases as described herein) and flow rates and optionally for flowing gas into one or more process stations prior to deposition in order to stabilize the pressure in the process station. A pressure control program may include code for controlling the pressure in the process station by regulating, for example, a throttle valve in the exhaust system of the process station, a gas flow into the process station, etc.

[0233] A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas (such as the soak gas) to the substrate.

[0234] A plasma control program may include code for setting RF power levels applied to the process electrodes in one or more process stations in accordance with the embodiments herein.

[0235] A pressure control program may include code for maintaining the pressure in the reaction chamber in accordance with the embodiments herein.

[0236] In some embodiments, there may be a user interface associated with system controller 2250. The user interface may include a display screen, graphical software displays of theDocket No. LAM1P088WOapparatus and / or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0237] In some embodiments, parameters adjusted by system controller 2250 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), pressure, temperature, etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing the user interface.

[0238] Signals for monitoring the process may be provided by analog and / or digital input connections of system controller 2250 from various process tool sensors. The signals for controlling the process may be output on the analog and digital output connections of process tool 2200. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0239] System controller 2250 may provide program instructions for implementing the abovedescribed deposition processes such as processes that employ a soak prior to initiating ALD for a substrate inserted into the reaction chamber, with the soak performed under any of the soak conditions described herein. The program instructions may control a variety of process parameters, such as direct current (DC) power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate in-situ deposition of film stacks according to various embodiments described herein.

[0240] The system controller will typically include one or more memory devices and one or more processors configured to execute the instructions so that the apparatus will perform a method in accordance with disclosed embodiments. Machine-readable media containing instructions for controlling process operations in accordance with disclosed embodiments may be coupled to the system controller.Examples

[0241] Example 1. A method, comprising:receiving a substrate having a frontside and a backside, wherein the substrate has a wafer bow from one or more frontside layers on the frontside and a backside layer; and exposing one or more portions of a backside layer to laser beams to modify the internal stress of the one or more portions.

[0242] Example 2. The method of any one of the previous examples, wherein exposing one or more portions of the backside layer to laser beams comprises annealing the one or moreDocket No. LAM1P088WOportions.

[0243] Example 3. The method of any one of the previous examples, further comprising depositing the backside layer.

[0244] Example 4. The method of any one of the previous examples, wherein the one or more portions is the entire backside layer.

[0245] Example 5. The method of any one of the previous examples, wherein the backside layer mitigates wafer bow from the one or more frontside layers.

[0246] Example 6. The method of any one of the previous examples, wherein the one or more portions have an elliptical shape.

[0247] Example 7. The method of any one of the previous examples, wherein the one or more portions have a rectangular shape.

[0248] Example 8. The method of any one of the previous examples, wherein the backside layer reduces in-plane distortion of the substrate caused by the one or more frontside layers.

[0249] Example 9. The method of any one of the previous examples, further comprising depositing an additional backside layer and exposing one or more portions of the additional backside layer to laser beams to modify one or more properties of the one or more exposed portions of the additional backside layer.

[0250] Example 10. A method of reducing bow in a substrate, the method comprising: receiving a substrate having a frontside and a backside, wherein the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction of the substrate, wherein the substrate has a backside layer on the backside of the substrate, wherein the backside layer compensates the first bow more than it compensates the second bow; andexposing one or more portions of a backside layer to laser beams to modify the internal stress of the one or more portions, wherein after exposure the backside layer further compensates the second bow.

[0251] Example 11. The method of any one of the previous examples, wherein the received substrate has a saddle-shaped bow.

[0252] Example 12. A method of reducing bow in a substrate, the method comprising: receiving a substrate having a frontside and a backside, wherein the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction of the substrate, wherein the substrate has a backside layer on the backside of the substrate, wherein the backside layer compensates the first bow more than it compensates the second bow; andDocket No. LAM1P088WOetching one or more portions of the backside layer using laser beams, wherein after etching the backside layer better compensates the second bow.

[0253] Example 13. The method of any one of the previous examples, wherein the backside layer before etching increases the second bow.

[0254] Example 14. The method of any one of the previous examples, further comprising depositing an additional backside layer, wherein the additional backside layer backfills the etched one or more portions of the backside layer.

[0255] Example 15. The method of any one of the previous examples, wherein the additional backside layer compensates the second bow more than it compensates the first bow.

[0256] Example 16. The method of any one of the previous examples, wherein a pitch between the one or more portions of the backside layer is between about 0.1 pm and about 10 pm.

[0257] Example 17. A method of reducing bow in a substrate, the method comprising: receiving a substrate having a frontside and a backside;exposing the backside of the substrate to laser beams to cause a tensile internal stress in the backside of the substrate; anddepositing a backside layer on the backside of the substrate having a tensile internal stress.

[0258] Example 18. The method of any one of the previous examples, wherein tensile internal stress of the substrate and the backside layer causes a wafer bow of at least about 1 mm.

[0259] Example 19. A method of reducing bow in a substrate, the method comprising: receiving a substrate having a frontside and a backside;etching one or more portions of the substrate using laser beams to create features; and depositing a backside layer on the backside of the substrate, wherein the backside layer fills the features and forms a uniform layer.

[0260] Example 20. The method of any one of the previous examples, further comprising planarizing the backside layer.

[0261] Example 21. A method of etching features in a substrate, the method comprising: receiving a substrate comprising one or more layers;modifying one or more layers in the substrate using laser beams; anddepositing a backside layer on the backside of the substrate, wherein the backside layer fills the features and forms a uniform layer.

[0262] Example 22. A method, comprising:Docket No. LAM1P088WOreceiving a substrate in a process chamber; anddepositing material on the substrate using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process, wherein during depositing one or more portions of the substrate are exposed to laser beams.

[0263] Example 23. The method of any one of the previous examples, wherein the laser beams heat the one or more portions of the substrate to a temperature of at least about 400 °C.

[0264] Example 24. The method of any one of the previous examples, wherein material substantially deposits only on the one or more portions of the substrate exposed to laser beams.

[0265] Example 25. The method of any one of the previous examples, wherein the CVD and ALD process each comprise flowing a species into the process chamber, and the laser beams cause a photochemical reaction of the species flowed into the process chamber.

[0266] Example 26. The method of any one of the previous examples, wherein the substrate has one or more features that correspond to the one or more portions of the substrate exposed to laser beams.

[0267] Example 27. The method of any one of the previous examples, wherein the one or more portions have a critical dimension of at least 1 pm.

[0268] Example 28. A method, comprising:receiving a substrate in a process chamber; andetching material on the substrate by:exposing one or more portions of the substrate to laser beams; andexposing the substrate to a chemical species to react with the one or more exposed portions.

[0269] Example 29. The method of any one of the previous examples, wherein exposing one or more portions of the substrate to laser beams occurs simultaneously with exposing the substrate to a chemical species.

[0270] Example 30. The method of any one of the previous examples, wherein exposing one or more portions of the substrate to laser beams occurs prior to exposing the substrate to a chemical species.

[0271] Example 31. The method of any one of the previous examples, wherein the one or more portions have a critical dimension of at least 1 pm.

[0272] Example 32. A substrate comprising:a laser absorption layer; andan annealing layer, wherein one or more properties of the annealing layer changes under annealing conditions of at least about 600 °C.Docket No. LAM1P088WO

[0273] Example 33. The substrate of any one of the previous examples, wherein the laser absorption layer is the outermost layer.

[0274] Example 34. The substrate of any one of the previous examples, wherein the laser absorption layer comprises one or more compositions from the group consisting of: amorphous silicon, silicon nitride, metal oxides, silicon oxide, carbon, metal, aluminum oxide, aluminum nitride, aluminum oxynitride, boron nitride, tungsten nitride, tungsten carbide, and tungsten carbide-nitride.

[0275] Example 35. The substrate of any one of the previous examples, wherein the laser absorption layer is a sacrificial layer.

[0276] Example 36. The substrate of any one of the previous examples, further comprising a thermal insulation layer.

[0277] Example 37. The substrate of any one of the previous examples, wherein the thermal insulation layer comprises one or more compositions from the group consisting of silicon oxide, silicon nitride, and low-k dielectric materials.

[0278] Example 38. The substrate of any one of the previous examples, further comprising a laser reflection and / or absorption layer.

[0279] Example 39. The substrate of any one of the previous examples, wherein the laser reflection and / or absorption layer comprises tungsten, titanium nitride, or both.

[0280] Example 40. A system for laser treatment of substrates, comprising:a process chamber, wherein the process chamber comprises:a laser;a substrate support; wherein the substrate support and the laser are movable with respect to each other; anda controller configured for performing any one of the examples above.

[0281] Example 41. The system of any one of the previous examples, wherein the laser comprises a fixed laser head, a galvo scanner, a beam shaper, a beam splitter, or any combinations thereof

[0282] Example 42. The system of any one of the previous examples, wherein substrate support and laser are movable along x- and y-dimensions relative to each other.

[0283] Example 43. The system of any one of the previous examples, wherein substrate support and laser are movable along radial and azimuthal dimensions relative to each other.

[0284] Example 44. The system of any one of the previous examples, wherein the laser is a pulsed laser.

[0285] Example 45. The system of any one of the previous examples, wherein the laserDocket No. LAM1P088WOcomprises a pilot laser, wherein the pilot laser determines a distance between the laser and a substrate surface.

[0286] Example 46. The system of any one of the previous examples, further comprising an inbound load lock, an outbound load lock, an atmospheric port, a wafer handling system, one or more other process chambers, or any combinations thereof, wherein the process chamber is located in one element selected from the group consisting of: the inbound load lock, the outbound load lock, or the atmospheric port.

[0287] Example 47. The system of any one of the previous examples, wherein the process chamber is configured to receive substrates from the wafer handling system.

[0288] Example 48. A method, comprising:receiving a substrate having a frontside and a backside, wherein the substrate has a wafer distortion from one or more frontside layers on the frontside and a backside layer; and exposing one or more portions of a backside layer to laser beams to modify an internal stress of the one or more portions.

[0289] Example 49. The method of any one of the previous examples, wherein exposing one or more portions of the backside layer to laser beams comprises annealing the one or more portions, wherein annealing of the one or more portions causes chemical reactions to occur within the one or more portions, recrystallization of the one or more portions, or both.

[0290] Example 50. The method of any one of the previous examples, wherein the one or more portions have an elliptical or rectangular shape.

[0291] Example 51. The method of any one of the previous examples, wherein the substrate has in-plane distortion caused by the one or more frontside layers, wherein after exposure of the one or more portions of the backside layer to laser beams the backside layer reduces inplane distortion (IPD) of the substrate.

[0292] Example 52. The method of any one of the previous examples, further comprising determining IPD of the substrate prior to exposing one or more portions, wherein exposing one or more portions of the backside layer to laser beams is based on the IPD of the substrate.

[0293] Example 53. The method of any one of the previous examples, further comprising depositing an additional backside layer and exposing one or more portions of the additional backside layer to laser beams to modify one or more properties of the one or more exposed portions of the additional backside layer.

[0294] Example 54. The method of any one of the previous examples, wherein the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction of the substrate, wherein the backside layer compensates theDocket No. LAM1P088WOfirst bow more than it compensates the second bow; and wherein after exposing the one or more portions of the backside layer, the backside layer compensates more of the second bow.

[0295] Example 55. The method of any one of the previous examples, wherein the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction of the substrate, wherein the backside layer compensates the first bow more than it compensates the second bow; and wherein exposing one or more portions of the backside layer to laser beams comprises etching the one or more portions of the backside layer, wherein after the etching the backside layer compensates the second bow more than before the etching.

[0296] Example 56. The method of any one of the previous examples, further comprising depositing an additional backside layer, wherein the additional backside layer backfills the etched one or more portions of the backside layer.

[0297] Example 57. The method of any one of the previous examples, wherein the additional backside layer compensates the second bow more than it compensates the first bow.

[0298] Example 58. The method of any one of the previous examples, wherein exposing portions of the backside layer to laser beams causes a tensile internal stress in the backside of the substrate; and depositing an additional backside layer on the backside of the substrate having a tensile internal stress.

[0299] Example 59. The method of any one of the previous examples, wherein exposing one or more portions of the backside layer to laser beams comprises etching one or more portions of the substrate to create features; and wherein the method further comprises depositing a backside layer on the backside of the substrate, wherein the backside layer fills the features and forms a uniform layer.

[0300] Example 60. The method of any one of the previous examples, further comprising etching the one or more portions of the backside layer exposed to laser beams, wherein unexposed portions of the backside layer are etched less than exposed portions.

[0301] Example 61. The method of any one of the previous examples, wherein the substrate comprises one or more additional backside layers, wherein the one or more of additional backside layers include one or more layers selected from the group consisting of:a laser absorption layer;a thermal insulation layer; anda laser reflection.

[0302] Example 62. The substrate of any one of the previous examples, wherein the laser absorption layer comprises one or more compositions from the group consisting of: amorphousDocket No. LAM1P088WOsilicon, silicon nitride, metal oxides, silicon oxide, carbon, metal, aluminum oxide, aluminum nitride, aluminum oxynitride, boron nitride, tungsten nitride, tungsten carbide, and tungsten carbide-nitride.

[0303] Example 63. The substrate of any one of the previous examples, wherein the thermal insulation layer comprises one or more compositions from the group consisting of silicon oxide, silicon nitride, and low-k dielectric materials.

[0304] Example 64. The substrate of any one of the previous examples, wherein the laser reflection layer, laser absorption layer, or both comprise tungsten, titanium nitride, or both.

[0305] Example 65. A method, comprising:receiving a substrate in a process chamber; andexposing the substrate to a process gas comprising a reactive species; and exposing one or more portions of the substrate to laser beams.

[0306] Example 66. The method of any one of the previous examples, wherein a material deposits on the one or more portions of the substrate exposed to laser beams and does not deposit on unexposed portions of the substrate.

[0307] Example 67. The method of any one of the previous examples, wherein the substrate is etched at the one or more portions of the substrate exposed to laser beams and is not etched at unexposed portions of the substrate.Conclusion

[0308] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Embodiments disclosed herein may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. Further, while the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that the specific embodiments are not intended to limit the disclosed embodiments. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

Docket No. LAM1P088WOCLAIMSWhat is claimed is:

1. A method, comprising:receiving a substrate having a frontside and a backside, wherein the substrate has a wafer distortion from one or more frontside layers on the frontside and a backside layer; and exposing one or more portions of a backside layer to laser beams to modify an internal stress of the one or more portions.

2. The method of claim 1, wherein exposing one or more portions of the backside layer to laser beams comprises annealing the one or more portions, wherein annealing of the one or more portions causes chemical reactions to occur within the one or more portions, recrystallization of the one or more portions, or both.

3. The method of claim 1, wherein the one or more portions have an elliptical or rectangular shape.

4. The method of claim 1, wherein the substrate has in-plane distortion caused by the one or more frontside layers, wherein after exposure of the one or more portions of the backside layer to laser beams the backside layer reduces in-plane distortion (IPD) of the substrate.

5. The method of claim 4, further comprising determining IPD of the substrate prior to exposing one or more portions, wherein exposing one or more portions of the backside layer to laser beams is based on the IPD of the substrate.

6. The method of claim 1, further comprising depositing an additional backside layer and exposing one or more portions of the additional backside layer to laser beams to modify one or more properties of the one or more exposed portions of the additional backside layer.

7. The method of claim 1, wherein the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction ofDocket No. LAM1P088WOthe substrate, wherein the backside layer compensates the first bow more than it compensates the second bow; andwherein after exposing the one or more portions of the backside layer, the backside layer compensates more of the second bow.

8. The method of claim 1, wherein the substrate has a first bow in a first direction of the substrate and a second bow in a second direction perpendicular to the first direction of the substrate, wherein the backside layer compensates the first bow more than it compensates the second bow; andwherein exposing one or more portions of the backside layer to laser beams comprises etching the one or more portions of the backside layer, wherein after the etching the backside layer compensates the second bow more than before the etching.

9. The method of claim 8, further comprising depositing an additional backside layer, wherein the additional backside layer backfills the etched one or more portions of the backside layer.

10. The method of claim 9, wherein the additional backside layer compensates the second bow more than it compensates the first bow.

11. The method of claim 1, wherein exposing portions of the backside layer to laser beams causes a tensile internal stress in the backside of the substrate; anddepositing an additional backside layer on the backside of the substrate having a tensile internal stress.

12. The method of claim 1, wherein exposing one or more portions of the backside layer to laser beams comprises etching one or more portions of the substrate to create features; andwherein the method further comprises depositing a backside layer on the backside of the substrate, wherein the backside layer fills the features and forms a uniform layer.

13. The method of claim 1, further comprising etching the one or more portions of the backside layer exposed to laser beams, wherein unexposed portions of the backside layer are etched less than exposed portions.Docket No. LAM1P088WO14. The method of claim 1, wherein the substrate comprises one or more additional backside layers, wherein the one or more of additional backside layers include one or more layers selected from the group consisting of:a laser absorption layer;a thermal insulation layer; anda laser reflection.

15. The substrate of claim 14, wherein the laser absorption layer comprises one or more compositions from the group consisting of: amorphous silicon, silicon nitride, metal oxides, silicon oxide, carbon, metal, aluminum oxide, aluminum nitride, aluminum oxynitride, boron nitride, tungsten nitride, tungsten carbide, and tungsten carbide-nitride.

16. The substrate of claim 14, wherein the thermal insulation layer comprises one or more compositions from the group consisting of silicon oxide, silicon nitride, and low-k dielectric materials.

17. The substrate of claim 14, wherein the laser reflection layer, laser absorption layer, or both comprise tungsten, titanium nitride, or both.

18. A method, comprising:receiving a substrate in a process chamber; andexposing the substrate to a process gas comprising a reactive species; and exposing one or more portions of the substrate to laser beams.

19. The method of claim 18, wherein a material deposits on the one or more portions of the substrate exposed to laser beams and does not deposit on unexposed portions of the substrate.

20. The method of claim 18, wherein the substrate is etched at the one or more portions of the substrate exposed to laser beams and is not etched at unexposed portions of the substrate.

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