Integrated assembly including embedded components

Abstract

Embodiments described herein generally relate to an assembly. In one or more embodiments, an assembly includes a substrate having a first surface and a second surface, the first surface opposite the second surface. A first redistribution layer (RDL) is disposed over the first surface. At least one non-embedded component disposed over the first RDL. At least one embedded component is disposed within the substrate and contacts the first RDL. At least one component interconnect connects the at least one embedded component to the at least one non-embedded component.

Description

INTEGRATED ASSEMBLY INCLUDING EMBEDDED COMPONENTS BACKGROUNDField

[0001] Embodiments of the present disclosure generally relate to an assembly. More specifically, embodiments described herein relate to an assembly with embedded components such as memory, active logic or passive die, with dual-sided thermal management.Description of the Related Art

[0002] Two recent advancements in the space of computing are Artificial Intelligence (Al) and High-Performance Computing (HPC). Al is used to perform tasks traditionally requiring human intelligence, such as learning, reasoning, and decision making. HPC is used to process large datasets and perform calculations at high speeds to solve advanced computational problems. Al and HPC are growing at a rapid pace, and as they do, the need for computational power is growing as well.

[0003] Al and HPC systems face performance limitations. For example, large-scale data movement introduces bottlenecks, active computing components generate substantial heat when performing intensive computations, and the fabrication of through-silicon vias can be costly and may adversely affect yield.

[0004] Accordingly, what is needed in the art is an assembly with embedded components such as memory, active logic or passive die, with dual-sided thermal management.SUMMARY

[0005] In one embodiment, an assembly is disclosed. The assembly includes a substrate having a first surface and a second surface, the first surface opposite the second surface. A first redistribution layer (RDL) is disposed over the first surface. At least one non-embedded component disposed over the first RDL. At least one embedded component is disposed within the substrate and contacts the first RDL. At least one component interconnect connects the at least one embedded component to the at least one non-embedded component.

[0006] In another embodiment, an assembly is disclosed. The assembly includes a substrate having a vertical high-density interconnect pathway (VHIP) therethrough. A first redistribution layer (RDL) is disposed over a first surface of the substrate. A second RDL is disposed under a second surface of the substrate. At least one nonembedded component is disposed over the first RDL. At least one embedded component is disposed at least partially within the second RDL. At least one component interconnect extends through the VHIP and connects the at least one nonembedded component to the at least one embedded component. At least one power interconnect extends through the VHIP and is connected to the at least one embedded component.

[0007] In another embodiment, an assembly is disclosed. The assembly includes a substrate having a vertical high-density interconnect pathway (VHIP) therethrough. A first redistribution layer (RDL) is disposed over a first surface of the substrate. The first RDL has a first non-embedded component disposed thereover. A second RDL is disposed under a second surface of the substrate. The second RDL has a second non-embedded component disposed thereunder. At least one component interconnect extends through the VHIP and connects the first non-embedded component to the second non-embedded component.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of the disclosure and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments.

[0009] Figure 1 is a schematic, cross-sectional view of an assembly having a first component configuration, according to embodiments.

[0010] Figure 2 is a schematic, cross-sectional view of an assembly having a second component configuration, according to embodiments.

[0011] Figure 3 is a schematic, cross-sectional view of an assembly having a third component configuration, according to embodiments.

[0012] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0013] Embodiments of the present disclosure generally relate to an assembly. More specifically, embodiments described herein relate to an assembly with embedded components such as memory, active logic or passive die, with dual-sided thermal management. Active and passive components are embedded within a substrate to alleviate shoreline constraints, enabling three-dimensional integration that increases available component placement area without enlarging the component footprint. This configuration reduces interconnect length between processors (e.g., a graphics processing unit) and memory components (e.g., high-bandwidth memory), allowing finer pitch and higher interconnect density, improving bandwidth and overall system performance. Vertical high-density interconnect pathways, containing dielectric material therethrough, are disposed throughout the substrate, allowing interconnects to reach embedded and non-embedded components on an opposite side of the substrate. Dual-sided thermal management, achieved by upper and lower heat spreaders, enhances heat removal efficiency, reduces peak temperatures, and minimizes thermal throttling.

[0014] Figure 1 is a schematic, cross-sectional view of an assembly 100 having a first component configuration 100A, according to embodiments. Figure 2 is a schematic, cross-sectional view of an assembly 100 having a second component configuration 100B, according to embodiments. Figure 3 is a schematic, cross-sectional view of an assembly 100 having a third component configuration 100C, according to embodiments.

[0015] The assembly 100 includes a substrate 102. The substrate 102 includes a silicon-containing material. The substrate 102 includes a first surface 102A (i.e. , anupper surface), and a second surface 102B (i.e., a lower surface) opposite to the first surface 102 A.

[0016] A first redistribution layer (RDL) 104A (i.e., an upper RDL) is disposed over the first surface 102A. The first RDL 104A includes a plurality of component interconnects 106 and a plurality of power interconnects 108. The plurality of component interconnects 106 facilitate communication between components of the assembly 100. The plurality of power interconnects 108 are configured to supply power to components of the assembly 100. The various configurations of the plurality of component interconnects 106 and the plurality of power interconnects 108 are described herein with respect to the various component configurations 100A, 100B, 100C. In one or more embodiments, a first encapsulation layer 110A (i.e., upper encapsulation layer) is disposed over the first RDL 104A.

[0017] The substrate 102 further includes a second RDL 104B (i.e., lower RDL) disposed under the second surface 102B. The second RDL 104B includes the plurality of power interconnects 108 therein. In one or more embodiments, the second RDL 104B may include the plurality of component interconnects 106 therein. The second RDL 104B is described herein with respect to the various component configurations 100A, 100B, 1000, as described below.

[0018] The assembly 100 includes non-embedded components 112A, 112B, 112C disposed over the first surface 102A. In one or more embodiments, the nonembedded components 112A, 112B, 1120 are disposed over the first encapsulation layer 110A. In one or more other embodiments, the non-embedded components 112A, 112B, 1120 are disposed directly on the first RDL 104A.

[0019] Each of the non-embedded components 112A, 112B, 112C may be any active component or passive component. The non-embedded components 112A, 112B, 1120 include, at least, one processor. At least one processor is a graphics processing unit (GPU), a central processing unit (CPU), an accelerated processing unit (APU), a data processing unit (DPU), a neural processing unit (NPU), a microcontroller unit (MCU), a digital signal processor (DSP), a tensor processing unit (TPU), or application-specific integrated circuit (ASIC). Any of the non-embedded components 112A, 112B, 112C may be a memory component. At least one memory component is a high-bandwidth memory (HBM), random access memory (RAM),static random access memory (SRAM), video random access memory (VRAM), dynamic random access memory (DRAM), read-only memory (ROM), orcache.

[0020] The plurality of component interconnects 106 electrically couple adjacent non-embedded components 112A, 112B, 112C to each other. The non-embedded component 112A is connected to the non-embedded component 112B by a first component interconnect 106A. The first component interconnect 106A is disposed within the first RDL 104A. The non-embedded component 112A is connected to the non-embedded component 112C by a second component interconnect 106B. The second component interconnect 106B is disposed within the first RDL 104A. In one or more examples, the non-embedded components 112B, 112C may be HBM or SRAM, while the non-embedded component 112A may be a GPU. Such connections therebetween facilitates communication between the GPU and memory.

[0021] The plurality of power interconnects 108 are configured to interface with a power source or ground plane (not shown) to supply power to the components of the assembly 100. A first power interconnect 108A is connected to the non-embedded component 112B. The non-embedded component 112B is connected to a power source or ground plane by the first power interconnect 108A. The first power interconnect 108A includes a first portion in the first RDL 104A, and a second portion in the first RDL 104A, the substrate 102, and the second RDL 104B. A second power interconnect 108B is connected to the non-embedded component 112C. The nonembedded component 112C is connected to a power source or ground plane by the second power interconnect 108B. The second power interconnect 108B includes a first portion in the first RDL 104A, and a second portion in the first RDL 104A, the substrate 102, and the second RDL 104B.

[0022] The plurality of component interconnects 106 and the plurality of power interconnects 108 are formed of a conductive material. The conductive material includes copper (Cu), aluminum (Al), tungsten (W), gold (Au), titanium (Ti), molybdenum (Mo), tantalum (Ta), or combinations thereof. In one or more embodiments, the plurality of component interconnects 106 may be formed of the same conductive material as the plurality of power interconnects 108. In one or more embodiments, the plurality of component interconnects 106 may be formed of a different conductive material as the plurality of power interconnects 108.

[0023] A first heat spreader 116A (i.e., upper heat spreader) may be disposed over, and in contact with, the non-embedded components 112A, 112B, 112C. The first heat spreader 116A is configured to take the heat produced by the non-embedded components 112A, 112B, 112C and distribute it therethrough, thereby transferring heat away from the non-embedded components 112A, 112B, 112C during operation. The first heat spreader 116A includes a conductive material. The conductive material may include copper (Cu), aluminum (Al), tungsten (W), gold (Au), titanium (Ti), molybdenum (Mo), tantalum (Ta), or combinations thereof.

[0024] The assembly 100 further includes embedded components 114A, 114B. Depending on the configuration, the embedded components 114A, 114B may be embedded into the substrate 102, the second RDL 104B, or a combination thereof. In one or more configurations, the embedded components 114A, 114B may be positioned at least partially outside of the second RDL 104B. Such configurations are described herein with respect to Figures 1-2.

[0025] Each of the embedded components 114A, 114B may be any active component or passive component. Each of the embedded components 114A, 114B may be a processor. The processor may be a GPU, a CPU, an APU, a DPU, an NPU, an MCU, a DSP, a TPU, or ASIC. Each of the embedded components 114A, 114B may be a memory component. The memory component may be HBM, RAM, SRAM, VRAM, DRAM, ROM, orcache. Each of the embedded components 114A, 114B may be a passive component. The passive component may be a transistor, switch, capacitor, resistor, or inductor.

[0026] Referring now to Figure 1, the assembly 100 having the first component configuration 100A includes embedded components 114A, 114B disposed within the substrate 102. The embedded components 114A, 114B contact the first RDL 104A.

[0027] The assembly 100 having the first component configuration 100A includes a plurality of component interconnects 106 that connect, and electrically couple, the non-embedded components 112A, 112B, 112C to the embedded components 114A, 114B. The embedded component 114A is connected to the non-embedded component 112A by a third component interconnect 106C. The third component interconnect 106C is disposed within the first RDL 104A. The embedded component 114B is connected to the non-embedded component 112A by a fourth componentinterconnect 106D. The fourth component interconnect 106D is disposed within the first RDL 104A. In one or more embodiments, the embedded component 114A is connected to the embedded component 114B by a fifth component interconnect 106E. The fifth component interconnect 106E is disposed within the first RDL 104A. Such configurations allow for interfacing and communication between the embedded components 114A, 114B, as well as between the embedded components 114A, 114B and the non-embedded components 112A, 112B, 112C.

[0028] The assembly 100 having the first component configuration 100A includes the plurality of power interconnects 108 that are configured to interface with a power source or ground plane (not shown) to supply power to the components of the assembly 100. A third power interconnect 108C is connected to the embedded component 114A. The embedded component 114A is connected to a power source or ground plane by the third power interconnect 108C. The third power interconnect 108C includes a first portion in the first RDL 104A, and a second portion in the first RDL 104A, the substrate 102, and the second RDL 104B. A fourth power interconnect 108D is connected to the embedded component 114B. The embedded component 114B is connected to a power source or ground plane by the fourth power interconnect 108D. The fourth power interconnect 108D includes a first portion in the first RDL 104A, and a second portion in the first RDL 104A, the substrate 102, and the second RDL 104B. In one or more embodiments, each of the embedded components 112A, 112B, 112C (and each of the non-embedded components 114A, 114B) have a dedicated power interconnect 108 coupled thereto to drive power to the respective component.

[0029] In high-performance assemblies, the available shoreline, defined as the lateral surface area adjacent to a processor (e.g., a GPU), is inherently limited. The shoreline defines the region where additional components, such as memory components (e.g., HBM), can be placed in proximity to the processor (e.g., GPU) for optimal performance. As the size of the processor increases to accommodate advanced computational capabilities, the remaining lateral space for other components decreases, constraining the number of devices that can be positioned on the same plane, restricting memory capacity, bandwidth, and overall system scalability.

[0030] For example, as previously mentioned, the non-embedded component 112B and the non-embedded component 112C may be HBM, while the nonembedded component 112A may be a GPU. Each of the non-embedded components 112B, 112C may have a width of about ten millimeters (mm), while the non-embedded component 112A may have a width of about 30 mm. Each of the non-embedded components 112B, 112C are separated from the non-embedded component 112A by a distance Di. Due to shoreline constraint, the distance Di may be between about 1 mm to about 3 mm.

[0031] Including the embedded components 114A, 114B within the substrate 102 alleviates shoreline constraint by introducing a third dimension for component placement. Rather than relying solely on the two-dimensional shoreline surrounding the non-embedded component 112A (e.g., the GPU), the first component configuration 100A allows active and / or passive components to be positioned within the substrate 102, effectively creating additional planes for integration.

[0032] Furthermore, a distance D2 between the embedded components 114A, 114B, and the non-embedded components 112A, 112B, 112C is smaller than the distance Di between the non-embedded components 112B, 112C, and the nonembedded component 112A. For example, the distance D2 may be on a micron (pm) scale, such as between about 2 pm and about 100 pm. In this way, by embedding components directly within the substrate 102, the distance D2 between the embedded components 114A, 114B and the non-embedded components 112 A, 112B, 112C is minimized, allowing the embedded components 114A, 114B to be positioned closer to the processor (e.g., non-embedded component 112A) than the non-embedded components 112B, 112C arranged laterally on the same plane. The maximum number of interconnects between the components is a function of the available pitch therebetween, which is, in turn, a function of the interconnect length. By reducing interconnect length (e.g., shortening the distance between the embedded and nonembedded components), the interconnects can be positioned at a finer pitch. This reduction in the distance D2 enables a higher density of a plurality of component interconnects 106 between the GPU and the memory, thereby increasing bandwidth and improving system performance.

[0033] Referring now to Figure 2, the assembly 100 having the second component configuration 100B includes embedded components 114A, 114B that are partially embedded within the second RDL 104B. In one or more embodiments, each of the embedded components 114A, 114B may be at least partially embedded within both the substrate 102 and the second RDL 104B. Each of the embedded components 114A, 114B may be any active or passive logic die, as discussed above.

[0034] The assembly having the second component configuration 100B further includes a vertical high-density interconnect pathway (VHIP) 118 within the substrate 102. The VHIP 118 extends through the substrate 102, from the first RDL 104A to the second RDL 104B.

[0035] The VHIP 118 contains the plurality of component interconnects 106 and the plurality of power interconnects 108 therethrough. The VHIP 118 has a dielectric material 120 disposed therein such that the portion of the plurality of component interconnects 106, and the portion of the plurality of power interconnects 108, positioned within the VHIP 118 are surrounded by the dielectric material 120. In one or more embodiments, the dielectric material 120 may be an epoxy-based material. The dielectric material may have a dielectric constant less than, or equal to, 3.5 at 10 gigahertz (GHz), and a dissipation factor of less than, or equal to, 0.01 at 10 GHz. The dielectric material may further include particles dispersed therethrough. The particles may be, for example, silicon dioxide (SiO2) or glass. The dielectric material may additionally include latent or anhydride-based curing agents, reactive with the epoxy resin system, silane coupling agents, photo-definable additives, toughening agents, laser-ablation promoters, or combinations thereof.

[0036] In one or more embodiments, the VHIP 118 is formed through a selective photolithography and etching operation. A plurality of first vias are etched therethrough. After the substrate 102 has been etched, the dielectric material 120 is disposed therethrough. In one example, the dielectric material 120 may be disposed therethrough by laminating the dielectric material 120 over the substrate 102 such that the dielectric material 120 flows into and substantially fills the plurality of first vias. The dielectric material 120 may then go through a curing operation (e.g., a thermal cure, ultraviolet cure, etc.) to harden the dielectric material 120. After hardening, another photolithography and etch operation may be conducted to etch a plurality ofsecond vias therethrough. The second plurality of vias are etched such that a portion of the dielectric material 120 remains surrounding each via. Finally, the plurality of second vias are filled with a conductive material, such as through a deposition or electroplating operation. The conductive material, for example, may be copper (Cu), aluminum (Al), tungsten (W), gold (Au), titanium (Ti), molybdenum (Mo), tantalum (Ta), or combinations thereof.

[0037] The assembly 100 having the second component configuration 100B includes a plurality of component interconnects 106 that connect, and electrically couple, the embedded components 114A, 114B to the non-embedded components 112A, 112B, 112C. The embedded component 114A is connected to the nonembedded component 112A by a sixth component interconnect 106F. The sixth component interconnect 106F is disposed within the first RDL 104A, and within the VHIP 118. The embedded component 114B is connected to the non-embedded component 112A by a seventh component interconnect 106G. The seventh component interconnect 106G is disposed within the first RDL 104A, and within the VHIP 118. In one or more embodiments, the embedded component 114A is connected to the embedded component 114B by an eighth component interconnect 106H. The eighth component interconnect 106H is disposed within the first RDL 104A, and within the VHIP 118. Such configurations allow for interfacing and communication between the embedded components 114A, 114B, as well as between the embedded components 114A, 114B and the non-embedded components 112A, 112B, 112C. In one or more embodiments, the embedded components 114A, 114B may be HBM or SRAM, while the non-embedded component 112A is a processor, such as a GPU.

[0038] The assembly 100 having the second component configuration 100B includes the plurality of power interconnects 108 that are configured to interface with a power source or ground plane (not shown) to supply power to the components of the assembly 100. A fifth power interconnect 108E is connected to the embedded component 114A. The embedded component 114A is connected to a power source or ground plane by the fifth power interconnect 108E. The fifth power interconnect 108E includes a first portion in the first RDL 104A and the VHIP 118, and a second portion in the first RDL 104A, the substrate 102, and the second RDL 104B. A sixth power interconnect 108F is connected to the embedded component 114B. Theembedded component 114B is connected to a power source or ground plane by the sixth power interconnect 108F. The sixth power interconnect 108F includes a first portion in the first RDL 104A and the VHIP 118, and a second portion in the first RDL 104A, the substrate 102, and the second RDL 104B. In one or more embodiments, each of the embedded components 112A, 112B, 112C (and each of the nonembedded components 114A, 114B) have a dedicated power interconnect 108 coupled thereto to drive power to the respective component.

[0039] The embedded components 114A, 114B and the non-embedded components 112A, 112B, 112C of the assembly 100 having the second component configuration 100B are separated by a distance D3. As shown in Figure 2, the distance D3 is larger than the distance D2 (e.g., the embedded components and the nonembedded components are spaced further apart in the second component configuration than in the first component configuration). As previously mentioned, an increased distance between components imposes limitations on achievable interconnect density therebetween. However, the distance D3 may still be on a pm scale, such as between about 2 pm and about 100 pm. Furthermore, the dielectric material 120 of the VHIP 118 increases electrical isolation between each of the interconnects therein, supporting a finer pitch therebetween.

[0040] Additionally, the embedded components 114A, 114B of the assembly 100 having the second component configuration 100B may be positioned at least partially outside the second RDL 104B such that a second heat spreader 116B (i.e., lower heat spreader) may be disposed thereunder, and in contact with the embedded components 114A, 114B. Such configuration enables thermal management of both the components over the first surface 102A and under the second surface 102B of the assembly 100 having the second component configuration 100B. This dual-sided thermal management approach enhances heat removal efficiency, reducing peak temperatures and thereby the need for thermal throttling.

[0041] Referring now to Figure 3, the assembly 100 having the third component configuration 100C includes only non-embedded components 112A, 112B, 112C, 112D, 112E (i.e., does not contain any embedded components).

[0042] The assembly 100 having the third component configuration 100C includes the non-embedded components 112D, 112E disposed under the second surface102B. In one or more embodiments, the non-embedded components 112D, 112E are disposed under a second encapsulation layer 110B (i.e., lower encapsulation layer). In one or more other embodiments, the non-embedded components are disposed directly under the second RDL 104B. Each of the non-embedded components 112A, 112B, 112C, 112D, 112E may be any active or passive logic die, as described above.

[0043] The assembly 100 having the third component configuration 100C includes a plurality of component interconnects 106 that connect, and electrically couple, the non-embedded components 112A, 112B, 112C to the non-embedded components 112D, 112E. The non-embedded component 112D is connected to the nonembedded component 112A by a ninth component interconnect 1061. The ninth component interconnect 1061 is disposed within the first RDL 104A, the VHIP 118, and the second RDL 104B. The non-embedded component 112E is connected to the non-embedded component 112A by a tenth component interconnect 106J. The tenth component interconnect 106J is disposed within the first RDL 104A, the VHIP 118, and the second RDL 104B. In one or more embodiments, the non-embedded component 112D is connected to the non-embedded component 112E by an eleventh component interconnect 106K. The eleventh component interconnect 106K is disposed within the first RDL 104A and the VHIP 118. Such configurations allow for interfacing and communication between non-embedded components 112D, 112E, as well as between non-embedded components 112D, 112E and non-embedded components 112A, 112B, 112C. In one or more examples, the non-embedded components 112D, 112E may be HBM or SRAM, while the non-embedded component 112A may be a GPU. Such connections therebetween facilitates communication between the GPU and memory.

[0044] The assembly 100 having the third component configuration 100C includes a plurality of power interconnects 108 that are configured to interface with a power source or ground plane (not shown) to supply power to the components of the assembly 100. A seventh power interconnect 108G is connected to the nonembedded component 112D. The non-embedded component 112D is connected to a power source or a ground plane by the seventh power interconnect 108G. The seventh power interconnect 108G includes a first portion in the first RDL 104A, the VHIP 118, and the second RDL 104B, and a second portion in the first RDL 104A, the substrate 102, and the second RDL 104B. An eighth power interconnect 108H isconnected to the non-embedded component 112E. The non-embedded component 112E is connected to a power source or a ground plane by the eighth power interconnect 108H. The eighth power interconnect 108H includes a first portion in the first RDL 104A, the VHIP 118, and the second RDL 104B, and a second portion in the first RDL 104A, the substrate 102, and the second RDL 104B. In one or more embodiments, each non-embedded component 112A, 112B, 112C, 112D, 112E may have a dedicated power interconnect 108 coupled thereto to drive power to the respective component.

[0045] As shown in Figure 3, the plurality of component interconnects 106 and the plurality of power interconnects 108 extend through the VHIP 118 and through the second RDL 104B to contact the non-embedded components 112D, 112E. The second RDL 104B may operate as a fan-out layer by redistributing these interconnects laterally across a larger footprint. By leveraging the second RDL 104B for both signal and power fan-out, the assembly may maintain high interconnect density.

[0046] The non-embedded components 112D, 112E and the non-embedded components 112A, 112B, 112C of the assembly 100 having the third component configuration 100C are separated by a distance D4. As shown in Figure 3, the distance D4 is larger than either of the distance D2 and the distance D3 (e.g., the embedded components and the non-embedded components are spaced further apart in the third component configuration than in the first component configuration or second component configuration). As previously mentioned, an increased distance between components imposes limitations on achievable interconnect density therebetween. However, the distance D4 may still be on a pm scale, such as between about 2 pm and about 100 pm. Furthermore, the dielectric material 120 of the VHIP 118 increases electrical isolation between each of the interconnects therein, supporting a finer pitch therebetween.

[0047] Additionally, the non-embedded components 112A, 112B, 112C of the assembly having the third component configuration 100C may include the second heat spreader 116B. Such configuration enables thermal management of both the components over the first surface 102A and the components under the second surface 102B of the assembly 100 having the third component configuration 100C.This dual-sided thermal management approach enhances heat removal efficiency, reducing peak temperatures and thereby the need for thermal throttling.

[0048] Benefits of the present disclosure include embedding active and passive components within the substrate to alleviate shoreline constraints, enabling three-dimensional integration that increases available component placement area without enlarging the component footprint. This configuration reduces interconnect length between processors (e.g., GPU) and memory components (e.g., HBM), allowing finer pitch and higher interconnect density, improving bandwidth and overall system performance. VHIPs, containing dielectric material therethrough, are disposed throughout the substrate, allowing interconnects to reach embedded and nonembedded components on an opposite side of the substrate. Dual-sided thermal management, achieved by upper and lower heat spreaders, enhances heat removal efficiency, reduces peak temperatures, and minimizes thermal throttling.

[0049] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

What is claimed is:

1. An assembly, comprising:a substrate having a first surface and a second surface, the first surface opposite the second surface;a first redistribution layer (RDL) disposed over the first surface;at least one non-embedded component disposed over the first RDL;at least one embedded component disposed within the substrate and contacting the first RDL; andat least one component interconnect connecting the at least one embedded component to the at least one non-embedded component.

2. The assembly of claim 1 , wherein the at least one non-embedded component comprises at least one of a graphics processing unit (GPU), a central processing unit (CPU), an accelerated processing unit (APU), a data processing unit (DPU), a neural processing unit (NPU), a microcontroller unit (MCU), a digital signal processor (DSP), a tensor processing unit (TPU), or an application-specific integrated circuit (ASIC).

3. The assembly of claim 2, wherein the at least one embedded component comprises at least one of high-bandwidth memory (HBM), random access memory (RAM), static random access memory (SRAM), video random access memory (VRAM), dynamic random access memory (DRAM), read-only memory (ROM), or cache.

4. The assembly of claim 2, wherein the at least one embedded component is a passive component.

5. The assembly of claim 1, wherein the at least one embedded component is separated from the at least one non-embedded component by a distance between about 2 microns (pm) and about 100 pm.

6. The assembly of claim 1 , wherein a heat spreader is disposed over the at least one non-embedded component.

7. An assembly, comprising:a substrate having a vertical high-density interconnect pathway (VHIP) therethrough;a first redistribution layer (RDL) disposed over a first surface of the substrate; a second RDL disposed under a second surface of the substrate;at least one non-embedded component disposed over the first RDL;at least one embedded component disposed at least partially within the second RDL;at least one component interconnect, wherein the at least one component interconnect extends through the VHIP and connects the at least one non-embedded component to the at least one embedded component; andat least one power interconnect, wherein the at least one power interconnect extends through the VHIP and is connected to the at least one embedded component.

8. The assembly of claim 7, wherein the at least one non-embedded component comprises at least one of a graphics processing unit (GPU), a central processing unit (CPU), an accelerated processing unit (APU), a data processing unit (DPU), a neural processing unit (NPU), a microcontroller unit (MCU), a digital signal processor (DSP), a tensor processing unit (TPU), or an application-specific integrated circuit (ASIC).

9. The assembly of claim 8, wherein the at least one embedded component includes at least one of high-bandwidth memory (HBM), random access memory (RAM), static random access memory (SRAM), video random access memory (VRAM), dynamic random access memory (DRAM), read-only memory (ROM), or cache.

10. The assembly of claim 9, wherein the at least one embedded component is a passive component.

11. The assembly of claim 7, wherein the at least one embedded component is positioned at least partially outside the second RDL.

12. The assembly of claim 7, wherein a first heat spreader is disposed over the at least one non-embedded component, and wherein a second heat spreader is disposed under the at least one embedded component.

13. The assembly of claim 7, wherein the at least one embedded component is separated from the at least one non-embedded component by a distance between about 2 microns (pm) and about 100 pm.

14. An assembly, comprising:a substrate having a vertical high-density interconnect pathway (VHIP) therethrough;a first redistribution layer (RDL) disposed over a first surface of the substrate, the first RDL having a first non-embedded component disposed thereover;a second RDL disposed under a second surface of the substrate, the second RDL having a second non-embedded component disposed thereunder; andat least one component interconnect, wherein the at least one component interconnect extends through the VHIP and connects the first non-embedded component to the second non-embedded component.

15. The assembly of claim 14, wherein the first non-embedded component is a graphics processing unit (GPU), a central processing unit (CPU), an accelerated processing unit (APU), a data processing unit (DPU), a neural processing unit (NPU), a microcontroller unit (MCU), a digital signal processor (DSP), a tensor processing unit (TPU), or an application-specific integrated circuit (ASIC).

16. The assembly of claim 15, wherein the second non-embedded component is high-bandwidth memory (HBM), random access memory (RAM), static random access memory (SRAM), video random access memory (VRAM), dynamic random access memory (DRAM), read-only memory (ROM), or cache.

17. The assembly of claim 14, wherein the VHIP includes a dielectric material disposed therethrough.

18. The assembly of claim 14, wherein the first non-embedded component is separated from the second non-embedded component by a distance between about 2 microns (pm) and about 100 pm.

19. The assembly of claim 14, wherein a first heat spreader is disposed over the first non-embedded component, and wherein a second heat spreader is disposed under the second non-embedded component.

20. The assembly of claim 14, wherein the second non-embedded component is a graphics processing unit (GPU), a central processing unit (CPU), an accelerated processing unit (APU), a data processing unit (DPU), a neural processing unit (NPU), a microcontroller unit (MCU), a digital signal processor (DSP), a tensor processing unit (TPU), or an application-specific integrated circuit (ASIC).

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