Automated 3D semantic segmentation of PCB x-ray CT images

Abstract

A method is provided for analyzing printed circuit boards (RGBs), microelectronic components, or other electronic components that involves acquiring 3D images, performing semantic segmentation to identify metal content, and post-processing the segmented data for netlist extraction. The system may employ an X-ray computed tomography (CT) scanner and a 3D U-Net architecture with a ResNet-18 backbone.

Description

25-055 (098121-00431)AUTOMATED 3D SEMANTIC SEGMENTATION OF PCB X-RAY CT IMAGESBACKGROUND

[0001] The invention disclosed herein relates to development tools, and in particular to design reconstruction of printed circuit boards, microelectronic components, and other electronic devices.

[0002] Printed Circuit Board (PCB) design reconstruction is essential for addressing part obsolescence, intellectual property recovery, compliance, quality assurance, and enhancing national capabilities. Traditional methods for PCB design extraction, both non-geometry-based and geometry-based, have limitations in accuracy, efficiency, and scalability.

[0003] Accordingly, what is needed is a system and method of reconstructing PCB's, microelectronic components, and other electronic devices having the features described herein.SUMMARY

[0004] According to one aspect of the disclosure, a method may include acquiring 3D images of an electronic device, segmenting the metal content from the 3D images, performing semantic segmentation of the junctions within the metal content, and post-processing the semantic segmentation of the junctions to extract netlists.

[0005] According to another aspect of the disclosure, a system for analyzing printed circuit boards (PCBs) may include an imaging device configured to acquire a plurality of 3D images of the PCBs, a processing unit configured to perform semantic segmentation on the acquired 3D images to identify metal content within the PCBs, and a post-processing module configured to process the segmented data to form a netlist representing the PCB's electrical connections.

[0006] According to another aspect of the disclosure, a non-transitory computer-readable medium may store instructions that, when executed by a processor, cause the processor to perform a method for analyzing PCBs, comprising acquiring a plurality of 3D images of the PCBs, performing semantic segmentation on the acquired 3D images to identify metal traces and junctions, and post-processing the segmented data to facilitate netlist extraction.1 MEl\59677957.vl25-055 (098121-00431)

[0007] These and other advantages and features will become more apparent from the following description taken in conjunction with the drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The subject matter, which is regarded as the disclosure, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features, and advantages of the disclosure are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

[0009] FIG. 1 is a block diagram illustrating the a process for reverse engineering printed circuit boards (PCB) according to an embodiment;

[0010] FIG. 2A - FIG. 2D are illustrations of 2D slices of X-Ray CT scan images from a PCB according to an embodiment;

[0011] FIG. 3A and FIG. 3B are illustrations of extracted metal content from the CT images according to an embodiment;

[0012] FIG. 4 are schematic illustrations showing the difference between straight and serpentine traces according to an embodiment;

[0013] FIG. 5A - FIG. 5F illustrate examples of synthetic samples generated to include a junction mask that is used as a label in a dataset for training a deep learning network;

[0014] FIG. 6 is a schematic illustration showing the first few steps of a layer placement procedure according to an embodiment;

[0015] FIG. 7A - and FIG. 7B are schematic illustrations showing a synthetic 3D PCB according to an embodiment;

[0016] FIG. 7C and FIG. 7D are schematic illustrations showing a corresponding junction mask for the synthetic 3D PCB of FIG. 7A and FIG. 7B respectively;

[0017] FIG. 8 is a schematic representation of dissections (64 x 128 x 128) with a stride of (16 x 32 x 32), equivalent to a 25% overlap according to an embodiment;2 MEl\59677957.vl25-055 (098121-00431)

[0018] FIG. 9A and FIG. 9B shows the predicted and post-processed junction mask of the commercial PCB of FIG 2A, from two different views;

[0019] FIG. 10A - FIG. 10B show the detected nets of the partially imaged commercial PCB in different colors as well as the detected junctions with their identifiers according to an embodiment;

[0020] FIG. 11A - 11H illustrate segmentation visualizations of a case study according to an embodiment;

[0021] FIG. 12 illustrates a 2-layer PCB mounted for imaging according to an embodiment;

[0022] FIG. 13A - FIG. 13B illustrate 2D slices of CT scan images of the PCB of FIG. 12;

[0023] FIG. 14A - FIG. 14B illustrate 3D segmented metal content and segmented junctions of the PCB of FIG. 12;

[0024] FIG. 15 illustrates nets and named junctions of the designed PCB according to an embodiment;

[0025] FIG. 16A - FIG. 16B illustrate two slices of the bent synthetic content and the corresponding junction labels according to an embodiment;

[0026] FIG. 17A - FIG. 17D illustrate 3D segmented metal content and the corresponding segmented junctions of the bent PCB of FIG. 12; and

[0027] FIG. 18A - FIG. 18C illustrate nets and named junctions of the bent PCB of FIG. 12.

[0028] The detailed description explains embodiments of the disclosure, together with advantages and features, by way of example with reference to the drawings.DETAILED DESCRIPTION

[0029] Disclosed herein are methods and apparatus for automated evaluations of printed circuit boards (PCB). The techniques combine image processing and machine learning to achieve three-dimensional (3D) semantic segmentation of PCB X-ray Computed Tomography (X-ray CT) images and subsequent netlist extraction. By employing a 3D U-Net architecture with a ResNet-18 backbone and training on synthetic data, techniques for direct 3D semantic segmentation significantly improving over prior art have been developed. The techniques eliminate the need for extensive labeled datasets by using inherently labeled synthetic data. The technology enhances ease of segmentation by significantly reducing or eliminating 3 MEl\59677957.vl25-055 (098121-00431)preprocessing efforts required for 2D image stacks. The technology also improves universality by expanding the scope of application beyond images with specific 2D stack criteria, segmenting the 3D image in its entirety. Additionally, embodiments enable the processing of images of PCBs that have undergone bending, which is common among PCBs with a thickness below a certain threshold. Implications of the technology extend beyond PCBs, finding applications in various physical and biological sciences where 3D image segmentation is desired. Embodiments include high-resolution 3D imaging, watershed segmentation, machine learning-based semantic segmentation, and netlist extraction. Validation with both synthetic and real-world PCB datasets shows high accuracy and robustness, offering a scalable solution for PCB design reconstruction.

[0030] It should be appreciated that while embodiments herein describe the method and system with respect to the analyzing of printed circuit boards, this is for example purposes and the claims should not be so limited. In other embodiments, the method and system may be used to analyze and reverse engineer other microelectronic devices and non-microelectronic devices without deviating from the teachings provided herein.

[0031] As a result, described herein is an automated method for reconstructing printed circuit board (PCB) designs using advanced 3D image analysis of X-ray CT scans. By combining image processing with machine learning, the technology overcomes limitations of traditional methods, such as the need for extensive labeled data and challenges in handling distorted PCBs. This enhances the efficiency and accuracy of PCB design recovery, crucial for managing part obsolescence and intellectual property recovery, and also extends to various fields requiring precise 3D image segmentation, including biological sciences. The technology represents a significant advancement in automated design reconstruction, offering robust and scalable solutions to industry challenges.

[0032] Generally, "reverse engineering" of Printed Circuit Boards (PCB) is the process of analyzing and reconstructing the design of an existing PCB. Reverse engineering is a desired tool for those interested in part obsolescence, intellectual property recovery, compliance and quality assurance, and enhancing national capabilities, among other things.

[0033] With regard to part obsolescence, when original design files are lost, or components become obsolete, reverse engineering helps in recreating the PCB layout and generating a netlist, which is a detailed list of the electronic components and their interconnections, to support continued production and maintenance. The backlog of parts, devices, and machines due to obsolete PCBs is a significant issue,4 MEl\59677957.vl25-055 (098121-00431)particularly in highly regulated industries like medical devices and automotive manufacturing. In the medical device industry, component obsolescence can cause serious delays and financial losses. For example, the sudden discontinuation of components can halt production and involve extensive regulatory approval for replacement devices, leading to months of downtime for devices waiting on critical parts. In the automotive sector, supply chain disruptions have similarly led to considerable backlogs. Jaguar Land Rover (JLR) reported a backlog affecting up to 10,000 cars at its peak due to parts shortages, including those related to obsolete PCBs. While improvements have been made, the backlog still numbers in the thousands. The PCB market, which supports a wide range of industries from consumer electronics to defense, faces constant challenges due to the rapid pace of technological advancements and obsolescence. According to Market Data Forecast, the market size is projected to grow from USD 76.12 billion in 2024 to USD 93.87 billion by 2029, indicating the scale at which obsolescence and supply chain issues could impact production across various sectors.

[0034] With regard to Intellectual Property (IP), in some cases, reverse engineering helps in recovering the intellectual property (IP) when the original design data is no longer available, ensuring that the design can be reused or modified. This differs from obsolescence management in that parts or devices may not be obsolete, but the IP is still lost.

[0035] With regard to Compliance and Quality Assurance, ensuring that a product complies with industry standards and regulations sometimes requires reverse engineering to verify the design and implementation. Additionally, the "build" must sometimes be compared against the "designed" specifications through a verification and validation process to ensure the fabrication process is reliable and that the parts are indeed the ones that were ordered.

[0036] With regard to enhancing national capabilities, and to improve national capabilities, the designs of other offshore manufactured components may need to be reverse engineered to be understood and potentially replicated or enhanced.

[0037] Turning to current methods and their challenges, it has been found that reverse engineering methods for PCBs can be broadly categorized into two types based on their approach: non-geometry-based methods that rely on functional testing, and geometry-based methods that utilize visual and imaging techniques.5 MEl\59677957.vl25-055 (098121-00431)

[0038] Category 1: Non-Geometry-Based Methods through Electrical Testing. These methods focus on assessing the functionality of the PCB without extracting the physical layout of traces and junctions: (1) Continuity Testing: This method uses a multimeter to test the continuity of traces and connections. By verifying the electrical pathways, continuity testing helps in creating a netlist, which is a representation of the electrical connectivity of the PCB. In terms of the drawbacks and Limitations, continuity testing is limited to simple PCBs and can be time-consuming for complex boards. It does not provide detailed physical layout information, making it insufficient for comprehensive reverse engineering; (2) In-Circuit Testing (ICT): Specialized equipment is used to test the functionality of the PCB while it remains assembled. ICT provides insights into the circuit's operation and helps identify hidden connections, ensuring that the PCB performs as intended. In terms of drawbacks and limitations, ICT may not detect all faults, particularly those related to intermittent issues or subtle component defects.

[0039] Category 2: Geometry-Based Methods through Imaging and Visualization. These methods involve extracting the physical layout of the PCB through imaging techniques, followed by an analysis step to reconstruct the PCB's design.

[0040] Step 1: Imaging: When inspecting and analyzing PCBs, different techniques are employed depending on whether the board is single-layer or multi-layer: (1) Single-Layer PCBs: For PCBs with only one layer, visual inspection and manual tracing can be employed. Alternatively, using a camera or scanner can capture the desired details. Drawbacks and Limitations: Manual tracing is labor-intensive and prone to human error. Conventional approaches of automated imaging can miss fine details; (2) Multi-Layer PCBs: For PCBs with multiple layers, imaging buried layers is crucial. Two main methods are used: (a) Destructive Methods: This involves consecutive delayering and imaging of the PCB. Methods for delayering include: (al) Chemical Stripping: Using chemicals to remove layers. Drawbacks and Limitations: Chemical stripping can damage sensitive components and requires careful handling of hazardous substances; (a2) Mechanical Stripping: Grinding or milling away layers. Drawbacks and Limitations: Mechanical stripping can introduce physical distortions and inaccuracies; (a3) Focused Ion Beam (FIB): Precision removal using ion beams. Drawbacks and Limitations: FIB is limited to small areas, making it impractical for large-scale analysis; (a4) Laser Ablation: Using lasers to remove layers. Drawbacks and Limitations: Laser ablation requires fine tuning of the recipe parameters which may in turn need significant experimentation. Imaging techniques for these methods include optical microscopy, confocal microscopy, and scanning electron microscopy (SEM); (b) Non-Destructive Methods: X-ray Computed Tomography (X-ray CT) is commonly used for non-destructive imaging, which is useful6 MEl\59677957.vl25-055 (098121-00431)when only a single instance of the board exists and needs to remain functional after analysis. Drawbacks and Limitations: X-ray CT may require fine-tuning of the imaging parameters, which can necessitate optimization efforts. Additionally, the image quality and level of detail that can be extracted can be affected by artifacts such as beam hardening.

[0041] Step 2: Analysis. Once images are acquired, they are analyzed to reconstruct the PCB's design. Various methods include: (1) Manual Analysis: The traditional method involving human inspection and interpretation of images. Drawbacks and Limitations: It is labor-intensive, time-consuming, and prone to human error; (2) Conventional Image Processing: Utilizing algorithms to process and analyze images. Drawbacks and Limitations: This method requires fine-tuning for specific cases, limiting its universality; (3) Machine Learning: Employing machine learning algorithms for image semantic segmentation, which involves classifying each pixel in an image into a predefined category, and image analysis. Drawbacks and Limitations: The effectiveness of this approach depends on the availability of large, annotated datasets, which are expensive to generate; (4) Hybrid Approaches: Combining image processing with machine learning can leverage the strengths of both methods. Drawbacks and Limitations: Hybrid approaches still face challenges related to data availability and the integration of different methodologies.

[0042] An additional challenge of the existing methods is that they are based on segmenting 2D image slices from a 3D volume, rather than segmenting the 3D volume itself. This approach faces challenges such as aligning the plane of images with the PCB layers and addressing distortions in the PCB shape. By treating images as 3D volumes, as provided herein, these issues can be mitigated.

[0043] PCB image segmentation presents challenges due to the complex geometry and physical distortions of PCBs. Traditional methods segment 2D slices from a 3D reconstructed volume and then stack the 2D slices, which introduces challenges when the image slices are not parallel to PCB layers-a common occurrence in image acquisition and reconstruction. This misalignment often requires substantial manual correction. Additionally, bent PCB layers cannot be effectively captured in 2D slices, leading to further inaccuracies. To address these limitations, we propose the first method for direct 3D semantic segmentation, which eliminates the need for slice alignment and ensures robustness against bending or distortions in PCB layers. Furthermore, deep machine learning-based segmentation methods typically involve large, labeled datasets, which are costly and time-intensive to produce.7 MEl\59677957.vl25-055 (098121-00431)

[0044] Accordingly, embodiments provided herein describe a method for automated semantic segmentation of PCB X-ray CT images and extraction of netlist information by combining image processing and machine learning algorithms and using synthetic data for training is presented.

[0045] Innovations of the technology disclosed herein include: 3D Volume Semantic Segmentation: Unlike traditional slice-by-slice methods, the technique segments directly in 3D, preserving spatial context and effectively handling bent PCBs, which are challenging for 2D methods. Synthetic Data Generation: generates labeled synthetic data for training, eliminating the need for costly and time-consuming real-world data acquisition and annotation. Combined Image Processing and Machine Learning: among other things, the techniques disclosed integrate image processing for initial segmentation with machine learning for semantic segmentation, leveraging the strengths of both techniques.

[0046] Fully Automated Procedure: In an embodiment, this may be a fully and entirely automated process, reducing manual effort and ensuring robust, scalable PCB design reconstruction.

[0047] Unlike other domains such as medical imaging, PCB segmentation involves unique challenges, including complex multi-layered structures, thin high-contrast features such as traces and vias, bending or misalignment during imaging, and the need to preserve precise connectivity information for netlist extraction. This method is the first automated approach utilizing a 3D U-Net architecture specifically configured for reverse engineering PCBs, addressing these challenges through a combination of

[0048] Generally, the process of the solution involves: Image Acquisition: The process begins with acquiring high-resolution 3D images of PCBs using a CT scan system. The raw 2D projection data from the CT scan is reconstructed into 3D volumetric images, providing detailed views of the PCB's internal structure. This is followed by Pre-Processing: Pre-processing techniques, including noise reduction and contrast enhancement, are applied to improve image quality. This is followed by Copper Content Isolation. To isolate the metal content, a watershed segmentation algorithm is used. This step ensures accurate identification of traces and junctions within the PCB. This is followed by 3D Semantic Segmentation: For semantic segmentation, a 3D U-Net architecture is employed with a pretrained ResNet-18 backbone.

[0049] Some embodiments herein provide for a U-Net architecture configured for three-dimensional semantic segmentation tasks. The U-Net architecture comprises an encoder-decoder structure with skip connections facilitating high-resolution output. The encoder section utilizes multiple convolutional blocks8 MEl\59677957.vl25-055 (098121-00431)to progressively down-sample the input image, extracting hierarchical features. Each convolutional block may include a sequence of 3D convolutional layers, followed by activation layers such as Rectified Linear Units (ReLU) and max-pooling operations. This architecture may integrate a ResNet-18 backbone to enhance feature extraction through residual learning, potentially initialized using pretrained weights to leverage transfer learning.

[0050] The decoder section includes mirror convolutional blocks to the encoder, employing up-sampling mechanisms to achieve dimensionality restoration, thereby reconstructing the spatial resolution of the original input. Skip connections between corresponding encoder and decoder layers allow for feature map concatenation, enhancing the model's ability to learn fine details by combining coarse, high-level information from deeper layers with fine, low-level details from earlier layers.

[0051] The architecture utilizes 3D convolutions to manage volumetric data, accommodating tasks requiring direct 3D image processing, which enhances segmentation accuracy for complex structures such as multilayered PCBs. An optimization process may be conducted using an Adam optimizer with a combined dice and focal loss function to address class imbalance and improve segmentation precision.

[0052] The training process involves data augmentation techniques to increase the diversity of training samples, thereby improving the generalization capability of the U-Net model. The architecture is designed for scalability and adaptability across various datasets, thus providing a robust solution for applications demanding high-resolution feature delineation in volumetric imaging contexts.

[0053] This network is trained using synthetic data, which simulates the variability and complexity of real-world PCBs. This is followed by Model Optimization: The machine learning model is optimized using the Adam optimizer, with a combined dice and focal loss function to handle class imbalance and improve segmentation accuracy. This is followed by Validation: Validation is conducted on both synthetic and real-world datasets, achieving high performance metrics. This is followed by Post-Processing: In the post-processing phase, the segmentation results are refined through overlapping dissection to ensure accurate boundary predictions, followed by voxel assignment and binary mask conversion. Additional operations, such as binary closing and small object removal, further enhance the segmentation quality. This is followed by Netlist Extraction: Finally, netlists are extracted from the semantically segmented images through automated identification of connectivity between junctions. Junctions and nets are assigned unique identifiers, and the connectivity is analyzed to construct a pseudo-netlist, which is validated through comparison with known designs.9 MEl\59677957.vl25-055 (098121-00431)

[0054] As used herein, an Adam optimizer is a stochastic optimization method that utilizes adaptive learning rates for different parameters. It combines the advantages of two other extensions of stochastic gradient descent: Adaptive Gradient Algorithm (AdaGrad) and Root Mean Square Propagation (RMSProp). Adam computes individual adaptive learning rates for each parameter from estimates of first and second moments of the gradients, using moving averages of the gradients and the squared gradients. The method is computationally efficient and requires little memory. It is widely used for training deep learning models due to its ability to handle sparse gradients and non-stationary objectives.

[0055] By offering a less expensive, less time-consuming, and more universal method for PCB design reconstruction, the embodiments herein mitigate issues related to part obsolescence, intellectual property recovery, and compliance. Additionally, this technique has broader applications in various physical and biological sciences where 3D image segmentation is desired.

[0056] Demonstration and Validation Examples. The methods have been demonstrated using a commercial 3-layer PCB. This PCB served as a practical example, illustrating each step of the reverse engineering process. For the Validation and Case Studies section, a fully manufactured 2-layer PCB was used to evaluate the effectiveness and accuracy of the method. This approach provided for verification of results against known ground truth data and assess the robustness of the techniques in practical applications.

[0057] The process of automating the reverse engineering of PCBs includes acquiring high-resolution 3D images of PCBs, segmenting the metal content, performing semantic segmentation of the junctions within the metal content, and post-processing the results to extract netlists. This process is schematically demonstrated in FIG. 1. Throughout this section, commercial 3-layer PCB was used to demonstrate each step of the techniques, providing a practical and detailed example of approaches taken. FIG. 1 sets forth an example of process flow for the PCB design reconstruction solution disclosed herein.

[0058] In the example of FIG. 1, the first step involves acquiring high-resolution 3D images of PCBs using an X-ray CT system. In one example, a Zeiss Xradia 520 Versa X-ray was used for acquiring these images. For PCBs with large length-width ratios, the length direction may not penetrate fully, or the short side may experience overexposure. To mitigate these issues, a method is employed to adjust the number of exposures at different rotation angles of the sample. This approach helps to balance the trade-offs in penetration and exposure, enabling the acquisition of usable volumetric data for subsequent analysis. This provides for an automated methodology for the semantic segmentation of PCB images. A key strength of 10 MEl\59677957.vl25-055 (098121-00431)the technique is its robustness and generalizability, as the method works effectively regardless of the imaging modality used. By validating this approach with CT images, which are often more challenging due to artifacts and limitations, the versatility of the techniques may be seen. Furthermore, it has been found that the methods perform even better with alternative imaging techniques, such as computed laminography (CL), which is better suited for scanning large PCBs. This flexibility ensures that a wide range of imaging conditions and technologies can be accommodated.

[0059] X-ray Imaging Parameters. The X-ray CT imaging machine may be configured with optimal or desired settings to balance resolution, scan time, and field of view. Parameters such as voltage, current, exposure time, voxel size, filter type, rotational speed, number of projections, and reconstruction algorithm are adjusted to ensure high-quality images while capturing the entire region of interest in the obtained images.

[0060] Image Reconstruction. The raw 2D projection data from the X-ray CT scan are reconstructed into 3D volumetric images using software, such as Reconstructor Scout-and-Scan(tm) software (version 14.0) provided by Zeiss for example. The resulting images provide a detailed view of the PCB's internal structure, including metal traces, vias, and junctions within the glass fiber material of the PCB.

[0061] FIG. 2A - FIG. 2D depicts 2D slices of X-ray CT scan images from a commercial PCB. The pixel size is 14.12 pm. The image size is 1074 x 1074 pixels. The field of view is approximately 15.16 mm x 15.16 mm.

[0062] Metal Content Segmentation. Watershed Segmentation. To isolate the metal content from the rest of the PCB materials, a watershed segmentation algorithm was applied. A watershed segmentation algorithm is a method utilized to partition an image into different regions based on the topology of its intensity values. It treats the image as a topographic surface, where each pixel's intensity corresponds to a height. The algorithm begins by identifying markers known as seeds, which serve as initial points for region growth. From these seeds, the algorithm simulates water flooding the surface, filling catchment basins until it reaches boundaries defined by higher intensity values. This process continues until the entire image is segmented into distinct regions, effectively delineating areas of interest. This method was chosen for its robustness in handling varying intensities and noise in the CT images.

[0063] While embodiments herein use the watershed segmentation algorithm, other algorithms may include, but are not limited to: K-means Clustering; Mean Shift; Graph Cut; Active Contour Models11 MEl\59677957.vl25-055 (098121-00431)(Snakes); Random Walker; Thresholding Methods; Region Growing; Level Set Method; Fuzzy C-Means Clustering; and Conditional Random Fields (CRF) for example.

[0064] Pre-processing. The 3D CT images were pre-processed to enhance their quality. This involves applying Gaussian smoothing to reduce noise and improve the clarity of the metal regions, facilitating more accurate segmentation.

[0065] Seed Generation. Seeds for the watershed algorithm are placed at the lower and upper percentiles of intensity values corresponding to specific glass fiber and metal content. The lower percentile seeds identify starting points within the glass fiber regions, while the upper percentile seeds ensure the inclusion of metal areas.

[0066] Watershed Algorithm. The watershed algorithm treats the image as a topographic surface, where the intensity values represent the height. Starting from the seeds, the algorithm floods the regions to segment the metal content from the rest of the PCB. The process begins by identifying these markers, known as seeds, which serve as the initial points for region growth. The algorithm then simulates water flooding from these seeds, filling up catchment basins and delineating boundaries where different regions meet. This flooding continues until the entire image is segmented, effectively isolating the metal regions. This step produces a binary mask of the metal regions, allowing for precise segmentation despite varying intensities and noise present in the CT images.

[0067] FIG. 3A and FIG. 3B show the extracted metal content from the CT images of the commercial PCB presented in FIG. 2A - FIG. 2D.

[0068] Junction Semantic Segmentation. Segmentation Using Neural Networks. A 3D U-Net architecture was employed with a pretrained ResNet-18 backbone for the task of semantic segmentation of junctions in the extracted metal content. The U-Net architecture is chosen for its effectiveness in image segmentation tasks, while the pretrained ResNet-18 backbone enhances feature extraction capabilities while leveraging the training on ImageNet.

[0069] A ResNet-18 backbone is an architecture used in deep learning models, particularly for image processing tasks such as feature extraction and classification. It consists of 18 layers, including both convolutional and identity layers, which organize the flow of data through the network.

[0070] Key characteristics of the ResNet-18 backbone include:12 MEl\59677957.vl25-055 (098121-00431)

[0071] Residual Learning Framework: Utilizes skip connections or shortcuts that bypass one or more layers, allowing gradients to flow through the network without vanishing, which helps in training deeper networks effectively. Convolutional Layers: The architecture is composed of basic building blocks consisting of convolutional layers followed by batch normalization and ReLU activation functions. These blocks perform transformations that extract hierarchical features from the input data. Identity Blocks: In these blocks, the input is added to the output of the convolutional layers, enabling the model to learn residual mappings instead of direct mappings, which enhances the ability to optimize the network. Downsampling: The network includes downsampling layers, specifically through strided convolutions, reducing the spatial dimensions of the input, allowing for the extraction of features at multiple scales. BottleNeck and Identity Layers Configuration: The layers are configured to allow both bottleneck and identity operations, permitting efficient parameter usage and model training stability.

[0072] This architecture serves as a robust feature extractor, often used as the foundational part of more complex models like U-Net for segmenting volumetric data in applications such as the semantic segmentation of PCB images.

[0073] U-Net Structure. The U-Net consists of an encoder-decoder structure with skip connections. The encoder progressively down-samples the input, extracting hierarchical features, while the decoder upsamples the features to the original resolution. The 3D U-Net extends this architecture into the third dimension, employing 3D convolutions and 3D max-pooling layers to capture volumetric spatial context.

[0074] ResNet-18 Backbone. The ResNet-18 backbone is integrated into the encoder to leverage its deep residual learning capabilities. This addition improves the model's ability to capture intricate details in the input data.

[0075] Transfer Learning. The pretrained 3D U-Net leverages transfer learning by initializing its weights from a 2D network trained on the large ImageNet dataset. This initialization helps in capturing low-level features effectively, which are then fine-tuned for the specific 3D segmentation task. The transfer learning approach reduces training time and improves model accuracy by utilizing the pretrained weights, allowing the network to adapt to the nuances of 3D data with a robust starting point.

[0076] As used herein, the term "ImageNet" refers to the ImageNet project, which is a large visual database designed for use in visual object recognition software research. More than 14 million images13 MEl\59677957.vl25-055 (098121-00431)have been hand-annotated by the project to indicate what objects are pictured and in at least one million of the images, bounding boxes are also provided.

[0077] Synthetic Data Generation. Creating a diverse and comprehensive dataset is essential for training our deep learning model for semantic segmentation of junctions from the 3D metal content. For this purpose, in some examples, synthetic datasets are created for semantic segmentation of PCB 2D images and adapted for the generation of a 3D synthetic dataset. The synthetic dataset simulates the variability and complexity of real-world PCBs.

[0078] 2D Synthetic Image Creation. To generate synthetic 3D PCB images, first 2D synthetic images are created with corresponding junction masks representing single-layer PCBs and the locations of the junctions.

[0079] Canvas Setup. A blank canvas of size 1536 x 1536 pixels is initialized. This size was chosen to provide ample space for complex trace patterns while allowing for cropping to the desired final size of 1024 x 1024 (Note that 1536 = 256 + 1024 + 256).

[0080] Junction Placement. A random number of junctions (10 ? n ? 20) are placed on the canvas. The junctions are represented as disks with random diameters, ensuring variability in the junction sizes.

[0081] Trace Generation. A random number (m) of traces are drawn to connect pairs of junctions. The number m is chosen to be up to 25% of the possible connections (nx(n+l) / 8). This ratio ensures a balanced number of connections without overwhelming the canvas. The traces are either regular traces (with 90% probability) or serpentine traces (with 10% probability), a ratio chosen to reflect the typical prevalence of straight connections in PCB designs while still including a reasonable number of serpentine traces to account for design variations. The shape-defining parameters for these traces are chosen randomly, as described in definitions below:

[0082] Regular Traces: These are the linear paths of random width used to connect various components on a PCB. These often need to change direction to connect different components or navigate around obstacles. Therefore, each regular trace is divided into segments, with a random number of bends or breaks (0 to 4). This variability allows the traces to adapt to the layout's complexity and mimic real-world PCB designs.14 MEl\59677957.vl25-055 (098121-00431)

[0083] Serpentine Traces: These traces are designed with intentional loops or meanders to match the length of other traces or introduce delays. Serpentine traces are generated with a random number of peaks (1 to 10) and peak values (1 to 100 pixels) with random width. This design choice reflects the need for precise timing adjustments in PCB layouts, where serpentine traces are used to manage signal timing and integrity.

[0084] FIG. 4 schematically shows the difference between straight and serpentine traces.

[0085] Cropping. The resulting 1536 x 1536 images and junction masks are cropped to 1024 x 1024 pixels. This is to have more realistic inputs for training the deep learning model as often the CT images may not cover the whole PCB or usually the size of the CT image is larger than the input size of the trained model.

[0086] Junction Mask. As the PCB images are synthetically generated using known parameters, each image automatically includes its junction mask to be used as a label in the dataset for training the deep learning network. FIG. 5A, FIG. 5C, and FIG. 5E shows examples of synthetic samples generated in this manner. FIG. 5B, FIG. 5D, and FIG. 5F illustrate the respective corresponding junction masks. Note that although these synthetic PCB layouts may differ significantly from real-world examples due to the random placement of junctions and creation of traces, they effectively serve the purpose of training the machine learning algorithm for semantically segmenting PCB images. The value of these generated scenarios lies in their ability to cover a wide diversity of possible PCB layouts, thereby enhancing the algorithm's robustness and generalization capabilities.

[0087] 3D Image Assembly. The next step involves assembling the 2D images into 3D synthetic PCB images.

[0088] Layer Placement. In one example, the goal of layer placement is to construct a synthetic 3D PCB image by systematically integrating multiple 2D PCB layers into a 3D volumetric space, ensuring realistic layer distribution and thickness variability. The 3D synthetic PCB assembly is performed as follows.

[0089] Initialization: starts with a blank 3D volumetric space of dimensions 128 x 1024 x 1024 voxels. This space represents the 3D structure of the PCB, where each slice corresponds to a layer in the z-dimension (depth).15 MEl\59677957.vl25-055 (098121-00431)

[0090] 2D Synthetic PCB Images: Prior to the 3D construction, we generate multiple 2D synthetic PCB images, each of size 1024 x 1024 pixels. These images represent single layers of the PCB, with randomly placed junctions and traces as described earlier.

[0091] Random Placement of Layers: To simulate the realistic distribution of PCB layers, 2D synthetic PCB images are placed approximately ten slices apart within the 128-slice volume. This spacing ensures that the layers are not too densely packed, mimicking the actual structure of multilayer PCBs. The exact placement of each 2D layer within the 128 slices is randomized. For instance, a 2D layer could be placed at slices 1, 11, 21, etc., but the exact starting slice is determined randomly within a range to introduce variability. This prevents a uniform pattern and adds to the realism of the synthetic 3D image.

[0092] Layer Thickness Variation: Each 2D PCB layer is assigned a random thickness between 2 to 4 slices. This thickness variation is essential to emulate the non-uniformity observed in real PCBs where different layers may have different thicknesses. If a layer is assigned a thickness of 3 slices, for example, the same 2D synthetic PCB image is repeated over three consecutive slices in the z-dimension. This repetition maintains the continuity of the layer across the assigned thickness.

[0093] Filling the Volume: The process of placing 2D layers, separated by approximately 10 slices and with random thicknesses, is repeated iteratively until the entire 128-slice volume is filled. This approach ensures that the 3D synthetic PCB image is fully populated with layers distributed throughout the volume. FIG. 6 schematically shows the first few steps of the layer placement procedure.

[0094] It should be noted that the layer placement method described here is solely for the purpose of generating synthetic 3D PCB images and does not apply to the processing or correction of stacking traces in real 3D reconstructed images.

[0095] Random 3D Rotation. The CT images of multilayer PCBs do not necessarily have layers parallel to the surface plane of the PCB sample, as manual mounting can introduce an angle. Therefore, after creating the 3D PCB of size 128 x 1024 x 1024 voxels, the entire volume is randomly rotated around the x, y, and z axes to simulate different poses that the PCB can take when mounted for imaging in the X-ray CT machine or the different ways that the 2D slices are generated from a 3D volumetric X-ray CT image.16 MEl\59677957.vl25-055 (098121-00431)

[0096] FIG. 7A and FIG. 7B show a synthetic 3D PCB sample and its corresponding junction mask (FIG.7C and FIG. 7D respectively), from two views. In an embodiment, these were created with Python 3.8 software code.

[0097] Dissection for Training. Due to the memory constraints of GPU, the input size of the 3D deep learning model is much smaller than 128 x 1024 x 1024 of the synthetic images. Therefore, to train the deep learning model, the 3D synthetic image volume and its corresponding mask volume are dissected into smaller sub-volumes.

[0098] Dissection Parameters. Each 3D image and its corresponding mask are dissected into subvolumes of size 64 x 128 x 128 voxels with a stride of 32 x 64 x 64 voxels. This overlapping dissection is not necessary during the training phase but is essential during the prediction phase to ensure that boundary regions are properly represented in at least one volume.

[0099] Final Dataset. 250 whole synthetic 3D PCBs images and masks are created. With the dissection and the stride size described above, each whole 3D image and its corresponding mask are dissected into (1 + (128 - 64) / 32) x (1 + (1024 - 128) / 64) x (1 + (1024 - 128) / 64) = 675 sub-images for training the deep learning network. Therefore, the dataset has a total of 168750 samples.

[0100] Note that while reducing the reliance on large datasets is a common trend in deep learning, sufficient and diverse training data remain desired for properly training a model. Generating synthetic data addresses the challenges of collecting real-world data for PCBs, which is prohibitively expensive due to the labor and machine time required for X-ray CT imaging. Each scan can take several hours, and obtaining thousands of images would significantly impact resources. Moreover, changes in imaging conditions, such as resolution or beam intensity, would involve collecting entirely new datasets. Synthetic data generation allows these limitations to be overcome by simulating diverse PCB scenarios, including variations in layer configurations, physical distortions (e.g., bent layers), and noise. This approach ensures scalability, adaptability, and robust training of the segmentation network.

[0101] Training Procedure. The 3D U-Net model with pretrained ResNet-18 backbone is trained on the generated synthetic dataset using the following procedure.

[0102] Optimizer and Learning Rate. The Adam optimizer is used with a learning rate of 0.0001. Adam is chosen for its adaptive learning rate properties, which help in achieving faster convergence.17 MEl\59677957.vl25-055 (098121-00431)

[0103] Loss Function. A combined dice and focal loss function is employed to enhance model performance in handling class imbalance and improving segmentation accuracy. The dice loss component addresses class imbalance (metal content versus background) by focusing on maximizing the overlap between the predicted segmentation and the ground truth, which is particularly useful for small classes (content here). The focal loss component mitigates the impact of easy negatives (the background or nontarget class) by down-weighting their contribution.

[0104] The Dice and Focal Loss functions are designed to improve the performance of neural networks in handling imbalanced data and enhancing segmentation accuracy in image processing tasks.

[0105] Dice Loss Function

[0106] The Dice loss function is particularly useful for segmentation tasks as it maximizes the overlap between the predicted segmentation and the ground truth. The Dice coefficient is a measure of how similar two sets are. The Focal loss function addresses class imbalance by focusing more on hard-to-classify examples, reducing loss contribution for well-classified examples. A combined loss function integrates both Dice and Focal Loss to handle both segmentation accuracy and class imbalance effectively.

[0107] Training Schedule. In one example, the model is trained for 25 epochs. Each epoch involves a full passthrough the training dataset, adjusting the model parameters to reduce or minimize the loss function.

[0108] Validation and Testing. The dataset is split into training (70%), validation (10%), and test (20%) sets. The model is selected based on validation loss, and its performance is evaluated on the test set. In an example, the model achieved a test Intersection over Union (loU) score of 0.9749 and an Fl score of 0.9868 at a threshold of 0.5.

[0109] Prediction and Post-Processing. During the prediction phase, the input 3D images are dissected into sub-volumes for processing by the trained model.

[0110] Overlapping Dissection. To ensure accurate predictions at the boundaries, the input image is dissected with a 1 / 4 overlap, resulting in sub-volumes of size 64 x 128 x 128 voxels with a stride of 16 x 32 x 32 voxels. This overlapping strategy mitigates boundary artifacts. (FIG. 8).

[0111] FIG. 8 provides a schematic representation of dissections (64 x 128 x 128) with a stride of (16 x 32 x 32), equivalent to a 25% overlap.18 MEl\59677957.vl25-055 (098121-00431)

[0112] Voxel Assignment. For voxels in the overlapping regions, the mean of the predictions from all overlapping sub-volumes is assigned. This averaging approach improves the accuracy of predictions for voxels at the boundaries of the sub-volumes.

[0113] Binary Mask Conversion. The output of the model is a softmax probability map, indicating the confidence of each voxel belonging to a metal trace or junction. A softmax probability map is an output of a neural network layer where each voxel's value represents the probability of belonging to a specific class, based on the softmax function. This function normalizes the raw output scores, converting them into a probability distribution over possible classes. The resulting map effectively highlights the confidence level for each voxel's classification, enabling segmentation decisions by identifying areas with higher probabilities for certain features or elements within the data.

[0114] Thresholding. In an example, a predefined threshold of 0.35 is applied to convert the probability map into a binary mask. Voxels with probabilities above the threshold are classified as metal traces or junctions, while others are classified as background.

[0115] Post-Processing. The initial binary mask undergoes post-processing operations to refine the segmentation: Binary Closing: A box structuring element is used to perform binary closing, which involves dilation followed by erosion. This process fills small holes and connects nearby components in binary images. The size of the structuring element is chosen based on the typical size of gaps and noise in the segmented images.

[0116] Small Object Removal: Objects smaller than a predefined size threshold are removed from the binary mask. This step eliminates noise and small artifacts that do not correspond to actual metal junctions.

[0117] FIG. 9A and FIG. 9B show the predicted and post-processed junction mask of the commercial PCB of FIG 2A - FIG. 2D, from two different views.

[0118] Pseudo-Netlist Extraction. With the segmented 3D images identifying the junctions, we proceed to extract a pseudo-netlist that describes the connectivity between these junctions on the PCB. By assigning each junction to the pins of the components on the PCB, the complete netlist can be created. As used herein a netlist is a detailed representation of the electrical connectivity within a printed circuit board (PCB). It is a structured collection of information that includes a list of the electronic components19 MEl\59677957.vl25-055 (098121-00431)used in the circuit, alongside the nodes or junctions that interconnect these components. Specifically, it outlines how each component terminal is connected to others within the circuit, facilitating an understanding of the electronic network's functionality and design.

[0119] Junction Identifiers. Each identified junction in the predicted junction mask is assigned a unique name, such as JI, J2, etc. This is done by detecting connected regions within the extracted junction mask. In one embodiment, junctions that are close and connected are segmented as a single junction and thus receive a single identifier. Manual or automatic inspection of the complete board with attached materials can then be used to identify and assign the correct pins of the components to these junctions.

[0120] Net Identifiers. Separate connected regions within the metal content are labeled using connected component analysis. Each component is assigned a unique net identifier, for example, Netl, Net2, etc. Each segmented junction belongs to exactly one net.

[0121] Junction-Net Assignment. In the process of assigning junctions to their respective nets, each junction within the junction mask is linked to a specific net by analyzing which net's voxels are present within the junction. In other words, each net is a connected region consisting of junctions and traces. To find which net a junction belongs to, the intersection of the junction with all nets is examined. Each junction must be entirely contained within a single component, ensuring accurate assignment.

[0122] Pseudo-Netlist Generation. The connectivity between components or junctions of the PCB is determined by analyzing the net assigned to the labeled junctions. Each net is a group of interconnected junctions using traces. The pseudo-netlist is then constructed by listing each net and its associated junctions.

[0123] FIG. lOA and FIG. 10B show the detected nets of the partially imaged commercial PCB. In an embodiment, the detected nets are displayed in different colors as well as the detected junctions with their identifiers. This shows colored nets and named junctions of the partially imaged commercial PCB.

[0124] Validation and Case Studies. Three case studies are presented to validate this method. The approach is further validated using a custom-designed, fully manufactured 2-layer PCB, assessing the accuracy and reliability of the design reconstruction process. Additionally, the challenge of handling physically distorted PCBs is addressed by introducing a bent version of a 2-layer PCB. To address these20 MEl\59677957.vl25-055 (098121-00431)distortion scenarios, a new deep learning network was trained, demonstrating the robustness of our approach in dealing with real-world imperfections and deformations.

[0125] Commercial PCB. The first case study, involving a commercial PCB used to illustrate various aspects of the proposed approach, is summarized in FIG. 11A - 11H. In FIG. 11A- FIG. 11H a summary of case study 1, commercial PCB, is presented. Segmentation visualizations were created with Python 3.8 code. The first set of images (FIG. 11A - FIG. 11B) include slices from the X-ray CT image, the second set of images include segmented metal content (FIG. 11C - FIG. 11D). In the third grouping (FIG. HE - FIG.11F), semantically segmented junctions are shown and in the fourth set (FIG. 11G - FIG. 11H), an extracted netlist is shown.

[0126] Custom 2-Layer PCB. A custom 2-layer PCB (FIG. 12) was designed and imaged to further validate our approach. The known circuit design of this PCB provided a reliable reference for evaluating our reverse engineering method. The 2-layer PCB, manufactured with a known netlist, was scanned using a CT scanner. The segmentation and netlist extraction steps were then applied to the scanned images. (FIGS.13A to 15).

[0127] In FIG. 12, the designed 2-layer PCB mounted for imaging is shown. In FIG. 13A and FIG. 13B, 2D slices of CT scan images of the designed PCB. The pixel size is 57.81 micrometers. The image size is 1108 (W) x 1276 (H) pixels. The field of view is approximately 64.09 mm x 73.75 mm.

[0128] In FIG. 14A and FIG. 14B, 3D segmented metal content (FIG. 14A) and segmented junctions (FIG.14B) of the designed PCB (created with Python 3.8 code) are shown.

[0129] As presented in Table 1, the pseudo-netlist of the designed PCB was extracted using the proposed method. By comparing to the known design, the accuracy of the method was successfully assessed.TABLE 121 MEl\59677957.vl25-055 (098121-00431)

[0130] FIG. 15 provides colored nets and named junctions of the designed PCB, obtained from the proposed method, (created with Python 3.8 code).

[0131] Bent PCB Handling. Physical distortions, such as bending, can complicate the reverse engineering process since PCB layers may not remain within flat planes that correspond to slices from the 3D image. To address this challenge, a dataset of bent PCBs was created and used to train a separate 3D U-Net model specifically for this scenario.

[0132] Dataset Creation. Synthetic 3D images of bent PCBs were generated by applying geometric transformations to the existing synthetic dataset. These transformations included bending, twisting, and warping to simulate real-world distortions. Figure 16A shows two slices of the content and the corresponding junctions of a bent synthetic sample used for training the network. As seen in the images, each slice only partially contains a PCB layer due to the geometric distortions in 3D.

[0133] In FIG. 16A and FIG. 16B, two slices of the bent synthetic content (FIG. 16A) and the corresponding junction labels (FIG. 16B).22 MEl\59677957.vl25-055 (098121-00431)

[0134] Training and Evaluation. The new model was trained using the same parameters as the original model but with the bent PCB dataset. To evaluate the performance of the new model, the technique was assessed with a bent PCB of a 2-layer design. Using this trained network, the technique was fully capable of reverse engineering the bent PCB. Note that the assignment of junction labels in Case Studies 2 and 3 represents two possible permutations corresponding to the same graph topology (i.e. connectivity arrangement). (FIGS. 17 and 18)

[0135] In FIG. 17A - FIG. 17D, 3D segmented metal content (FIG. 17A, FIG. 17C) and the corresponding segmented junctions (FIG. 17B, FIG. 17D) of the bent designed PCB. (created with Python 3.8 code) are shown.

[0136] In FIG. 18, nets and named junctions are shown for a bent PCB. In an embodiment, the nets are displayed to the user as colored nets and named junctions of the bent PCB (created with Python 3.8 code).

[0137] Integration of Image Processing and Machine Learning. The integration of image processing and machine learning in this method in some examples achieves full automation while ensuring computational efficiency and accuracy. Preprocessing steps, such as watershed segmentation, isolate regions of interest, reducing the computational burden for subsequent machine learning-based semantic segmentation. This method achieves a high degree of automation, reducing or eliminating the need for manual intervention, which is common in existing PCB design reconstruction methods. As a result, the method is labor-efficient, error-free, and capable of extracting netlists with 100% accuracy.

[0138] Discussion of Validation Testing. To validate the segmentation accuracy and its practical utility, performance using standard metrics like Intersection over Union (loU) and Fl score was evaluated, and a comprehensive comparison of the extracted pseudo-netlist with the expected netlist derived from the known PCB design was conducted. This step directly assessed the method's ability to produce functionally correct outputs. In tests completed, the extracted netlist achieved a 100% match with the expected netlist, demonstrating the robustness and reliability of in real-world applications.

[0139] It should be appreciated that in an example the synthetic dataset, consisting of 168,750 subvolumes from 250 synthetic PCBs, was used for training the deep learning model. In contrast, validation was performed on a set of independent cases, including a custom-designed 2-layer PCB, a bent version of the same PCB, and a complex commercial 3-layer PCB. These validation cases were selected to evaluate23 MEl\59677957.vl25-055 (098121-00431)the method's robustness across diverse scenarios and ensure its generalizability to real-world applications.

[0140] Discussion of Scalability. The scalability of the technique is achieved through synthetic data generation, which reduces or eliminates costly and time-intensive real-world datasets, and full automation, which reduces or minimizes manual intervention. The efficiency of direct 3D segmentation further enhances the method's adaptability to diverse PCB configurations. The successful validation of the method on synthetic, designed, bent, and commercial PCBs highlights its robustness and suitability for various industrial scenarios.

[0141] Comparison with other methods. Table 2 and Table 3 provide a comparison between the proposed method and other existing methods.24 MEl\59677957.vl25-055 (098121-00431)TABLE 3

[0142] Thus, an automated method is provided for the design reconstruction of PCBs utilizing 3D semantic segmentation of X-ray CT images and netlist extraction is provided. By integrating advanced image processing techniques with machine learning algorithms, a robust and efficient approach to accurately segment copper traces and junctions within PCBs has been provided. Unlike previous methods, this does not rely on extensive labeled datasets, at least in part due to the use of inherently labeled synthetic data. Additionally, by performing direct 3D segmentation, the techniques significantly improve the ease, accuracy, robustness, and universality of the process, eliminating the need to fix the orientation of images.

[0143] This capability also allows for the effective processing of images of PCBs that have undergone bending, a common occurrence in PCBs with smaller thicknesses. The broader implications of this approach extend to various physical and biological sciences where 3D image segmentation is vital. This approach has been validated on both synthetic and real-world PCB datasets, demonstrating high accuracy and reliability.

[0144] By improving the efficiency of PCB design reconstruction, the proposed automated approach mitigates issues related to part obsolescence, intellectual property recovery, and compliance. Future work25 MEl\59677957.vl25-055 (098121-00431)will focus on further refining the model, expanding the dataset, and exploring additional applications within the area of 3D image analysis and interpretation.

[0145] In some embodiments, a computer program product is provided. The computer program product (CPP) may reside in a non-transitory machine-readable medium. A processor may be configured to execute instructions from the computer program product and to receive three-dimensional images from an imaging device, such as an X-ray computed tomography device. The instructions direct the processor to perform semantic segmentation with a 3D U-Net architecture that includes a ResNet-18 backbone. The instructions may reference inherently labeled synthetic data for training. The instructions may generate a netlist that reconstructs printed circuit board connectivity. The instructions may also address physical bending or distortion in printed circuit boards. The instructions are useful for part obsolescence management and intellectual property recovery by analyzing three-dimensional data in a single pass. The instructions extend to other domains that benefit from volumetric image segmentation.

[0146] Some additional applications and advantages may be realized. For example, in aerospace, the technology may be used to provide volumetric inspection for composite structures. A system may be used to obtain three-dimensional datasets to locate internal flaws in a single pass. The pipeline adapts to curved shapes without manual labels. In automotive assembly, the system may be used to detect cracks in cast metal housings with three-dimensional inspection. A similar approach applies to forensic examination of mechanical parts. An operator reconstructs internal features in incomplete or damaged samples. The technology extends to archaeological and biomedical research for volumetric segmentation and analysis.

[0147] This approach offers end-to-end segmentation of volumetric data. This approach relies minimally on manual annotations. This approach supports multiple imaging modalities within a uniform framework. This approach integrates with design and modeling software. This approach verifies structural integrity across diverse industries in a rapid manner.

[0148] Generally, a computing environment may be included and incorporates both hardware and software elements that enable the detailed analysis and reconstruction of electronic systems. Such an environment often interfaces with imaging technologies like computed tomography (CT), which generates high-resolution, volumetric data of PCBs. CT imaging captures internal layers of a PCB without physical disassembly, preserving the integrity of components and connections.26 MEl\59677957.vl25-055 (098121-00431)

[0149] The environment leverages artificial intelligence (Al) to process and interpret complex imaging data. Al algorithms, often developed through machine learning techniques, analyze CT scans to identify individual layers, traces, vias, and components within the PCB. Training these algorithms typically requires extensive datasets, including labeled real-world data and inherently labeled synthetic data. Synthetic datasets may be generated to simulate PCB structures, offering diverse examples that can account for variations in design, manufacturing processes, and material properties.

[0150] One aspect of this computing environment is its ability to handle inherently labeled synthetic data, which serves as an effective training resource for Al. Synthetic data eliminates ambiguities in labeling, enabling precise training of Al models fortasks such as feature recognition, defect detection, and reconstruction of PCB schematics. By integrating these capabilities, the system provides a robust platform for reverse engineering, enhancing accuracy and efficiency.

[0151] The integration of Al and imaging technologies enables the generation of detailed three-dimensional digital twins of PCBs. These digital models allow for analysis, design replication, and the identification of potential vulnerabilities. The computing environment also supports applications such as compliance verification, forensic analysis, and design optimization, making it invaluable in fields like electronics manufacturing, quality assurance, and cybersecurity.

[0152] By combining advanced imaging techniques, Al-driven analysis, and versatile data-handling capabilities, this computing environment represents a transformative tool for reverse engineering PCBs, advancing the state of the art and addressing critical challenges in the electronics industry.

[0153] All statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0154] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be noted that the terms "first", "second", "third", "upper", "lower", and the like may be used herein to27 MEl\59677957.vl25-055 (098121-00431)modify various elements. These modifiers do not imply a spatial, sequential, or hierarchical order to the modified elements unless specifically stated.

[0155] Various embodiments of the invention are described herein with reference to the related drawings. Alternative embodiments of the invention can be devised without departing from the scope of this invention. Various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and / or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein.

[0156] The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains" or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0157] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms "a plurality" may be understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term "connection" may include both an indirect "connection" and a direct "connection."

[0158] The terms "about," "substantially," "approximately," and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, "about" can include a range of ± 8% or 5%, or 2% of a given value.28 MEl\59677957.vl25-055 (098121-00431)

[0159] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.

[0160] While the disclosure is provided in detail in connection with only a limited number of embodiments, it should be readily understood that the disclosure is not limited to such disclosed embodiments. Rather, the disclosure can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the disclosure. Additionally, while various embodiments of the disclosure have been described, it is to be understood that the exemplary embodiment(s) may include only some of the described exemplary aspects. Accordingly, the disclosure is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.29 MEl\59677957.vl

Claims

25-055 (098121-00431)Claims1. A method comprising:acquiring 3D images of an electronic device;segmenting the metal content from the 3D images;performing semantic segmentation of the junctions within the metal content; and post-processing the semantic segmentation of the junctions to extract netlists.

2. The method of claim 1, wherein the acquiring of 3D images comprises using X-ray computed tomography (CT) scanning to obtain 3D images of the electronic device.

3. The method of claim 1, wherein the acquiring of 3D images comprises using computed laminography scanning to obtain 3D images of the electronic device.

4. The method of claim 1, wherein the segmenting of the metal content comprises applying a watershed segmentation algorithm to isolate metal traces and junctions from other electronic device materials.

5. The method of claim 4, wherein the watershed segmentation algorithm includes placing seeds within glass fiber regions and metal areas based on intensity values, followed by simulating a flooding process from the seeds to delineate metal content.

6. The method of claim 1, wherein the performing of semantic segmentation utilizes a 3D U-Net architecture with a ResNet-18 backbone.

7. The method of claim 1, wherein the post-processing comprises using overlapping dissection and voxel assignment to ensure accurate boundary predictions.

8. The method of claim 1, further comprising generating synthetic 3D electronic device images for training the semantic segmentation model.

9. The method of claim 1, wherein the post-processing includes assigning unique identifiers to junctions and nets for netlist extraction.

10. The method of claim 1, wherein the semantic segmentation is trained using inherently labeled synthetic data.

11. A system for analyzing printed circuit boards (PCBs), the system comprising:an imaging device configured to acquire a plurality of 3D images of the PCBs;30 MEl\59677957.vl25-055 (098121-00431)a processing unit configured to perform semantic segmentation on the acquired 3D images to identify metal content within the PCBs;a post-processing module configured to process the segmented data to form a netlist representing the PCB's electrical connections.

12. The system of claim 11, wherein the imaging device comprises an X-ray computed tomography (CT) scanner configured to obtain 3D images of the PCBs.

13. The system of claim 11, wherein the processing unit includes executable computer code to use a 3D U-Net architecture with a ResNet-18 backbone for semantic segmentation.

14. The system of claim 11, wherein the processing unit includes computer code when executed on the processing unit to generate synthetic 3D PCB images for training the semantic segmentation model.

15. The system of claim 11, wherein the post-processing module includes a component for assigning unique identifiers to junctions and nets for netlist extraction.

16. The system of claim 11, wherein the post-processing module facilitates overlapping dissection and voxel assignment to ensure accurate boundary predictions.

17. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method for analyzing PCBs, the method comprising:acquiring a plurality of 3D images of the PCBs;performing semantic segmentation on the acquired 3D images to identify metal traces and junctions;post-processing the segmented data to facilitate netlist extraction.

18. The non-transitory computer-readable medium storing instructions of claim 17, wherein the post-processing further includes applying a watershed segmentation algorithm to delineate metal traces and junctions from the remaining PCB materials.

19. The non-transitory computer-readable medium storing instructions of claim 17, wherein the performing of semantic segmentation utilizes a 3D U-Net architecture with a ResNet-18 backbone for identifying metal traces and junctions.31 MEl\59677957.vl25-055 (098121-00431)20. The non-transitory computer-readable medium storing instructions of claim 17, wherein the post-processing includes assigning unique identifiers to junctions and nets to facilitate netlist extraction.32 MEl\59677957.vl

Images