Linear map decoding of convolutional codes

Abstract

A new decoder and decoding process is disclosed. The decoder is a linear maximum a posteriori (LMAP) decoder for decoding rate ½ convolution codes, and includes: a soft-input soft-output (SISO) forward decoding module comprising a plurality of shift registers that generates forward decoding outputs; and a (SISO) backward decoding module comprising a plurality of shift registers that generates backward decoding outputs; wherein: the input to the LMAP decoder is soft symbol estimates (SSE) of received code symbols; and a bidirectional MAP decoding output is obtained by combining the forward decoding outputs and the backward decoding outputs.

Description

LINEAR MAP DECODING OF CONVOLUTIONAL CODESTECHNICAL FIELD

[0001] The present disclosure relates to error-correction coding and, more particularly, to a decoder and decoding techniques for convolutional codes used in communication and data-storage systems.BACKGROUND

[0002] Reference to any prior art in the specification is not an acknowledgment or suggestion that this prior art forms part of the common general knowledge in any jurisdiction or that this prior art could reasonably be expected to be understood, regarded as relevant, and / or combined with other pieces of prior art by a skilled person in the art.

[0003] Communication channels are typically noisy and / or unreliable. To ensure that data is transmitted and received accurately and reliably, error correction is typically used in communication networks. Convolutional codes (CCs) are one of most widely used error control codes (ECCs) used in modern communication systems, such as cellular networks, Wi-Fi systems, space and satellite communications, data storage and magnetic recording. They have also been widely used to concatenate with other ECCs, such as Reed-Solomon codes, to provide capacity approaching performance. CCs are the constituent codes of one of the first capacity-approaching concatenated codes - turbo codes.

[0004] Two of the commonly used CC decoding algorithms are Viterbi algorithm (VA) and the BCJR maximum a posteriori probability (MAP) algorithm. VA generates a hard-decision or soft-decision (soft output Viterbi Algorithm) estimate of the information symbols with a minimum sequence error probability. The BCJR MAP algorithm performs symbol-by-symbol decoding of information symbols and achieves an optimal symbol error probability. As the MAP algorithm produces soft output information, it is suitable for iterative decoding of turbo codes and serial concatenated codes.

[0005] The original VA and MAP decoding requires adding tail bits (i.e., extra bits appended to the end of a convolutionally encoded message) to force the encoder to return to all-zero states at the end of the encoding process and this introduces significant rate loss, particularly for a short block length.

[0006] A key limitation of these decoding algorithms is high computing complexity. In addition, these and other known decoding algorithms require frequent and complex cache and memory access due to metric table and / or trellis lookups, which significantly contribute to delays and complexity in decoding implementations. Because of this, decoding CCs with constraint lengths k> 10 is challenging when using the VA or the MAP algorithms. As a result, CCs in practical communication and storage systems have been limited to shorter constraint lengths. For example, 802.1 la Wi-Fi and the 4G LTE use a tail-biting CC with a constraint length of 7.

[0007] Some reduced complexity decoders, such as serial and parallel list Viterbi decoders, have been developed by producing a rank ordered list of codewords (or encoded messages) according to their likelihoods and selecting the best L decoding estimates. There is a complexity-performance trade-off in such Viterbi algorithms. A smaller list size leads to suboptimal decoding, while a larger list size significantly increases the decoding complexity.

[0008] Accordingly, there exists a need for better decoders and / or decoding processes that reduce delay and / or complexity.SUMMARY

[0009] According to a first aspect of the present disclosure there is provided a linear maximum a posteriori (LMAP) decoder for decoding rate ½ convolution codes, the decoder includes: a soft-input soft-output (SISO) forward decoding module comprising a plurality of shift registers that generates forward decoding outputs; and a (SISO) backward decoding module comprising a plurality of shift registers that generates backward decoding outputs; wherein: the input to the LMAP decoder is soft symbol estimates (SSE) of received code symbols; and a bidirectional MAP decoding output is obtained by combining the forward decoding outputs and the backward decoding outputs.

[0010] The SISO forward decoding module may include a first forward decoding dual encoder comprising N-l shift registers, where N is the number of states in a corresponding convolutional encoder and a second forward decoding dual encoder comprising N-l shift registers; and the SISO backward decoding module comprises a first backward decoding dual encoder comprising N-l shift registers and a second backward decoding dual encoder comprising N-l shift registers.

[0011] Further, the first forward decoding dual encoder and the first backward decoding dual encoder each include a self-updating register.

[0012] Further still, the first forward decoding dual encoder and the second forward decoding dual encoder are associated with corresponding first and second decoder polynomials that define connection coefficients of the first and second forward decoding dual encoders associated with the input.

[0013] In some embodiments, the first backward decoding dual encoder and the second backward decoding dual encoder are associated with the corresponding third and fourth decoder polynomials that are the reverse polynomials of the first and second decoder polynomials, respectively.

[0014] It will be appreciated that the rate ½ convolutional code may be a recursive systematic code (RSC) or a non-systematic code (NSC) and the RSC or the NSC is generated by a code generator polynomial. Further, the first and second decoder polynomials and the third and fourth decoder polynomials may be derived from the code generator polynomial.

[0015] In some embodiments, the shift registers in the first and second forward dual encoders include a sequence of register labels, where each register label represents a set of encoder memory indices used by the corresponding shift register.

[0016] The sequence of register labels of the second forward dual encoder may be generated by a recursive label synthesizer having a plurality of shift registers having the same connection coefficients as the second forward dual encoder and including symmetric difference operations between the plurality of shift registers.

[0017] In some embodiments, the sequence of register labels of the first forward dual encoder excluding the self-updating register is generated based on the sequence of register labels of the second forward dual encoder. Further, the register label of theself-updating register is determined by comparing the sequence of register labels of the first forward dual encoder and second forward dual encoder and identifying a unique register label that appears only in the sequence of register labels of the second forward dual encoder. Further still, a connection coefficient of the self-updating register is determined based on the register label of the self-updating register.

[0018] In some other embodiments, each of the shift registers in the first and second backward dual encoders includes register label. A sequence of the register labels in the first and second backward dual encoders are the reverse of the sequence of the register labels in the first and second forward dual encoders, respectively.

[0019] According to another aspect of the present disclosure there is provided a linear maximum a posteriori (LMAP) decoding method. The method includes obtaining the LMAP decoder of the first aspect; initializing register labels of each of the shift registers in the LMAP decoder to 1; inputting soft symbol estimates (SSE) of received code symbols to the LMAP decoder; updating register values of the plurality of shift registers in the forward decoding module for each time k based on the SSE of the received code symbols; updating register values of the plurality of shift registers in the backward decoding module for each time k in reverse temporal order; and determining bidirectional LLR of an input binary code based on the updated register values.

[0020] In some embodiments, updating the register values of the plurality of shift registers in the forward decoding module for each time k comprises: updating register values of the N-l shift registers in the first forward dual encoder; updating register values of the N-l shift registers in the second forward dual encoder; combining register values of the first and second forward dual encoders; and updating the register values of the first and second forward dual encoders based on the combined register values.

[0021] Further, updating the register values of the plurality of shift registers in the backward decoding module for each time k comprises: updating register values of the N-l shift registers in the first backward dual encoder in reverse temporal order; updating register values of the N-l shift registers in the second backward dual encoder in reverse temporal order; combining register values of the first and second backwarddual encoders; and updating the register values of the first and second backward dual encoders based on the combined register values.

[0022] In some embodiments, generating the bidirectional decoding output further comprising performing an additional register label mapping for a NSC.BRIEF DESCRIPTION OF DRAWINGS

[0023] Fig. 1 is a schematic of a trellis for a 4-state recursive systematic code (RSC).

[0024] Fig. 2 is a block diagram illustrating an LMAP decoder for a rate A code according to aspects of the present disclosure.

[0025] Fig. 3 is a flowchart illustrating an example method for determining connection coefficients of the LMAP decoder of Fig. 2 according to aspects of the present disclosure.

[0026] Fig. 4 is a flowchart illustrating an example method for determining register labels for the shift registers of the LMAP decoder of Fig. 2 according to aspects of the present disclosure.

[0027] Fig. 5 is a block diagram of a recursive label synthesizer of the LMAP decoding for a general RSC code.

[0028] Fig. 6 is a flowchart illustrating an example decoding process according to aspects of the present disclosure.

[0029] Fig. 7 is a chart showing bit error rate (BER) performance comparison for decoding (1, 7 / 5)oct RSC.

[0030] Fig. 8 is a chart showing bit error rate (BER) performance comparison for decoding (1, 23 / 25)oct RSC.

[0031] Fig. 9 is a chart showing bit error rate (BER) performance comparison for decoding (1, 561 / 573)octRSC.

[0032] Fig. 10 is a chart showing bit error rate (BER) performance comparison for decoding (1, 53 / 75)oct NSC.

[0033] Fig. 11 is a chart showing BER performance comparison for decoding (171, 133)octNSC with both zero-tailing and tail-biting schemes.

[0034] Fig. 12 is a chart depicting BLER performance for tail-biting NSC against PPV bounds with block length of 64.

[0035] Fig. 13 is a chart depicting BLER performance for tail-biting NSC against PPV bounds for block length of 128.

[0036] Fig. 14 is a chart depicting a comparison of decoding time between LMAP and BCJR with respect to code memory order.DETAILED DESCRIPTION

[0037] Aspects of the present disclosure introduce a new decoder and decoding process. The decoding process is called a linear MAP (LMAP) decoding. In some embodiments, the LMAP decoding can be used for a rate- 1 / 2 CC, which are types of codes where for every 1 bit of original data, 2 bits are transmitting, effectively doubling the amount of data sent. In other embodiments, the LMAP decoding described herein can be used for other fraction rate codes such as rate % codes.

[0038] The LMAP decoder includes two modules - a forward decoding module and a backward decoding module, each including dual encoders, associated with two constituent codes. Each decoding module is made up of one or more shift registers. A bidirectional MAP decoding output is obtained by the decoding process by combining the contents of respective forward and backward dual encoders.

[0039] If soft symbol estimates (SSE) of convolutional coded symbols is applied as the dual encoder input, then its output produces the SSE of information symbols of MAP decoding.

[0040] As the LMAP decoder is represented using simple shift registers, the currently disclosed LMAP decoder maps naturally to hardware registers and thus can be easily implemented. Furthermore, the decoding operations can be implemented in parallel using a data array and inner product operation in programming, leading to fast decoding, even for a very large-state codes.

[0041] As discussed previously, cache and memory access are significant sources of delay and complexity in previously known decoders and decoding processes, inaddition to them being computationally complex. In contrast, the presently disclosed decoder and decoding process not only considerably reduce the computation complexity but also achieve superior cache utilization efficiency through localized register access.

[0042] Simulation results demonstrate that the presently disclosed decoding process achieves the same performance as the BCJR MAP decoding but has a significantly reduced decoding delay. In simulations, the LMAP decoding was found to be 12 times and 331 times faster than BCJR for CCs with m = 2 and m = 8, where m is the memory length of the CC.

[0043] As such, the presently disclosed LMAP decoder unlocks decoding of very large state codes (VLSC) with near-capacity performance, overcoming the complexity limitations of existing decoding algorithms. For a block length of 64, and a VLSC of memory length m = 14, the LMAP decoding process surpasses the random coding union (RCU) bound by approximately 0.5dB.

[0044] These and other aspects of the present disclosure will be described in detail in the following sections.BCJR decoding

[0045] The BCJR algorithm operates on a trellis, which is a graphical representation of the state transitions of a convolutional code over time. A trellis maps out all possible paths that the encoder could take as it processes input bits, providing a structured way to visualize and compute probabilities during decoding. Fig. 1 illustrates an example trellis 100 for a 4-state ( 1,7 / 5)oct recursive systematic code (RSC). Each node 102 in the trellis 100 represents a possible state of the convolutional encoders at a given time step. The trellis 100 includes 2 time steps, time k and time k+1. The lines 104 connecting the states 102 represent transitions between states 102, which correspond to input bits and the resulting output symbols.

[0046] By operating on the trellis 100, the BCJR algorithm calculates three probability metrics at each time step. These include a forward metrics, a, that indicates a probability of being in a particular state given previous observations. The forward metrics is computed left to right in the trellis 100. The second probability metrics is a backward metrics, ft. that indicates the probability of observing future symbols given the current state and it is computed right to left in the trellis 100. Thethird probability metrics is branch metrics, y, that indicates the likelihood of transitioning between states based on the received signal and the channel model. The typical BCJR decoding process includes six main steps. Initially, the decoder starts in an all-zero state. Then, the forward metric is computed for each time step by moving from the start of the trellis to the end for each state s at time t as αt(s). This represents the likelihood of arriving at state 5 after observing the first t symbols. This is computed recursively for each time step. Next, the backward metric βt(s) is calculated by moving from the end of the trellis back to the start. This represents the likelihood of observing the remaining symbols given state 5 at time t. This is also computed recursively for each time step.

[0047] For each transition between states, the branch metric is computed, which combines the channel observation and transition probability. Thereafter, a posterior probability (APP) for each bit is calculated using the three computed metrics. This yields a soft output or likelihood for each bit. Finally, a hard decision (i.e., 0 or 1) is made by the decoder based on the likelihoods for each bit.

[0048] Examination of the forward decoding of the BCJR algorithm reveals an interesting recursive relationship that motivates the proposed LMAP decoder. In particular, if the SSE is known, the decoding can be performed in reverse by following the same process as the encoder.LMAP decoder

[0049] Inventors of the present disclosure have identified that the BCJR decoding can be performed using a dual encoder design. Fig. 2 depicts the LMAP decoder 200. The decoder 200 includes a forward decoding module 202 and a backward decoding module 204.

[0050] The forward decoding module 202 includes two dual encoders, DFi and DF2, which generate the decoding output and the normalization coefficients. The forward decoding module 202 includes 2mshift registers 206, where m is the memory length of the encoder. An explicit expression for these two dual encoders DF 1 and DF2 can be obtained from a code generator polynomial. Coefficients of the generator polynomial dictate the connections 208 between the shift registers 206. Further, each shift register 206 is labelled. Each register label represents a set of encoder memory indices that the shift register 206 reads and / or writes to.

[0051] The two dual encoders DFi and DF2 compute and update all the dual encoder memories in different orders using different shift register structures where the inputs of these two dual encoders are the soft symbol estimates (SSE) of the received coded symbols. The explicit order of memories for each dual encoder can be derived as discussed in detail later.

[0052] Similarly, the backward decoding module 204 includes two dual encoders DBi and DB2. The backward decoding module 204 is similar to the forward decoding module in that it also includes 2mshift registers 206. However, the labels of the shift registers 206 are reversed and the connection coefficients are also reversed. These dual encoders also generate the decoding output and the normalization coefficients.

[0053] Further, one of the forward dual encoders (e.g., DFi) and one of the backward dual encoders (e.g., DBi) includes a self-updating register (SUR) 210. This register is labelled as 5 in DFi and DBi and it is always updated recursively from itself.

[0054] The bidirectional MAP decoding output is obtained by linearly combining the shift register contents of DFi and DBi, and that of DF2 and DB2.

[0055] The LMAP decoder 200 can decode any rate 1 / 2 RSC where the feedforward polynomial is a primitive polynomial, referred to as the primitive RSC codes. Further, it can be extended from RSC code to non-systematic codes (NSC). The LMAP decoder structure for a NSC is identical to that of an RSC when the generator polynomials are the same, but the LMAP decoder for NSC requires additional register label mapping.

[0056] The connections and register labels of the dual encoders DFi, DF2, DBi, and DB2 can be calculated offline. By using forward and backward modules 202, 204 in a dual encoder architecture, the presently disclosed decoder 200 has a simple architecture and each module 202, 204 can be implemented using simple linear shift registers. The bi-directional computation can then be performed based on various combinations of the forward and backward modules 202, 204, making the architecture and the computations relatively simple.

[0057] The following sections describe the process for determining the parameters of the LMAP decoder 200 and the decoding process.Obtaining the parameters of the LMAP decoder

[0058] A rate 1 / 2 recursive systematic code (RSC) with a constraint length k = n+1 can be represented by the following generator polynomial - gf(x) = (1, af(x) / qf(x)), (1)

[0059] where n is the memory length, af(x) is a primitive polynomial of degree n and qf(x) is also a primitive polynomial of degree n. The degree n is equal to the memory length m of the CC. Its LMAP decoder 200 is depicted in Fig. 2. af(x) can be represented as af(x) = xn+ an-1xn-1... + a1x + 1 and qf(x) can be representedas qf(x) = xn+ ... + q1x + 1.

[0060] The original binary information sequence is denoted by b and represented as (b1, b2, . . . , bL) and the binary codeword of b is denoted by c and represented as (c1, c2, . . . , cL). It will be understood that ck= (ck, ck) and ck= bk. xbis the BPSK modulated binary symbols and represented as (xb1, xb2, . . . , xbL), while xcis the BPSK modulated codeword symbol sequence of c and represented as (xc1, xc2, . .■, xcL), where xCk= (xci,xcz).

[0061] The received signal sequence is denoted by y = (y1, y2, . . . , yL), where yk= (y1k, y2k). pc1k(ℓ) and pc2k(ℓ), with ℓ ∈ {0, 1}, denote the APPs of {c1k= ℓ} and {c2k= ℓ}, respectively.

[0062] Consider a BPSK modulation and assume that 0 and 1 are modulated into 1 and -1. Then, the soft symbol estimates (SSEs) of ckand ckare given by x̂c1k= pc1k(0) - pc1k(1) and x̂c2k= pc2k(0) - pc2k(1). For simplicity, let 풫c(ℓ1ℓ2) = 풫c(ℓ1) 풫c(ℓ2).

[0063] x̂brepresents the SSEs of bkobtained by decoding y. Particularly, x̂band x̂bdenote the SSEs of bkobtained based on y1kand y2kat time k, and Lband Lbdenote their respective log-likelihood ratios (LLRs). Then we have the following relationship between LLR and SSE -X I 1b= log6— k i-xhDi k 1+x.2Lb2 = log—bk'-xbzk(2)Then, SSE of the combined LLR Lbi+ Lb2, denoted by xbi© xb2, is given by(3)which is the optimal combining of xbiand xb2.

[0064] The LMAP decoder 200 can be defined by the following parameter set:T) = ds, dh(x), df2(x), 5, 1, J, (4) where:

[0065] dsis the coefficient associated with xc2 in the connection to the selfupdating register (SUR) F^ in DF1, while 5 is the label of SUR 210.

[0066] d^ (x) is the decoder polynomial and it is represented by - d^(x) = 1 + d^x + d^x2+....+ d^123xw-3+ xN~2(5) It defines the connection coefficients associated with the decoder inputs xc2 in DF i, and J = (Ji, J2,..., <7W-2) is the sequence of register labels in DF 1, excluding the SUR F^\ where register F^ is shifted toin next time slot.

[0067] df2(x) is the decoder polynomial and it is represented by - df2(x) = 1 + d®x + d^x2+....+ d^l2xN~2+ xw-1(6)This decoder polynomial defines the connection coefficients associated with the decoder inputs xc2 in DF2, 1 = ( / 1;I2, ■ ■ ■, fjv-2) is the sequence of register labels in DF2, where register F^ is shifted toin next time slot.

[0068] The parameter set 2) fully determines the LMAP decoder 200. Specifically, for DBi and DB2, their register structure is defined by similar primitive polynomials - dbi(x) = 1 + d^l3x + d^_4x2+....+ d^xN~2(7) dh2(x) = 1 + d^l2x + +....+ d^xN~2+ (8) dbi(x) and dbz(x) are the reversed polynomials of df (x) and df x).

[0069] Additionally, the sequences of register labels in DB 1 and DB2 are J = N-2> JN-3> ■ ■ ■, <7i) and I = (IN-i> IN-2, ■ ■ ■> Ii), respectively. Thus, DBi and DB2 have exactly reverse memory-labelling structures compared to DFi and DF2.

[0070] Each register label represents a set of encoder memory indices. For instance,= F423 with label 5 = { 1, 2, 3} denotes a self-updating register 210, indicating that this self-updating register is associated with the SSE of encoder memories Mi, M2, and M3.

[0071] Further, excluding the SURs 310, DFi and DF2 always have the same start and end register labels. Similarly, DBi and DB2 also share the same start and end register labels. In other words, Ji = Ii and JN-2 = IN-I.

[0072] Further still, excluding the SURs, the end register label in forward and backward decoding corresponds to the SSE of memory used to determine xbkin the forward and backward directions, respectively. Thus, the end labels can be directly inferred from the dual decoder or generator polynomial. Specifically, JN-2 = IN-I=Ilf and <7i = / i = Ub. Uf and Ubare index sets of memories used to determine xbkin forward and backward directions, respectively. Ilf and Ilbcan be defined as follows:Ilf = { t: 77 #= 0, 1 < i < n — 1 },11^ = { r. ¥= 0, 2 < i < n } (9) Where r = cq ® for 1 < i < n — 1.

[0073] As seen in Fig. 2, the inputciis connected to all registers in DFi and DBi, while the input xcz is connected to only a subset of registers and their connection coefficients are defined by (x) and d / j](x). respectively. That is, the input xciis used to calculate the SSEs of all shift registers 206 in DFi and DBi. In contrast, DF2 and DB2 are recursive and only the input xcz is connected to a subset of registers, where the connection coefficients of xcz are defined by d2(x) and d / j2(x. respectively.

[0074] As described previously, given a rate A RSC with polynomial g(x), determining the parameter set 2) is sufficient to define the LMAP decoder 200. The parameter set 2) can be determined offline prior to real-time decoding. Once the decoder 200 is determined, it does not change during the decoding process.

[0075] A method for determining the decoder polynomials is described next with reference to Fig. 3. The method 300 commences at step 302, where the generator polynomial g(x) = (1, is first obtained.

[0076] Next, at step 304, the complementary polynomial z(x) of the polynomial g(x) is determined. Since the feedforward generator polynomial ctf is a primitive polynomial of degree «, it always divides x2”-1+ 1 = xw-1+ 1. A complementary polynomial Zf (x) of the polynomial g(x) can therefore be defined as -2-x+l x^+l7- (10)« / ((* A) « / (x)

[0077] Then, at step 306, the decoder polynomial df2(x)that defines the connection coefficients in DF2 is determined based on the generator polynomial and the complementary polynomial. The forward dual encoder DF2 associated with decoder inputs xc2 is given by - qy(X) qf(x) zf(x) df2(x)cij-(x) aj-(x) Zf(x) xw-1+ 1so we have,dz( ) = zz( ) ' ^(x) (11)

[0078] Finally, at step 308, the decoder polynomial d^ (x) that defines the connection coefficients associated with the decoder inputs xc2 in DF i is determined based on the complementary polynomial and the generator polynomial,(x)can be derived by multiplying with qy (x), i.e.,

[0079] Once the decoder polynomials d^x) and df2(x) for DF1 and DF2 are determined, all connection coefficients in DFi, DF2, DBi, and DB2 are determined.Determining the Decoder Register Label Sequences

[0080] Once the connection coefficients for each of the forward and backward decoding modules 202, 204 are determined, register label sequences are determined for each of the shift registers 206 in DFi, DF2, DBi and DB2.

[0081] Fig. 4 illustrates an example method 400 for determining the register label sequences according to one aspect of the present disclosure.

[0082] The method 400 commences at step 402, where the feedforward generator polynomial aj(x) and the memory indices set lf is obtained (based on equation 9).

[0083] Next, at step 404, the sequence of register labels I in DF2 are determined. The label sequence I can be generated by a recursive label synthesizer (RLS), as shown in Fig. 5. The RLS 500 functions as a feedback encoder, generated by l / aj(x), where the feedback connection coefficients are identical to those of the forward dual encoder for g(x), but the multiplication operation (i.e., ®) is now replaced by a symmetric difference operation SDO (i.e., A). A symmetric difference operation (SDO) is defined as an operation, which retains only the elements that differ between two sets. For example, the SDO operation between two sets { 1 } and {1, 2} will result in an output of {2}, which is the element that is only present in the second set but not in the first set. Similarly, an SDO operation between two a set including { 1, 3, 4, 5} and a set including {1, 2, 4} will result in an output of {2, 3, 5} as these are the elements in each set that are not present in the other set.

[0084] The shift register contents in RLS 500 are denoted by, where i G { 1..., n} represents a set of registers 502, each of which stores a set of memory indices fromthe encoder. For example, if Mi = {1, 2, 3}, it stores a set indicating memories Mi, M2 and M3 in the encoder.

[0085] To obtain the label sequence I, the shift registers 502 of the RLS 500 are initialized as Mi = {i}, for i = 1,..., n. This initialization is the same as the original memory indices order in the encoder of the polynomial g(x), as well as the memory SSE indices order in the dual encoder.

[0086] Then, a normal recursive encoding process of RLS 500 is performed, where the output of the RLS encoder 500 is taken from the last shift register 502. After N -2 shifts, the RLS encoder 500 Obtains a temporary label sequenceThen the final label sequence I is obtained by performing a circular shift over I. Specifically, the label sequence I is determined by the RLS 500 through the following steps:

[0087] 1. Initialize Mi = {i} for i = 1,..., n, and the sequence / ' = ({n})

[0088] 2. Compute - Ai; - A At(13) where SDO is applied to all candidate sets Mi that meet the condition at ¥= 0.

[0089] 3. Shift the content of Mi — 1 to Mj, i.e., — 1 for i = n, n~l 2- Particularly, update M1as M1= M.

[0090] 4. Output the last register of RLS 500 i.e., A, and prepend it to i.e., I' = (Mn, / ').

[0091] 5. Repeat steps 2-3 N - 2 times until / ' would contain its first duplicate element. The sequence is stopped before adding the duplicate element.

[0092] If a x) is primitive, register label sequence / ' will transverse the non-empty power set J>{ 1,..., n} \ 0 in a certain order. This set includes all possible non-empty subsets of {1,..., n}. For example, power set P {1, 2, 3} will include 2n-l (i.e., 7) possible non-empty subsets of {1, 2,3} such as - {{1}, {2}, {3}, {1, 2}, {1, 3}, {2, 3}, {1, 2, 3}}. In general, I ' has the cardinality of 2n- 1 = N - 1, and the steps 2-3 will repeat for N - 2 iterations.

[0093] Next, a circular shift is performed on I' to obtain I. Specifically, let I'j denote the jthelement of I'. The index / is identified where I'j = Ilf, = {i = I't = Ilf,! < i < N — 1}. Then, I is determined as - / = (ry+1,ry+2. rN-i,i\,i'2. i'j) (14)

[0094] The sequence of register labels J in DF 1 are then determined at step 406 based on register label sequence I. As described previously, the relationship between DFi and DF2 is given by (1 + x) df^x) = d^2(x). This relationship is used to determine the sequence of register labels J based on the register labels I. In particular, the ithregister label in J is determined to be the symmetric difference of the first i register labels in I. Specifically -(15)for i = 1, 2,..., N - 2.

[0095] The sequence of register labels in DBi and DB2 are similarly determined. In particular, the register labels of DBi and DB2 have the reverse order of the register labels in DFi and DF2, respectively.

[0096] Finally, at step 408, the coefficient dsand the label 5 for the self-updating registers 210 is specified based on the register label sequences determined for DF 1 and DF2.

[0097] As described previously, excluding the self-updating register, DF 1 ends with the same register labels as DF2. Thus, the labels of the self-updating registers 210 can be determined by comparing all existing labels J in DFi and I in DF2and finding a unique label that appears only in DF2. In other words, the label 5 of the selfupdating registers can be directly determined by: 5 = I / J. The coefficient dsfor the connection to self-updating register can be readily determined based on the content of 5; specifically,

[0098] Label 5 is an index set of encoder memory. Then, ds= 1 if does not contain the first memory in the encoder, and ds= 0 otherwise. For example, ds= 1 if = {2, 3}, while ds = 0 if 5 = {1, 2, 3}.

[0099] By performing methods 300 and 400, all the parameters in the set 2) for the LMAP decoder 200 are determined. It will be appreciated that the identification of these parameters can happen offline - i.e., before the LMAP decoder 200 is used for decoding.LMAP Decoding Process

[0100] Fig. 6 depicts an example method 600 for LMAP decoding using the decoder 200. The input to the forward decoding modules 202 (i.e., DF i and DF2) is (xC1, xC2,..., xCL), while the input to the backward decoding modules 204 (i.e., DBi and DB2) is reversed as (xCL,..., xC2, xC1). The decoding method 600 commences at step 602, where all register values are initialized to 1. Specifically, the register values for DFi, DF2, DBi and DB2 are all set to 1.

[0101] Next, at step 604, the registers in the forward decoding module are updated. Updating the registers includes four steps (606-612) for each time k. For forward decoding, the first step, 606, is to update the DF 1 registers. This includes, at time L, calculating the updated register values F^ [k + 1] based on F^ [Zc] for i = 2, 3,..., N - 2. This is represented by the following equation - d(1)d2['t+1l =fi‘llK Vj (v>) ' <17> In particular, the register value for the first shift register in DF 1 (with label Ji) at time k+1 is a product of the two SSE inputs xciand xc2.

[0102] The next step, 608, in forward decoding is to update the DF2 registers. This includes, at time L, calculating the updated register values for Fj ^ [k + 1] based on F;® [Zc] and only xcz for j = 2, 3,..., N - 2. This is represented by the following equation -(y.) ‘ (is)

[0103] In particular, the register value for the first register in DF2 at time k+1 is updated as - Fz® [k + 1] = F^^ [k].

[0104] At the third step, 610, the updated register values are combined. That is, for each register label J, G J and its identical counterpart It G I (where It andJ; represent the same set of memory indices in the encoder), their register values are combined according to - F^[k + l] =i(FW[k + l] +F®[k + l]) (19)

[0105] where i, = 1 + Fj^[k] ■ xci■ xcz is a constant normalization factor for all combinations at time k. Note that FF [k + 1] is used to represent the combined value.

[0106] Similarly, for the self-updating registers 210, identical counterpart labels from I are identified and combined as follows - Fsc[k + l] = ^(F / 1)[k + l] +F®[k + l]) (20)

[0107] Finally, all registers in both DFi and DF2 are updated with their respective combined values. Specifically, for each pair of identical labels G I and J, G j - F^[k + 1] = FF[k + 1], F^[k + l] = FF[k + l] (21)

[0108] Also, for the SUR 210 label 5 and its counterpart IsG I - FsW[k + 1] = Fsc[k + 1],F®[ / c + l] = Fsc[ / c + 1] (22)

[0109] This synchronization ensures that both DFi and DF2have identical register values after each update cycle, maintaining consistency between them.

[0110] It should be understood that while each pair of identical labels needs to be identified, this identification process does not need to occur in real-time during decoding. In fact, the correspondence between each pair of identical labels can be established a priori, once the sets and J are determined in method 400. This predetermined mapping allows for efficient register combination without the overhead of dynamic label matching.[oni] At step 614, the registers of the backward decoding modules are updated. The backward decoding processes (i.e., DBi and DB2) are performed analogously to the forward decoding, but in reverse temporal order. Specifically, the process begins at time L and proceeds backwards, updating the register values at time k based on the register values and inputs at time k + 1. The details of this method however are the same as that described with respect to the forward decoding described at step 604 and therefore are not described here again in detail.

[0112] After the register values are updated for the forward and backward decoders, for each time k in the forward and backward decoding modules 202, 204, register values are used to determine the final bidirectional LLR of the input binary code bk at step 616. Precisely, the final bidirectional LLR of the binary code is obtained as - 1+* 1 Wi) Lbk= log) - - (23)l-x 1 (Sfc-M / c)\ck) where 5k and pi are computed at each time k from the register values in DFi, DF2, DBi, and DB2.

[0113] If auxiliary variables Fj^[k] = = 1 and dg1' = d^l2= l, then, / k is simply determined as - d S (xci) ‘ F™ [k] ■ [k] + (xcz)s■ [k] ■ B™ [k] (24)And 5k is computed as -d(2)st= i + S?=?(«c.) + <25> Substituting equations 24 and 25 into 23 obtains the bidirectional LLR of bk.

[0114] It should be appreciated that terms (xci)1and [xc2 )7do not increasecomputational complexity in real-time implementation, despite their exponential form. This is because the connections related to X2 are predefined in the decoder structure, and d-7)and d)2)are fixed values set by the decoder configuration.LMAP decodins of a general rate 1 / 2 NSC

[0115] This section describes how the LMAP decoder 200 and decoding process (described with reference to Fig. 6) can be used for decoding NSCs. A rate 1 / 2 NSC may be denoted as CNSC and its generator polynomial may be g^Cx) =cij-(x)^ with amemory length n and constraint length K = n + 1. Thepolynomialis a primitive polynomial of degree n.

[0116] The LMAP decoder structure of the NSC (? (%), ci^(x) is identical to that of the RSC when the generator polynomials qf(x)and are the same, except for the computation of the final bidirectional LLR estimates. This structural equivalence highlights the versatility of the LMAP decoder 200, allowing a single decoder implementation to work for both code types.

[0117] Further, given q (x) and u^(x), the parameter set 2) is determined in the same manner as for RSC (as described above with respect to methods 300 and 400). Once the parameter set 2) is determined, the LMAP decoder 200 for NSC is ready for real-time decoding via register updates. The register updating process is also identical to that used for RSC, as described previously with respect to method steps 604 and 606 of method 600.

[0118] However, to generate the bidirectional output, the LMAP decoder 200 for NSC requires an additional register label mapping, in contrast to the RSC decoder.

[0119] Consider a set V that denotes the index set of memory SSEs used to determine x / jfcin the forward direction based on the decoder input xci. Set V can be defined as - V= {i\ qi 0, 1 < i < n — 1 } U {n} (26)

[0120] For any register labelled J, (which is a set of memory indices), its V-adjusted label, denoted as can be defined as(27)

[0121] That is,is obtained by the SDO between and V. Similarly, the V -adjusted labels / '7and <5" can be defined as - Z / ! A d AV, S' A S AV(28)

[0122] For instance, if q_f(x) = 1 + x + x2+ x3, then the set V = {1, 2, 3}. Then, for Ji = 1, its V-adjusted label becomes J'_i = {1}△{1, 2, 3} = {2, 3}.

[0123] It will be appreciated that since I and J U 5 traverse the non-empty power setJ’]!,..., n} \ 0, there must be G J and I'i G I for anyG J and G / . Therefore, any V-adjusted registers are also registers in the LMAP decoder 202.

[0124] Finally, the bidirectional LLR of bk is obtained as δk+xc1μk+xc1δ'k+μ'k(29>

[0125] where δk, δ'k, μkand μ'kare computed at each time k from the register values in DFi, DF2, DBi, and DB2. Specifically, δkand μkare computed as described previously with respect to the RSC decoding process in Fig. 6. In contrast, δ'k and μ'k are derived using V-adjusted labels. Then μ'k is determined as – (30)In contrast to μk, μ'kis derived by replacing all register values in the forward decoding with their corresponding V-adjusted register values.

[0126] Similarly, 5'k is computed as - d(22 _ 6k’ = F^[k] + ^ (x F™ [k] - B^ [k] + F™ [fc].B^[k] (31)v 1\LkJ ‘f.'+1UV-11

[0127] Here, δ'kis obtained by replacing all register values in the forward decoding with their corresponding V-adjusted register values.

[0128] Accordingly, for NSC, in the last step of the decoding method 600, in addition to Bk andvalues of B'k and 6'kare also computed before the LLR is computed, B'kaiqd 6'kare computed similarly to Bkaiqd 8k. with the only difference being the substitution of forward register labels with their V-adjusted counterparts. Further, the equation for computing LLR is different from that used for computing LLR for RSC.

[0129] The previous sections describe decoders and decoding processes where the generator polynomials (1, ci (x) / q (x)), where af(x) is a primitive polynomial. For codes with generator polynomials (1, q (x) / ci^(x)) also using the primitivepolynomial a_f(x), the LMAP decoder 200 can be implemented similarly, with the main difference being the exchange of xcand xcthroughout the decoder 200 and the computation of the final LLR Lb. This type of decoder may be useful for turbo code decoding.

[0130] Each xciand xc2 is obtained using one exponential operation, two additions, and one division. Further, during forward decoding each register in DF i requires two multiplications to update its value, whereas each register in DF2 requires one multiplication to update its value. One addition and one division operation are required to combine each register in DFi with its counterpart in DF2. The number of operations in backward decoding is the same as in forward decoding. Computing μkneeds 3N multiplications and N additions, whereas computing δkrequires 2(N − 1) + 1 multiplications and N additions. Finally, computing Lbkrequires 3 multiplications, 4 additions, and one logarithm.

[0131] In summary, at each time k, LMAP decoding needs, 10(N − 1) + 3N + 27 multiplications and 2(N − 1) + 2N + 27 additions. This is much lesser than the number of computations required by other known decoding processes such as BCJR.

[0132] The space requirements of the LMAP decoding process can be categorized into two components - static configuration storage and dynamic operation storage. For static storage, N fixed register label mappings are stored, each of which requires m bits. Further, 2(N - 2) connection coefficients are stored. For dynamic storage, forward decoder modules have N - 1 shift registers for DF 1 and DF2, respectively. The backward decoder modules have similar number of shift registers. Since registers in DFi and DF2 (also, DBi and DB2) hold identical values after each update cycle, (N-l) values of forward decoding and (N-l) values of backward decoding are stored at each time k to compute the bidirectional LLR. Further, for each time k, one LLR is stored. Assuming each soft value is quantized with nqbits, the total memory space required by LMAP is Nm+2(N−2)+4(N−1)nq+ 2nqNL + 3nqL = L(2nqN + nq) + N(m + 4nq+ 2) − 4(nq+ 1) bits.

[0133] Finally, the LMAP decoding process requires 4(N - 1) sequential register accesses per time step, and 2(N - 1) register value accesses for LLR computation per time step.

[0134] Therefore, in terms of the cache efficiency and hardware implementation, the LMAP decoder 200 and decoding process 600 can achieve superior cache utilization through localized register access and its structure maps naturally to hardware registers.Simulation results

[0135] In this section, the performance and computational efficiency of the proposed LMAP algorithm are evaluated through extensive simulations using MATLAB 2021a on an Intel(R) Core(TM) i7-10700F CPU. For each data point in the bit error rate (BER) curves, the simulation was run until at least 3000 bit errors were collected to ensure statistical reliability. The results demonstrate the effectiveness of LMAP across different code parameters and decoding scenarios, including both recursive systematic codes (RSC), non-systematic codes (NSC), and tail biting convolutional code (TB-CC).

[0136] For RSC codes, three different code configurations with increasing complexity were examined. As depicted in Fig. 7, for the (1, 7 / 5)Oct code, both forward-only and bi-directional LMAP decoding performs virtually identical to their BCJR counterparts. The bi-directional LMAP and BCJR achieve significantly better performance than forward-only decoders, with LMAP bi-directional reaching a BER of 10-5 at approximately 6 dB SNR, matching the BCJR algorithm’s performance.

[0137] For the more complex (1, 23 / 25)oct with m = 4 code shown in Fig. 8, the bidirectional LMAP decoder 200 matches the performance of the BCJR decoder. Furthermore, the (1, 561 / 573)octRSC with m = 8 is evaluated in Fig. 9. The bidirectional LMAP achieves same BER performance to bi-directional BCJR across the entire SNR range, while requiring significantly less computational resources.

[0138] The performance of LMAP for NSC was evaluated with the (53, 75 )oct code, as illustrated in Fig. 10. The bi-directional LMAP achieves performance identical to the bi-directional BCJR algorithm. For the (171, 133)Oct NSC shown in Fig. 11, both zero-tailing and tail -biting configurations are evaluated. The circular state initialization method is utilized to implement the tail-biting NSC. Specifically, for a message sequence b = (bi, b2,..., b ) of length L, the initial state so is set as the last K bits of the message sequence, where K is the constraint length of the code. This ensures that after encoding the entire message sequence, the encoder naturally returnsto the state so, creating a circular trellis structure. To effectively decode such TB-CC, the LMAP decoding process is applied in a wrap-around manner with several key modifications to the method steps 604 and 606 for updating the forward and backward decoding registers values in method 600. These modifications include initializing all shift registers to 0 instead of the initialization to 1 prior to decoding. Further, decoding process itself requires multiple iterations, where each iteration processes the received sequence in a cyclical manner. Since TB-CC ensures the start state matches the final state, decoding is continuously performed from positions 1 to L, then seamlessly continuing from L+l to 2L, and so on until t iterations are completed. After these iterations, the register values from the final L time steps are used to compute the bi-directional LLR values.

[0139] When decoding TB-CC, the maximum number of iterations over the sequence is set to five. The simulation results in Fig. 11 show that the bi-directional LMAP achieves performance equivalent to the BCJR across the entire SNR range. While the tail-biting variant exhibits slightly lower performance compared to zerotailing, it maintains the performance equivalence between LMAP and BCJR implementations. This consistency across different termination schemes further validates the robustness of the LMAP decoding process.

[0140] The BLER performance of LMAP for tail -biting codes is evaluated against finite block length bounds for two different block lengths. As depicted in Fig. 12, for blocklength 64 with message length L = 32, the (5621,7173)octwith m = 11 TB-CC exhibits exceptional performance, closely approaching both the normal approximation (NA) and meta-converse bounds. Notably, the code surpasses the random coding union (RCU) bound by approximately 0.5 dB at a BLER of 10-3, demonstrating that well-designed TB-CCs can achieve near-optimal performance at this block length.

[0141] Fig. 13 extends the comparison to block length 128 with message length L=64. As shown, both the (45145, 77507)octand (51303, 73171)octTB-CCs with with m = 14 demonstrate strong error-correction capabilities, with the code (51303, 73171)octshowing superior performance at higher SNRs. Particularly, the (51303, 73171)octTB-CC outperforms the classical (128,64) BCH code across thehigh SNR range. These results underscore the significant advantages of well-designed TB-CCs for short blocklength applications.

[0142] The decoding efficiency advantage of LMAP over BCJR is quantified in Table 1 below, which presents decoding times across various code configurations, based on Matlab simulations. For the basic ( 1, -) RSC, LMAP demonstrates a 12- ' octtimes speed improvement over BCJR. This advantage becomes more significant for codes with higher memory order, reaching a remarkable 331 -times speedup for the ( 1, — ) RSC. The NSC implementations show similar efficiency gains, with speed \ 573 / 0Cimprovements of 73-times and 132-times for the (53,75)octand (171,133)octcodes, respectively. / 23\ I 7\( 1,- 1 RSC 1,— RSC (1,^) RSC' -’7 OC \ Zb / 0Cf V 573joctt AlgorithmTime (ms) Ratio Time (ms) Ratio Time (ms) Ratio LMAP 0.67 0.75 1.5812 43 331 8.16 32.30 523.18 BCJR(53, 75)octASC (5621, 7173) TB-CC (171, 133)octiVSCAlgorithmTime (ms) Ratio Time (ms) Ratio Time (ms) Ratio LMAP 0.857 0.96 20.1273 132 110 62.29 127.10 2231.75 BCJR

[0143] The relationship between decoding time and code memory order is illustrated in Fig. 14. While the BCJR algorithm shows clear exponential growth (as seen in trend 1402) in computation time with increasing memory order, LMAP maintains near-linear scaling up to memory order 9 (as seen in trend 1404). Beyond this point, LMAP does exhibit exponential behaviour, but with a much lower slope compared to BCJR. At memory order 11, LMAP requires approximately 12.6 ms for decoding, compared to 4272.6 ms for BCJR, representing a dramatic efficiency improvement while maintaining equivalent error-correction performance.

[0144] These results demonstrate that LMAP provides a competitive advantage to BCJR, particularly for high-memory convolutional codes where computational efficiency is crucial. The bi-directional variant of LMAP consistently matches the error-correction performance of BCJR, while maintaining substantial efficiency advantages across all code configurations.

[0145] It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text or drawings. All of these different combinations constitute various alternative aspects of the invention.

[0146] As used herein, except where the context requires otherwise, the term "comprise" and variations of the term, such as "comprising", "comprises" and "comprised", are not intended to exclude further additives, components, integers or steps.

Claims

1. CLAIMS1. A linear maximum a posteriori (LMAP) decoder for decoding rate ½ convolution codes, the decoder comprising:a soft-input soft-output (SISO) forward decoding module comprising a plurality of shift registers that generates forward decoding outputs; anda (SISO) backward decoding module comprising a plurality of shift registers that generates backward decoding outputs;wherein:the input to the LMAP decoder is soft symbol estimates (SSE) of received code symbols; anda bidirectional MAP decoding output is obtained by combining the forward decoding outputs and the backward decoding outputs.

2. The LMAP decoder of claim 1, wherein:the SISO forward decoding module comprises a first forward decoding dual encoder comprising N-l shift registers, where N is the number of states in a corresponding convolutional encoder and a second forward decoding dual encoder comprising N-l shift registers; andthe SISO backward decoding module comprises a first backward decoding dual encoder comprising N-l shift registers and a second backward decoding dual encoder comprising N-l shift registers.

3. The LMAP decoder of claim 2, wherein the first forward decoding dual encoder and the first backward decoding dual encoder each comprise a self-updating register.

4. The LMAP decoder of any one of claims 2-3, wherein the first forward decoding dual encoder and the second forward decoding dual encoder are associated withcorresponding first and second decoder polynomials that define connection coefficients of the first and second forward decoding dual encoders associated with the input.

5. The LMAP decoder of any one of claims 2-4, wherein the first backward decoding dual encoder and the second backward decoding dual encoder are associated with the corresponding third and fourth decoder polynomials that are the reverse polynomials of the first and second decoder polynomials, respectively.

6. The LMAP decoder of any one of claims 1-5, wherein the rate ½ convolutional code is a recursive systematic code (RSC) or a non-systematic code (NSC).

7. The LMAP decoder of claim 6, wherein the RSC or the NSC is generated by a code generator polynomial.

8. The LMAP decoder of claim 7, wherein the first and second decoder polynomials and the third and fourth decoder polynomials are derived from the code generator polynomial.

9. The LMAP decoder of any one of claims 2-8, wherein the shift registers in the first and second forward dual encoders include a sequence of register labels, wherein each register label represents a set of encoder memory indices used by the corresponding shift register.

10. The LMAP decoder of claim 9, wherein the sequence of register labels of the second forward dual encoder is generated by a recursive label synthesizer having a plurality of shift registers having the same connection coefficients as the second forward dual encoder and including symmetric difference operations between the plurality of shift registers.

11. The LMAP decoder of claim 10, wherein the sequence of register labels of the first forward dual encoder excluding the self-updating register is generated based on the sequence of register labels of the second forward dual encoder.

12. The LMAP decoder of claim 10 or 11, wherein the register label of the selfupdating register is determined by comparing the sequence of register labels of the first forward dual encoder and second forward dual encoder and identifying a unique register label that appears only in the sequence of register labels of the second forward dual encoder.

13. The LMAP decoder of claim 12, wherein a connection coefficient of the selfupdating register is determined based on the register label of the self-updating register.

14. The LMAP decoder of any one of claims 9-13, wherein the each of the shift registers in the first and second backward dual encoders includes register label, a sequence of the register labels in the first and second backward dual encoders being the reverse of the sequence of the register labels in the first and second forward dual encoders, respectively.

15. A linear maximum a posteriori (LMAP) decoding method, the method comprising:obtaining the LMAP decoder of any one of claims 1-14;initializing register labels of each of the shift registers in the LMAP decoder to 1; inputting soft symbol estimates (SSE) of received code symbols to the LMAP decoder;updating register values of the plurality of shift registers in the forward decoding module for each time k based on the SSE of the received code symbols;updating register values of the plurality of shift registers in the backward decoding module for each time k in reverse temporal order; anddetermining bidirectional LLR of an input binary code based on the updated register values.

16. The LMAP decoding method of claim 15, wherein updating the register values of the plurality of shift registers in the forward decoding module for each time k comprises:updating register values of the N-l shift registers in the first forward dual encoder; updating register values of the N-l shift registers in the second forward dual encoder; combining register values of the first and second forward dual encoders; and updating the register values of the first and second forward dual encoders based on the combined register values.

17. The LMAP decoding method of claim 16, wherein updating the register values of the plurality of shift registers in the backward decoding module for each time k comprises:updating register values of the N-l shift registers in the first backward dual encoder in reverse temporal order;updating register values of the N-l shift registers in the second backward dual encoder in reverse temporal order;combining register values of the first and second backward dual encoders; and updating the register values of the first and second backward dual encoders based on the combined register values.

18. The method of any one of claims 15-17, wherein generating the bidirectional decoding output further comprising performing an additional register label mapping for a NSC.

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