Display panel and display apparatus

Abstract

A display panel, comprising: a substrate (10), and a plurality of first wires (111), a plurality of second wires (112), light emitting units (21) and functional chips (30) disposed on the substrate (10). The number of the light emitting units (21) is not less than twice the number of the functional chips (30). The plurality of first wires (111) are disposed in a same layer and extend along a first direction (D1). The functional chips (30) comprise: first-type pins (311) and second-type pins (321). Some of the first-type pins (311) are connected to the first wires (111), and the others of the first-type pins (311) are connected to the light emitting units (21). The second-type pins (321) achieve connection of two first wires (111) by means of the second wires (112).

Description

Display panel and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Micro LEDs and mini LEDs have advantages such as small size and high brightness. Display devices using these light-emitting devices are mainly used in augmented reality (AR), virtual reality (VR), television (TV), and outdoor displays. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This embodiment provides a display panel and a display device, which can reduce the cost of the display panel.

[0005] On one hand, this embodiment provides a display panel, including: a substrate, a plurality of first traces, a plurality of second traces disposed on the substrate, light-emitting units, and functional chips. The number of light-emitting units is not less than twice the number of functional chips. The plurality of first traces are disposed on the same layer and extend along a first direction. The functional chip includes: a first type of pins and a second type of pins; some of the first type of pins are connected to the first traces, and others of the first type of pins are connected to the light-emitting units, and the second type of pins connect two first traces through the second traces.

[0006] In some exemplary embodiments, the functional chip includes: a first functional chip and a second functional chip, wherein the first functional chip includes the first type of pins and the second functional chip includes the second type of pins.

[0007] In some exemplary embodiments, the second functional chip includes a first substrate, the plurality of second traces are located on the first substrate, and the second type of pins are located on the side of the plurality of second traces away from the first substrate.

[0008] In some exemplary embodiments, the substrate includes a bonding region, and the second functional chip is located on a side away from the bonding region in the first direction.

[0009] In some exemplary embodiments, the functional chip includes a first functional chip and a third functional chip, wherein the first functional chip includes the first type of pins and the third functional chip includes the first type of pins and the second type of pins.

[0010] In some exemplary embodiments, the second type of pins of the third functional chip are located around the first type of pins along a second direction, and the second direction intersects the first direction.

[0011] In some exemplary embodiments, the substrate includes a bonding region, and the third functional chip is located on a side away from the bonding region in the first direction.

[0012] In some exemplary embodiments, the substrate includes a first surface and a second surface disposed opposite to each other, the light-emitting unit and the functional chip being located on the first surface, and the bonding area being located on the second surface. The display panel further includes a side connection line configured to connect at least one first trace located on the first surface to the bonding area.

[0013] In some exemplary embodiments, the plurality of second traces are disposed on the same layer as the plurality of first traces.

[0014] In some exemplary embodiments, the functional chip further includes: a plurality of pixel circuits and at least one shift register circuit group; the at least one shift register circuit group is configured to provide pixel control signals to the plurality of pixel circuits, the at least one shift register circuit group and the plurality of pixel circuits are configured to be connected to the first trace through some of the first type of pins, and the plurality of pixel circuits are configured to be connected to the light-emitting unit through others of the first type of pins.

[0015] In some exemplary embodiments, the display panel further includes: a first connection electrode disposed on the substrate, wherein the first type of pin is connected to the first trace or the light-emitting unit through the first connection electrode; the first connection electrode and the plurality of first traces are in the same layer.

[0016] In some exemplary embodiments, the number of first traces arranged in the gap between two adjacent first connecting electrodes along the second direction is less than or equal to two, and the second direction intersects the first direction.

[0017] In some exemplary embodiments, the display panel further includes: a second connection electrode disposed on the substrate, the light-emitting unit being connected to other pins of the first type via the second connection electrode, and the minimum distance between the second connection electrode and the adjacent first connection electrode along the second direction being greater than or equal to 100 micrometers.

[0018] In some exemplary embodiments, the first type of pin of the functional chip connected to the light-emitting unit is adjacent to the light-emitting unit in a second direction, and the second type of pin is located on one side of the first type of pin connected to the light-emitting unit in the first direction, and the second direction intersects the first direction.

[0019] In some exemplary embodiments, the functional chip further includes a third type of pin, which is configured to form an array arrangement with at least one of the first type of pin and the second type of pin.

[0020] In some exemplary embodiments, the light-emitting unit includes multiple light-emitting elements that emit light of different colors.

[0021] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0022] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects will become clear.

[0023] Overview of the attached figures

[0024] The accompanying drawings are used to provide an understanding of the technical solutions disclosed herein and form part of the specification. They are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure and do not constitute a limitation on the technical solutions of the present disclosure.

[0025] Figure 1 is a partial perspective view of a display panel according to at least one embodiment of the present disclosure;

[0026] Figure 2 is a partial plan view of a display panel according to at least one embodiment of the present disclosure;

[0027] Figure 3 is a partial planar schematic diagram of a substrate according to at least one embodiment of the present disclosure;

[0028] Figure 4 is a partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0029] Figure 5 is a schematic diagram of the connection electrodes of the first connection region and the second connection region of the substrate in at least one embodiment of the present disclosure;

[0030] Figure 6 is a pin diagram of a first functional chip according to at least one embodiment of the present disclosure;

[0031] Figure 7 is a schematic diagram of the architecture of a first functional chip according to at least one embodiment of the present disclosure;

[0032] Figure 8A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0033] Figure 8B is a circuit diagram of another pixel circuit according to at least one embodiment of the present disclosure;

[0034] Figure 9 is a circuit diagram of a first shift register circuit according to at least one embodiment of the present disclosure;

[0035] Figure 10 is a circuit diagram of a second shift register circuit according to at least one embodiment of the present disclosure;

[0036] Figure 11 is a plan view of the first peripheral region of a substrate according to at least one embodiment of the present disclosure;

[0037] Figure 12 is a plan view of a second functional chip according to at least one embodiment of the present disclosure;

[0038] Figure 13 is another partial plan view of a display panel according to at least one embodiment of the present disclosure;

[0039] Figure 14 is a schematic diagram of the connection electrodes of the first connection region and the second connection region in at least one embodiment of the present disclosure;

[0040] Figure 15 is a pin diagram of a third functional chip according to at least one embodiment of the present disclosure;

[0041] Figure 16 is another partial plan view of a display panel according to at least one embodiment of the present disclosure;

[0042] Figure 17 is a schematic diagram of another connection electrode of the first connection region and the second connection region in at least one embodiment of the present disclosure;

[0043] Figure 18 is a pin diagram of a functional chip according to at least one embodiment of the present disclosure;

[0044] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0045] Detailed Explanation

[0046] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0047] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0048] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0049] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0050] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "coupling" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or link; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Connection" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0051] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0052] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0053] In this specification, "approximately" and "about" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" includes values ​​differing by less than 10%, such as values ​​differing by less than 5%.

[0054] Light-emitting diodes (LEDs) are widely used in various product fields requiring high brightness and often operating in harsh outdoor environments due to their advantages such as high brightness, high reliability, adjustable color temperature, environmental friendliness, long lifespan, and low power consumption. With technological advancements, the size of LEDs used in these fields is becoming increasingly smaller, reaching the micro-LED range of less than 50 micrometers (µm).

[0055] In some implementations, during the fabrication of the display panel, an active matrix (AM) backplane is first fabricated, and then the light-emitting diodes are transferred and bonded to the AM backplane. When the spacing between the driving circuits of the display backplane is large, the space utilization of the display backplane is low, which can easily lead to increased costs.

[0056] This embodiment provides a display panel, including: a substrate, a plurality of first traces, a plurality of second traces disposed on the substrate, light-emitting units, and functional chips. The number of light-emitting units is not less than twice the number of functional chips. The plurality of first traces are disposed on the same layer and extend along a first direction. The functional chip includes: first type pins and second type pins. Some of the first type pins are connected to the first traces, and others of the first type pins are connected to the light-emitting units. The second type pins connect two first traces through the second traces.

[0057] The display panel provided in this embodiment uses a passive matrix (PM) substrate, on which the light-emitting units and functional chips are mounted. The first type of pins of the relatively small functional chip are used to drive the light-emitting units, which helps improve substrate utilization and reduce the manufacturing cost of the display panel. Furthermore, signal transmission between the two first traces is achieved through the second traces and the second type of pins of the functional chip, ensuring that signal transmission across the entire surface can be achieved with only a single trace layer on the substrate, further reducing manufacturing costs.

[0058] In some exemplary embodiments, the functional chip may include a first functional chip and a second functional chip. The first functional chip may include a first type of pins, and the second functional chip may include a second type of pins. For example, the first functional chip may include only the first type of pins, and the second functional chip may include only the second type of pins. In this example, the first functional chip drives the light-emitting unit to emit light, and the second type of pins, which realize signal transmission between the first traces, are separately set in the second functional chip. This ensures that signal transmission can be achieved by setting only a single trace layer on the substrate, thereby helping to reduce manufacturing costs.

[0059] In some exemplary embodiments, the functional chip may include a first functional chip and a third functional chip. The first functional chip may include a first type of pins, and the third functional chip may include a first type of pin and a second type of pins. In this example, the third functional chip can not only drive the light-emitting unit to emit light, but also realize signal transmission between the first traces. This ensures that signal transmission can be achieved by setting only a single trace layer on the substrate, thereby helping to reduce manufacturing costs.

[0060] In some exemplary embodiments, the functional chip may further include a third type of pins. The third type of pins may be configured to form an array arrangement with at least one of the first type of pins and the second type of pins. By setting the third type of pins so that the pins of the functional chip are arranged in an array, it is beneficial to ensure the connection stability between the functional chip and the substrate.

[0061] The following examples illustrate the solution of this embodiment.

[0062] Figure 1 is a partial perspective view of a display panel according to at least one embodiment of the present disclosure. Figure 2 is a partial plan view of a display panel according to at least one embodiment of the present disclosure. Figure 3 is a partial plan view of a substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figures 1 to 3, the display panel may include: a substrate 10, a light-emitting unit 21 disposed on the substrate 10, and a functional chip 30. The functional chip 30 may include a first functional chip 31 and a second functional chip 32. Figure 1 mainly illustrates the positional relationship between the light-emitting unit 21 and the functional chip 30 on the substrate 10. It can be understood that the first functional chip 31 is connected to the light-emitting unit 21 and the first trace 111, and the first trace 111 is connected to the side connection line 15.

[0063] The substrate 10 can be a rigid substrate, such as a glass substrate; or the substrate 10 can be a flexible substrate, such as a polyimide (PI) substrate.

[0064] In some examples, the substrate 10 may include: an effective region AA, a first peripheral region B1 located on opposite sides of the effective region AA along a first direction D1, and a second peripheral region B2. The effective region AA may be rectangular. In other examples, the effective region AA may be circular, elliptical, or other shapes.

[0065] In some examples, the light-emitting unit 21 and the first functional chip 31 can be located in the effective area AA. The first functional chip 31 can be configured to drive the light-emitting unit 21 to emit light. The number of light-emitting units 21 can be no less than twice the number of first functional chips 31. One first functional chip 31 can be configured to drive at least two light-emitting units 21 to emit light. For example, one first functional chip 31 can be configured to drive four light-emitting units 21 to emit light.

[0066] In some examples, the second functional chip 32 may be located in the first peripheral region B1. Multiple second functional chips 32 disposed in the first peripheral region B1 may be arranged along a second direction D2. The second direction D2 intersects the first direction D1 and is parallel to the plane containing the substrate 10; for example, the second direction D2 may be perpendicular to the first direction D1. In other examples, the first peripheral region B1 may contain only one second functional chip 32.

[0067] In some examples, as shown in Figure 3, the effective area AA may include multiple first connecting areas A1 and multiple second connecting areas A2. The first connecting areas A1 and the second connecting areas A2 may be approximately rectangular. In other examples, the first connecting areas A1 and the second connecting areas A2 may be circular, elliptical, or other shapes. This embodiment does not limit the number of first connecting areas A1 and second connecting areas A2.

[0068] In some examples, at least one first connection region A1 may be provided with at least one light-emitting unit 21; for example, each first connection region A1 may be provided with one light-emitting unit 21. At least one second connection region A2 may be provided with at least one first functional chip 31; for example, each second connection region A2 may be provided with one first functional chip 31. In other examples, at least one first connection region A1 may be provided with multiple light-emitting units 21; and at least one second connection region A2 may be provided with multiple first functional chips 31.

[0069] In some examples, multiple first connection regions A1 can be arranged in an array along a first direction D1 and a second direction D2. Multiple first connection regions A1 arranged sequentially along the first direction D1 can form a column of first connection regions, and multiple first connection regions A1 arranged sequentially along the second direction D2 can form a row of first connection regions. The second direction D2 can also be referred to as the row direction, and the first direction D1 can also be referred to as the column direction.

[0070] In some examples, multiple second connecting regions A2 can be arranged in an array along a first direction D1 and a second direction D2. Multiple second connecting regions A2 arranged sequentially along the first direction D1 can form a column of second connecting regions, and multiple second connecting regions A2 arranged sequentially along the second direction D2 can form a row of second connecting regions. Multiple second connecting regions A2 can be positioned between multiple first connecting regions A1. For example, multiple second connecting regions A2 can be staggered with multiple first connecting regions A1 along the first direction D1 and the second direction D2. For example, a row of second connecting regions can be located between two adjacent rows of first connecting regions, and a column of second connecting regions can be located between two adjacent columns of first connecting regions. A column of second connecting regions can be positioned between the i-th column and the (i+1)-th column of first connecting regions, where i can be an odd number or an even number. In other examples, a row of second connecting regions can be positioned between every two adjacent rows of first connecting regions; or, a column of second connecting regions can be located between two adjacent columns of first connecting regions and aligned with the first connecting regions A1 along the second direction D2. This embodiment is not limited in this respect.

[0071] In some examples, the first peripheral region B1 may include a plurality of third connecting regions B10 arranged sequentially along the second direction D2. For example, the third connecting regions B10 may be aligned with a column of first connecting regions along the first direction D1, or the orthographic projection of the third connecting regions B10 on the second direction D2 may be located between two adjacent columns of first connecting regions. At least one third connecting region B10 may be provided with at least one second functional chip 32; for example, each third connecting region B10 may be provided with one second functional chip 32. In other examples, the first peripheral region B1 may include a third connecting region B10, which may be provided with one second functional chip 32.

[0072] In some examples, as shown in Figures 1 and 2, the display panel may further include multiple sets of first traces 11 disposed on the substrate 10. The multiple sets of first traces 11 may be disposed on the same layer. Each set of first traces 11 may include multiple first traces 111 extending along a first direction D1 within the effective region AA. The multiple sets of first traces 11 may be spaced apart along a second direction D2. At least one set of first traces 11 may be configured to transmit signals to multiple first functional chips 31 arranged along the first direction D1, and at least two adjacent sets of first traces 11 may be configured to be electrically connected through at least one second functional chip 32 in a first peripheral region B1.

[0073] The positions of the multiple sets of first traces 11 in Figures 1 and 2 are for illustrative purposes only. Among the multiple first traces 111 belonging to the same set of first traces 111, the orthographic projection of some first traces 111 on the substrate 10 may overlap with the orthographic projection of the functional chip 30 connected to it on the substrate 10, while other first traces 111 and functional chips 30 may be arranged at intervals. This embodiment does not limit this.

[0074] Figure 4 is a partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure. The third direction D3 is perpendicular to the plane containing the first direction D1 and the second direction D2. The substrate 10 may include a first surface 10a and a second surface 10b disposed opposite each other along the third direction D3. The effective area AA, the first peripheral area B1, and the second peripheral area B2 may all be located on the first surface 10a, and the bonding area of ​​the substrate 10 may be located on the second surface 10b. The bonding area may house a driver chip 40. The first surface 10a may also be referred to as the display surface of the display panel, and the second surface 10b may also be referred to as the non-display surface or back surface of the display panel.

[0075] In some examples, as shown in Figures 1 and 4, the display panel may further include side connection lines 15 located in the second peripheral region B2. The side connection lines 15 may be configured to connect at least one first trace 111 of the first surface 10a to a bonding area of ​​the second surface 10b. The surface of the side connection lines 15 away from the substrate 10 may be covered by a protective layer 20. For example, multiple side connection lines 15 may be connected to at least one set of first traces 11 extending from the effective region AA. These multiple side connection lines 15 may extend from the second peripheral region B2 to the bonding area of ​​the second surface 10b and connect to a driver chip 40 located in the bonding area, thereby achieving an electrical connection between at least one set of first traces 11 and the driver chip (e.g., an integrated circuit (IC)). The driver chip 40 may be configured to provide various signals, such as data signals, clock signals, and power signals, to multiple first functional chips 31 within the effective region AA via the multiple side connection lines 15 and at least one set of first traces 11. In other examples, the bonding area may be located on the first side of the substrate, the second peripheral area B2 may serve as the bonding area, the driver chip may be disposed in the second peripheral area B2 and electrically connected to at least one set of first traces 11 extending to the second peripheral area B2.

[0076] In some examples, in a direction perpendicular to the display panel (e.g., third direction D3), the display panel may include: a first conductive layer, a first insulating layer, and a second conductive layer sequentially disposed on the substrate 10. Multiple first traces 111 may be located on the first conductive layer, and multiple side connection lines 15 may be located on the second conductive layer. The first insulating layer may have multiple vias exposing portions of the surface of the first conductive layer, such that portions of the first conductive layer exposed in the first connection region A1 can be bonded to the light-emitting unit 21, portions of the first conductive layer exposed in the second connection region A2 can be bonded to the first functional chip 31, portions of the first conductive layer exposed in the first peripheral region B1 can be bonded to the second functional chip 32, and portions of the first conductive layer exposed in the second peripheral region B2 can be connected to the second conductive layer. For example, the materials of the first and second conductive layers may be metallic. The material of the first insulating layer may include an inorganic insulating material. The first insulating layer may also be referred to as a passivation layer.

[0077] In some examples, during the fabrication of the display panel, a substrate is provided, a metal material is deposited on the substrate, and the metal material is patterned using a patterning process to form a first conductive layer; subsequently, a first insulating material is deposited, and the first insulating material is patterned to form a first insulating layer. The first insulating layer may have multiple vias. The light-emitting unit 21, the first functional chip 31, and the second functional chip 32 are transferred and bonded to the substrate 10 using a mass transfer process, and connected to the corresponding exposed portions of the first conductive layer. Black adhesive is applied to the chip surface to prevent the chip from reflecting ambient light and affecting the overall display effect. A second conductive layer, including multiple side connection lines 15, is formed in the second peripheral region B2 using a chemical gold process.

[0078] The "patterning process" described in this example includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic, inorganic, or transparent conductive materials; and for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; and etching can be performed using any one or more of dry and wet etching. This embodiment does not impose any limitations.

[0079] Figure 5 is a schematic diagram of the connection electrodes of the first connection region and the second connection region of the substrate in at least one embodiment of the present disclosure. Figure 6 is a schematic diagram of the pins of the first functional chip in at least one embodiment of the present disclosure. In some examples, as shown in Figure 5, a second connection region A2 may be located in the middle of four first connection regions A1 arranged in a 2×2 array. The first functional chip disposed in the second connection region A2 may be configured to drive the light-emitting units disposed in the four first connection regions A1. The first conductive layer may include: a plurality of first traces 111, a plurality of third traces 113, a plurality of second connection electrodes 210 located in the first connection region A1, and a plurality of first connection electrodes 310 located in the second connection region A2.

[0080] In some examples, the light-emitting unit 21 disposed in the first connection region A1 can be connected to a plurality of second connection electrodes 210. The plurality of second connection electrodes 210 can be configured to be connected to some first connection electrodes 310 in the second connection region A2 via a plurality of third traces 113. The plurality of second connection electrodes 210 in the first connection region A1 can be arranged in an array along a first direction D1 and a second direction D2, for example, in a three-row, two-column arrangement. The orthographic projection of a single second connection electrode 210 on the substrate 10 can be approximately rectangular.

[0081] In some examples, a single first connection area A1 can correspond to one light-emitting unit 21. A light-emitting unit 21 can include three light-emitting elements emitting different colors of light, such as a first light-emitting element emitting a first color of light, a second light-emitting element emitting a second color of light, and a third light-emitting element emitting a third color of light. The first color of light can be red, the second color of light can be green, and the third color of light can be blue. For example, the light-emitting unit 21 can include a blue LED, and red and green quantum dot materials located above a portion of the blue LED. The blue light emitted by the blue LED passes through the quantum dot film, and some of the blue light can be converted into red and green light. The unconverted blue light can mix with the red and green light emitted by the quantum dot film to form high-quality white light, thereby improving the color gamut and color performance of the display panel. In other examples, a single first connection area A1 can correspond to multiple light-emitting units, and each light-emitting unit can be configured to emit one color of light.

[0082] In some examples, the light-emitting unit 21 may include three light-emitting elements, three first light-emitting pins, and three second light-emitting pins. The first electrode (e.g., anode) of each light-emitting element may be connected to one first light-emitting pin, and the second electrode (e.g., cathode) of each light-emitting element may be connected to one second light-emitting pin. The three first light-emitting pins and the three second light-emitting pins may be electrically connected one-to-one with six second connection electrodes 210 arrayed within the first connection region A1. For example, the three second connection electrodes 210 connected to the three second light-emitting pins may be a single integrated structure, configured to receive the same power signal (e.g., a second power signal).

[0083] In some examples, as shown in FIG5, a plurality of first connection electrodes 310 in the second connection region A2 can be arranged in an array along a first direction D1 and a second direction D2. The orthographic projection of a single first connection electrode 310 on the substrate 10 can be approximately rectangular. The plurality of first connection electrodes 310 may include a plurality of first-type connection electrodes 310-1 and a plurality of second-type connection electrodes 310-2. The plurality of first-type connection electrodes 310-1 can be configured to transmit signals (e.g., clock signals, power signals, data signals, cascaded signals, etc.) to the first functional chip 31, and the plurality of second-type connection electrodes 310-2 can be configured to output driving signals generated by the first functional chip 31, the driving signals being used to drive the light-emitting unit 21 to emit light. The plurality of second-type connection electrodes 310-2 can, for example, be located on the periphery of the plurality of first-type connection electrodes 310-1. For example, the second-type connection electrodes 310-2 can be located on the side of the first-type connection electrodes 310-1 closer to the second connection electrode 210.

[0084] In some examples, as shown in Figure 6, the first functional chip 31 may include a first type of pin 311. The first type of pin 311 may include a first driving pin 311-1 and a second driving pin 311-2. The pins of the first functional chip 31 may be electrically connected to the first connection electrode 310 of the second connection region A2. Specifically, the first driving pin 311-1 can be connected to the first trace 111 via the first type of connection electrode 310-1, and the second driving pin 311-2 can be connected to the light-emitting unit 21 via the second type of connection electrode 310-2, the third trace 113, and the second connection electrode 210. The first type of connection electrode 310-1 and the connected first trace 111 can be an integral structure, and the second type of connection electrode 310-2, the connected third trace 113, and the second connection electrode 210 can be an integral structure.

[0085] In some examples, the second driving pin 311-2 in the first type of pin 311 can be configured to provide a driving signal to the light-emitting unit 21, and the first driving pin 311-1 in the first type of pin 311 can be configured to transmit signals of the first trace 111 (such as clock signals, power signals, data signals, cascaded signals, etc.).

[0086] In some examples, as shown in Figure 6, the first functional chip 31 may also include a third type of pin 313. The third type of pin 313 can be configured to form an array arrangement with the first type of pin 311, thereby improving the connection stability between the first functional chip 31 and the substrate 10. After determining the number X1 of the first type of pins 311 of the first functional chip 31, when determining the number of rows H1 and columns L1 of the first type of pins 311 arranged in the array, the number of rows H1 and columns L1 whose product is closest to X1 can be obtained under the condition that the absolute value of the difference between the number of rows H1 and the number of columns L1 is not greater than k (for example, k can be 4 or 5). Then, the number of third type pins can be H1×L1-X1. Here, H1, L1, and X1 are all positive integers. After determining the position of the first type of pins 311, the third type of pin 313 can be placed in the vacant positions in the pin array. Taking the pin array of the first functional chip shown in Figure 6 as an example, the pins of the first functional chip can be arranged in eight rows and six columns. In a row, the second driving pin 311-2 of the first type of pins 311 can be located on both sides of the first driving pin 311-1 along the second direction D2. For example, the middle four pins of a row are the first driving pins 311-1, and the pins at both ends are the second driving pins 311-2. If there is at least one second driving pin 311-2 in the middle position of the last row, then the remaining positions of the row can be filled with third type pins 313. In some other examples, when the number of first type pins X1 of the first functional chip is the same as the product of the number of rows H1 and the number of columns L1, the third type of pins can be omitted from the first functional chip.

[0087] In some examples, as shown in Figures 1, 2, and 5, multiple first traces 111 extending along the first direction D1 within the effective area AA are arranged in the same layer, for example, they can all be located in the first conductive layer. Figure 5 only illustrates several first traces 111 as an example. Multiple sets of first traces 11 can be arranged at intervals along the second direction D2 and multiple columns of first connection areas A1. Multiple sets of first traces 11 can extend along the first direction D1 to the first peripheral area B1, and at least one set of first traces 11 can extend along the first direction D1 to the second peripheral area B2. Two adjacent sets of first traces 11 can be configured to be connected in the first peripheral area B1 through at least one second functional chip 32. At least one set of first traces 11 can be configured to transmit signals to multiple first functional chips 31 arranged along the first direction D1. At least one set of first traces 11 can be connected to multiple first-type connection electrodes 310-1 in multiple second connection areas A2 arranged along the first direction D1, configured to transmit signals to the first functional chips 31. Among them, at least one of the first traces 111 in a group of first traces 11 can be integrated with the first type of connection electrode 310-1 that transmits the same signal in multiple second connection regions A2 arranged along the first direction D1, so as to realize signal transmission along the first direction D1.

[0088] In some examples, as shown in Figure 5, multiple first traces 111 within a group of first traces 11 can pass through the gaps between multiple first connection electrodes 310 along a first direction D1, thereby transmitting signals between adjacent first functional chips 31 along the first direction D1. Adjacent first connection electrodes 310 within the second connection region A2 can have a first spacing U1 in the second direction D2. The first spacing U1 can satisfy the requirement that the space for arrangement is less than or equal to that of two first traces 111, so as to avoid short circuits caused by trace crossing.

[0089] In some examples, the minimum distance U2 between the first connection electrode 310 in the second connection region A2 and the second connection electrode 210 in the adjacent first connection region A1 can be greater than or equal to 100 micrometers, thereby avoiding the reflection of the first functional chip 31 from affecting the luminous efficiency of the light-emitting unit 21.

[0090] In some examples, the first functional chip 31 may further include: multiple pixel circuits and at least one shift register circuit group. The at least one shift register circuit group is connected to the multiple pixel circuits and configured to provide pixel control signals (e.g., scan signals, reset control signals, and light emission control signals) to the multiple pixel circuits. The multiple pixel circuits may be configured to provide drive signals to the light emission unit 21 via the second drive pin 311-2 in the first type of pin 311 to drive the light emission unit 21 to emit light. For example, one first functional chip 31 may be configured to drive four light emission units 21 to emit light. In other examples, the first functional chip 31 may further include a multiplexing control circuit (MUX), which may be configured to provide data signals to the multiple pixel circuits.

[0091] In some examples, the first driving pin 311-2 in the first type of pins 311 of the first functional chip 31 can be connected to multiple pixel circuits and to the second type of connection electrode 310-2 in the second connection area A2. It is then connected to the light-emitting unit 21 via the third trace 113 and the second connection electrode 210, thereby providing a driving signal to the light-emitting unit 21. The first driving pin 311-1 in the first type of pins 311 can be connected to the signal terminals of multiple pixel circuits and at least one shift register circuit group, configured to transmit signals required by the first functional chip 31, such as transmitting data signals, initial signals, and first power signals to multiple pixel circuits, and transmitting clock signals, cascade signals, and power signals to at least one shift register circuit group.

[0092] In some examples, the first functional chip 31 may include a second substrate, which may be a glass substrate. During the fabrication of the first functional chip 31, multiple circuits can be fabricated on the second substrate using various process technologies such as LTPS and LTPO, followed by the fabrication of multiple pins, and then laser cutting can be used to form multiple first functional chips 31.

[0093] In some examples, to ensure the contact area between the first connection electrode and the pin of the first functional chip 31 within the second connection region A2, the dimensions of the first functional chip 31 can satisfy the following relationship: Sin5°×(((w×m+(m-1)×c)×1 / 2) 2 +((h×n+(n-1)×c)×1 / 2) 2 ) 1 / 2 ) < h;

[0094] Where w is the width of the pins of the first functional chip (e.g., the length along the second direction D2), h is the length of the pins (e.g., the length along the first direction D1), c is the spacing between adjacent pins (e.g., the spacing along the first direction D1 and the second direction D2 is the same), m is the number of driving pins along the first direction D1, and n is the number of driving pins along the first direction. During the transfer of the first functional chip to the substrate, the arrangement of the first functional chip on the transfer base film has a rotation angle of less than or equal to 5 degrees.

[0095] Figure 7 is a schematic diagram of the architecture of a first functional chip according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 7, the first functional chip may include: multiple sets (e.g., more than or equal to 3 sets) of pixel circuits and multiple shift register circuit groups (e.g., including a first shift register circuit group and a second shift register circuit group). The first shift register circuit group may include: n first shift register circuits GOA, where n is an integer greater than or equal to 3; the second shift register circuit group may include: at least one second shift register circuit EOA. Figure 7 illustrates an example of a first functional chip driving four light-emitting units (including 12 light-emitting elements). The first functional chip may include six (i.e., n=6) cascaded first shift register circuits GOA, one second shift register circuit EOA, and four sets of pixel circuits (including 12 pixel circuits, such as pixel circuits R11, G11, B11, R12, G12, B12, R21, G21, B21, R22, G22, and B22).

[0096] In some examples, as shown in Figure 7, each pixel circuit can be configured to provide a driving signal to a light-emitting element. The 12 pixel circuits can be divided into four groups, and each group of pixel circuits can drive one light-emitting unit. For example, combining Figures 5 and 7, pixel circuits R11, G11, and B11 can be a group, configured to provide a driving signal to the light-emitting unit on the upper left side of the second connection area A2 where the first functional chip is located; pixel circuits R12, G12, and B12 can be a group, configured to provide a driving signal to the light-emitting unit on the upper right side of the second connection area A2 where the first functional chip is located; pixel circuits R21, G21, and B21 can be a group, configured to provide a driving signal to the light-emitting unit on the lower left side of the second connection area A2 where the first functional chip is located; and pixel circuits R22, G22, and B22 can be a group, configured to provide a driving signal to the light-emitting unit on the lower right side of the second connection area A2 where the first functional chip is located. Pixel circuits R11, R12, R21, and R22 can be configured to provide driving signals to the corresponding first light-emitting element, pixel circuits G11, G12, G21, and G22 can be configured to provide driving signals to the corresponding second light-emitting element, and pixel circuits B11, B12, B21, and B22 can be configured to provide driving signals to the corresponding third light-emitting element.

[0097] In some examples, the four groups of pixel circuits can be arranged in an array. For instance, the three pixel circuits in each group can be arranged in the same way, and the four groups of pixel circuits can be arranged in a 2×2 array. Pixel circuits located in the same row can receive the same data signal. For example, pixel circuits R11, G11, B11, R12, G12, and B12 can all be connected to the first data terminal DL1; pixel circuits R21, G21, B21, R22, G22, and B22 can all be connected to the second data terminal DL2. Pixel circuits located in the same column can receive the same scan signal. For example, pixel circuits R11 and R21 can be connected to the same scan line. All pixel circuits of the first functional chip can be connected to the same initial signal terminal INIT and the first power supply terminal VDD.

[0098] The first type of pins of the first functional chip will be illustrated below with examples of pixel circuits, the first shift register circuit, and the second shift register circuit.

[0099] Figure 8A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. As shown in Figure 8A, the pixel circuit can be an 11T3C structure, including first transistors T1 to eleventh transistors T11, and first capacitors C1 to third capacitors C3. The third transistor T3 can be a driving transistor. The gate of the third transistor T3 can be electrically connected to the first pixel node P1, the first terminal of the third transistor T3 can be electrically connected to the second pixel node P2, and the second terminal of the third transistor T3 can be electrically connected to the third pixel node P3. The gate of the second transistor T2 can be electrically connected to the scan line GL, the first terminal of the second transistor T2 can be electrically connected to the third pixel node P3, and the second terminal of the second transistor T2 can be electrically connected to the first pixel node P1. The gate of the first transistor T1 can be electrically connected to the first reset control terminal RST1, the first terminal of the first transistor T1 can be electrically connected to the initial signal terminal INIT, and the second terminal of the first transistor T1 can be electrically connected to the first pixel node P1. The gate of the fourth transistor T4 can be electrically connected to the scan line GL, the first terminal of the fourth transistor T4 can be electrically connected to the data terminal DL, and the second terminal of the fourth transistor T4 can be electrically connected to the second pixel node P2. The gate of the fifth transistor T5 can be electrically connected to the light emission control terminal EM, the first terminal of the fifth transistor T5 can be electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 can be electrically connected to the second pixel node P2. The gate of the sixth transistor T6 can be electrically connected to the fifth pixel node P5, the first terminal of the sixth transistor T6 can be electrically connected to the third pixel node P3, and the second terminal of the sixth transistor T6 can be electrically connected to the fourth pixel node P4. The gate of the seventh transistor T7 can be electrically connected to the first reset control terminal RST1, the first terminal of the seventh transistor T7 can be electrically connected to the initial signal terminal INIT, and the second terminal of the seventh transistor T7 can be electrically connected to the fourth pixel node P4.

[0100] In some examples, the gate of the eighth transistor T8 can be electrically connected to the second reset control terminal RST2, the first terminal of the eighth transistor T8 can be electrically connected to the data terminal DL, and the second terminal of the eighth transistor T8 can be electrically connected to the gate of the ninth transistor T9. The first terminal of the ninth transistor T9 can be electrically connected to the light emission control terminal EM, and the second terminal of the ninth transistor T9 can be electrically connected to the fifth pixel node P5. The gate of the tenth transistor T10 can be electrically connected to the first reset control terminal RST1, the first terminal of the tenth transistor T10 can be electrically connected to the data terminal DL, and the second terminal of the tenth transistor T10 can be electrically connected to the gate of the eleventh transistor T11. The first terminal of the eleventh transistor T11 can be electrically connected to the first control terminal HF, and the second terminal of the eleventh transistor T11 can be electrically connected to the fifth pixel node P5.

[0101] In some examples, the first electrode of the first capacitor C1 is electrically connected to the first power supply terminal VDD, and the second electrode of the first capacitor C1 is electrically connected to the first pixel node P1. The first electrode of the second capacitor C2 is electrically connected to the initial signal terminal INIT, and the second electrode of the second capacitor C2 is electrically connected to the gate of the ninth transistor T9. The first electrode of the third capacitor C3 is electrically connected to the initial signal terminal INIT, and the second electrode of the third capacitor C3 is electrically connected to the gate of the eleventh transistor T11.

[0102] In some examples, pixel circuits located in the same column within the first functional chip are connected to the same scan line GL, the same first reset control terminal RST1, and the same second reset control terminal RST2. The scan line GL, the first reset control terminal RST1, and the second reset control terminal RST2 connected to this column of pixel circuits can be connected to different first shift register circuits GOA. The light emission control terminal EM connected to all pixel circuits within the first functional chip can be connected to the second shift register circuit EOA. Multiple pixel circuits within the first functional chip can be connected to the same first control terminal HF and the same initial signal terminal INIT1. Pixel circuits located in the first row within the first functional chip are all connected to the first data terminal DL1, and pixel circuits located in the second row are all connected to the second data terminal DL2. Multiple pixel circuits within the first functional chip are electrically connected to the same initial signal terminal INIT, the first power supply terminal VDD, and the first control terminal HF. The first data terminal DL1, the second data terminal DL2, the initial signal terminal INIT, the first power supply terminal VDD, and the first control terminal HF can be electrically connected to corresponding first drive pins 311-1 in the first type of pins.

[0103] In some examples, the fourth pixel node P4 of multiple pixel circuits within the first functional chip can be electrically connected one-to-one with multiple second driving pins 311-2, thereby realizing the electrical connection between the first electrode of the light-emitting element EL within the light-emitting unit and the fourth pixel node P4 of the corresponding pixel circuit. The second electrode of the light-emitting element EL can be electrically connected to the trace VSS that transmits the second power signal through the second connection electrode of the first connection region A1.

[0104] Figure 8B is a circuit diagram of another pixel circuit according to at least one embodiment of the present disclosure. As shown in Figure 8B, the pixel circuit of this example can be a 7T1C structure. The pixel circuit may include a first transistor T1 to a seventh transistor T7, and a first capacitor C1. The third transistor T3 can be a driving transistor. The gate of the third transistor T3 can be electrically connected to the first pixel node P1, the first terminal of the third transistor T3 can be electrically connected to the second pixel node P2, and the second terminal of the third transistor T3 can be electrically connected to the third pixel node P3. The gate of the second transistor T2 can be electrically connected to the scan line GL, the first terminal of the second transistor T2 can be electrically connected to the third pixel node P3, and the second terminal of the second transistor T2 can be electrically connected to the first pixel node P1. The gate of the first transistor T1 can be electrically connected to the reset control terminal RST, the first terminal of the first transistor T1 can be electrically connected to the initial signal terminal INIT, and the second terminal of the first transistor T1 can be electrically connected to the first pixel node P1. The gate of the fourth transistor T4 can be electrically connected to the scan line GL, the first electrode of the fourth transistor T4 can be electrically connected to the data terminal DL, and the second electrode of the fourth transistor T4 can be electrically connected to the second pixel node P2. The gate of the fifth transistor T5 can be electrically connected to the light emission control terminal EM, the first electrode of the fifth transistor T5 can be electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 can be electrically connected to the second pixel node P2. The gate of the sixth transistor T6 can be electrically connected to the fifth pixel node P5, the first electrode of the sixth transistor T6 can be electrically connected to the third pixel node P3, and the second electrode of the sixth transistor T6 can be electrically connected to the fourth pixel node P4. The gate of the seventh transistor T7 can be electrically connected to the reset control terminal RST, the first electrode of the seventh transistor T7 can be electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 can be electrically connected to the fourth pixel node P4. The first electrode of the first capacitor C1 is electrically connected to the first power supply terminal VDD, and the second electrode of the first capacitor C1 is electrically connected to the first pixel node P1.

[0105] The signal transmission method of the pixel circuit in this example can be referred to the description in Figure 8A, so it will not be repeated here.

[0106] Figure 9 is a circuit diagram of a first shift register circuit according to at least one embodiment of the present disclosure. As shown in Figure 9, the first shift register circuit can be an 8T2C structure, and may include a first control transistor M1 to an eighth control transistor M8, as well as a first four capacitors C4 and a fifth capacitor C5.

[0107] In some examples, the gate of the first control transistor M1 is electrically connected to the first clock signal terminal GCK, the first terminal of the first control transistor M1 is connected to the first cascade input terminal G(a-1), and the second terminal of the first control transistor M1 is electrically connected to the first control node N1. The gate of the second control transistor M2 is electrically connected to the first control node N1, the first terminal of the second control transistor M2 is electrically connected to the first clock signal terminal GCK, and the second terminal of the second control transistor M2 is electrically connected to the second control node N2. The gate of the third control transistor M3 is electrically connected to the first clock signal terminal GCK, the first terminal of the third control transistor M3 is electrically connected to the fourth power supply terminal VGL, and the second terminal of the third control transistor M3 is electrically connected to the second control node N2. The gate of the fourth control transistor M4 is electrically connected to the second control node N2, the first terminal of the fourth control transistor M4 is electrically connected to the third power supply terminal VGH, and the second terminal of the fourth control transistor M4 is electrically connected to the first cascade output terminal G(a). The gate of the fifth control transistor M5 is electrically connected to the third control node N3. The first electrode of the fifth control transistor M5 is electrically connected to the second clock signal terminal GCB, and the second electrode of the fifth control transistor M5 is electrically connected to the first cascade output terminal G(a). The gate of the sixth control transistor M6 is electrically connected to the second control node N2. The first electrode of the sixth control transistor M6 is electrically connected to the third power supply terminal VGH, and the second electrode of the sixth control transistor M6 is electrically connected to the first electrode of the seventh control transistor M7. The gate of the seventh control transistor M7 is electrically connected to the second clock signal terminal GCB, and the second electrode of the seventh control transistor M7 is electrically connected to the first control node N1. The gate of the eighth control transistor M8 is electrically connected to the fourth power supply terminal VGL. The first electrode of the eighth control transistor M8 is electrically connected to the first control node N1, and the second electrode of the eighth control transistor M8 is electrically connected to the third control node N3. The first electrode of the fourth capacitor C4 is electrically connected to the third control node N3, and the second electrode of the fourth capacitor C4 is electrically connected to the first cascade output terminal. The first electrode of the fifth capacitor C5 is electrically connected to the second control node N2, and the second electrode of the fifth capacitor C5 is electrically connected to the third power supply terminal VGH.

[0108] Figure 10 is a circuit diagram of a second shift register circuit according to at least one embodiment of the present disclosure. As shown in Figure 10, the second shift register circuit can be an 8T2C structure, such as including a first light-emitting control transistor S1 to a seventh light-emitting control transistor S7 and a sixth capacitor C6 to an eighth capacitor C8.

[0109] In some examples, the gate of the first light-emitting control transistor S1 is electrically connected to the third clock signal terminal ECK, the first terminal of the first light-emitting control transistor S1 is electrically connected to the second cascade input terminal E(b-1), and the second terminal of the first light-emitting control transistor S1 is electrically connected to the fourth control node N4. The gate of the second light-emitting control transistor S2 is electrically connected to the fourth power supply terminal VGL, the first terminal of the second light-emitting control transistor S2 is electrically connected to the fourth control node N4, and the second terminal of the second light-emitting control transistor S2 is electrically connected to the fifth control node N5. The gate of the third light-emitting control transistor S3 is electrically connected to the fifth control node N5, the first terminal of the third light-emitting control transistor S3 is electrically connected to the fourth power supply terminal VGL, and the second terminal of the third light-emitting control transistor S3 is electrically connected to the second cascade output terminal E(b). The gate of the fourth light-emitting control transistor S4 is electrically connected to the sixth control node N6, the first terminal of the fourth light-emitting control transistor S4 is electrically connected to the third power supply terminal VGH, and the second terminal of the fourth light-emitting control transistor S4 is electrically connected to the second cascade output terminal E(b). The gates of the first fifth light-emitting control transistor S5a and the second fifth light-emitting control transistor S5b are both electrically connected to the seventh control node N7. The first electrode of the second fifth light-emitting control transistor S5b is electrically connected to the sixth control node N6, and the second electrode of the second fifth light-emitting control transistor S5b is electrically connected to the first electrode of the first fifth light-emitting control transistor S5a. The second electrode of the first fifth light-emitting control transistor S5a is electrically connected to the first electrode of the eighth capacitor C8. The second electrode of the eighth capacitor C8 is electrically connected to the seventh control node N7. The gate of the sixth light-emitting control transistor S6 is electrically connected to the fourth control node N4. The first electrode of the sixth light-emitting control transistor S6 is electrically connected to the third power supply terminal VGH, and the second electrode of the sixth light-emitting control transistor S6 is electrically connected to the sixth control node N6. The gate of the seventh light-emitting control transistor S7 is electrically connected to the second cascaded input terminal E(b-1). The first electrode of the seventh light-emitting control transistor S7 is electrically connected to the third power supply terminal VGH, and the second electrode of the seventh light-emitting control transistor S7 is electrically connected to the seventh control node N7. The first electrode of the sixth capacitor C6 is electrically connected to the third power supply terminal VGH, and the second electrode of the sixth capacitor C6 is electrically connected to the sixth control node N6. The first electrode of the seventh capacitor C7 is electrically connected to the fifth control node N5, and the second electrode of the seventh capacitor C7 is electrically connected to the second cascaded output terminal E(b).

[0110] In this example, taking the first functional chip in Figure 7, which includes six first shift register circuits (e.g., the first shift register circuits from stage a to stage a+5) and one second shift register circuit (e.g., the second shift register circuit of stage b), the first input terminal GIN can be electrically connected to the first cascaded input terminal G(a-1) of the first shift register circuit of stage a, and the first output terminal GOUT can be electrically connected to the first cascaded output terminal G(a+5) of the first shift register circuit of stage a+5. The second input terminal EIN can be electrically connected to the second cascaded input terminal of the second shift register circuit of stage b, and the second output terminal EOUT can be electrically connected to the second cascaded output terminal of the second shift register circuit of stage b. Here, a and b are both positive integers.

[0111] In some examples, the first clock signal terminal GCK, the second clock signal terminal GCB, the third clock signal terminal ECK, the fourth clock signal terminal ECB, the third power supply terminal VGH, the fourth power supply terminal VGL, the first input terminal GIN, the first output terminal GOUT, the second input terminal EIN, and the second output terminal EOUT can be electrically connected to multiple first drive pins 311-1 in the first type of pins.

[0112] In some examples, taking the circuit structures shown in Figures 7 to 10 as examples, the multiple first traces of the display panel may include: a trace connected to the first data terminal DL1, a trace connected to the second data terminal DL2, a trace connected to the first power supply terminal VDD, a trace connected to the first control terminal HF, a trace connected to the initial signal terminal INIT, a trace connected to the first clock signal terminal GCK, a trace connected to the second clock signal terminal GCB, a trace connected to the third clock signal terminal ECK, a trace connected to the fourth clock signal terminal ECB, a trace connected to the third power supply terminal VGH, a trace connected to the fourth power supply terminal VGL, a trace connected to the first input terminal GIN, a trace connected to the first output terminal GOUT, a trace connected to the second input terminal EIN, a trace connected to the second output terminal EOUT, and a trace VSS for transmitting the second power signal. In this example, a group of first traces may include the aforementioned multiple first traces, and different groups of first traces that receive or transmit the same signal can be connected through second traces.

[0113] Figure 11 is a plan view of the first peripheral region of a substrate according to at least one embodiment of the present disclosure. Figure 12 is a plan view of the second functional chip according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 11, a plurality of third connection electrodes 320 may be disposed in the first peripheral region. The plurality of third connection electrodes 320 may be arranged in an array along the first direction D1 and the second direction D2, as illustrated in Figure 11 with a four-row, six-column configuration. The orthographic projection of the third connection electrodes 320 onto the substrate may be rectangular. This embodiment is not limited in this respect.

[0114] In some examples, the plurality of third connection electrodes 320 located in the first peripheral region may include a first group of third connection electrodes 320a and a second group of third connection electrodes 320b. The first group of third connection electrodes 320a and the second group of third connection electrodes 320b may be arranged along the second direction D2. The first group of third connection electrodes 320a may be connected to a first set of traces 11a, and the second group of third connection electrodes 320b may be connected to another set of first traces 11b. The plurality of first traces 111 in a set of first traces 11a may be electrically connected one-to-one with the plurality of third connection electrodes 320 in the first group of third connection electrodes 320a; the plurality of first traces 111 in a set of first traces 11b may be electrically connected one-to-one with the plurality of third connection electrodes 320 in the second group of third connection electrodes 320b. For example, the first traces 111 in the second direction D2 that are far from the first connection region may be electrically connected to the third connection electrodes 320 that are far from the effective region, and the first traces 111 in the second direction D2 that are close to a peripheral region may be electrically connected to the third connection electrodes 320 that are close to the effective region. In this example, the first trace 111 and the connected third connection electrode 320 can be an integral structure.

[0115] In some examples, as shown in Figure 12, the second functional chip 32 may include a first substrate 300 and second type pins 321 disposed on the first substrate 300. Multiple second traces 112 may be disposed on the first substrate 300. The multiple second traces 112 may be located on the side of the second type pins 321 closest to the first substrate 300. The second type pins 321 may be arranged in an array along a first direction D1 and a second direction D2, for example, in a four-row, six-column arrangement. The multiple second traces 112 may extend in the same direction, for example, all extending along the second direction D2. At least two second type pins 321 transmitting the same signal can be electrically connected through at least one second trace 112. For example, two second type pins 321 located in the same row and transmitting the same signal can be electrically connected through a single second trace 112.

[0116] In some examples, the plurality of second-type pins 321 may include: a first group of second-type pins 321a and a second group of second-type pins 321b. The first group of second-type pins 321a and the second group of second-type pins 321b may be arranged along a second direction D2, and the first group of second-type pins 321a and the second group of second-type pins 321b may be symmetrically arranged. The length of the second trace 112 connected to the second-type pins 321 in the first group of second-type pins 321a adjacent to the second group of second-type pins 321b is less than the length of the second trace 112 connected to the second-type pins 321 in the first group of second-type pins 321a away from the second group of second-type pins 321b. The plurality of second-type pins 321 may be electrically connected one-to-one with the plurality of third connection electrodes 320 in the second connection area. For example, the first group of second-type pins 321a may be electrically connected to the first group of third connection electrodes 320a, and the second group of second-type pins 321b may be electrically connected to the second group of third connection electrodes 320b.

[0117] In some examples, in a direction perpendicular to the second functional chip (e.g., a third direction), the second functional chip may include: a first substrate 300, a first metal layer disposed on the first substrate 300, a second insulating layer, and a second metal layer. Multiple second traces 112 may be located on the first metal layer, and multiple second type pins 321 may be located on the second metal layer. The second insulating layer may have multiple vias, through which the second type pins 321 can be electrically connected to the ends of corresponding second traces 112. The second traces 112 may be configured to connect two second type pins 321 transmitting the same signal, such that after the second type pins 321 are connected to their corresponding third connection electrodes, first traces 111 transmitting the same signal in different groups can be electrically connected.

[0118] In some examples, the first substrate 300 can be a rigid material, such as glass, quartz, plastic, PET, PMMA, etc. During the fabrication of the second functional chip, a first metal layer, a second insulating layer, and a second metal layer can be sequentially deposited on the first substrate using a patterning process, and then multiple second functional chips can be formed using laser cutting.

[0119] In other examples, the second functional chip 32 may also include a third type of pins. After the number X2 of the second type of pins 321 of the second functional chip 321 is determined, when determining the number of rows H2 and columns L2 of the second type of pins 321 arranged in the array, the number of rows H2 and columns L2 whose product is closest to X2 can be obtained under the condition that the absolute value of the difference between the number of rows H2 and the number of columns L2 is not greater than k. Then the number of third type pins can be H2×L2-X2. Where H2, L2 and X2 are all positive integers. After the position of the second type of pins 321 is determined, the third type of pins can be set in the empty positions in the pin array. In this example, the connection stability between the second functional chip 32 and the substrate 10 can be improved by setting the third type of pins.

[0120] In some examples, the pin array layout size requirement of the second functional chip 32 can be similar to that of the pin array layout size requirement of the first functional chip, satisfying the aforementioned relationship. Therefore, it will not be elaborated further here.

[0121] In this example, first traces transmitting the same signal within different groups of first traces can be electrically connected via second-type pins of a second functional chip and second traces. This example utilizes a second functional chip positioned within a first peripheral area to achieve electrical connections between different groups of first traces. It supports signal transmission within a single trace layer in an effective area, which can help reduce costs.

[0122] Figure 13 is another partial plan view of a display panel according to at least one embodiment of the present disclosure. Figure 14 is a schematic diagram of the connection electrodes of the first connection region and the second connection region according to at least one embodiment of the present disclosure. Figure 15 is a pin diagram of the third functional chip according to at least one embodiment of the present disclosure.

[0123] In some examples, as shown in Figures 13 to 15, the substrate 10 may include a bonding area, which may be located in the second peripheral region B2 or on the back side of the substrate 10. The display panel may include a first functional chip 31 and a third functional chip 33 disposed on the substrate 10. The third functional chip 33 may be located on the side away from the bonding area along a first direction D1. The third functional chip 33 may include a first type of pin 311 and a second type of pin 321. The first type of pin 311 and the second type of pin 321 may be arranged in an array along the first direction D1 and the second direction D2. The second type of pin 321 may be located on at least one side of the first type of pin 311 along the second direction D2. For example, the second type of pin 321 may be located on both sides of the first type of pin 311 along the second direction D2. The second type of pin 321 may include a first group of second type pins 321a located on one side of the first type of pin 311 along the second direction D2, and a second group of second type pins 321b located on the other side of the first type of pin 311 along the second direction D2.

[0124] In some examples, as shown in Figure 15, the third functional chip 33 may also include a fourth trace 14. The fourth trace 14 may be configured to connect either a first-type pin 311 or a second-type pin 321 that transmits the same signal, or to connect a second-type pin 321 that transmits the same signal. For example, second-type pins 321a and 321b that transmit the same signal can be connected via the fourth trace 14. The fourth trace 14 may be located on the side of the first-type pin 311 and the second-type pin 321 closest to the substrate of the third functional chip 33.

[0125] In some examples, the second connection region A2 of the substrate 10 may be provided with a first connection electrode 310 and a third connection electrode 320. The third connection electrode 320 may be located along the second direction D2 on at least one side of the first connection electrode 310. For example, the plurality of third connection electrodes 320 located in the second connection region A2 may include: a first group of third connection electrodes 320a and a second group of third connection electrodes 320b. The first group of third connection electrodes 320a may be located along the second direction D2 on one side of the first connection electrode 310, and the second group of third connection electrodes 320b may be located along the second direction D2 on the other side of the first connection electrode 310.

[0126] In some examples, multiple second traces 112 may be located on the substrate 10 and disposed on the same layer as multiple first traces 111. The multiple second traces 112 may extend along a second direction D2. Third connection electrodes 320 within two adjacent second connection regions A2 along the second direction D2 can be connected via the second traces 112 extending along the second direction D2. A first group of third connection electrodes 320a within a second connection region A2 may be electrically connected to a second group of third connection electrodes 320b within an adjacent second connection region A2 via the multiple second traces 112. A second trace 112 may be configured to connect two third connection electrodes 320 transmitting the same signal but located in different second connection regions A2. The second trace 112 and the connected third connection electrode 320 may be an integral structure.

[0127] In some examples, the third functional chip 33 may further include a third type of pins. After determining the number X3 of the first type of pins 311 and the second type of pins 321 of the third functional chip 33, when determining the number of rows H3 and columns L3 of the first type of pins 311 and the second type of pins 321 arranged in the array, the number of rows H3 and columns L3 whose product is closest to X3 can be obtained under the condition that the absolute value of the difference between the number of rows H3 and the number of columns L3 is not greater than k. Then the number of third type pins can be H3×L3-X3. Where H3, L3 and X3 are all positive integers. After determining the positions of the first type of pins 311 and the second type of pins 321, the third type of pins can be set in the empty positions in the pin array. In this example, setting third type of pins can improve the connection stability between the third functional chip 33 and the substrate 10.

[0128] In some examples, the third functional chip 33 can integrate the functions of the first functional chip and the second functional chip in the foregoing embodiments. The circuit architecture of the third functional chip 33 can be referred to the circuit architecture of the first functional chip in the foregoing embodiments. The structure of the first functional chip in this example is similar to that of the first functional chip in the foregoing embodiments, so it will not be described again here.

[0129] In some examples, the pin array layout size requirement of the third functional chip 33 can be similar to that of the pin array layout size requirement of the first functional chip in the aforementioned embodiments, satisfying the aforementioned relationship. Therefore, it will not be elaborated further here.

[0130] This example achieves signal transmission along the second direction D2 of the display panel by setting a third functional chip far from the bonding area and a second trace set on the same layer as the first trace. The second functional chip can be omitted, and the functions of the second functional chip and the first functional chip can be integrated into the third functional chip, which can help reduce the manufacturing cost of the display panel.

[0131] Figure 16 is another partial planar schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 17 is another schematic diagram of connection electrodes in the first connection region and the second connection region according to at least one embodiment of the present disclosure. Figure 18 is a pin diagram of a functional chip according to at least one embodiment of the present disclosure. In some examples, as shown in Figures 16 to 18, the display panel may include a functional chip 30. The functional chip 30 may include a first type of pin 311 and a second type of pin 321. The first type of pin 311 may include a first driving pin 311-1 and a second driving pin 311-2. The first driving pin 311-1 in the first type of pin 311 may be connected to a first trace 111, and the second driving pin 311-2 in the first type of pin 311 may be connected to a light-emitting unit 21 through a third trace 113. Multiple functional chips 30 may be arranged in an array along a first direction D1 and a second direction D2.

[0132] In some examples, the second driving pin 311-2 may be located on at least one side of the first driving pin 311-1 along the second direction D2, such as on both sides of the first driving pin 311-1 along the second direction D2. The second driving pin 311-2 may be adjacent to the connected light-emitting unit 21 in the second direction D2. The second type pin 321 may be located on one side of the second driving pin 311-2 in the first direction D1. The second type pin 321 may not be adjacent to the light-emitting unit 21 in the second direction D2, and may be located on both sides of the first driving pin 311-1 along the second direction D2, so that the second type pin 321 can be connected to the second trace 112 extending along the second direction D2 to realize signal transmission along the second direction D2.

[0133] In some examples, a first connection region A1 is provided with a plurality of second connection electrodes 210. The plurality of second connection electrodes 210 transmitting the second power signal within the first connection region A1 can be a single integrated structure and electrically connected to a first trace 111 extending along the first direction D1 for transmitting the second power signal, for example, they can be a single integrated structure. The first trace 111 can pass through the gap between adjacent connection electrodes (e.g., adjacent first connection electrodes 310 or first connection electrodes 310 and adjacent third connection pins 320) within the second connection region.

[0134] In some examples, the second connection region can be provided with multiple first connection electrodes 310 and multiple third connection electrodes 320. The first connection electrodes 310 can be connected to a first type of pin 311, and the third connection electrodes 320 can be connected to a second type of pin 321. The third connection electrode 320 can be connected to a second trace 112 extending along the second direction D2, for example, it can be an integral structure. The second trace 112 and the first trace 111 can be disposed on the same layer. The first connection electrode 310 can include a first type of connection electrode 310-1 and a second type of connection electrode 310-2. The first type of connection electrode 310-1 and the connected first trace 111 can be an integral structure, and the second type of connection electrode 310-2 and the connected third trace 113 can be an integral structure.

[0135] In some examples, the first trace 111, the second trace 112, and the third trace 113 do not intersect each other and can be set in the same layer, thereby reducing the manufacturing cost.

[0136] In some examples, the functional chip 30 may also include a third type of pin. The third type of pin can be configured to form an array arrangement with the first type of pin 311 and the second type of pin 321, thereby improving the connection stability between the functional chip 30 and the substrate 10. After determining the number X4 of the first type of pin 311 and the second type of pin 321 of the functional chip 30, when determining the number of rows H4 and columns L4 of the first type of pin 311 and the second type of pin 321 arranged in the array, the number of rows H4 and columns L4 whose product is closest to X4 can be obtained under the condition that the absolute value of the difference between the number of rows H4 and the number of columns L4 is not greater than k. Therefore, the number of the third type of pin can be H4 × L4 - X4. Here, H4, L4, and X4 are all positive integers. After determining the positions of the first type of pin 311 and the second type of pin 321, the third type of pin can be placed in the empty positions in the pin array.

[0137] The functional chip 30 in this example can integrate the functions of the first functional chip and the second functional chip in the aforementioned embodiments. The circuit architecture of the functional chip 30 can be referred to the circuit architecture of the first functional chip in the aforementioned embodiments, so it will not be described again here.

[0138] This example demonstrates how signal transmission along a second direction in the display panel can be achieved through a second type of pin on the functional chip and a second trace disposed on the same layer as the first trace, which can help reduce the manufacturing cost of the display panel. Further descriptions of the display panel in this example can be found in the foregoing embodiments and will not be repeated here.

[0139] This embodiment also provides a display device, including the display panel as described above.

[0140] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 19, the display device 91 may include a display panel 910. The display panel 910 may be a Micro-LED display panel or a Mini-LED display panel. The display device 91 may be a product with image (including static images or dynamic images, wherein the dynamic images may be video) display capabilities, such as applications in vehicle displays, vehicle lights, interactive light carpets, vehicle windows, shopping mall displays, augmented reality (AR) devices, virtual reality (VR) devices, etc. However, this embodiment is not limited in this respect.

[0141] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0142] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display panel, comprising: A substrate, a plurality of first traces and a plurality of second traces disposed on the substrate, a light-emitting unit and a functional chip; The number of light-emitting units is not less than twice the number of functional chips; The plurality of first traces are arranged on the same layer and extend along the first direction; The functional chip includes: a first type of pins and a second type of pins; some of the first type of pins are connected to the first trace, and others of the first type of pins are connected to the light-emitting unit; the second type of pins connect the two first traces through the second trace.

2. The display panel according to claim 1, wherein, The functional chip includes: a first functional chip and a second functional chip, wherein the first functional chip includes the first type of pins and the second functional chip includes the second type of pins.

3. The display panel according to claim 2, wherein, The second functional chip includes a first substrate, the plurality of second traces are located on the first substrate, and the second type of pins are located on the side of the plurality of second traces away from the first substrate.

4. The display panel according to claim 2, wherein, The substrate includes a bonding area, and the second functional chip is located on the side away from the bonding area in the first direction.

5. The display panel according to claim 1, wherein, The functional chip includes a first functional chip and a third functional chip, wherein the first functional chip includes the first type of pins, and the third functional chip includes the first type of pins and the second type of pins.

6. The display panel according to claim 5, wherein, The second type of pin of the third functional chip is located around the first type of pin along a second direction, and the second direction intersects the first direction.

7. The display panel according to claim 5, wherein, The substrate includes a bonding area, and the third functional chip is located on the side away from the bonding area in the first direction.

8. The display panel according to claim 4 or 7, wherein, The substrate includes a first side and a second side disposed opposite to each other, the light-emitting unit and the functional chip are located on the first side, and the bonding area is located on the second side; The display panel further includes a side connection line configured to connect at least one first trace located on the first surface to the bonding area.

9. The display panel according to any one of claims 5 to 8, wherein, The plurality of second traces are arranged on the same layer as the plurality of first traces.

10. The display panel according to claim 1, wherein, The functional chip further includes: a plurality of pixel circuits and at least one shift register circuit group; the at least one shift register circuit group is configured to provide pixel control signals to the plurality of pixel circuits, the at least one shift register circuit group and the plurality of pixel circuits are configured to be connected to the first trace through some of the first type of pins, and the plurality of pixel circuits are configured to be connected to the light-emitting unit through other of the first type of pins.

11. The display panel according to claim 1, further comprising: A first connection electrode is disposed on the substrate, and the first type of pin is connected to the first trace or the light-emitting unit through the first connection electrode. The first connecting electrode and the plurality of first traces are in the same layer.

12. The display panel according to claim 11, wherein, The number of first traces arranged in the gap between two adjacent first connecting electrodes along the second direction is less than or equal to two, and the second direction intersects the first direction.

13. The display panel according to claim 11, further comprising: A second connection electrode is disposed on the substrate, and the light-emitting unit is connected to some other pins of the first type through the second connection electrode. The minimum distance between the second connection electrode and the adjacent first connection electrode along the second direction is greater than or equal to 100 micrometers.

14. The display panel according to claim 1, wherein, The first type of pin of the functional chip connected to the light-emitting unit is adjacent to the light-emitting unit in a second direction, and the second type of pin is located on one side of the first type of pin connected to the light-emitting unit in the first direction, and the second direction intersects the first direction.

15. The display panel according to claim 1, wherein, The functional chip further includes a third type of pin, which is configured to form an array arrangement with at least one of the first type of pin and the second type of pin.

16. The display panel according to any one of claims 1 to 15, wherein, The light-emitting unit includes multiple light-emitting elements that emit light of different colors.

17. A display device comprising a display panel as claimed in any one of claims 1 to 16.

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