Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device. The array substrate comprises a base substrate (101), which comprises a display area (AA) and a non-display area (DP) located on at least one side of the display area (AA); a plurality of dummy pixel electrodes (102), which are arranged in at least one row within the non-display area (DP); two first signal lines (103), which are located on the side of the plurality of dummy pixel electrodes (102) away from the display area (AA), the first signal lines (103) being first common electrode lines (CL1); and a plurality of first transistors (104), the orthographic projection of the plurality of first transistors (104) on the base substrate (101) overlapping the orthographic projection of the two first signal lines (103) on the base substrate (101).

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0003] This disclosure provides an array substrate, a display panel, and a display device, with the specific solutions as follows:

[0004] On one hand, embodiments of this disclosure provide an array substrate, including:

[0005] A substrate, the substrate including a display area and a non-display area located on at least one side of the display area;

[0006] Multiple virtual pixel electrodes are arranged in at least one row in the non-display area;

[0007] Two first signal lines are located on the side of the plurality of virtual pixel electrodes away from the display area, and the first signal lines are first common electrode lines;

[0008] A plurality of first transistors, wherein the orthographic projections of the plurality of first transistors on the substrate overlap with the orthographic projections of the two first signal lines on the substrate.

[0009] In some embodiments, in the array substrate provided in the present disclosure, a plurality of second transistors are provided on the side of each row of virtual pixel electrodes near the display area;

[0010] The plurality of first transistors and the plurality of second transistors adjacent to the row of virtual pixel electrodes furthest from the display area are approximately symmetrical about the center line extending along the row direction of that row of virtual pixel electrodes.

[0011] In some embodiments, in the array substrate provided in the present disclosure, two second signal lines are provided on the side of each row of virtual pixel electrodes near the display area;

[0012] The two first signal lines and the two second signal lines adjacent to the row of virtual pixel electrodes furthest from the display area are approximately symmetrical about the center line extending along the row direction of that row of virtual pixel electrodes.

[0013] In some embodiments, in the array substrate provided in the present disclosure, the second signal line closest to the display area is a gate line, and the two first signal lines and the other second signal lines besides the second signal line closest to the display area are all first common electrode lines.

[0014] In some embodiments, the array substrate provided in this disclosure further includes data lines and second common electrode lines alternately arranged at the different column gaps of the virtual pixel electrodes;

[0015] The first electrode of the second transistor in which the first common electrode lines overlap is electrically connected to the second common electrode lines, and the second electrode of the second transistor in which the first common electrode lines overlap is spaced apart from the data lines.

[0016] In some embodiments, the array substrate provided in this disclosure further includes a pixel electrode located in the display area, and a plurality of transition electrodes in the non-display area on the same layer as the pixel electrode. The first electrode of the second transistor whose first common electrode lines overlap, and the first electrode of the first transistor are respectively electrically connected to different transition electrodes.

[0017] In some embodiments, the array substrate provided in this disclosure further includes a common electrode that overlaps with the pixel electrode. The common electrode includes a plurality of first hollow structures, and the orthographic projections of the plurality of transition electrodes on the substrate overlap with the orthographic projections of the plurality of first hollow structures on the substrate.

[0018] In some embodiments, the array substrate provided in this disclosure further includes data lines and second common electrode lines alternately arranged at the different column gaps of the virtual pixel electrodes;

[0019] The first electrode of the first transistor is electrically connected to the second common electrode line, and the second electrode of the first transistor is spaced apart from the data line.

[0020] In some embodiments, in the array substrate provided in the present disclosure, the non-display area includes a first non-display area for bonding a driving circuit, and a second non-display area located on the side of the display area away from the first non-display area;

[0021] The array substrate further includes a common electrode bus surrounding the non-display area. The common electrode bus includes a first common electrode segment located in the first non-display area and a second common electrode segment located in the second non-display area. The line width of the second common electrode segment is greater than the line width of the first common electrode segment.

[0022] In some embodiments, the array substrate provided in this disclosure further includes data lines extending from the column gaps of the virtual pixel electrodes, wherein the parasitic capacitance of the data lines and the first common electrode segment is approximately equal to the parasitic capacitance of the data lines and the second common electrode segment.

[0023] In some embodiments, the array substrate provided in this disclosure further includes data lines extending from the column gaps of the virtual pixel electrodes. The second common electrode segment includes at least one second hollow structure. The overlap length between the first common electrode segment and the data line in the column direction is a first length. The length of the second common electrode segment in the column direction is a second length. The overlap length between the at least one second hollow structure and the data line in the column direction is a third length. The first length is approximately equal to the difference between the second length and the third length.

[0024] In some embodiments, in the array substrate provided in the present disclosure, the plurality of virtual pixel electrodes are arranged in one row between the first common electrode segment and the display area, and in two rows between the second common electrode segment and the display area.

[0025] In some embodiments, the array substrate provided in the present disclosure further includes a plurality of pixel electrodes arranged in an array in the display area, and a plurality of gate lines located at the row gaps of the pixel electrodes, wherein two gate lines are provided at the row gaps of two adjacent rows of pixel electrodes.

[0026] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.

[0027] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0028] Figure 1 is a schematic diagram of the structure of the array substrate provided in an embodiment of this disclosure;

[0029] Figure 2 is an enlarged structural diagram of region Z1 in Figure 1;

[0030] Figure 3 is a schematic diagram of the structure of the layer containing the grid lines in Figure 2;

[0031] Figure 4 is a schematic diagram of the structure of the layer where the data line is located in Figure 2;

[0032] Figure 5 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 2;

[0033] Figure 6 is a schematic diagram of the structure of the layer where the pixel electrode is located in Figure 2;

[0034] Figure 7 is a magnified structural diagram of region Z2 in Figure 2;

[0035] Figure 8 is an enlarged structural diagram of region Z3 in Figure 1;

[0036] Figure 9 is an enlarged structural diagram of region Z4 in Figure 8;

[0037] Figure 10 is a cross-sectional view along line I-I' in Figure 9;

[0038] Figure 11 is a schematic diagram of an alternative structure to Figure 9;

[0039] Figure 12 is a schematic diagram of another alternative structure to Figure 9;

[0040] Figure 13 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0041] Figure 14 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0043] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0044] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0045] The display area (Active Area, AA) and non-display area of ​​a liquid crystal display panel differ significantly in shape, size, and density. This results in large fluctuations and poor uniformity in the edge areas of the display area (AA) due to variations in manufacturing processes (e.g., coating, exposure, development, etching). In some embodiments, dummy pixels (D) can be placed around the display area (AA) to act as a transition, ensuring the uniformity of the pixels in the display area (AA) and thus guaranteeing the image quality of the panel. Optionally, the dummy pixels have the same shape, size, and layer structure as the pixels in the display area (AA), but they do not perform display functions; their pixel electrodes are non-conductive and are obscured by a black matrix (BM) or ink.

[0046] For dual-gate driven products, there are two traces between two adjacent rows of pixels, between two adjacent rows of virtual pixels, and between adjacent rows of virtual pixels. However, the trace on the side of the virtual pixel furthest from the display area AA is only one. This results in some blank areas at the edge of the virtual pixels. During the substrate fabrication process, this leads to poor uniformity of the edge area, and the virtual transistors intersecting with the traces will exhibit unevenness.

[0047] To address the aforementioned technical problems, this disclosure provides an array substrate. Figure 1 is a schematic diagram of the array substrate provided in this disclosure, Figure 2 is an enlarged schematic diagram of the Z1 region in Figure 1, and Figures 3 to 6 are layer-by-layer diagrams of the conductive layers in Figure 2. As can be seen from Figures 1 to 6, the array substrate of this disclosure may include:

[0048] The substrate 101 includes a display area AA and a non-display area located on at least one side of the display area AA. For example, the non-display area includes a first non-display area DP and a second non-display area DPO placed opposite each other, and two third non-display areas GL&GR connecting the first non-display area DP and the second non-display area DPO. The first non-display area DP can be used to bond a driving circuit (e.g., a flexible circuit board FPC, a source driving circuit Source IC, etc.), and one or both of the two third non-display areas GL&GR can be provided with a gate driving circuit GOA.

[0049] Multiple virtual pixel electrodes 102 are arranged in at least one row in the non-display area. Bright edges caused by metal trace reflections are prone to occur in the first non-display area DP and the second non-display area DPO because the virtual pixel electrodes 102 are not conductive and are obscured by a black matrix (BM) or ink. Therefore, setting virtual pixels can reduce this defect. The more rows of virtual pixels, the lower the defect risk; however, the virtual transistors (DTFTs) in the virtual pixels increase the load on the data lines DL. Therefore, this disclosure allows for the addition of 1-2 rows of virtual pixels. Considering that the second non-display area DPO has more wiring space than the first non-display area DP, this disclosure allows for one row of virtual pixels in the first non-display area DP and two rows of virtual pixels in the second non-display area DPO.

[0050] Two first signal lines 103 are located on the side of the plurality of virtual pixel electrodes 102 away from the display area AA, and the first signal lines 103 are the first common electrode lines CL1. In some embodiments, the first signal lines 103 may be located in a gate metal layer, and the material of the gate metal layer may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). Optionally, the gate metal layer may be a single-layer structure or a stacked structure. For example, the gate metal layer is a single-layer structure consisting of a molybdenum metal layer, an aluminum metal layer, or a copper metal layer.

[0051] Multiple first transistors 104 are provided, and their orthogonal projections on the substrate 101 overlap with the orthogonal projections of the two first signal lines 103 on the substrate 101. Each first transistor 104 is a virtual transistor DTFT that is not conductive with the virtual pixel electrode 102. In some embodiments, the first transistor 104 can be a P-type transistor or an N-type transistor; the active layer material of the first transistor 104 can be amorphous silicon, polycrystalline silicon, indium gallium zinc oxide, etc.; the gate g of the first transistor 104 can be located above the active layer, and / or, the gate g of the first transistor 104 can be located below the active layer; optionally, the gate g of the first transistor 104 is integrally disposed with the first signal line 103.

[0052] In the array substrate provided in the embodiments of this disclosure, two first signal lines 103 and a first transistor 104 overlapping with the two first signal lines 103 are provided on the side of the virtual pixel away from the display area AA. This is equivalent to adding a trace and a virtual transistor DTFT overlapping with the trace in the blank area on the side of the virtual pixel away from the display area AA. This can improve the uniformity of the edge area of ​​the virtual pixel and prevent uneven transition of the virtual transistor.

[0053] In some embodiments, as shown in Figures 1 to 6, each row of virtual pixel electrodes 102 has a plurality of second transistors 105 and two second signal lines 106 on the side closest to the display area AA. The second signal line 106 closest to the display area AA is a gate line GL, and the other second signal lines 106 are first common electrode lines CL1. The second transistors 105 (labeled TFTs) overlapping the gate lines GL are electrically connected to the pixel electrode 107, and the second transistors 105 overlapping the first common electrode lines CL1 are not conductive with the virtual pixel electrodes 102 and belong to the virtual transistor DTFT. Optionally, the plurality of first transistors 104 and the plurality of second transistors 105 adjacent to the row of virtual pixel electrodes 102 furthest from the display area AA are approximately symmetrical about the center line MN extending along the row direction of that row of virtual pixel electrodes 102; the two first signal lines 103 and the two second signal lines 106 adjacent to the row of virtual pixel electrodes 102 furthest from the display area AA are approximately symmetrical about the center line MN extending along the row direction X of that row of virtual pixel electrodes 102. This maximizes the uniformity of the virtual pixel edge region and prevents uneven transition of the virtual transistor TFT.

[0054] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 2 to 6, may further include data lines DL and second common electrode lines CL2 alternately arranged at different column gaps of virtual pixel electrodes 102. Figure 7 shows an enlarged schematic diagram of the Z2 region of Figure 2. As can be seen from Figures 2 to 7, the first electrode s of the second transistor 105, in which the first common electrode lines CL1 overlap, is electrically connected to the second common electrode line CL2; the second electrode d of the second transistor 105, in which the first common electrode lines CL2 overlap, is spaced apart from the data line DL; the first electrode s of the first transistor 104 is electrically connected to the second common electrode line CL2, and the second electrode d of the first transistor 104 is spaced apart from the data line DL. Optionally, one of the first electrode s and the second electrode d may be the source and the other the drain; this disclosure does not specifically limit this.

[0055] The more virtual pixel rows there are, the more virtual transistors (DTFTs) there are, which increases the load on the data line DL and affects charging capability. In related technologies, the second electrode d of the virtual transistor DTFT is connected to the data line DL, and a common voltage (Com) is applied to the gate of the virtual transistor DTFT. Parasitic capacitance exists between the two different signals, leading to an increased load on the data line DL. The first electrode s of the virtual transistor DTFT is in a floating state. In this disclosure, the second electrode d of the first transistor 104 and the second transistor 105, which serve as virtual transistor DTFTs, is disconnected from the data line DL, making it float. The first electrode s is connected to the second common electrode line CL2, and a common voltage is applied. Because the gate g of the first transistor 104 and the second transistor 105 of the virtual transistor DTFT is applied to the common voltage, no parasitic capacitance is generated between the two identical signals. Therefore, the load on the data line DL can be reduced, and the panel charging capability can be improved.

[0056] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 2 to 6, may further include a pixel electrode 107 located in the display area AA, and multiple transition electrodes 108 in non-display areas (e.g., the first non-display area DP and the second non-display area DPO) that are on the same layer and made of the same material as the pixel electrode 107. Two gate lines GL may be provided at the row gap between adjacent rows of pixel electrodes 107. The first electrode s of the second transistor 105, which overlaps with the first common electrode line CL1, and the first electrode s of the first transistor 104 are electrically connected to different transition electrodes 108. Since the pixel electrode 107 is electrically connected to the transistor TFT within the display area AA, this disclosure adds transition electrodes 108 connecting the virtual transistor DTFT (including the first transistor 104 and the second transistor 105 overlapping with the first common electrode line CL1). This ensures that pixels near the periphery in the display area AA have a similar process environment to pixels far from the periphery in the display area AA, which is beneficial for improving display quality.

[0057] Referring to Figures 2 through 6, the array substrate of this disclosure may further include a common electrode 109 overlapping with the pixel electrode 107. That is, this disclosure can be used in ADS panels. Optionally, one of the common electrode 109 and the pixel electrode 107 may be a slit electrode, and the other a block electrode. This disclosure illustrates this by using the pixel electrode 107 as a slit electrode and the common electrode 109 as a block electrode. The common electrode 109 can be connected to the second common electrode line CL2 through a hole drilled within the display area AA to reduce resistance. Optionally, to avoid short-circuiting between the common electrode 109 and the pixel electrode 107, the common electrode 109 at the connection point between the pixel electrode 107 and the transistor can be removed. To ensure a similar process environment, the common electrode 109 at the connection position between the transition electrode 108 and the virtual transistor DTFT can also be removed. In other words, the common electrode 109 may include multiple first hollow structures OW1. The orthographic projection of the transition electrode 108 on the substrate 101 and the orthographic projection of the first hollow structure OW1 on the substrate 101 overlap with each other. For example, the orthographic projection of the transition electrode 108 on the substrate 101 is located within the orthographic projection of the first hollow structure OW1 on the substrate 101.

[0058] In some embodiments, FIG8 shows an enlarged structural schematic diagram of region Z3 in FIG1. ​​Referring to FIG2 and FIG8, the array substrate provided in this disclosure may further include a common electrode bus 110 surrounding the non-display area AA. The common electrode bus 110 may include a first common electrode segment 1101 located in the first non-display area DP and a second common electrode segment 1102 located in the second non-display area DPO. The second common electrode line CL2 is electrically connected to the first common electrode segment 1101 and the second common electrode segment 1102. The first common electrode line CL1 and the common electrode bus 110 are integrally disposed within the third non-display area GL&GR to form a parallel loop to reduce resistance. FIG9 is an enlarged structural schematic diagram of region Z4 in FIG8, and FIG10 is a cross-sectional view along line I-I' in FIG9. As shown in FIG9 and FIG10, the second common electrode line CL2 may be fabricated using a source / drain metal layer, and the second common electrode segment 1102 may be fabricated using a gate metal layer. Adapter vias V1 and V2 are provided on the second common electrode line CL2 and the second common electrode segment 1102. The V1 adapter via on the second common electrode line CL2 penetrates the first insulating layer 111, and the V2 adapter via on the second common electrode line CL2 penetrates the first insulating layer 111 and the second insulating layer 112. Optionally, the second common electrode line CL2 and the second common electrode segment 1102 are electrically connected through a conductive film 113 of the same layer and material as the pixel electrode 107. The connection method between the second common electrode line CL2 and the first common electrode segment 1101 is similar and will not be described in detail here.

[0059] Excessive resistance in the common electrode bus 110 can easily lead to display defects such as image retention (I / S) and greenish tint. In related technologies, the width of the first common electrode segment 1101 is approximately the same as the width of the second common electrode segment 1102 (e.g., within ±5% error range due to factors such as process and measurement). In this disclosure, the width of the second common electrode segment 1102 is greater than the width of the first common electrode segment 1101, so as to make full use of the space of the second non-display area DPO where the second common electrode segment 1102 is located to reduce the resistance of the common electrode bus 110, thereby improving display quality.

[0060] Figure 11 is a schematic diagram of an alternative structure to Figure 9 provided in an embodiment of this disclosure. In Figure 11, the width A of the second common electrode line 1102 is approximately the same as the width of the first common electrode segment 1101 in the related art. As shown in Figure 11, the data line DL passes through the second common electrode segment 1102. Parasitic capacitance is generated between the two signal lines with different voltages. With fixed insulation layer thickness, metal resistivity, etc., the larger the overlap area between the two, the larger the parasitic capacitance. The overlap area between the data line DL and the second common electrode segment 1102 in Figure 11 is defined as equal to the overlap length A of the second common electrode line 1102 and the data line DL multiplied by the width of the data line DL. With the width of the data line DL unchanged, ensuring that A remains unchanged can ensure that the overlap area and parasitic capacitance remain unchanged.

[0061] Since the width of the second common electrode segment 1102 in this disclosure is greater than the width of the first common electrode segment 1101, and the data line DL passes through the first common electrode segment 1101 and the second common electrode segment 1102, in order to ensure that the parasitic capacitance of the data line DL and the first common electrode segment 1101 is approximately equal to (for example, within ±5% error range caused by process, measurement, etc.) the parasitic capacitance of the data line DL and the second common electrode segment 1102, the portion of the second common electrode segment 1102 overlapping with the data line DL needs to be etched away to form at least one second hollow structure OW2. Furthermore, if the overlap length of the first common electrode segment 1101 and the data line DL in the column direction Y is the first length, the length of the second common electrode segment 1102 in the column direction Y is the second length, and the overlap length of all the second hollow structures OW2 and the data line DL in the column direction Y is the third length, it is necessary to ensure that the first length is approximately equal to (for example, within ±5% error range caused by process, measurement, etc.) the difference between the second length and the third length.

[0062] Figure 12 is a schematic diagram of another alternative structure of Figure 9 provided in an embodiment of this disclosure. As shown in Figures 9, 11, and 12, the first length of the overlap between the first common electrode segment 1101 and the data line DL can be equal to A in Figure 11. The second length of the second common electrode segment 1102 in the column direction Y is A1+B1+A2+B2+A3 in Figure 9 and A1+B+A2 in Figure 12. The third length of the overlap between the entire second hollow structure OW2 and the data line DL in the column direction Y is B1+B2 in Figure 9 and B in Figure 12. In this disclosure, A can be equal to A1+A2+A3 or A1+A2. This reduces the resistance of the common electrode bus 110 while keeping the parasitic capacitance between the common electrode bus 110 and the data line DL unchanged, reducing the load on the data line DL and improving the charging capability. Considering the large space of the second non-display area DPO, this disclosure can also widen the line width of the second common electrode segment 1102 compared to Figures 9 and 12. It is only necessary to ensure that after widening, A1+A2+A3+…+An=A, and to carve out B1+B2+B3+…Bn-1 second hollow structures OW2 at the corresponding positions, so as to achieve consistent parasitic capacitance and reduce the resistance of the common electrode bus 110.

[0063] Based on the same inventive concept, this disclosure provides a display panel, as shown in FIG13, including the array substrate 001 provided in this disclosure embodiment and a counter substrate 002 disposed opposite to the array substrate 001. Since the principle of solving the problem by this display panel is similar to the principle of solving the problem by the array substrate described above, the implementation of the display panel provided in this disclosure embodiment can refer to the implementation of the array substrate provided in this disclosure embodiment, and repeated details will not be described again.

[0064] In some embodiments, as shown in FIG13, the display panel provided in this disclosure may further include a liquid crystal layer 003 between the array substrate 001 and the opposing substrate 002. In some embodiments, a first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001, wherein the polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0065] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG14, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0066] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0067] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0068] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0069] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; Multiple virtual pixel electrodes are arranged in at least one row in the non-display area; Two first signal lines are located on the side of the plurality of virtual pixel electrodes away from the display area, and the first signal lines are first common electrode lines; A plurality of first transistors, wherein the orthographic projections of the plurality of first transistors on the substrate overlap with the orthographic projections of the two first signal lines on the substrate.

2. The array substrate as claimed in claim 1, wherein, Each row of virtual pixel electrodes has a plurality of second transistors on the side closest to the display area; The plurality of first transistors and the plurality of second transistors adjacent to the row of virtual pixel electrodes furthest from the display area are approximately symmetrical about the center line extending along the row direction of that row of virtual pixel electrodes.

3. The array substrate as described in claim 2, wherein, Two second signal lines are provided on the side of each row of virtual pixel electrodes closest to the display area; The two first signal lines and the two second signal lines adjacent to the row of virtual pixel electrodes furthest from the display area are approximately symmetrical about the center line extending along the row direction of that row of virtual pixel electrodes.

4. The array substrate as claimed in claim 3, wherein, The second signal line closest to the display area is a gate line, and the two first signal lines and the other second signal lines besides the second signal line closest to the display area are all first common electrode lines.

5. The array substrate as claimed in claim 4, wherein, It also includes data lines and a second common electrode line that are alternately arranged at the different column gaps of the virtual pixel electrode; The first electrode of the second transistor in which the first common electrode lines overlap is electrically connected to the second common electrode lines, and the second electrode of the second transistor in which the first common electrode lines overlap is spaced apart from the data lines.

6. The array substrate as claimed in claim 5, wherein, It also includes pixel electrodes located in the display area, and multiple transition electrodes in the non-display area on the same layer as the pixel electrodes. The first electrode of the second transistor, whose first common electrode lines overlap, and the first electrode of the first transistor are respectively electrically connected to different transition electrodes.

7. The array substrate as claimed in claim 6, wherein, It also includes a common electrode that overlaps with the pixel electrode. The common electrode includes a plurality of first hollow structures. The orthographic projections of the plurality of transition electrodes on the substrate overlap with the orthographic projections of the plurality of first hollow structures on the substrate.

8. The array substrate according to any one of claims 1 to 7, wherein, It also includes data lines and a second common electrode line that are alternately arranged at the different column gaps of the virtual pixel electrode; The first electrode of the first transistor is electrically connected to the second common electrode line, and the second electrode of the first transistor is spaced apart from the data line.

9. The array substrate according to any one of claims 1 to 8, wherein, The non-display area includes a first non-display area for bonding the driving circuit, and a second non-display area located on the side of the display area away from the first non-display area; The array substrate further includes a common electrode bus surrounding the non-display area. The common electrode bus includes a first common electrode segment located in the first non-display area and a second common electrode segment located in the second non-display area. The line width of the second common electrode segment is greater than the line width of the first common electrode segment.

10. The array substrate as claimed in claim 9, wherein, It also includes data lines extending between the columns of the virtual pixel electrodes, wherein the parasitic capacitance of the data lines and the first common electrode segment is approximately equal to the parasitic capacitance of the data lines and the second common electrode segment.

11. The array substrate as claimed in claim 9 or 10, wherein, It also includes a data line extending from the column gap of the virtual pixel electrode, the second common electrode segment including at least one second hollow structure, the overlap length of the first common electrode segment and the data line in the column direction being a first length, the length of the second common electrode segment in the column direction being a second length, the overlap length of the at least one second hollow structure and the data line in the column direction being a third length, and the first length being approximately equal to the difference between the second length and the third length.

12. The array substrate according to any one of claims 9 to 11, wherein, The plurality of virtual pixel electrodes are arranged in one row between the first common electrode segment and the display area, and in two rows between the second common electrode segment and the display area.

13. The array substrate according to any one of claims 1 to 12, wherein, It also includes a plurality of pixel electrodes arranged in an array in the display area, and a plurality of gate lines located at the row gaps of the pixel electrodes, wherein two gate lines are provided at the row gaps of two adjacent rows of pixel electrodes.

14. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 13.

15. A display device, wherein, It includes the display panel as described in claim 14, and a backlight module located on the light-incident side of the display panel.

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