Wiring substrate and display device

Abstract

A wiring substrate and a display device. The wiring substrate comprises a base substrate (101), a first conductive layer (110), a first insulating layer group (120), a second conductive layer (130), and a second insulating layer group (140). The wiring substrate further comprises a plurality of conductive structures located in a peripheral region (BB), each conductive structure comprises a first sub-pad (151) located in the second conductive layer, a conductive extension portion (153) connected to the first sub-pad, and at least one first via hole (V1) and at least one second via hole (V2) running through the first insulating layer group; an orthographic projection of the first sub-pad on the base substrate is located outside an orthographic projection of the second insulating layer group on the base substrate; the conductive extension portion is covered by the second insulating layer group; the first sub-pad is located in a bonding region (B2); at least part of the conductive extension portion is located in a lead-out region (B1); a part of the first sub-pad of each conductive structure is located in the at least one first via hole; and the conductive extension portion is directly connected to signal lines (160) of the first conductive layer by means of the at least one second via hole. Thus, the risk of bonding failure caused by heat in the bonding region can be avoided, ensuring the bonding effect.

Description

Wiring substrate and display device Technical Field

[0001] Embodiments of this disclosure relate to a wiring substrate and a display device. Background Technology

[0002] Liquid crystal display (LCD) is the earliest and most mature display technology. Organic light-emitting diode (OLED) display technology is the next generation of display technology after LCD, and the technology is already very mature.

[0003] In recent years, with the rapid development of the micro light-emitting diode (MLED) industry, the application of micro light-emitting diodes has become increasingly widespread. Micro light-emitting diodes include sub-millimeter light-emitting diodes (Mini LED) and micro light-emitting diodes (Micro LED). Micro light-emitting diodes have excellent performance such as lower power consumption, faster response, longer lifespan, and higher color saturation and contrast. With technological breakthroughs, Mini LED and Micro LED displays will become the next generation of display technologies after LCD and OLED. Summary of the Invention

[0004] This disclosure provides a wiring substrate and a display device. By connecting the first sub-pad to the signal line through a conductive extension, the risk of bonding failure caused by heat in the bonding area can be avoided, thus ensuring the bonding effect.

[0005] At least one embodiment of this disclosure provides a wiring substrate, comprising: a substrate; a first conductive layer located on the substrate and including a plurality of signal lines; a first insulating layer group located on a side of the first conductive layer away from the substrate; a second conductive layer located on a side of the first insulating layer group away from the substrate; and a second insulating layer group located on a side of the second conductive layer away from the substrate, wherein the wiring substrate includes an in-plane region and a peripheral region at least partially surrounding the in-plane region, the peripheral region including a lead-out region and a bonding region, the wiring substrate further including a plurality of conductive structures located in the peripheral region, each conductive structure including a first sub-pad located in the second conductive layer, a conductive extension connected to the first sub-pad, and at least one first insulating layer group penetrating the first insulating layer group. The first via and at least one second via are provided, wherein the orthographic projection of the first via on the substrate is outside the orthographic projection of the second insulating layer group on the substrate, and the orthographic projection of the second via on the substrate is inside the orthographic projection of the second insulating layer group on the substrate. The orthographic projection of the first sub-pad on the substrate is outside the orthographic projection of the second insulating layer group on the substrate. The conductive extension is covered by the second insulating layer group. The first sub-pad is located in the bonding area. At least a portion of the conductive extension is located in the lead-out area. A portion of the first sub-pad of each conductive structure is located in the at least one first via. The conductive extension is directly connected to the signal line of the first conductive layer through the at least one second via.

[0006] For example, in a wiring substrate provided in an embodiment of this disclosure, the plurality of signal lines of the first conductive layer extend to the in-plane region. The in-plane region of the wiring substrate further includes a plurality of first pads and a plurality of second pads. Each first pad is configured to be connected to an electrode of a micro-driver chip, and each second pad is configured to be connected to an electrode of a micro-light-emitting diode. The in-plane region of the wiring substrate further includes a plurality of conductive traces. The first pads and the second pads are connected through the conductive traces and connected to the signal lines through the conductive traces so that the micro-driver chip drives the micro-light-emitting diode to emit light.

[0007] For example, in a wiring substrate provided in an embodiment of this disclosure, the ratio of the area of ​​the orthogonal projection of the at least one second via of each conductive structure onto the substrate to the area of ​​the orthogonal projection of the at least one first via onto the substrate is greater than or equal to 0.8.

[0008] For example, in a wiring substrate provided in an embodiment of this disclosure, the first sub-pad and the conductive extension both extend along a first direction, and the ratio of the dimension of the at least one second via of each conductive structure along the first direction to the dimension of the at least one first via along the first direction is greater than or equal to 0.8.

[0009] For example, in a wiring substrate provided in an embodiment of this disclosure, the first sub-pad and the conductive extension both extend along a first direction. The conductive extension of each conductive structure includes a first sub-part and a second sub-part. The first sub-part connects the first sub-pad and the second sub-part, and the second sub-part is directly connected to the signal line of the first conductive layer through the at least one second via.

[0010] For example, in a wiring substrate provided in an embodiment of this disclosure, the ratio of the dimension of the at least one second via of each of the conductive structures along the first direction to the sum of the dimensions of the conductive extension and the first sub-pad along the first direction is less than or equal to 0.5.

[0011] For example, in a wiring substrate provided in an embodiment of this disclosure, the wiring substrate further includes a plurality of conductive traces located in the in-plane region and in the second conductive layer. The plurality of conductive traces include adjacent conductive traces that are adjacent to and spaced apart from the conductive structure. The distance between the adjacent conductive traces and the conductive structure is greater than or equal to 200 μm.

[0012] For example, in a wiring substrate provided in one embodiment of this disclosure, the spacing between the adjacent conductive traces and the conductive structure ranges from 200μm to 800μm.

[0013] For example, in a wiring substrate provided in an embodiment of this disclosure, the plurality of signal lines include a first type of signal line, wherein the orthographic projections of M conductive extensions of the conductive structure on the substrate overlap with the orthographic projection of one of the first type of signal lines on the substrate, where M is greater than 1, and the plurality of signal lines also include a second type of signal line, wherein the orthographic projection of one conductive extension of the conductive structure on the substrate overlaps with the orthographic projection of one of the second type of signal lines on the substrate.

[0014] For example, in a wiring substrate provided in one embodiment of this disclosure, the conductive extensions of the M conductive structures are connected to each other.

[0015] For example, in a wiring substrate provided in an embodiment of this disclosure, the ratio of the sum of the areas of the at least one second via of the M conductive structures projected onto the substrate to the sum of the areas of the at least one first via of the M conductive structures projected onto the substrate is greater than or equal to 0.8.

[0016] For example, in a wiring substrate provided in an embodiment of this disclosure, each of the conductive structures further includes a second sub-pad located in the first conductive layer. The first sub-pad is directly connected to the second sub-pad through the at least one first via. The second sub-pad is also connected to the signal line located in the first conductive layer.

[0017] For example, in a wiring substrate provided in one embodiment of this disclosure, the ends of the conductive extensions of the plurality of conductive structures near the in-plane region are flush.

[0018] For example, in a wiring substrate provided in an embodiment of this disclosure, the plurality of conductive structures are arranged along a second direction, the first sub-pad and the conductive extension of each conductive structure extend along the first direction, the dimension of the first via of each conductive structure along the first direction is greater than or equal to the dimension along the second direction, and the dimension of the second via of each conductive structure along the first direction is greater than or equal to the dimension along the second direction.

[0019] For example, in a wiring substrate provided in an embodiment of this disclosure, the plurality of conductive structures are arranged along a second direction, and the first sub-pad and the conductive extension of each conductive structure extend along the first direction. The first boundary of the second insulating layer group is located between the orthogonal projections of the at least one first via and the at least one second via on the substrate. Along the first direction, the minimum distance between the first boundary of the second insulating layer group and the at least one first via is greater than or equal to 300 μm, and the distance between the first boundary of the second insulating layer group and the at least one second via is greater than or equal to 100 μm.

[0020] For example, in a wiring substrate provided in an embodiment of this disclosure, the first insulating layer group includes a first insulating layer and a first passivation layer stacked together, the thickness of the first insulating layer being greater than the thickness of the first passivation layer; the second insulating layer group includes a second insulating layer and a second passivation layer stacked together, the thickness of the second insulating layer being greater than the thickness of the second passivation layer.

[0021] For example, in a wiring substrate provided in an embodiment of this disclosure, the wiring substrate further includes a supplementary insulating layer, the supplementary insulating layer being located between the first conductive layer and the second conductive layer, and the second boundary of the supplementary insulating layer being further away from the first via in the orthographic projection on the substrate than the first boundary of the second insulating layer group.

[0022] For example, in a wiring substrate provided in an embodiment of this disclosure, the conductive extension of each conductive structure includes a first sub-part and a second sub-part. The first sub-part connects the first sub-pad and the second sub-part. The second sub-part is directly connected to the signal line of the first conductive layer through the at least one second via. The plurality of signal lines include a first type of signal line. The orthographic projection of the conductive extensions of the M conductive structures onto the substrate is located within the orthographic projection of a first type of signal line onto the substrate. At least one of the first conductive pad, the first sub-part, and the second sub-part of the M conductive structures is spaced apart.

[0023] For example, in a wiring substrate provided in one embodiment of this disclosure, the depth of the first via is less than or equal to the depth of the second via.

[0024] For example, in a wiring substrate provided in an embodiment of this disclosure, the in-plane region of the wiring substrate includes a plurality of first pads and a plurality of second pads at least partially located in the second conductive layer, each of the first pads being configured to be connected to the electrodes of the micro-driver chip, and each of the second pads being configured to be connected to the electrodes of the micro-light-emitting diode.

[0025] For example, in a wiring substrate provided in an embodiment of this disclosure, the plurality of first pads and the plurality of second pads are at least partially located in the second conductive layer, and the conductive traces connected to the first pads or the second pads are located in the second conductive layer.

[0026] For example, in a wiring substrate provided in an embodiment of this disclosure, the material of the first conductive layer includes copper, and the material of the second conductive layer includes copper.

[0027] For example, in a wiring substrate provided in an embodiment of this disclosure, the in-plane region of the wiring substrate includes a plurality of first pads at least partially located in the second conductive layer. Each first pad is configured to be connected to an electrode of a micro-driver chip. The plurality of first pads are divided into a plurality of first pad groups, each first pad group including a plurality of first pads. The plurality of first pad groups are arranged in an array along the first direction and the second direction to form a plurality of first pad columns extending along the first direction and arranged along the second direction. The plurality of first pad groups in each first pad column include interconnect pad groups. The plurality of first pads in the interconnect pad groups include first sub-pads, which are adjacent along the first direction. The two first sub-pads of the two interconnect pads of the two first pad columns are connected to each other by a first connection line. The first connection line includes a first connection sub-part and at least one second connection sub-part connected to each other. The first connection sub-part is located in the first conductive layer, and the second connection sub-part is located in the second conductive layer. The in-plane area of ​​the wiring substrate also includes a plurality of second pads at least partially located in the second conductive layer and a plurality of conductive traces located in the second conductive layer. Each second pad is configured to be connected to an electrode of a micro light-emitting diode. The first pads and the second pads are connected by the conductive traces to enable the micro driver chip to drive the micro light-emitting diode to emit light.

[0028] For example, in a wiring substrate provided in an embodiment of this disclosure, the plurality of second pads are divided into a plurality of second pad pairs, the plurality of second pad pairs are divided into a plurality of second pad groups, each second pad group includes a plurality of second pad pairs, the plurality of second pad pairs in each second pad group are connected in series sequentially, one end of the plurality of second pad pairs in the second pad group is connected to the drive voltage signal line in the plurality of signal lines through the conductive trace, and the other end is connected to the first pad of the first pad group through the conductive trace.

[0029] For example, in a wiring substrate provided in an embodiment of this disclosure, the plurality of signal lines include a third type of signal line located between two adjacent first pad columns. The third type of signal line extends along the first direction. The third type of signal line also includes a first interval and a first body portion and a second body portion located on both sides of the first interval. The orthographic projection of the first connecting sub-part of the first connecting line on the substrate overlaps with the orthographic projection of the first interval of the third type of signal line on the substrate. The second conductive layer also includes a first bridging wire, which connects the first body portion and the second body portion.

[0030] For example, in a wiring substrate provided in one embodiment of this disclosure, the dimension of the first bridging wire along the second direction is greater than the dimension of the first connecting sub-part along the first direction.

[0031] For example, in a wiring substrate provided in an embodiment of this disclosure, the plurality of signal lines further includes a fourth type of signal line located between two adjacent first pad columns. The fourth type of signal line extends along the first direction, and the orthographic projection of the second connecting portion of the first connecting line on the substrate overlaps with the orthographic projection of the fourth type of signal line on the substrate.

[0032] For example, in a wiring substrate provided in an embodiment of this disclosure, the fourth type of signal line includes a second bridge wire and a third main body portion and a fourth main body portion located on both sides of the second bridge wire. The second bridge wire, the third main body portion and the fourth main body portion are all located in the first conductive layer. The ratio of the dimension of the third main body portion and the fourth main body portion along the second direction to the dimension of the second bridge wire along the second direction is greater than or equal to 3. The orthographic projection of the second connecting sub-part on the substrate overlaps with the orthographic projection of the second bridge wire on the substrate.

[0033] For example, in a wiring substrate provided in one embodiment of this disclosure, the dimension of the first bridging wire along the second direction is greater than or equal to the dimension of the second bridging wire along the second direction.

[0034] For example, in a wiring substrate provided in one embodiment of this disclosure, a virtual extension line passing through the end of the first connecting sub-part and extending along the first direction passes through the fourth type of signal line.

[0035] For example, in a wiring substrate provided in an embodiment of this disclosure, a fourth signal line includes a first edge and a second edge opposite to each other along a second direction, the first edge being closer to the third signal line than the second edge, the second bridging wire being located between the first edge and the second edge and closer to the second edge, or the second bridging wire being located at the second edge, and the first connecting sub-part extending to the second bridging wire and spaced apart from the second bridging wire.

[0036] For example, in a wiring substrate provided in an embodiment of this disclosure, the first connecting line includes two second connecting sub-parts, the first connecting sub-parts being located between the two second connecting sub-parts and connecting the two second connecting sub-parts together.

[0037] For example, in a wiring substrate provided in an embodiment of this disclosure, the plurality of first pads of the interconnect pad group further include second sub-pads. The two second sub-pads of the two interconnect pads of two adjacent first pad columns along the first direction are connected to each other by a second connection line. The second connection line includes a third connection sub-part and at least one fourth connection sub-part. The third connection sub-part is located in the first conductive layer, and the fourth connection sub-part is located in the second conductive layer. A shielding line is provided between the first connection sub-part and the third connection sub-part. The shielding line is located in the first conductive layer and connected to the ground line among the plurality of signal lines.

[0038] For example, in a wiring substrate provided in one embodiment of this disclosure, the ratio of the length of the shielding wire to the length of the first connecting sub-part is greater than or equal to 0.8.

[0039] For example, in a wiring substrate provided in one embodiment of this disclosure, the ratio of the length of the first connecting sub-part to the length of the first connecting line is greater than 0.5.

[0040] At least one embodiment of this disclosure provides a display device including the wiring substrate described in any of the preceding claims. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0042] Figure 1 is a schematic diagram of a substrate bonding structure;

[0043] Figure 2 shows the failure diagram of the defective product;

[0044] Figure 3 is a plan view of a wiring substrate provided in an embodiment of this disclosure;

[0045] Figure 4 is a partially enlarged schematic diagram of the wiring substrate shown in Figure 3 at the selected location;

[0046] Figure 5 is a cross-sectional view of the wiring substrate shown in Figure 4 along section line KK.

[0047] Figure 6 is a cross-sectional view of the wiring substrate shown in Figure 4 along section line LL.

[0048] Figure 7 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0049] Figure 8 is a cross-sectional view of the wiring substrate shown in Figure 4 along the section line MM.

[0050] Figure 9 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0051] Figure 10 is a cross-sectional view of the wiring substrate shown in Figure 9 along the section line MM.

[0052] Figure 11 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0053] Figure 12 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0054] Figure 13 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0055] Figure 14 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0056] Figure 15 is a cross-sectional view of the wiring substrate shown in Figure 14 along section line KK.

[0057] Figure 16 is a cross-sectional view of the wiring substrate shown in Figure 14 along section line LL;

[0058] Figure 17 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0059] Figure 18 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0060] Figure 19 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0061] Figure 20 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0062] Figure 21 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0063] Figure 22A is another enlarged view of the wiring substrate shown in Figure 3 at the selected location;

[0064] Figure 22B is another enlarged view of the wiring substrate shown in Figure 22A at the selected location;

[0065] Figure 23 is a partially enlarged schematic diagram of the wiring substrate shown in Figure 22B at the selected location;

[0066] Figure 24 is a film layer diagram of a micro light-emitting diode substrate;

[0067] Figure 25 is a partial planar structure diagram and a failure diagram of a micro light-emitting diode substrate;

[0068] Figure 26 is a plan view of a wiring substrate provided in an embodiment of this disclosure;

[0069] Figure 27 is a partially enlarged schematic diagram of the wiring substrate shown in Figure 26 at the selected location;

[0070] Figure 28 is a partially enlarged schematic diagram of the wiring substrate shown in Figure 27 at the selected location;

[0071] Figure 29 is a schematic diagram of the film layers of the wiring substrate shown in Figure 26;

[0072] Figure 30 is another enlarged view of the wiring substrate shown in Figure 26 at the selected location;

[0073] Figure 31 is a partially enlarged schematic diagram of the wiring substrate shown in Figure 30 at the selected location; and

[0074] Figure 32 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0076] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0077] The components or structures in the accompanying drawings are not drawn to scale. For clarity, the dimensions of the components or structures may be exaggerated or reduced, but this should not be used to limit the scope of this disclosure. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components may be omitted.

[0078] Unless otherwise defined, the features such as "parallel," "perpendicular," and "identical" used in the embodiments of this disclosure include strictly defined cases of "parallel," "perpendicular," and "identical," as well as cases involving a certain degree of error, such as "approximately parallel," "approximately perpendicular," and "approximately identical." For example, the aforementioned "approximately" may indicate that the difference between the compared objects is within 10% or 5% of the average value of the compared objects. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component or element is implied to mean that the component or element may be one or more, or can be understood as at least one. "At least one" refers to one or more, and "more" refers to at least two. In the embodiments of this disclosure, "same-layer arrangement" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). Here, "same-layer" does not always mean that the multiple film layers have the same thickness or that the multiple film layers have the same height in a cross-sectional view.

[0079] Currently, common Mini-LED glass substrates typically employ double-layer or single-layer copper trace designs. For Mini-LED product designs with narrow bezels or high partitioning, due to space limitations, double-layer copper technology is generally used to fabricate the in-plane driving circuitry. However, during product reliability testing, insufficient product reliability was found.

[0080] Figure 1 is a schematic diagram of a substrate bonding structure. Figure 1(a) is a plan view, and Figure 1(b) is a cross-sectional view along the cutting line HH. As shown in Figure 1, the existing double-layer copper trace design involves two copper layers, copper layer 01 and copper layer 02, on a glass substrate 00, with an insulating layer 03 and a passivation layer 04 for insulation. Copper layer 01 is used as the signal line 05. The bonding area consists of a pad 06 on copper layer 01 directly connected to the signal line 05 within the surface of copper layer 01. A pad 07 of copper layer 02 is placed on the pad 06 of copper layer 01, and the pads 06 and 07 are connected through vias in the insulating layer 03 and the passivation layer 04. After bonding, the bonding pins of the circuit board directly contact the pad 07 of copper layer 02, and current flows through the circuit board, pad 07, and pad 06 into the signal line 05 of copper layer 01.

[0081] However, existing products exhibit complete lamp failure during reliability testing. Analysis reveals a significant increase in impedance in the bonding area. The impedance of normal products ranges from 0.5 to 2 ohms, while that of defective products ranges from tens of ohms to tens of kiloohms. Figure 2 shows the failure diagram of the defective product. Figure 2(a) is a microscopic view of the defective product failure, and Figure 2(b) is a structural schematic diagram of the failure. As shown in Figure 2, delamination occurs between gaskets 06 and 07 in the defective product, with a gap 08 between them. This increases the contact impedance, preventing normal signal transmission and resulting in complete lamp failure, thus causing the product reliability test to fail.

[0082] This disclosure provides a wiring substrate and a display device. The wiring substrate includes a substrate, a first conductive layer, a first insulating layer group, a second conductive layer, and a second insulating layer group. The first conductive layer is located on the substrate and includes a plurality of signal lines. The first insulating layer group is located on the side of the first conductive layer away from the substrate. The second conductive layer is located on the side of the first insulating layer group away from the substrate, and the second insulating layer group is located on the side of the second conductive layer away from the substrate. The wiring substrate includes an in-plane region and a peripheral region at least partially surrounding the in-plane region. The peripheral region includes a lead-out region and a bonding region. The wiring substrate also includes a plurality of conductive structures located in the peripheral region. Each conductive structure includes a first sub-pad located in the second conductive layer, a conductive extension connected to the first sub-pad, and at least one first via and at least one second via penetrating the first insulating layer group. The orthographic projection of the at least one first via onto the substrate is outside the orthographic projection of the second insulating layer group onto the substrate, and the orthographic projection of the at least one second via onto the substrate is within the orthographic projection of the second insulating layer group onto the substrate. The orthographic projection of the first sub-pad onto the substrate is outside the orthographic projection of the second insulating layer group onto the substrate. The conductive extension is covered by the second insulating layer group. The first sub-pad is located in the bonding region, and at least a portion of the conductive extension is located in the lead-out region. A portion of the first sub-pad of each conductive structure is located within at least one first via, and the conductive extension is directly connected to the signal line of the first conductive layer through at least one second via. Thus, the first sub-pad located in the second conductive layer can be connected to the signal line located in the first conductive layer through the conductive extension. The conductive extension is covered by the second insulating layer group, which protects the conductive extension. By connecting the first sub-pad to the signal line through the conductive extension, the risk of failure caused by heat in the bonding area can be avoided, thus ensuring the bonding effect.

[0083] The wiring substrate and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0084] This disclosure provides a wiring substrate. Figure 3 is a plan view of a wiring substrate provided in this disclosure; Figure 4 is a partially enlarged view of the wiring substrate shown in Figure 3 at the selected location; Figure 5 is a cross-sectional view of the wiring substrate shown in Figure 4 along section line KK; Figure 6 is a cross-sectional view of the wiring substrate shown in Figure 4 along section line LL.

[0085] As shown in Figures 3 to 6, the wiring substrate 100 includes a substrate 101, a first conductive layer 110, a first insulating layer group 120, a second conductive layer 130, and a second insulating layer group 140. The first conductive layer 110 is located on the substrate 101 and includes a plurality of signal lines 160. The first insulating layer group 120 is located on the side of the first conductive layer 110 away from the substrate 101. The second conductive layer 130 is located on the side of the first insulating layer group 120 away from the substrate 101, and the second insulating layer group 140 is located on the side of the second conductive layer 130 away from the substrate 101. The wiring substrate 100 includes an in-plane region AA and a peripheral region BB that at least partially surrounds the in-plane region AA. The peripheral region BB includes a lead-out region B1 and a bonding region B2. The wiring substrate 100 also includes a plurality of conductive structures located in the peripheral region BB. Each conductive structure includes a first sub-pad 151 located in the second conductive layer 130, a conductive extension 153 connected to the first sub-pad 151, and at least one first via V1 and at least one second via V2 penetrating the first insulating layer group 120. The orthographic projection of the at least one first via V1 onto the substrate 101 is outside the orthographic projection of the second insulating layer group 140 onto the substrate 101, and the orthographic projection of the at least one second via V2 onto the substrate 101 is within the orthographic projection of the second insulating layer group 140 onto the substrate 101. The orthographic projection of the first sub-pad 151 onto the substrate 101 is outside the orthographic projection of the second insulating layer group 140 onto the substrate 101, and the conductive extension 153 is covered by the second insulating layer group 140. The first sub-pad 151 is located in the bonding region B2, and at least a portion of the conductive extension 153 is located in the lead-out region B1. A portion of the first sub-pad 151 of each conductive structure is located in at least one first via V1, and the conductive extension 153 is directly connected to the signal line 160 of the first conductive layer 110 through at least one second via V2.

[0086] In the wiring substrate 100 provided in this embodiment, the conductive structure includes a first sub-pad 151 located in the bonding region B2 and a conductive extension 153 connected to the first sub-pad 151 and at least partially located in the lead-out region B1. The conductive extension 153 is connected to a signal line 160 located in the first conductive layer 110 through at least one second via V2. Thus, the first sub-pad 151 located in the second conductive layer 130 can be connected to the signal line 160 located in the first conductive layer 110 via the conductive extension 153. The conductive extension 153 is covered by a second insulating layer group 140, which protects the conductive extension 153.

[0087] For example, the wiring substrate 100 can be a micro-light-emitting diode substrate, and multiple micro-light-emitting diodes and multiple micro-driving chips can be bonded to the wiring substrate so that the micro-driving chips control the light emission of the micro-light-emitting diodes. Compared with the array substrate of liquid crystal display (LCD) or the light-emitting substrate of organic light-emitting diode display (OLED), the current value of the sub-pads in the bonding area of ​​the wiring substrate is hundreds of times that of the sub-pads in the bonding area of ​​the array substrate of LCD or the light-emitting substrate of OLED. When current passes through the bonding area B2, especially when a large current passes through the bonding area B2, a large amount of heat is generated in the bonding area B2. If the bonding area B2 uses two interconnected pads, the heat will cause the two pads to separate, resulting in bonding failure. By connecting the first sub-pad 151 to the signal line 160 through the conductive extension 153, the risk of bonding failure caused by the heat in the bonding area B2 can be avoided, ensuring the bonding effect. For example, the wiring substrate 100 can be used in the backlight module of a liquid crystal display panel. For example, the wiring substrate 100 can also be used for direct display. This disclosure does not limit the scope of the embodiments.

[0088] In some examples, as shown in Figures 4 to 6, the orthographic projection of the conductive extension 153 of each conductive structure onto the substrate 101 overlaps with the orthographic projection of the signal line 160 on the first conductive layer 110 onto the substrate 101. For example, the orthographic projection of the first sub-pad 151 of each conductive structure onto the substrate 101 does not overlap with the orthographic projection of the signal line 160 or conductive trace on the first conductive layer 110 onto the substrate 101.

[0089] In some examples, as shown in FIG5, the conductive extension 153 is located in the second conductive layer 130. For example, the conductive extension 153 and the first sub-pad 151 are formed using the same material and the same patterning process. Therefore, the figure schematically shows that the conductive extension 153 and the first sub-pad 151 use the same filling pattern.

[0090] In some examples, as shown in Figures 4 to 6, the ratio of the area of ​​the orthographic projection of the at least one second via V2 of each conductive structure onto the substrate 101 to the area of ​​the orthographic projection of the at least one first via V1 onto the substrate 101 is greater than or equal to 0.8. That is, the ratio of the sum of the areas of the orthographic projections of all second vias V2 of each conductive structure onto the substrate 101 to the sum of the areas of the orthographic projections of all first vias V1 onto the substrate 101 is greater than or equal to 0.8. This improves current throughput. For example, this ratio can be 0.9, 1, 1.2, 1.5, etc., which will not be elaborated further here.

[0091] In some examples, as shown in FIG4, the first sub-pad 151 of each conductive structure extends along a first direction X. For example, the conductive extension 153 of each conductive structure extends along the first direction X. For example, multiple conductive structures are arranged along a second direction Y, where the first direction X and the second direction Y intersect. For example, the first sub-pad 151 and the conductive extension 153 are elongated. Of course, the shapes of the first sub-pad 151 and the conductive extension 153 are not limited in the embodiments of this disclosure.

[0092] In some examples, as shown in Figure 4, the dimension of the first via V1 of each conductive structure along the first direction X is greater than or equal to the dimension along the second direction Y. For example, the dimension of the second via V2 of each conductive structure along the first direction X is greater than or equal to the dimension along the second direction Y. This allows for maximizing the area of ​​the first via V1 and the second via V2, improving current throughput. For example, the first via V1 and the second via V2 may be elongated. Of course, the shapes of the first via V1 and the second via V2 are not limited in this embodiment.

[0093] In some examples, as shown in Figure 4, both the first sub-pad 151 and the conductive extension 153 extend along the first direction X. The ratio of the dimension D2 of the at least one second via V2 of each conductive structure along the first direction X to the dimension D1 of the at least one first via V1 along the first direction X is greater than or equal to 0.8. That is, the ratio of the sum of the dimensions of all second vias V2 of each conductive structure along the first direction X to the sum of the dimensions of all first vias V1 along the first direction X is greater than or equal to 0.8. This improves current throughput. For example, this ratio can be 0.9, 1, 1.2, 1.5, etc., which will not be elaborated here. The figure schematically shows that dimension D2 is the sum of dimensions D21 and dimension D22.

[0094] In some examples, as shown in Figures 4 and 5, the conductive extension 153 of each conductive structure includes a first sub-part 1531 and a second sub-part 1532. The first sub-part 1531 connects the second sub-part 1532 and the first sub-pad 151. The second sub-part 1532 is directly connected to the signal line 160 of the first conductive layer 110 through a second via V2. This maximizes the spacing between the second via V2 and the first sub-pad 151 in the first direction X, avoiding adverse effects of heat during the bonding process on the conduction between the second sub-part 1532 and the signal line 160, thus ensuring the reliability of the bonding.

[0095] In some examples, as shown in FIG4, the ratio of the dimension D2 of the at least one second via V2 along the first direction X of each conductive structure to the sum of the dimensions D3 of the conductive extension 153 and the first sub-pad 151 along the first direction X is less than or equal to 0.5. Therefore, the distance D between the second via V2 and the first sub-pad 151 in the first direction X can be maximized. For example, this ratio is less than or equal to 0.4. For example, this ratio is less than or equal to 0.3, and so on.

[0096] In some examples, as shown in Figures 4 and 5, multiple conductive structures are arranged along the second direction Y, and the first sub-pad 151 and conductive extension 153 of each conductive structure extend along the first direction X. The orthographic projection of the first boundary L1 of the second insulating layer group 140 onto the substrate 101 lies between the orthographic projections of the first via V1 and the second via V2 onto the substrate 101. Along the first direction X, the minimum spacing D4 between the first boundary L1 of the second insulating layer group 140 and the first via V1 is greater than or equal to 300 μm. This minimizes the influence of the second insulating layer group 140 on the first sub-pad 151, avoiding adverse effects on bonding. For example, this spacing D4 is greater than or equal to 350 μm, or greater than or equal to 400 μm, which will not be elaborated further here.

[0097] In some examples, as shown in Figures 4 and 5, the minimum distance D5 between the first boundary L1 of the second insulating layer group 140 and the second via V2 is greater than or equal to 100 μm. This allows for maximum coverage of the second via V2 to protect the conductive extension 153. For example, this distance D5 may be greater than or equal to 150 μm, or greater than or equal to 200 μm, and will not be elaborated further here.

[0098] In some examples, as shown in Figure 5, the depth of the first via V1 is less than or equal to the depth of the second via V2. This minimizes the depth of the first via V1, ensuring reliable bonding.

[0099] In some examples, as shown in Figures 4 and 5, the conductive structure includes a first via V1. For example, a first via V1 extends along a first direction X. By providing a via in the same area, compared to providing multiple first vias V1, providing a single first via V1 allows for a larger area of ​​the first via V1. This increases the contact area of ​​the first sub-pad 151 and reduces the impedance of the conductive structure. Of course, this disclosure does not limit this aspect. For example, the conductive structure may also include multiple first vias V1. Thus, if one first via V1 fails to conduct, conduction can be achieved through other vias, improving the stability of the bonding. For example, the multiple first vias V1 of the conductive structure are arranged along the first direction X.

[0100] In some examples, as shown in Figures 4 and 5, the conductive structure includes two second vias V2. Of course, the number of second vias V2 in the conductive structure is not limited in the embodiments of this disclosure. For example, the conductive structure may also include multiple second vias V2. Thus, if one second via V2 fails to conduct, conduction can be achieved through other vias, improving the stability of the bonding. For example, the multiple second vias V2 of the conductive structure are arranged along the first direction X.

[0101] Figure 7 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location.

[0102] As shown in Figure 7, the conductive structure of the wiring substrate includes a second via V2. For example, the second via V2 extends along the first direction X. By providing a single second via V2 within the same region, compared to providing multiple second vias V2, the area of ​​the second via V2 can be increased. Therefore, when the conductive structure includes a second via V2, the contact area between the conductive extension 153 and the signal line 160 can be increased, thereby improving current carrying capacity.

[0103] Other features of the conductive structure shown in Figure 7 can be found in other embodiments of this document, and will not be described in detail here. For example, the cross-sectional views of Figure 7 along section lines KK, LL, and MM can be found in Figures 5, 6, and 8 below, and will not be described in detail here.

[0104] Figure 8 is a schematic cross-sectional view of the wiring substrate shown in Figure 4 along section line MM. As shown in Figures 4 and 8, the plurality of signal lines 160 include a first type of signal line 1601. The orthographic projections of M conductive extensions 153 of conductive structures on the substrate 101 overlap with the orthographic projection of one first type of signal line 1601 on the substrate 101, where M is greater than 1. The figures schematically show the overlap of the orthographic projections of at least eight conductive extensions 153 of conductive structures on the substrate 101 with the orthographic projection of one first type of signal line 1601 on the substrate 101. For example, the first type of signal line 1601 includes a driving voltage line, a ground line, a working voltage line, etc. The type of the first type of signal line 1601 is not limited in the embodiments of this disclosure.

[0105] In some examples, as shown in Figures 4 and 8, the orthographic projection of the second via V2 of the M conductive structures onto the substrate 101 lies within the orthographic projection of a first signal line 1601 onto the substrate 101.

[0106] In some examples, as shown in Figures 4 and 8, at least two conductive extensions 153 of the M conductive structures are spaced apart. For example, all conductive extensions 153 of the M conductive structures are spaced apart. For example, at least two conductive structures among the M conductive structures are spaced apart. For example, all M conductive structures are spaced apart from each other. Therefore, when the conductive extension 153 of one conductive structure fails to conduct to the signal line 160, conduction can be achieved through the conductive extensions 153 of other conductive structures to the signal line 160, improving the stability of the bonding.

[0107] In some examples, as shown in Figures 4 and 8, the conductive extension 153 of each conductive structure includes a first sub-section 1531 and a second sub-section 1532, with at least two first sub-sections 1531 of the M conductive structures spaced apart. For example, the first sub-sections 1531 of the M conductive structures are all spaced apart. For example, at least two second sub-sections 1532 of the M conductive structures are spaced apart. For example, the second sub-sections 1532 of the M conductive structures are all spaced apart.

[0108] In some examples, as shown in FIG4, the plurality of signal lines 160 further include a second type of signal line 1602, wherein the orthographic projection of a conductive extension 153 of a conductive structure on the substrate 101 overlaps with the orthographic projection of a second type of signal line 1602 on the substrate 101. For example, the second type of signal line 1602 includes address signal lines 160, clock signal lines 160, signal connection lines, etc. The type of the second type of signal line 1602 is not limited in the embodiments of this disclosure.

[0109] In some examples, as shown in FIG4, the orthographic projection of the at least one second via V2 of a conductive structure onto the substrate 101 lies within the orthographic projection of a second signal line 1602 onto the substrate 101.

[0110] In some examples, as shown in Figure 4, the first sub-pads 151 of the M conductive structures are spaced apart. This ensures the discharge of conductive adhesive during the bonding process.

[0111] Figure 9 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location; Figure 10 is a cross-sectional view of the wiring substrate shown in Figure 9 along the section line MM.

[0112] As shown in Figures 9 and 10, the plurality of signal lines 160 include a first type of signal line 1601. The orthographic projection of the conductive extensions 153 of the M conductive structures onto the substrate 101 overlaps with the orthographic projection of one first type of signal line 1601 onto the substrate 101. At least two conductive extensions 153 of the M conductive structures are connected to each other. By connecting at least two conductive extensions 153 of the M conductive structures to each other, not only are the size, shape, and position of the second via V2 no longer limited by the size or shape of a single conductive extension 153, facilitating the design of the conductive structure, but the total area of ​​the conductive extensions 153 of the M conductive structures is also increased, thereby increasing the total area of ​​the second via V2 of the M conductive structures and further improving the current throughput. For example, all conductive extensions 153 of the M conductive structures are connected. For example, all conductive extensions 153 in the M conductive structures are connected as one unit. The figures schematically show that the second vias V2 of the M conductive structures are spaced apart from each other; however, the embodiments disclosed herein do not limit this. For example, the second vias V2 of the interconnected conductive extensions 153 can also be interconnected, thereby increasing the total area of ​​the second vias V2 and improving current throughput.

[0113] In some examples, as shown in FIG9, the conductive extension 153 of each conductive structure includes a first sub-section 1531 and a second sub-section 1532, and at least two first sub-sections 1531 of the M conductive structures are connected to each other. For example, all the first sub-sections 1531 of the M conductive structures are connected to each other.

[0114] In some examples, as shown in Figures 9 and 10, at least two second sub-parts 1532 of the M conductive structures are connected to each other. For example, all the second sub-parts 1532 of the M conductive structures are connected to each other.

[0115] In some examples, as shown in FIG9, the orthographic projection of the at least one second via V2 of the M conductive structures onto the substrate 101 lies within the orthographic projection of a first signal line 1601 onto the substrate 101.

[0116] In some examples, as shown in Figure 9, all conductive extensions 153 of the M conductive structures are interconnected, and the ratio of the sum of the areas of the second vias V2 of the M conductive structures projected onto the substrate 101 to the sum of the areas of the first vias V1 of the M conductive structures projected onto the substrate 101 is greater than or equal to 0.8. This improves current throughput. For example, this ratio can be 0.9, 1, 1.2, 1.5, etc., which will not be elaborated further here.

[0117] Other features of the conductive structure shown in Figure 9 can be found in other embodiments of this document, and will not be described in detail here. For example, the cross-sectional views along section line KK and section line LL in Figure 9 can be found in Figures 5 and 6, and will not be described in detail here.

[0118] Figure 11 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location.

[0119] As shown in Figure 11, the conductive structure of the wiring substrate includes a second via V2, and a plurality of signal lines 160 include a first type of signal line 1601. The orthographic projections of the conductive extensions 153 of the M conductive structures on the substrate 101 overlap with the orthographic projections of the first type of signal line 1601 on the substrate 101, and the conductive extensions 153 of the M conductive structures are interconnected. Including a second via V2 in the conductive structure increases the contact area between the conductive extensions 153 and the signal lines 160, improving current throughput. By connecting the conductive extensions 153 of the M conductive structures, the design of the conductive structure is facilitated, and current throughput is further improved. The figure schematically shows the second vias V2 of the M conductive structures spaced apart; however, this is not a limitation of the embodiments disclosed herein. For example, the second vias V2 of the interconnected conductive extensions 153 can also be interconnected, thereby increasing the total area of ​​the second vias V2 and improving current throughput.

[0120] Other features of the conductive structure shown in Figure 11 can be found in other embodiments herein, and will not be described in detail here. For example, the cross-sectional views of Figure 11 along section line KK and section line LL can be found in Figures 5 and 6. For example, the cross-sectional view of Figure 11 along section line MM can be found in Figure 10, and will not be described in detail here.

[0121] Figure 12 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location.

[0122] As shown in Figure 12, the plurality of signal lines 160 include a first type of signal line 1601. The orthographic projections of the conductive extensions 153 of M conductive structures on the substrate 101 overlap with the orthographic projection of one first type of signal line 1601 on the substrate 101. Each conductive extension 153 of the conductive structure includes a first sub-part 1531 and a second sub-part 1532. For example, at least two second sub-parts 1532 of the M conductive structures are connected to each other. For example, all the second sub-parts 1532 of the M conductive structures are connected to each other. For example, at least two first sub-parts 1531 of the M conductive structures are spaced apart from each other. For example, all the first sub-parts 1531 of the M conductive structures are spaced apart from each other. By connecting at least two second sub-parts 1532, the design of the second via V2 of the conductive structure is facilitated, and the current throughput can be improved. By spaced at least two first sub-parts 1531 from each other, defects in the first sub-parts 1531 can be prevented from affecting adjacent first sub-parts 1531, thus improving the stability of the bonding.

[0123] Other features of the conductive structure shown in Figure 12 can be found in other embodiments of this document, and will not be described in detail here. For example, the cross-sectional views of Figure 12 along section line KK and section line LL can be found in Figures 5 and 6. For example, the cross-sectional view of Figure 12 along section line MM can be found in Figure 10, and will not be described in detail here.

[0124] Figure 13 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location.

[0125] As shown in Figure 13, the plurality of signal lines 160 include a first type of signal line 1601. The orthographic projection of the conductive extensions 153 of M conductive structures on the substrate 101 overlaps with the orthographic projection of one first type of signal line 1601 on the substrate 101. Each conductive extension 153 of the conductive structure includes a first sub-part 1531 and a second sub-part 1532. For example, at least two second sub-parts 1532 of the M conductive structures are spaced apart. For example, all the second sub-parts 1532 of the M conductive structures are spaced apart. For example, at least two first sub-parts 1531 of the M conductive structures are connected to each other. For example, all the first sub-parts 1531 of the M conductive structures are connected to each other. By spacing at least two second sub-parts 1532 from each other, when one second sub-part 1532 fails to conduct, conduction can be achieved through the other second sub-parts 1532, improving the stability of the bonding.

[0126] Other features of the conductive structure shown in Figure 13 can be found in other embodiments of this document, and will not be described in detail here. For example, the cross-sectional views of Figure 13 along section line KK and section line LL can be found in Figures 5 and 6. For example, the cross-sectional view of Figure 13 along section line MM can be found in Figure 10, and will not be described in detail here.

[0127] Figure 14 is another enlarged view of the wiring substrate shown in Figure 3 at the selected position; Figure 15 is a cross-sectional view of the wiring substrate shown in Figure 14 along section line KK; Figure 16 is a cross-sectional view of the wiring substrate shown in Figure 14 along section line LL.

[0128] As shown in Figures 14 to 16, each conductive structure of the wiring substrate further includes a second sub-pad 152 located in the first conductive layer 110. The first sub-pad 151 is directly connected to the second sub-pad 152 through at least one first via V1, and the second sub-pad 152 is also connected to the signal line 160 located in the first conductive layer 110. Thus, the first sub-pad 151 can also be connected to the signal line 160 located in the first conductive layer 110 through the second sub-pad 152.

[0129] In some examples, as shown in Figure 15, the second sub-pad 152 is located in the first conductive layer 110. For example, the second sub-pad 152 and the signal line 160 located in the first conductive layer 110 are formed using the same material and the same patterning process. Therefore, the figure schematically shows that the second sub-pad 152 and the signal line 160 use the same fill pattern.

[0130] In some examples, as shown in Figure 14, the conductive structure includes a first via V1. For example, the conductive structure includes two second vias V2. The number of first vias V1 in this disclosure is not limited, and there may be multiple first vias V1; the number of second vias V2 is also not limited, and there may be one or more second vias V2.

[0131] Figure 17 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location.

[0132] As shown in Figure 17, the conductive structure of the wiring substrate includes a second via V2. Including a second via V2 in the conductive structure increases the contact area between the conductive extension 153 and the signal line 160, thereby improving current throughput.

[0133] Other features of the conductive structure shown in Figure 17 can be found in other embodiments of this document, and will not be described in detail here. For example, the cross-sectional views of Figure 17 along section line KK, section line LL, and section line MM can be found in Figures 15, 16, and 8, and will not be described in detail here.

[0134] In some examples, as shown in Figure 14, a cross-sectional view of the wiring substrate 100 along the section line MM can be seen in Figure 8. The plurality of signal lines 160 include a first type of signal line 1601. The orthographic projections of M conductive extensions 153 of conductive structures onto the substrate 101 overlap with the orthographic projection of one first type of signal line 1601 onto the substrate 101. At least two conductive extensions 153 of the M conductive structures are spaced apart. Therefore, when the conductive extension 153 of one conductive structure fails to conduct, conduction can be achieved through the conductive extensions 153 of other conductive structures, improving the stability of the bonding.

[0135] Figure 18 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location.

[0136] As shown in Figure 18, a cross-sectional view of the wiring substrate along the section line MM can be found in Figure 10. The plurality of signal lines 160 include a first type of signal line 1601. The orthographic projections of the conductive extensions 153 of M conductive structures on the substrate 101 overlap with the orthographic projection of one first type of signal line 1601 on the substrate 101. At least two conductive extensions 153 of the M conductive structures are connected to each other. This not only facilitates the design of the conductive structure but also improves current throughput. For example, all conductive extensions 153 of the M conductive structures are connected.

[0137] In some examples, as shown in FIG18, the conductive extension 153 of each conductive structure includes a first sub-section 1531 and a second sub-section 1532, and at least two first sub-sections 1531 of the M conductive structures are connected to each other. For example, all the first sub-sections 1531 of the M conductive structures are connected to each other. For example, at least two second sub-sections 1532 of the M conductive structures are connected to each other. For example, all the second sub-sections 1532 of the M conductive structures are connected to each other.

[0138] Other features of the conductive structure shown in Figure 18 can be found in other embodiments of this document, and will not be described in detail here. For example, the cross-sectional schematic diagrams along section line KK and section line LL of Figure 18 can be found in Figures 15 and 16, and will not be described in detail here.

[0139] Figure 19 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location.

[0140] As shown in Figure 19, a plurality of signal lines 160 include a first type of signal line 1601. The orthographic projection of M conductive extensions 153 of conductive structures onto the substrate 101 overlaps with the orthographic projection of one first type of signal line 1601 onto the substrate 101. The conductive structure of the wiring substrate 100 includes a second via V2, and the conductive extensions 153 of the M conductive structures are interconnected. When the conductive structure includes a second via V2, the contact area between the conductive extension 153 and the signal line 160 can be increased, thereby improving current conduction performance. By connecting the conductive extensions 153 of the M conductive structures to each other, the design of the conductive structure is facilitated, and current conduction performance is further improved. The figure schematically shows that the second vias V2 of the M conductive structures are spaced apart from each other; however, this is not a limitation of the embodiments disclosed herein. For example, the second vias V2 of the interconnected conductive extensions 153 can also be interconnected, thereby increasing the total area of ​​the second vias V2 and improving current conduction performance.

[0141] Other features of the conductive structure shown in Figure 19 can be found in other embodiments of this document, and will not be described in detail here. For example, the cross-sectional views of Figure 19 along section line KK, section line LL, and section line MM can be found in Figures 15, 16, and 10, and will not be described in detail here.

[0142] Figure 20 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location.

[0143] As shown in Figure 20, the plurality of signal lines 160 include a first type of signal line 1601. The orthographic projection of the conductive extensions 153 of M conductive structures on the substrate 101 overlaps with the orthographic projection of one first type of signal line 1601 on the substrate 101. Each conductive extension 153 of a conductive structure includes a first sub-part 1531 and a second sub-part 1532. At least two second sub-parts 1532 of the M conductive structures are connected to each other. For example, all the second sub-parts 1532 of the M conductive structures are connected to each other. For example, at least two first sub-parts 1531 of the M conductive structures are spaced apart from each other. For example, all the first sub-parts 1531 of the M conductive structures are spaced apart from each other. By connecting at least two second sub-parts 1532, the design of the second via V2 of the conductive structure is facilitated, and the current throughput can be improved. By spaced at least two first sub-parts 1531 from each other, defects in the first sub-parts 1531 can be prevented from affecting adjacent first sub-parts 1531, improving the stability of the bonding.

[0144] Other features of the conductive structure shown in Figure 20 can be found in other embodiments of this document, and will not be described in detail here. For example, the cross-sectional views of Figure 20 along section line KK, section line LL, and section line MM can be found in Figures 15, 16, and 10, and will not be described in detail here.

[0145] Figure 21 is another enlarged view of the wiring substrate shown in Figure 3 at the selected location.

[0146] As shown in Figure 21, the plurality of signal lines 160 include a first type of signal line 1601. The orthographic projection of the conductive extensions 153 of M conductive structures on the substrate 101 overlaps with the orthographic projection of one first type of signal line 1601 on the substrate 101. Each conductive extension 153 of the conductive structure includes a first sub-part 1531 and a second sub-part 1532. For example, at least two second sub-parts 1532 of the M conductive structures are spaced apart. For example, the second sub-parts 1532 31 of the M conductive structures are all spaced apart. For example, at least two first sub-parts 1531 of the M conductive structures are connected to each other. For example, the first sub-parts 1531 of the M conductive structures are all connected to each other. By having at least two second sub-parts 1532 spaced apart from each other, when one second sub-part 1532 fails to conduct, conduction can be achieved through the other second sub-parts 1532, improving the stability of the bonding.

[0147] Other features of the conductive structure shown in Figure 21 can be found in other embodiments of this document, and will not be described in detail here. For example, the cross-sectional views of Figure 21 along section line KK, section line LL, and section line MM can be found in Figures 15, 16, and 10, and will not be described in detail here.

[0148] In some examples, as shown in Figures 4, 7, 9, 11 to 14, and 17 to 21, the wiring substrate further includes a plurality of conductive traces 131 located in the second conductive layer 130. The plurality of conductive traces 131 include adjacent conductive traces 131a that are adjacent to and spaced apart from the conductive structure, with a spacing D6 between the adjacent conductive traces 131a and the conductive structure greater than or equal to 200 μm. This prevents short circuits between the conductive extension 153 located in the second conductive layer 130 and the conductive traces 131. For example, the spacing D6 can be greater than or equal to 300 μm, which will not be elaborated further here. For example, there may be no other conductive traces 131 directly between the adjacent conductive trace 131a and the conductive structure. For example, the adjacent conductive trace 131a may also be the conductive trace 131 with the closest spacing to the conductive structure.

[0149] In some examples, as shown in Figures 4, 7, 9, 11 to 14, and 17 to 21, multiple conductive traces 131 are located in the in-plane region AA. For example, the conductive traces 131 can be connection traces in the in-plane region AA. Of course, this disclosure does not limit this. For example, the conductive traces 131 can also be located in the lead-out region B1.

[0150] In some examples, as shown in Figures 4, 7, 9, 11 to 14, and 17 to 21, the spacing D6 between adjacent conductive traces 131a in the in-plane region AA and the conductive structure ranges from 200 μm to 800 μm. This allows for minimizing the size of the surrounding region BB. For example, the spacing D6 may range from 300 μm to 600 μm, which will not be elaborated further here.

[0151] In some examples, as shown in Figures 4, 7, 9, 11 to 14, and 17 to 21, the conductive extension 153 extends along a first direction X, and the virtual extension lines L2 of the conductive extensions 153 of multiple conductive structures extending along the first direction X intersect with the same adjacent conductive trace 131a. For example, the figures schematically show at least 13 virtual extension lines L2 of conductive structures intersecting with the same adjacent conductive trace 131a. For example, the positions of the adjacent conductive traces 131a and the spacing D6 between the adjacent conductive traces 131a and the conductive structures can be roughly arranged, thereby facilitating the design of the conductive structures in the lead-out area and the bonding area.

[0152] In some examples, as shown in Figures 4, 7, 9, 11 to 14, and 17 to 21, the ends of the conductive extensions 153 of the multiple conductive structures near the in-plane region AA are flush. This facilitates the arrangement of the conductive structures in the peripheral region and the arrangement and appearance of the first sub-pad 151 of the second insulating layer group 140.

[0153] Figure 22A is another enlarged view of the wiring substrate shown in Figure 3 at the selected position; Figure 22B is another enlarged view of the wiring substrate shown in Figure 22A at the selected position; Figure 23 is another enlarged view of the wiring substrate shown in Figure 22B at the selected position.

[0154] As shown in Figures 3, 22A, 22B, and 23, the wiring substrate 100 can be a micro-light-emitting diode (LED) substrate. For example, this LED substrate can be used in the backlight module of a liquid crystal display panel. For example, this LED substrate can also be used for direct display. This disclosure does not limit the scope of the application. For example, during the lighting process of the display device containing the LED substrate, after a large current passes through the first sub-pad 151, it can be connected to the signal line 160 of the first conductive layer 110 via the conductive extension 153, avoiding the bonding failure problem caused by the heat generated by the large current causing the pads in the bonding area B2 to detach.

[0155] In some examples, as shown in Figures 3, 22A, 22B, and 23, multiple signal lines 160 of the first conductive layer 110 extend into the in-plane region AA. The in-plane region AA of the wiring substrate 100 also includes multiple first pads P1 and multiple second pads P2. Each first pad P1 is configured to connect to an electrode of a micro-driver chip, and each second pad P2 is configured to connect to an electrode of a micro-light-emitting diode. The in-plane region AA of the wiring substrate 100 also includes multiple conductive traces 131. The first pads P1 and second pads P2 are connected via conductive traces 131 and connected to signal lines to enable the micro-driver chip to drive the micro-light-emitting diodes to emit light. Thus, multiple micro-light-emitting diodes and multiple micro-driver chips can be bonded to the wiring substrate 100 via the first and second pads, enabling the micro-driver chip to drive the micro-light-emitting diodes to emit light.

[0156] In some examples, as shown in Figures 3, 22A, 22B, and 23, at least a portion of multiple first pads P1 and multiple second pads P2 are located in the second conductive layer 130, and conductive traces 131 connected to the first pads P1 or second pads P2 are located in the second conductive layer 130. For example, at least a portion of the first pads P1, at least a portion of the second pads P2, the conductive traces 131 connected to the first pads P1 or second pads P2, the first sub-pads 151, and the conductive extensions 153 are formed using the same material and the same patterning process. For example, the signal line 160 extending into the in-plane region and the second sub-pad 152 are formed using the same material and the same patterning process. By including two conductive layers in the in-plane region of the wiring substrate, high partitioning and narrow bezels of the wiring substrate can be achieved. For example, the above-described structure of the wiring substrate 100 in the in-plane region AA is also called a double copper structure. Of course, the embodiments disclosed herein are not limited in this respect.

[0157] In some examples, at least a portion of the first pad and at least a portion of the second pad may also be located on the first conductive layer, and the conductive traces connected to the first pad or the second pad may also be located on the first conductive layer. For example, at least a portion of the first pad, at least a portion of the second pad, the conductive traces connected to the first pad or the second pad, the signal lines extending into the in-plane region, and the second sub-pad are formed using the same material and the same patterning process. The wiring substrate achieves communication between the first sub-pad and the signal lines through conductive extensions located on the second conductive layer. For example, the above-described structure of the wiring substrate in the in-plane region is also referred to as a single copper structure.

[0158] In some examples, as shown in Figures 22A, 22B, and 23, multiple first pads P1 are divided into multiple first pad groups GP1, each first pad group GP1 comprising multiple first pads P1. For example, the figures schematically show a first pad group GP1 comprising 12 first pads P1. For example, a first pad group GP1 is bonded to a micro-driver chip.

[0159] In some examples, as shown in Figures 22A, 22B, and 23, multiple second pads P2 are divided into multiple second pad pairs PP2, and these pairs are further divided into multiple second pad groups GP2. Each second pad group GP2 includes multiple second pad pairs PP2. The multiple second pad pairs PP2 of each second pad group GP2 are connected in series. One end T01 of the series-connected multiple second pad pairs PP2 of the second pad group GP2 is connected to the drive voltage signal line Vled in multiple signal lines 160 via a conductive trace 131, and the other end is connected to the first pad P1 of the first pad group GP1 via a conductive trace 131. For example, the figures schematically show a second pad group including four second pad pairs PP2 for bonding four micro LEDs, that is, four micro LEDs are connected in series in one lamp area. Four second pads PP2 are connected in series via conductive trace 131. One end of the four second pads PP2 connected in series is connected to the driving voltage signal line Vled, and the other end is connected to the first pad P1 of the first pad group GP1. Thus, the micro-driver chip can drive the micro light-emitting diode.

[0160] For example, a micro-driver chip controls multiple second pad groups, and correspondingly, a first pad group GP1 is connected to multiple second pad groups.

[0161] In some examples, as shown in Figures 22A and 22B, the signal line 160 of the first conductive layer 110 extends along the first direction X to the in-plane region AA. For example, the portion of the signal line 160 in the in-plane region AA includes a turning segment 160a, the orthographic projection of the turning segment 160a onto the substrate overlapping the orthographic projection of the conductive trace 131 onto the substrate. For example, the conductive trace 131 is a conductive trace connected to a first pad P1 or a second pad P2. For example, the orthographic projection of the turning segment 160a onto the substrate overlaps with the orthographic projection of the first pad P1 or the second pad P2 onto the substrate. The turning segment 160a of the signal line 160 is located in the first conductive layer 110, and the conductive trace 131, the first pad P1, and the second pad P2 are located in the second conductive layer 130. By making them overlap, the signal line 160 can converge in the in-plane region AA, reducing the size of the peripheral area and facilitating the implementation of a narrow bezel on the wiring substrate. The signal lines 160 converge in the in-plane region AA, which allows the conductive structure 150 to be closer to the in-plane region, making the wiring substrate structure more compact and reducing the size of the peripheral region.

[0162] In some examples, as shown in Figures 22A and 22B, the turning segment 160a of the signal line 160 extends in a direction intersecting the first direction X. For example, the turning segment 160a extends in the second direction Y.

[0163] In some examples, as shown in Figures 22A, 22B, and 23, the plurality of conductive traces 131 located in the in-plane region AA include adjacent conductive traces 131a that are adjacent to and spaced apart from the conductive structure 150. For example, there are no other conductive traces 131 between this adjacent conductive trace 131a and the conductive structure 150. For example, this adjacent conductive trace 131a may be the conductive trace 131 with the closest spacing to the conductive structure. For example, the spacing D6 between the adjacent conductive trace 131a in the in-plane region AA and the conductive structure ranges from 200μm to 800μm. Thus, the size D of the surrounding region BB can be minimized as much as possible. For example, the spacing D6 ranges from 300μm to 600μm, which will not be elaborated further here.

[0164] Other features of the conductive structure shown in Figure 23 can be found in other embodiments herein, and will not be described in detail here. For example, the cross-sectional views along section lines KK, LL, and MM of Figure 23 can be found in Figures 5, 6, and 8, and will not be described in detail here. For example, the partially enlarged view of the wiring substrate at the selected location shown in Figure 22B can also be found in Figures 4, 7, 9, 11 to 14, and 17 to 21, and will not be described in detail here.

[0165] In some examples, as shown in Figures 5 and 15, the first insulating layer group 120 includes a first insulating layer 121 and a first passivation layer 122 stacked together. For example, the second insulating layer group 140 includes a second insulating layer 141 and a second passivation layer 142 stacked together. For example, the materials of the first insulating layer 121 and the second insulating layer 141 include resin adhesive. The first insulating layer 121 and the second insulating layer 141 can isolate water and oxygen and also have protective functions such as preventing scratches. For example, the materials of the first passivation layer 122 and the second passivation layer 142 include silicon nitride. The first passivation layer 122 and the second passivation layer 142 can prevent oxidation of the first conductive layer 110 and the second conductive layer 130. For example, the thickness of the first insulating layer 121 is greater than the thickness of the first passivation layer 122. For example, the thickness of the second insulating layer 141 is greater than the thickness of the second passivation layer 142.

[0166] In some examples, as shown in Figures 5 and 15, the first insulating layer group 120 includes two first passivation layers 122 and at least one first insulating layer 121 located between the two first passivation layers 122. For example, the second passivation layer 142 of the second insulating layer group 140 is closer to the second conductive layer 130 than the second insulating layer 141.

[0167] In some examples, as shown in Figures 5 and 15, the wiring substrate 100 further includes a supplementary insulating layer 129 located between the first conductive layer 110 and the second conductive layer 130. The supplementary insulating layer 129 further isolates water and oxygen, ensuring the performance of the wiring substrate 100. For example, the supplementary insulating layer 129 may be located between two first passivation layers 122 of the first insulating layer 121 group, and on the side of the first passivation layer 122 closer to the second conductive layer 130.

[0168] In some examples, as shown in Figures 5 and 15, the orthographic projection of the second boundary L2 of the supplementary insulating layer 129 onto the substrate 101 is farther from the first via V1 than the first boundary L1 of the second insulating layer group 140. This avoids the impact of the increased height of the first via V1 caused by the addition of the supplementary insulating layer 129, thus preventing any impact on bonding.

[0169] In some examples, as shown in Figures 5 and 15, along the first direction X, the minimum spacing D7 between the second boundary L2 of the supplementary insulating layer group 129 and the first boundary L1 of the second insulating layer group 140 is greater than or equal to 50 μm.

[0170] In some examples, as shown in Figure 5, the minimum spacing D8 between the second boundary L2 of the supplementary insulating layer 129 group and at least one second via V2 along the first direction X is greater than or equal to 50 μm. This allows for maximum protection of the signal line 160 of the first conductive layer 110.

[0171] In some examples, as shown in Figures 5 and 15, the depth of the first via V1 is less than or equal to the depth of the second via V2. This minimizes the depth of the first via V1, ensuring reliable bonding.

[0172] In some examples, the material of the first conductive layer includes copper. For example, the material of the second conductive layer includes copper. For example, the materials of the first conductive layer and the second conductive layer are a stacked material containing copper. For example, the stacked material is a stack of molybdenum-niobium alloy (MoNb), copper (Cu), and molybdenum-niobium alloy (MoNb). For example, the bottom layer of molybdenum-niobium alloy can improve adhesion, and the top layer of molybdenum-niobium alloy can be used for oxidation protection.

[0173] In some examples, the substrate can be a glass substrate.

[0174] In some examples, as shown in Figures 5 and 15, a buffer layer 102 disposed on the substrate 101 is also included. This can eliminate stress and improve adhesion.

[0175] In some examples, the distance between the edge of the conductive structure away from the in-plane region and the edge of the substrate ranges from 0.1 mm to 5 mm. For example, the distance ranges from 0.5 mm to 2 mm.

[0176] Figure 24 shows a film layer diagram of a micro-LED substrate. As shown in Figure 24, the micro-LED substrate includes two metal layers: copper layer 01 and copper layer 02. Copper layer 02 is located on top of copper layer 01. Copper layer 02 only includes a passivation layer 04. In some products, copper layer 02 only includes a passivation layer 04 and an insulating layer. Its reliability is directly related to the thickness of the passivation layer 04 on copper layer 02. When the thickness of the passivation layer 04 is constant, reliability testing revealed that because the passivation layer 04 cannot completely isolate moisture, the entry of moisture causes corrosion of the traces on copper layer 02.

[0177] Figure 25 shows a partial planar structure diagram and failure diagram of a micro-LED substrate. As shown in Figures 24 and 25(a), in the wiring scheme of the micro-LED substrate, the clock signal line and address signal line control the odd and even columns of micro-driver chips and are located in copper layer 01. On the top side, that is, the side of the in-plane region away from the bonding area, the solder pads of the clock signal line and address signal line of the first micro-driver chip in the odd column are connected to the solder pads of the clock signal line and address signal line of the first micro-driver chip in the even column through connection 08 and connection 09, respectively. Connection 08 and connection 09 are located in copper layer 02 with a thickness of 0.9μm. Only a passivation layer 04 covers it, which is not sufficiently protective and is prone to corrosion during the reliability process, resulting in line breakage, inability to transmit signals, and consequently, the entire row of lamps going out. As shown in Figure 25(b), the reliability results show that the connection 08 and connection 09 are prone to corrosion, and the corrosion failure rate is relatively high. Since the connection 08 and connection 09 are located in the copper layer 02 and have a small width, corrosion can easily cause the line to break and the signal to be unable to be transmitted. This can cause the entire row of lamps controlled by the even-numbered micro-drive chip to fail to turn off, resulting in product failure.

[0178] Figure 26 is a planar schematic diagram of a wiring substrate provided in an embodiment of the present disclosure; Figure 27 is a partially enlarged schematic diagram of the wiring substrate shown in Figure 26 at the selected position; Figure 28 is a partially enlarged schematic diagram of the wiring substrate shown in Figure 27 at the selected position; Figure 29 is a schematic diagram of the film layer of the wiring substrate shown in Figure 26.

[0179] As shown in Figures 26 to 29, the wiring substrate 100 includes a substrate 101, a first conductive layer 110, a first insulating layer group 120, a second conductive layer 130, and a second insulating layer group 140. The first conductive layer 110 is located on the substrate 101 and includes a plurality of signal lines 160. The first insulating layer group 120 is located on the side of the first conductive layer 110 away from the substrate 101. The second conductive layer 130 is located on the side of the first insulating layer group 120 away from the substrate 101, and the second insulating layer group 140 is located on the side of the second conductive layer 130 away from the substrate 101. The in-plane region AA of the wiring substrate 100 includes a plurality of first pads P1 at least partially located on the second conductive layer 130. Each first pad P1 is configured to be connected to an electrode of a micro-driver chip. The plurality of first pads P1 are divided into a plurality of first pad groups GP1, and each first pad group GP1 includes a plurality of first pads P1. For example, the diagram schematically shows a first pad group GP1 comprising 12 first pads P1. For example, a first pad group GP1 is bonded to a micro-driver chip.

[0180] Multiple first pad groups GP1 are arranged in an array along a first direction X and a second direction Y to form multiple first pad columns R01 extending along the first direction X and arranged along the second direction Y. Six first pad columns G01 are schematically shown in the figure. Each first pad column R01's multiple first pad groups GP1 includes an interconnect pad group GP11, and the multiple first pads P1 of the interconnect pad group GP11 include first sub-pads P11. The two first sub-pads P11 of the two interconnect pad groups GP11 of two adjacent first pad columns R01 along the first direction X are connected to each other by a first connection line 171. The first connection line 171 includes a first connection sub-port 1711 and at least one second connection sub-port 1712 connected to each other, the first connection sub-port 1711 being located in the first conductive layer 110, and the second connection sub-port 1712 being located in the second conductive layer 130. For example, the first connection line 171 extends generally along the second direction Y. It should be noted that there may be other structures between two adjacent first pad columns R01, and there may be no first pad column R01 between two adjacent first pad columns R01. For example, the first connection sub-part 1711 and the second connection sub-part 1712 are connected through a via V0.

[0181] In this example, the first connecting line 171 includes a first connecting sub-part 1711 and a second connecting sub-part 1712. The first connecting sub-part 1711 is located on the first conductive layer 110. Above the first conductive layer 110 are a first insulating layer group 120 and a second insulating layer group 140. The first connecting sub-part 1711 has more protective layers, which can significantly improve the protection of the first connecting sub-part 1711 and the first connecting line 171, and significantly improve the product's corrosion resistance and service life. For details on the first insulating layer group 120 and the second insulating layer group 140, please refer to the previous description; they will not be repeated here.

[0182] In some examples, as shown in Figures 27 and 28, the first connection line 171 includes a first connection sub-section 1711 and two second connection sub-sections 1712. The first connection sub-section 1711 is located between the two second connection sub-sections 1712 and connects the two second connection sub-sections 1712 together. The two second connection sub-sections 1712 are respectively connected to the first sub-pad P11 of the interconnect pad group GP11 of the two adjacent first pad columns R01. The first connection sub-section 1711 is located between the two second connection sub-sections 1712, and its two ends are respectively connected to the two second connection sub-sections 1712.

[0183] In some examples, as shown in Figures 27 and 28, multiple signal lines 160 include a third signal line 1603 located between two adjacent first pad rows R01, extending along a first direction X. The third signal line 1603 also includes a first spacing 16030 and a first main body portion 16031 and a second main body portion 16032 located on either side of the first spacing 16030. The orthographic projection of the first connecting sub-portion 1711 of the first connecting line 171 onto the substrate 101 overlaps with the orthographic projection of the first spacing 16030 of the third signal line 1603 onto the substrate 101. The second conductive layer 130 also includes a first bridging wire 16033 connecting the first main body portion 16031 and the second main body portion 16032. Through the arrangement of the first spacing 16030 and the first bridging wire 16033, the first connecting sub-portion 1711 can be located on the first conductive layer 110 without affecting the conduction of the third signal line 1603. For example, the third signal line 1603 can be a drive voltage line.

[0184] In some examples, as shown in Figures 27 and 28, the first bridging wire 16033 extends along a first direction X. For example, the dimension D9 of the first bridging wire 16033 along the second direction Y is greater than the dimension D10 of the first connecting sub-portion 1711 along the first direction X. By increasing the dimension D9 of the first bridging wire 16033 along the second direction Y, the impedance of the first bridging wire 16033 can be reduced, and the corrosion resistance of the first bridging wire 16033 can be improved. For example, the first body portion 16031 and the second body portion 16032 can be connected by multiple first bridging wires 16033.

[0185] In some examples, as shown in Figures 27 and 28, the plurality of signal lines 160 further includes a fourth signal line 1604 located between two adjacent first pad columns R01. The fourth signal line 1604 extends along a first direction X, and the orthographic projection of the second connecting portion 1712 of the first connecting line 171 onto the substrate 101 overlaps with the orthographic projection of the fourth signal line 1604 onto the substrate 101. For example, the fourth signal line 1604 may be a ground line or a signal connection line located on the first conductive layer 110, etc.

[0186] In some examples, as shown in Figures 27 and 28, the fourth signal line 1604 includes a signal connection line 1605. The ratio of the dimension of the signal connection line 1605 along the second direction Y to the dimension of the second connection sub-portion 1712 along the first direction X is less than 5, thereby minimizing crosstalk between signals. For example, the signal connection line 1605 has a uniform width along the second direction Y.

[0187] In some examples, as shown in Figures 27 and 28, the fourth signal line 1604 includes a second bridging wire 16042 and a third main body portion 16043 and a fourth main body portion 16044 located on both sides of the second bridging wire 16042. The second bridging wire 16042, the third main body portion 16043, and the fourth main body portion 16044 are all located in the first conductive layer 110. The ratio of the dimension D11 of the third main body portion 16043 and the fourth main body portion 16044 along the second direction Y to the dimension D12 of the second bridging wire 16042 along the second direction Y is greater than or equal to 3. The orthographic projection of the second connecting sub-portion 1712 on the substrate 101 overlaps with the orthographic projection of the second bridging wire 16042 on the substrate 101. Therefore, the overlap area between the second connecting sub-portion 1712 and the fourth signal line 1604 can be reduced, thereby reducing crosstalk between the signal lines 160. For example, the ratio may be greater than or equal to 5, or greater than or equal to 7, and so on. For example, the fourth type of signal line 1604 can be a ground line.

[0188] In some examples, as shown in Figures 27 and 28, the dimension D9 of the first bridging wire 16033 along the second direction Y is greater than or equal to the dimension D12 of the second bridging wire 16042 along the second direction Y. The first bridging wire 16033 is located in the second conductive layer 130; increasing the dimension D9 of the first bridging wire 16033 can improve corrosion resistance. The second bridging wire 16042 overlaps with the second connector sub-part 1712; decreasing the dimension D12 of the second bridging wire 16042 can reduce crosstalk between signal lines 160.

[0189] In some examples, as shown in Figures 27 and 28, a virtual extension line L3, passing through the end of the first connector 1711 and extending along the first direction X, passes through the fourth signal line 1604. This allows the length of the first connector 1711 to be maximized, thereby improving the corrosion resistance of the first connector 171.

[0190] In some examples, as shown in Figures 27 and 28, the fourth signal line 1604 includes a first edge 16045 and a second edge 16046 opposite each other along the second direction Y. The first edge 16045 is closer to the third signal line 1603 than the second edge 16046. The second bridging wire 16042 is located between the first edge 16045 and the second edge 16046 and is closer to the second edge 16046. The first connecting sub-part 1711 extends to the second bridging wire 16042 and is spaced apart from the second bridging wire 16042. This allows the length of the first connecting sub-part 1711 to be maximized.

[0191] In some examples, as shown in Figures 27 and 28, the second bridge wire 16042 is located at the second edge 16046, and the first connecting sub-part 1711 extends to the second edge 16046 of the fourth signal line 1604 and is spaced apart from the second bridge wire 16042. This allows the length of the first connecting sub-part 1711 to be maximized.

[0192] In some examples, as shown in Figures 27 and 28, the ratio of the length of the first connecting sub-part 1711 to the length of the first connecting line 171 is greater than 0.5. For example, this ratio is greater than 0.8. For example, this ratio is greater than 1. For example, this ratio is greater than 1.5. For example, this ratio is greater than 2. For example, this ratio is greater than 3. These will not be listed individually here.

[0193] In some examples, as shown in Figures 27 and 28, the plurality of first pads P1 of the interconnect pad group GP11 further includes second sub-pads P12. Two second sub-pads P12 of two interconnect pad groups GP11 of two adjacent first pad columns R01 along the first direction X are connected to each other by a second connection line 172. The second connection line 172 includes a third connection sub-portion 1721 and at least one fourth connection sub-portion 1722. The third connection sub-portion 1721 is located in the first conductive layer 110, and the fourth connection sub-portion 1722 is located in the second conductive layer 130. For example, the second connection line 172 extends generally along the second direction Y. The third connection sub-portion 1721 is located in the first conductive layer 110, thereby improving the corrosion resistance of both the third connection sub-portion 1721 and the second connection line 172.

[0194] In some examples, as shown in Figures 27 and 28, the second connecting line 172 includes a third connecting sub-section 1721 and two fourth connecting sub-sections 1722, with the third connecting sub-section 1721 located between the two fourth connecting sub-sections 1722 and connecting the two fourth connecting sub-sections 1722 together.

[0195] In some examples, as shown in Figures 27 and 28, the orthographic projection of the third connecting sub-part 1721 onto the substrate 101 overlaps with the orthographic projection of the first spacing 16030 of the third signal line 1603 onto the substrate 101.

[0196] In some examples, as shown in Figures 27 and 28, the orthographic projection of the fourth connection sub-portion 1722 onto the substrate 101 overlaps with the orthographic projection of the fourth signal line 1604 onto the substrate 101. For example, the orthographic projection of the fourth connection sub-portion 1722 onto the substrate 101 overlaps with the orthographic projection of the second bridge wire 16042 onto the substrate 101. For example, the third connection sub-portion 1721 extends to the second bridge wire 16042 and is spaced apart from the second bridge wire 16042.

[0197] In some examples, as shown in Figures 27 and 28, the first connecting line 171 and the second connecting line 172 are arranged substantially parallel. For example, the first connecting sub-section 1711 and the third connecting sub-section 1721 are arranged substantially parallel. For example, the second connecting sub-section 1712 and the fourth connecting sub-section 1722 are arranged substantially parallel. For example, the first connecting sub-section 1711 and the third connecting sub-section 1721 overlap with the first interval 16030 of the same third type signal line 1603. For example, the second connecting sub-section 1712 and the fourth connecting sub-section 1722 overlap with the second bridging wire 16042 of the same fourth type signal line 1604.

[0198] In some examples, as shown in Figures 27 and 28, the length of the first connecting sub-part 1711 is approximately equal to the length of the third connecting sub-part 1721.

[0199] In some examples, as shown in Figures 27 and 28, a shielding line 173 is provided between the first connecting sub-part 1711 and the third connecting sub-part 1721. The shielding line 173 is located in the first conductive layer 110 and is connected to the ground wire among the plurality of signal lines 160. Thus, the shielding line 173 can shield the signal between the first connecting sub-part 1711 and the third connecting sub-part 1721, reducing signal crosstalk.

[0200] In some examples, as shown in Figures 27 and 28, the fourth signal line 1604 includes a ground wire, and the shielding wire 173 located in the first conductive layer 110 is directly connected to the fourth signal line 1604 located in the first conductive layer 110. Since the fourth signal line 1604, the first connecting sub-part 1711, and the shielding wire 173 are all located in the first conductive layer 110, not only is the structural design of the three components simpler, but the shielding wire 173 can also be directly connected to the fourth signal line 1604, ensuring current flow performance.

[0201] In some examples, as shown in Figure 27, the ratio of the length of the shielding wire 173 to the length of the first connecting sub-part 1711 is greater than or equal to 0.8. For example, this ratio is equal to 1. Similarly, the ratio of the length of the shielding wire 173 to the length of the third connecting sub-part 1721 is greater than or equal to 0.8. For example, this ratio is equal to 1. This allows for better shielding of the signal between the first connecting sub-part 1711 and the third connecting sub-part 1721.

[0202] In some examples, as shown in Figure 27, a driving voltage line and ground lines located on both sides of the driving voltage line are included between two adjacent first pad columns R01. The driving voltage line is a third type of signal line 1603, and the ground line is a fourth type of signal line 1604. Of course, this disclosure does not limit this. The area between two adjacent first pad columns R01 can be entirely composed of third type of signal lines 1603, or entirely composed of fourth type of signal lines 1604, or at least include one third type of signal line 1603, or at least include one fourth type of signal line 1604. These will not be elaborated further here.

[0203] In some examples, as shown in Figure 27, the in-plane region AA of the wiring substrate 100 further includes a plurality of second pads P2 at least partially located on the second conductive layer 130 and a plurality of conductive traces 131 located on the second conductive layer 130. Each second pad P2 is configured to be connected to an electrode of a micro-LED. The first pad P1 and the second pad P2 are connected via the conductive traces 131 to enable the micro-driver chip to drive the micro-LED to emit light. The first pad P1 and the second pad P2 are also connected via the conductive traces 131 to a signal line 160 located on the first conductive layer 110. The signal line 160 of the first conductive layer 110 and the conductive traces 131 of the second conductive layer 130 can be interconnected via vias V4.

[0204] In some examples, as shown in Figure 27, multiple second pads P2 are divided into multiple second pad pairs PP2, and multiple second pad pairs PP2 are divided into multiple second pad groups. Each second pad group includes multiple second pad pairs PP2. The multiple second pad pairs PP2 of each second pad group are connected in series. One end T01 of the multiple second pad pairs PP2 connected in series in the second pad group is connected to the drive voltage signal line Vled in multiple signal lines 160 through conductive trace 131, and the other end T02 is connected to the first pad P1 of the first pad group GP1 through conductive trace 131.

[0205] Figure 30 is another enlarged view of the wiring substrate shown in Figure 26 at the selected location; Figure 31 is another enlarged view of the wiring substrate shown in Figure 30 at the selected location.

[0206] As shown in Figures 30 and 31, each pair of adjacent first pad rows R01 includes a driving voltage line and ground lines located on both sides of the driving voltage line. Both the driving voltage line and the ground lines are third-type signal lines 1603. This allows the lengths of the first connecting sub-section 1711 and the third connecting sub-section 1721 to be as long as possible, improving the corrosion resistance of the first connecting line 171 and the second connecting line 172.

[0207] In some examples, as shown in Figures 30 and 31, the shielding wire 173 is connected via via V3 to the first bridge wire 16033 and the second bridge wire 16042 located in the second conductive layer 130. For example, the length of the shielding wire 173 is approximately equal to the length of the first connector sub-portion 1711 or the second connector sub-portion 1712.

[0208] In some examples, as shown in Figure 29, the thickness of the first conductive layer 110 is greater than the thickness of the second conductive layer 130. For example, the ratio of the thickness of the first conductive layer 110 to the thickness of the second conductive layer 130 is greater than 2. For example, the ratio is greater than 3. For example, the thickness of the first conductive layer 110 is 3.6 μm, and the thickness of the second conductive layer 130 is 0.9 μm. Because the thickness of the first conductive layer 110 is greater than the thickness of the second conductive layer 130, the impedance of the first conductive layer 110 is less than the impedance of the second conductive layer 130, which can reduce the heat generation of the traces located on the first conductive layer 110. For example, it can reduce the heat generation of the first connector 1711, improve the corrosion resistance of the first connector 1711, and significantly improve the corrosion resistance of the first connector 171.

[0209] In some examples, as shown in Figure 26, the wiring substrate 100 includes an in-plane region AA and a peripheral region BB that at least partially surrounds the in-plane region AA, the peripheral region BB including a bonding region B2. For example, the first connection line 171 and the second connection line 172 are located on the side of the in-plane region AA away from the bonding region B2. For example, this side is also referred to as the top side.

[0210] In some examples, as shown in Figures 26 and 27, the first connection line 171 connects the first sub-pads P11 of the interconnection pad group GP11 of the first first pad column R01 and the second first pad column R01 to each other. Similarly, the first sub-pads P11 of the third first pad column R01 and the fourth first pad column R01 are interconnected via the first connection line 171, and will not be described in detail here. Likewise, the second connection line 172 connects the second sub-pads P12 of the interconnection pad group GP11 of the first first pad column R01 and the second first pad column R01 to each other. Similarly, the second sub-pads P12 of the third first pad column R01 and the fourth first pad column R01 are interconnected via the second connection line 172, and will not be described in detail here. For example, the first connection line is used for interconnecting the address signal lines of adjacent first pad columns, and the second connection line is used for interconnecting the clock signal lines of adjacent first pad columns.

[0211] This disclosure also provides a display device. FIG32 is a schematic diagram of a display device provided in an embodiment of this disclosure. As shown in FIG32, the display device 200 includes any of the wiring substrates 100 mentioned above. Thus, the display device has the beneficial effects corresponding to the beneficial effects of the wiring substrate, which will not be described again here.

[0212] For example, the display device 200 can be any product or component with display function, such as a television, laptop, tablet, mobile phone, navigator, wearable device, virtual reality device, etc.

[0213] The following points need to be explained:

[0214] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0215] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0216] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A wiring substrate, comprising: Substrate; The first conductive layer is located on the substrate and includes multiple signal lines; The first insulating layer group is located on the side of the first conductive layer away from the substrate. The second conductive layer is located on the side of the first insulating layer group away from the substrate. as well as The second insulating layer group is located on the side of the second conductive layer away from the substrate. The wiring substrate includes an in-plane region and a peripheral region that at least partially surrounds the in-plane region. The peripheral region includes a lead-out region and a bonding region. The wiring substrate also includes a plurality of conductive structures located in the peripheral region. Each of the conductive structures includes a first sub-pad located in the second conductive layer, a conductive extension connected to the first sub-pad, and at least one first via and at least one second via penetrating the first insulating layer group. The at least one first via, when projected onto the substrate, is outside the projection of the second insulating layer group onto the substrate. The at least one second via, when projected onto the substrate, is within the projection of the second insulating layer group onto the substrate. The first sub-pad, when projected onto the substrate, is outside the projection of the second insulating layer group onto the substrate. The conductive extension is covered by the second insulating layer group. The first sub-pad is located in the bonding region, and at least a portion of the conductive extension is located in the lead-out region. A portion of the first sub-pad of each of the conductive structures is located in the at least one first via, and the conductive extension is directly connected to the signal line of the first conductive layer through the at least one second via.

2. The wiring substrate according to claim 1, wherein, The plurality of signal lines of the first conductive layer extend into the in-plane region. The in-plane region of the wiring substrate further includes a plurality of first pads and a plurality of second pads, each first pad being configured to be connected to an electrode of a micro-driver chip, and each second pad being configured to be connected to an electrode of a micro-light-emitting diode. The in-plane area of ​​the wiring substrate further includes a plurality of conductive traces. The first pad and the second pad are connected through the conductive traces and connected to the signal line through the conductive traces so that the micro-driver chip drives the micro-light-emitting diode to emit light.

3. The wiring substrate according to claim 1, wherein, The ratio of the area of ​​the orthogonal projection of the at least one second via of each of the conductive structures onto the substrate to the area of ​​the orthogonal projection of the at least one first via onto the substrate is greater than or equal to 0.

8.

4. The wiring substrate according to claim 3, wherein, Both the first sub-pad and the conductive extension extend along a first direction, and the ratio of the dimension of the at least one second via of each conductive structure along the first direction to the dimension of the at least one first via along the first direction is greater than or equal to 0.

8.

5. The wiring substrate according to claim 1, wherein, Both the first sub-pad and the conductive extension extend along a first direction. The conductive extension of each conductive structure includes a first sub-part and a second sub-part. The first sub-part connects the first sub-pad and the second sub-part, and the second sub-part is directly connected to the signal line of the first conductive layer through the at least one second via.

6. The wiring substrate according to claim 1, wherein, The ratio of the dimension of the at least one second via of each of the conductive structures along the first direction to the sum of the dimensions of the conductive extension and the first sub-pad along the first direction is less than or equal to 0.

5.

7. The wiring substrate according to any one of claims 1-6, wherein, The wiring substrate also includes a plurality of conductive traces located in the in-plane region and in the second conductive layer. The plurality of conductive traces include adjacent conductive traces that are adjacent to and spaced apart from the conductive structure, wherein the distance between the adjacent conductive traces and the conductive structure is greater than or equal to 200 μm.

8. The wiring substrate according to claim 7, wherein, The spacing between the adjacent conductive traces and the conductive structure ranges from 200μm to 800μm.

9. The wiring substrate according to any one of claims 1-8, wherein, The plurality of signal lines includes a first type of signal line, wherein the orthographic projections of M conductive extensions of the conductive structures onto the substrate overlap with the orthographic projection of one of the first type of signal lines onto the substrate, and M is greater than 1. The plurality of signal lines also includes a second type of signal line, wherein the orthographic projection of the conductive extension of one of the conductive structures onto the substrate overlaps with the orthographic projection of the second type of signal line onto the substrate.

10. The wiring substrate according to claim 9, wherein, The conductive extensions of the M conductive structures are interconnected.

11. The wiring substrate according to claim 10, wherein, The ratio of the sum of the areas of the at least one second via of the M conductive structures projected onto the substrate to the sum of the areas of the at least one first via of the M conductive structures projected onto the substrate is greater than or equal to 0.

8.

12. The wiring substrate according to any one of claims 1-11, wherein, Each of the conductive structures further includes a second sub-pad located in the first conductive layer. The first sub-pad is directly connected to the second sub-pad through the at least one first via. The second sub-pad is also connected to the signal line located in the first conductive layer.

13. The wiring substrate according to any one of claims 1-12, wherein, The ends of the conductive extensions of the plurality of conductive structures near the in-plane region are flush.

14. The wiring substrate according to any one of claims 1-13, wherein, The plurality of conductive structures are arranged along a second direction, and the first sub-pad and the conductive extension of each conductive structure extend along the first direction. The dimension of the first via of each of the conductive structures along the first direction is greater than or equal to the dimension along the second direction, and the dimension of the second via of each of the conductive structures along the first direction is greater than or equal to the dimension along the second direction.

15. The wiring substrate according to any one of claims 1-14, wherein, The plurality of conductive structures are arranged along a second direction, and the first sub-pad and the conductive extension of each conductive structure extend along the first direction. The first boundary of the second insulating layer group is located between the orthogonal projections of the at least one first via and the at least one second via on the substrate. Along the first direction, the minimum distance between the first boundary of the second insulating layer group and the at least one first via is greater than or equal to 300 μm, and the distance between the first boundary of the second insulating layer group and the at least one second via is greater than or equal to 100 μm.

16. The wiring substrate according to claim 15, wherein, The first insulating layer group includes a first insulating layer and a first passivation layer stacked together, the thickness of the first insulating layer being greater than the thickness of the first passivation layer; the second insulating layer group includes a second insulating layer and a second passivation layer stacked together, the thickness of the second insulating layer being greater than the thickness of the second passivation layer.

17. The wiring substrate according to claim 16, wherein, The wiring substrate further includes a supplementary insulating layer located between the first conductive layer and the second conductive layer, wherein the second boundary of the supplementary insulating layer is further away from the first via in the orthographic projection on the substrate than the first boundary of the second insulating layer group.

18. The wiring substrate according to any one of claims 1-17, wherein, The conductive extension of each of the aforementioned conductive structures includes a first sub-part and a second sub-part. The first sub-part connects the first sub-pad and the second sub-part, and the second sub-part is directly connected to the signal line of the first conductive layer through the at least one second via. The plurality of signal lines includes a first type of signal line, wherein the orthographic projection of the M conductive extensions of the conductive structure onto the substrate lies within the orthographic projection of one of the first type of signal lines onto the substrate. At least one of the first conductive pad, the first sub-part, and the second sub-part of the M conductive structures is arranged at intervals.

19. The wiring substrate according to any one of claims 1-18, wherein, The depth of the first via is less than or equal to the depth of the second via.

20. The wiring substrate according to any one of claims 1-19, wherein, The plurality of first pads and the plurality of second pads are at least partially located in the second conductive layer, and the conductive traces connected to the first pads or the second pads are located in the second conductive layer.

21. The wiring substrate according to claim 20, wherein, The first conductive layer is made of copper, and the second conductive layer is made of copper.

22. The wiring substrate according to any one of claims 1-21, wherein, The in-plane region of the wiring substrate includes a plurality of first pads at least partially located in the second conductive layer. Each first pad is configured to be connected to an electrode of a micro-driver chip. The plurality of first pads are divided into a plurality of first pad groups, each first pad group including a plurality of first pads. The plurality of first pad groups are arranged in an array along a first direction and a second direction to form a plurality of first pad columns extending along the first direction and arranged along the second direction. The plurality of first pad groups in each first pad column include interconnect pad groups. The plurality of first pads in the interconnect pad groups include first sub-pads. The two first sub-pads of two interconnect pads in two adjacent first pad columns along the first direction are connected to each other by a first connection line. The first connection line includes a first connection sub-part and at least one second connection sub-part connected to each other, the first connection sub-part being located in the first conductive layer, and the second connection sub-part being located in the second conductive layer. The in-plane region of the wiring substrate further includes a plurality of second pads located at least partially in the second conductive layer and a plurality of conductive traces located in the second conductive layer. Each second pad is configured to be connected to an electrode of a micro light-emitting diode. The first pad and the second pad are connected through the conductive traces to enable the micro driver chip to drive the micro light-emitting diode to emit light.

23. The wiring substrate according to claim 22, wherein, The plurality of second pads are divided into a plurality of second pad pairs, and the plurality of second pad pairs are divided into a plurality of second pad groups. Each second pad group includes a plurality of second pad pairs. The plurality of second pad pairs in each second pad group are connected in series sequentially. One end of the plurality of second pad pairs connected in series in the second pad group is connected to the drive voltage signal line in the plurality of signal lines through the conductive trace, and the other end is connected to the first pad of the first pad group through the conductive trace.

24. The wiring substrate according to claim 22, wherein, The plurality of signal lines include a third type of signal line located between two adjacent first pad rows. The third type of signal line extends along the first direction. The third type of signal line also includes a first spacer and a first body portion and a second body portion located on both sides of the first spacer. The first connecting sub-part of the first connecting line overlaps with the orthographic projection of the first spacer of the third type of signal line on the substrate. The second conductive layer also includes a first bridging wire that connects the first body portion and the second body portion.

25. The wiring substrate according to claim 24, wherein, The dimension of the first bridging wire along the second direction is greater than the dimension of the first connecting sub-part along the first direction.

26. The wiring substrate according to claim 24, wherein, The plurality of signal lines also includes a fourth type of signal line located between two adjacent first pad columns, the fourth type of signal line extending along the first direction, wherein the orthographic projection of the second connecting portion of the first connecting line on the substrate overlaps with the orthographic projection of the fourth type of signal line on the substrate.

27. The wiring substrate according to claim 26, wherein, The fourth type of signal line includes a second bridge wire and a third main body and a fourth main body located on both sides of the second bridge wire. The second bridge wire, the third main body and the fourth main body are all located in the first conductive layer. The ratio of the dimension of the third main body and the fourth main body along the second direction to the dimension of the second bridge wire along the second direction is greater than or equal to 3. The orthographic projection of the second connecting sub-part on the substrate overlaps with the orthographic projection of the second bridge wire on the substrate.

28. The wiring substrate according to claim 27, wherein, The dimension of the first bridging wire along the second direction is greater than or equal to the dimension of the second bridging wire along the second direction.

29. The wiring substrate according to claim 26, wherein, A virtual extension line passing through the end of the first connector and extending along the first direction passes through the fourth signal line.

30. The wiring substrate according to claim 27, wherein, The fourth type of signal line includes a first edge and a second edge opposite each other along a second direction, wherein the first edge is closer to the third type of signal line than the second edge, and the second bridging wire is located between the first edge and the second edge and closer to the second edge, or the second bridging wire is located at the second edge. The first connecting part extends to the second bridge wire and is spaced apart from the second bridge wire.

31. The wiring substrate according to any one of claims 22-30, wherein, The first connecting line includes two second connecting sub-parts, the first connecting sub-parts being located between the two second connecting sub-parts and connecting the two second connecting sub-parts together.

32. The wiring substrate according to any one of claims 22-31, wherein, The plurality of first pads in the interconnect pad group further include second sub-pads. Two second sub-pads of two interconnect pads in two adjacent first pad columns along the first direction are connected to each other via a second connection line. The second connection line includes a third connection sub-section and at least one fourth connection sub-section. The third connection sub-section is located in the first conductive layer, and the fourth connection sub-section is located in the second conductive layer. A shielding wire is provided between the first connecting sub-part and the third connecting sub-part. The shielding wire is located in the first conductive layer and is connected to the ground wire among the plurality of signal lines.

33. The wiring substrate according to claim 32, wherein, The ratio of the length of the shielding wire to the length of the first connecting sub-part is greater than or equal to 0.

8.

34. The wiring substrate according to any one of claims 22-33, wherein, The ratio of the length of the first connecting sub-part to the length of the first connecting line is greater than 0.

5.

35. A display device comprising a wiring substrate according to any one of claims 1-34.

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