Array substrate and display apparatus

Abstract

Provided are an array substrate and a display apparatus. The array substrate comprises a base substrate, and, located on the base substrate, a plurality of data lines, a plurality of thin film transistors and a plurality of pixel electrodes. The plurality of data lines are arranged in a first direction, and each of the plurality of data lines extends in a second direction. Each of the thin film transistors comprises a first source / drain electrode, a gate electrode and a second source / drain electrode, wherein the first source / drain electrode is electrically connected to a data line, and the orthographic projection of the first source / drain electrode on the base substrate at least partially overlaps the orthographic projection of the gate electrode on the base substrate. The plurality of pixel electrodes are located on the side of the plurality of data lines away from the base substrate, and each pixel electrode is electrically connected to a second source / drain electrode. The plurality of thin film transistors comprise at least one first transistor. The area of the orthographic projection of the first source / drain electrode of the first transistor on the base substrate is less than the area of the orthographic projection of a second source / drain electrode on the base substrate. The parasitic capacitance between each data line and a gate line in the array substrate is smaller, thus helping to reduce power consumption of the data lines.

Description

Array substrate and display device Technical Field

[0001] At least one embodiment of this disclosure relates to an array substrate and a display device. Background Technology

[0002] With the development of technology, reducing the power consumption of thin film transistor liquid crystal displays (TFT LCDs) has become one of the important trends in the development of electronic display technology. The driving factors of this trend mainly come from several aspects, such as the popularization of mobile devices, energy-saving and environmental protection policies, the progress of display technology, and market competition.

[0003] For example, with the widespread adoption of portable electronic devices such as smartphones, tablets, and smartwatches, consumers have increasingly higher demands for device battery life. Reducing the power consumption of display screens is key to improving the overall battery life of devices. For instance, as electronic products are a significant energy consumer, reducing their power consumption is crucial for achieving energy conservation and emission reduction. For example, with the continuous advancement of display technology, such as the application of new backlight technologies (e.g., Mini LED, Micro LED), low-power driving circuits, and intelligent brightness adjustment algorithms, TFT LCDs can significantly reduce power consumption while maintaining display quality. Furthermore, in the highly competitive electronics market, low power consumption has become a crucial means of product differentiation. Continuously optimizing display technology to reduce product power consumption has become an important method for enhancing market competitiveness. Summary of the Invention

[0004] At least one embodiment of this disclosure provides an array substrate, including a substrate, multiple data lines, multiple thin-film transistors, and multiple pixel electrodes. The multiple data lines are located on the substrate and are arranged along a first direction. Each data line extends along a second direction, and both the first and second directions are parallel to the substrate and intersect each other. The multiple thin-film transistors are located on the substrate, and each thin-film transistor includes a first source / drain electrode, a gate electrode, and a second source / drain electrode. The first source / drain electrode is electrically connected to the data lines, and the orthographic projection of the first source / drain electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate. The multiple pixel electrodes are located on the side of the multiple data lines away from the substrate, and each pixel electrode is electrically connected to the second source / drain electrode. The multiple thin-film transistors include at least one first transistor, and the orthographic projection area of ​​the first source / drain electrode of the first transistor on the substrate is smaller than the orthographic projection area of ​​the second source / drain electrode on the substrate.

[0005] For example, according to at least one embodiment of the array substrate provided in this disclosure, the second source-drain electrode of the first transistor includes a bent portion and a second source-drain electrode connection portion connected to each other, the bent portion being closer to the first source-drain electrode than the second source-drain electrode connection portion, the bent portion being electrically connected to the pixel electrode through the second source-drain electrode connection portion, wherein the bent portion includes an opening, a portion of the first source-drain electrode extending from the opening into the area enclosed by the bent portion.

[0006] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the first source / drain electrode of the first transistor extends along the first direction.

[0007] For example, according to at least one embodiment of the present disclosure, the array substrate of the plurality of thin-film transistors further includes at least one second transistor, wherein the projected area of ​​the first source / drain electrode of the second transistor on the substrate is greater than the projected area of ​​the second source / drain electrode on the substrate.

[0008] For example, according to at least one embodiment of the present disclosure, the array substrate further includes: a common electrode located on the side of the plurality of data lines and the plurality of thin-film transistors away from the substrate, the pixel electrode being configured to form an electric field with the common electrode, wherein the at least one second transistor includes at least one dummy transistor, the array substrate further includes a plurality of at least one common electrode line, the plurality of pixel electrodes including at least one dummy pixel electrode, the second source / drain electrode of the dummy transistor being electrically connected to the dummy pixel electrode, the first source / drain electrode of the dummy transistor being electrically connected to the common electrode line, and the common electrode line being electrically connected to the common electrode.

[0009] For example, according to at least one embodiment of the present disclosure, the array substrate includes a display area and a non-display area, at least a portion of the non-display area surrounds the display area, the display area is configured to display, and the dummy transistor is located in the non-display area.

[0010] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of thin-film transistors include a plurality of transistor pairs, each transistor pair including a first transistor and a second transistor, wherein the first source / drain electrode of the first transistor and the second source / drain electrode of the second transistor are both connected to the same data line.

[0011] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the projected area of ​​the first source / drain electrode of the first transistor on the substrate is smaller than the projected area of ​​the second source / drain electrode of the second transistor on the substrate.

[0012] For example, according to at least one embodiment of the present disclosure, the plurality of pixel electrodes are arrayed in a first direction and a second direction to form a plurality of pixel electrode rows arranged along the second direction and a plurality of pixel electrode columns arranged along the first direction. The plurality of pixel electrodes include a plurality of pixel electrode pairs, each pixel electrode pair including a first pixel electrode and a second pixel electrode. The first pixel electrode and the second pixel electrode are respectively located in adjacent pixel electrode rows and adjacent pixel electrode columns. The second source / drain electrode of the first transistor is electrically connected to the first pixel electrode, and the second source / drain electrode of the second transistor is electrically connected to the second pixel electrode.

[0013] For example, according to at least one embodiment of the present disclosure, the array substrate further includes a plurality of gate lines, each of the gate lines extending along the first direction, the plurality of gate lines including a plurality of gate line pairs, each of the gate line pairs including a first gate line and a second gate line spaced apart in the second direction, the gate line pairs being located between adjacent pixel electrode rows in the second direction, the first gate line being configured to be electrically connected to the gate of the first transistor, and the second gate line being configured to be electrically connected to the gate of the second transistor.

[0014] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of pixel electrodes are arrayed in a first direction and a second direction to form a plurality of pixel electrode rows arranged along the second direction and a plurality of pixel electrode columns arranged along the first direction. The plurality of pixel electrodes include a plurality of pixel electrode pairs, each pixel electrode pair including a first pixel electrode and a second pixel electrode. The first pixel electrode and the second pixel electrode are respectively located in adjacent pixel electrode rows. There are at least two columns of the pixel electrode between the first pixel electrode and the second pixel electrode. Each pixel electrode includes an electrode body portion and an electrode connection portion connected to each other. The electrode connection portion of the first pixel electrode is electrically connected to the second source / drain electrode of the first transistor, and the electrode connection portion of the second pixel electrode is electrically connected to the second source / drain electrode of the second transistor.

[0015] For example, according to at least one embodiment of the array substrate provided in this disclosure, the electrode connection portion of at least one pixel electrode includes a plurality of sub-connection portions, each sub-connection portion including a first end and a second end opposite to each other, the first end of each sub-connection portion being connected to the electrode body portion, and the second end of each sub-connection portion being electrically connected to the first source-drain electrode of the corresponding transistor.

[0016] For example, in an array substrate provided according to at least one embodiment of the present disclosure, each of the sub-connections extends in a direction from the first end to the second end, and at least one sub-connection of the electrode connection gradually decreases in width perpendicular to its extension direction.

[0017] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the extending direction of the sub-connection intersects the first direction and the second direction.

[0018] For example, according to at least one embodiment of the array substrate provided in this disclosure, the first source / drain electrode and the second source / drain electrode of the first transistor are located on the same layer. The array substrate further includes a plurality of active structures, each of which is located between the second source / drain electrode and the gate of the first transistor. The orthographic projection of the active structure on the substrate falls into the orthographic projection of the gate of the first transistor on the substrate. The edge of the curved portion of the second source / drain electrode of the first transistor away from the first source / drain electrode has a preset distance from the edge of the active structure. The preset distance satisfies: D≤(f1) 2 +d1 2 +f2 2 +d2 2 ) 0.5

[0019] In the formula, D represents the preset distance, f1 represents the process fluctuation value of the active structure, d1 represents the alignment deviation of the active structure, f2 represents the process fluctuation value of the second source-drain electrode, and d1 represents the alignment deviation of the second source-drain electrode.

[0020] For example, according to at least one embodiment of the present disclosure, the array substrate further includes a common electrode and a plurality of transmission lines arranged along the first direction, the common electrode being located on the side of the plurality of data lines and the plurality of thin-film transistors away from the substrate, the pixel electrode being configured to form an electric field with the common electrode; each of the transmission lines extends along the second direction and is electrically connected to the common electrode, and in the first direction, a plurality of the transmission lines are present between adjacent pairs of transistors.

[0021] At least one embodiment of this disclosure also provides a display device, including an array substrate, a counter substrate, and a liquid crystal layer as described in any of the above embodiments, wherein the counter substrate is disposed opposite to the array substrate, and the liquid crystal layer is located between the array substrate and the counter substrate. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0023] Figure 1 is a partial schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0024] Figure 2 is a planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0025] Figure 3 is a partial schematic diagram of another array substrate provided in at least one embodiment of the present disclosure.

[0026] Figure 4 is a partial schematic diagram of another array substrate provided in at least one embodiment of the present disclosure.

[0027] Figure 5 is a partial schematic diagram of another array substrate provided in at least one embodiment of the present disclosure.

[0028] Figure 6 is a partial schematic diagram of another array substrate provided in at least one embodiment of the present disclosure.

[0029] Figure 7 is a schematic diagram of some of the film layers in the array substrate shown in Figure 6.

[0030] Figure 8 is a schematic diagram of a first transistor in an array substrate provided in at least one embodiment of the present disclosure.

[0031] Figure 9 is a cross-sectional schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0032] Figure 10 is a schematic diagram of the structure of a display device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0035] The features such as "perpendicular," "parallel," and "identical" used in the embodiments of this disclosure include features in the strict sense of "perpendicular," "parallel," and "identical," as well as cases where "approximately perpendicular," "approximately parallel," and "approximately identical" include a certain degree of error. Taking into account the measurement and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. The "center" in the embodiments of this disclosure can include a position strictly located at the geometric center and a position approximately located at the center of a small area surrounding the geometric center.

[0036] In general, a variety of measures can be taken to reduce the power consumption of TFT LCDs.

[0037] For example, power consumption can be reduced by optimizing the backlight system, that is, by using more efficient LED backlight sources, such as Mini LEDs or Micro LEDs, and by using local dimming technology to reduce the backlight brightness of non-display areas in the array substrate, thereby reducing overall power consumption.

[0038] For example, power consumption can be reduced by improving the driver circuit, i.e., by using low-power driver ICs and more optimized circuit designs to reduce energy loss during the driving process.

[0039] For example, power consumption can be reduced by implementing intelligent brightness adjustment. This involves using an ambient light sensor to monitor ambient brightness in real time and automatically adjusting the screen brightness to suit viewing needs, thus avoiding energy waste caused by an overly bright or dim screen.

[0040] For example, power consumption can be reduced by optimizing the pixel structure, that is, by improving the pixel arrangement and circuit design, increasing the pixel aperture ratio and light transmittance, thereby reducing power consumption while maintaining the display effect.

[0041] By optimizing the pixel structure to reduce power consumption, the pixel aperture ratio and light transmittance can be increased to maintain good image quality. Optimizing the pixel structure can also improve the stability of the display effect. In addition, by improving the circuit design of the pixels, the transmission and conversion process of the driving signal can be optimized.

[0042] Based on this, at least one embodiment of the present disclosure provides an array substrate, including a substrate, multiple data lines, multiple thin-film transistors, and multiple pixel electrodes. The multiple data lines are located on the substrate and are arranged along a first direction. Each data line extends along a second direction, and both the first and second directions are parallel to the substrate and intersect each other. The multiple thin-film transistors are located on the substrate, and each thin-film transistor includes a first source / drain electrode, a gate electrode, and a second source / drain electrode. The first source / drain electrode is electrically connected to the data lines, and the orthographic projection of the first source / drain electrode on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate. The multiple pixel electrodes are located on the side of the multiple data lines away from the substrate, and each pixel electrode is electrically connected to the second source / drain electrode. The multiple thin-film transistors include at least one first transistor, and the orthographic projection area of ​​the first source / drain electrode of the first transistor on the substrate is smaller than the orthographic projection area of ​​the second source / drain electrode on the substrate.

[0043] In at least one embodiment of the array substrate provided by this disclosure, the projected area of ​​the first source-drain electrode of the first transistor on the substrate is smaller than the projected area of ​​the second source-drain electrode on the substrate, and the data line is electrically connected to the first source-drain electrode, thereby making the parasitic capacitance between the data line and the gate line smaller, which helps to reduce the power consumption of the data line and reduce the delay of the data signal, so as to improve the pixel charging efficiency.

[0044] The array substrate and display device provided in the embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings, so that the corresponding technical solutions can be clearer and easier to understand.

[0045] Figure 1 is a partial schematic diagram of an array substrate provided in at least one embodiment of the present disclosure; Figure 2 is a planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0046] As shown in Figure 1, the array substrate includes a substrate (not shown), and multiple data lines 100 and multiple thin-film transistors 200 located on the substrate. The multiple data lines 100 are located on the substrate, arranged along a first direction X, and each data line 100 extends along a second direction Y. Each thin-film transistor 200 includes a first source / drain electrode 201, a gate 203, and a second source / drain electrode 202. For example, the first source / drain electrode 201 can be a source, and the second source / drain electrode 202 can be a drain, but it is not limited to this. The terms source and drain are relative and can be used interchangeably. For example, one of the first source / drain electrode 201 and the second source / drain electrode 202 can be a source, and the other can be a drain. The first source / drain electrode 201 is electrically connected to the data lines 100 to receive data signals from the data lines 100.

[0047] For example, as shown in Figure 1, the array substrate may include multiple sub-pixels, each of which includes a thin-film transistor 200. The array substrate also includes multiple pixel electrodes 300, located on the side of the multiple data lines 100 away from the substrate. Each pixel electrode 300 is electrically connected to a second source / drain electrode 202. For example, an insulating layer exists between the pixel electrode 300 and the second source / drain electrode 202, and the pixel electrode 300 can be electrically connected to the second source / drain electrode 202 through a via (not shown) penetrating the insulating layer. For example, the array substrate also includes a common electrode 800, located between the substrate and the pixel electrodes 300. For example, the common electrode 800 is configured to form an electric field with the pixel electrodes 300. For example, a liquid crystal layer (not shown) may be disposed on one side of the array substrate, and the electric field formed between the common electrode 800 and the pixel electrodes 300 can drive the liquid crystal molecules in the liquid crystal layer to deflect for display. For example, the common electrode 800 can be a single-piece structure, such as being disposed across the entire surface. In some embodiments, the common electrode may also be located on the side of the pixel electrode away from the substrate, and the embodiments of this disclosure are not limited thereto.

[0048] As shown in Figure 1, both the first direction X and the second direction Y are parallel to the substrate, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0049] As shown in Figure 1, the orthographic projections of the first source / drain electrodes 201 of each thin-film transistor 200 onto the substrate at least partially overlap with the orthographic projections of the gate 203 onto the substrate. For example, the orthographic projections of the first source / drain electrodes 201 of each thin-film transistor 200 onto the substrate may fall completely or partially into the orthographic projection of the gate 203 onto the substrate. For example, the orthographic projections of the second source / drain electrodes 202 of each thin-film transistor 200 onto the substrate also at least partially overlap with the orthographic projections of the gate 203 onto the substrate.

[0050] As shown in Figure 1, the plurality of thin-film transistors 200 include at least one first transistor 210. The orthographic projection area of ​​the first source-drain electrode 201 of the first transistor 210 on the substrate is smaller than the orthographic projection area of ​​the second source-drain electrode 202 on the substrate. The orthographic projection of the first source-drain electrode 201 of the first transistor 210 on the substrate falls within the orthographic projection of the gate 203 of the first transistor 210 on the substrate. The orthographic projection of the second source-drain electrode 202 of the first transistor 210 on the substrate at least partially overlaps with the orthographic projection of the gate 203 of the first transistor 210 on the substrate. In some embodiments, the orthographic projections of the first source-drain electrode 201 and the second source-drain electrode 202 of the first transistor 210 on the substrate may both fall within the orthographic projection of the gate 203 of the first transistor 210 on the substrate, and the embodiments of this disclosure are not limited thereto. For example, the first source-drain electrode 201 of the first transistor 210 and the data line 100 can be an integral structure, located on the same layer, and using the same conductive material. For example, a portion of the first source-drain electrode 201 of the first transistor 210 is surrounded by the second source-drain electrode 202, but is not limited thereto.

[0051] In at least one embodiment of the array substrate provided by this disclosure, the projected area of ​​the first source-drain electrode of the first transistor on the substrate is smaller than the projected area of ​​the second source-drain electrode on the substrate, and the data line is electrically connected to the first source-drain electrode, thereby making the parasitic capacitance between the data line and the gate smaller, which helps to reduce the power consumption of the data line and reduce the delay of the data signal, so as to improve the pixel charging efficiency.

[0052] For example, as shown in FIG1, the first source-drain electrode 201 of the first transistor 210 extends along the first direction X. For example, the dimension of the first source-drain electrode 201 in the second direction Y is smaller than the dimension of the second source-drain electrode 202 in the second direction Y.

[0053] This configuration minimizes the overlap area between the first source / drain electrode and the gate electrode in the direction perpendicular to the substrate, thereby reducing parasitic capacitance. This helps reduce the power consumption of the data line and the delay of the data signal, thus improving pixel charging efficiency.

[0054] For example, as shown in FIG1, the second source / drain electrode 202 of the first transistor 210 includes a bent portion 2021 and a second source / drain electrode connection portion 2022 connected to each other. The bent portion 2021 is closer to the first source / drain electrode 201 than the second source / drain electrode connection portion 2022, and the bent portion 2021 is electrically connected to the pixel electrode 300 through the second source / drain electrode connection portion 2022. For example, the orthographic projection of the bent portion 2021 on the substrate is "C"-shaped or "U"-shaped, but not limited thereto. For example, the second source / drain electrode connection portion 2022 extends along a first direction. For example, the bent portion 2021 includes an opening 20210, a portion of the first source / drain electrode 201 extending from the opening 20210 into the area enclosed by the bent portion 2021. For example, the first source / drain electrode 201 and the bent portion 2021 are spaced apart from each other. For example, one end of the first source / drain electrode 201 is located in the area enclosed by the bend 2021, and the other end of the first source / drain electrode 201 is located outside the area enclosed by the bend 2021, and the other end of the first source / drain electrode 201 is connected to the data line 100. For example, the first source / drain electrode 201 and the second source / drain electrode 202 are located in the same layer and are made of the same material, but the embodiments of this disclosure are not limited in this respect.

[0055] For example, as shown in FIG2, the array substrate includes a display area 410 and a non-display area 420, at least a portion of the non-display area 420 surrounding the display area 410, which is configured for display. For example, the non-display area 420 may be located on at least one side of the display area 410. For example, the non-display area 420 may surround the display area 410, meaning the display area 410 can be enclosed by the non-display area 420. For example, the non-display area 420 may also be located in other positions, depending on the specific requirements. For example, the aforementioned first transistor may be located in the display area 410 to reduce the power consumption of the data lines and the delay of the data signal by reducing the parasitic capacitance between the data lines and the gate lines in the display area 410, thereby improving pixel charging efficiency.

[0056] For example, Table 1 shows a schematic diagram of the simulation results for a general-purpose transistor and a first transistor. For example, the general-purpose transistor can be the second transistor shown in Figure 3 below, and specific details can be found in the following embodiments.

[0057] For example, as shown in Table 1, when the voltage of the data line increases from 0V to 25V, compared to a conventional transistor, the resistance R of the data line connected to the first transistor remains essentially unchanged at 1.951KΩ. The parasitic capacitance between the data line and the gate connected to the first transistor decreases from 69pF to 50pF, a reduction of 27%, thereby reducing the data line delay time from 0.134µs to 0.097µs. Therefore, using the first transistor provided in at least one embodiment of this disclosure can effectively reduce the parasitic capacitance between the data line and the gate line, thereby improving the data line response speed and reducing signal delay.

[0058] For example, as shown in Table 2, the end of the data line closer to the driver chip is the near end, and the end farther from the driver chip is the far end. For instance, for a standard transistor, when the data line voltage rises from 0V to 25V, the rise time at the near end is 0.953 microseconds, and the rise time at the far end is 0.958 microseconds, with a corresponding time difference ΔT of 0.005 microseconds. When the data line voltage drops from 25V to 0V, the fall time at the near end is 0.652 microseconds, and the fall time at the far end is 0.736 microseconds, with a corresponding time difference ΔT of 0.084 microseconds. For example, for the first transistor, when the data line voltage rises from 0V to 25V, the rise time at the near end is 0.943 microseconds, and the rise time at the far end is 0.953 microseconds, with a corresponding time difference ΔT of 0.01 microseconds. When the voltage on the data line drops from 25V to 0V, the fall time at the near end of the data line is 0.526 microseconds, and the fall time at the far end is 0.590 microseconds, corresponding to a time difference ΔT of 0.064 microseconds. This shows that when the voltage on the data line rises from 0V to 25V, the rise time difference between the near and far ends is essentially the same and relatively small. However, when the voltage drops from 25V to 0V, the fall time difference between the near and far ends differs significantly, with the first transistor shortening the difference by approximately 24% compared to a conventional transistor. This demonstrates that the signal transmission between the near and far ends of the data line connected by the first transistor is uniform, resulting in less signal delay.

[0059] For example, as shown in Table 3, at the same display grayscale (255 grayscale), three array substrates using ordinary transistors were selected as samples 1, 2, and 3, respectively. The temperatures of driver chip 1 and driver chip 2 in each sample were measured, and the average value of the six measured temperature values ​​was obtained, which is 68.88℃. At the same display grayscale (255 grayscale), two array substrates using first transistors were selected as samples 1 and 2, respectively. The temperatures of driver chip 1 and driver chip 2 in each sample were measured, and the average value of the four measured temperature values ​​was obtained, which is 65.35℃, a reduction of approximately 5.12%. Therefore, it can be seen that using first transistors is beneficial for reducing the operating temperature of the driver chips in the array substrate.

[0060] Table 1. Capacitor Simulation Results

[0061] Table 2 Simulation Results of Data Line Waveform Delay Time

[0062] Table 3. Temperature Simulation Results of Driver Chips

[0063] Figure 3 is a partial schematic diagram of another array substrate provided in at least one embodiment of the present disclosure.

[0064] For example, as shown in FIG3, the plurality of thin-film transistors 200 in the array substrate may include at least one second transistor 220. The projected area of ​​the first source / drain electrode 201 of the second transistor 220 on the substrate is larger than the projected area of ​​the second source / drain electrode 202 on the substrate. For example, the array substrate may include a plurality of first transistors 210 (see FIG1) and a plurality of second transistors 220. For example, the number of second transistors 220 in the array substrate is less than the number of first transistors 210. For example, as shown in FIG3 and FIG4, the plurality of first transistors 210 may be located in the display area 410 and the plurality of second transistors 420 may be located in the non-display area 420, but the embodiments of the present disclosure are not limited thereto.

[0065] For example, by including a second transistor in the array substrate (e.g., including a second transistor while including a plurality of first transistors), it is beneficial to balance the parasitic capacitance of the gate line connected to the gate of the thin-film transistor, thereby facilitating the efficient transmission of the gate signal.

[0066] For example, as shown in FIG3, at least one second transistor 220 in the array substrate includes at least one dummy transistor 230, and the array substrate also includes at least one common electrode line 110, and the plurality of pixel electrodes 300 include at least one dummy pixel electrode 3001. For example, the second source / drain electrode 202 of the dummy transistor 230 is electrically connected to the dummy pixel electrode 3001, the first source / drain electrode 201 of the dummy transistor 230 is electrically connected to the common electrode line 110, and the common electrode line 110 is electrically connected to a common electrode (not shown in the figure, for example, the common electrode is located on the side of the pixel electrode away from the substrate). For example, the difference between the dummy transistor 230 and the first transistor 210 described in the above embodiments lies in the connection method.

[0067] This configuration, by making the projected area of ​​the first source / drain electrode connected to the dummy data line on the substrate larger than the projected area of ​​the second source / drain electrode on the substrate, and by electrically connecting the dummy data line to the common electrode, helps to increase the parasitic capacitance between the common electrode and the gate line through the first source / drain electrode, thereby helping to maintain the stability of the voltage of the common electrode.

[0068] For example, as shown in Figures 2 and 3, the dummy transistor 230 can be located in the non-display area 420, thereby reducing the impact on the display effect of the display area 410 while maintaining the stability of the voltage of the common electrode.

[0069] Figure 4 is a partial schematic diagram of another array substrate provided in at least one embodiment of the present disclosure.

[0070] For example, the structure of the thin-film transistors in the array substrate shown in Figure 4 is different from that shown in Figure 1. For example, the plurality of thin-film transistors 200 include a plurality of transistor pairs 2000, and each transistor pair 2000 includes a first transistor 210 and a second transistor 220. For example, in the transistor pair 2000, the first source-drain electrode 201 of the first transistor 210 and the second source-drain electrode 202 of the second transistor 220 are both connected to the same data line 100.

[0071] For example, as shown in Figure 4, in transistor pair 2000, the first source / drain electrode 201 of the first transistor 210 and the second source / drain electrode 202 of the second transistor 220 are connected to the same data line 100 through the same connection structure 250. For example, in the first direction X, the first source / drain electrode 201 of the first transistor 210 and the second source / drain electrode 202 of the second transistor 220 are located on opposite sides of the connected data line 100. For example, the projected area of ​​the first source / drain electrode 201 of the first transistor 210 on the substrate is smaller than the projected area of ​​the second source / drain electrode 202 of the second transistor 220 on the substrate. For example, the parasitic capacitance between the first source / drain electrode 201 of the first transistor 210 and the gate line 500 is smaller than the parasitic capacitance between the second source / drain electrode 202 of the second transistor 220 and the gate line 500.

[0072] By connecting the first source / drain electrode of the first transistor and the second source / drain electrode of the second transistor to the same data line, it is beneficial to balance the parasitic capacitance between the data line and different gate lines, so that the data line can transmit signals stably and keep the power consumption of the data line stable.

[0073] For example, as shown in FIG. 4, a plurality of pixel electrodes 300 are arrayed in a first direction X and a second direction Y to form a plurality of pixel electrode rows 310 arranged along the second direction Y and a plurality of pixel electrode columns 320 arranged along the first direction X. For example, at least a portion of the orthographic projection of each pixel electrode 300 on the substrate falls into the orthographic projection of a common electrode (not shown) on the substrate. For example, the array substrate also includes a plurality of transmission lines 600, each transmission line 600 extending along the second direction Y. For example, in the first direction X, there may be a transmission line 600 between adjacent transistor pairs 2000. For example, the transmission line 600 may serve as a common electrode line, for example, the common electrode is electrically connected to the plurality of transmission lines 600 to receive a common electrode signal and to reduce the resistance of the common electrode. For example, the plurality of transmission lines 600 may receive the same common electrode signal, thereby maintaining a constant voltage of the common electrode. For example, the pixel electrode 300 may be made of a transparent material. For example, the pixel electrode 300 can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) to maintain good conductivity while allowing light to pass through.

[0074] For example, as shown in Figure 4, the plurality of pixel electrodes 300 includes a plurality of pixel electrode pairs 3000. Each pixel electrode pair 3000 includes a first pixel electrode 301 and a second pixel electrode 302. The first pixel electrode 301 and the second pixel electrode 302 are respectively located in adjacent pixel electrode rows 310 and adjacent pixel electrode columns 320. For example, the second source / drain electrode 202 of the first transistor 210 is electrically connected to the first pixel electrode 301, and the second source / drain electrode 202 of the second transistor 220 is electrically connected to the second pixel electrode 302.

[0075] For example, as shown in Figure 4, multiple pixel electrode pairs 3000 are arranged in a one-to-one correspondence with multiple transistor pairs 2000. For example, in the first direction X, the first pixel electrode 301 and the second pixel electrode 302 in the pixel electrode pair 3000 are located on both sides of the data line 100 connected to the first transistor 210 and the second transistor 220 in the transistor pair 2000, respectively. For example, in the second direction Y, the first pixel electrode 301 and the second pixel electrode 302 in the pixel electrode pair 3000 are located on both sides of the transistor pair 2000. For example, in the second direction Y, the first transistor 210 in the transistor pair 2000 is closer to the first pixel electrode 301 than the second transistor 220, and the second transistor 220 in the transistor pair 2000 is closer to the second pixel electrode 302 than the first transistor 210, thereby facilitating connection to the corresponding pixel electrode 300.

[0076] For example, as shown in FIG4, the array substrate further includes multiple gate lines 500, each gate line 500 extending along a first direction X. For example, the extension direction of the gate line 500 refers to its main extension direction. For example, the gate line 500 may also include portions that do not extend along the first direction X, and the embodiments of this disclosure do not limit this.

[0077] For example, as shown in FIG4, the multiple gate lines 500 include multiple gate line pairs 5000, each gate line pair 5000 including a first gate line 510 and a second gate line 520 spaced apart in the second direction Y. For example, the gate line pairs 5000 are located between adjacent pixel electrode rows 310 in the second direction Y, the first gate line 510 is configured to be electrically connected to the gate 203 of the first transistor 210, and the second gate line 520 is configured to be electrically connected to the gate 203 of the second transistor 220. For example, the first gate line 510 and the second gate line 520 in the gate line pair 500 can be two independent signal lines, and the first gate line 510 and the second gate line 520 can be driven individually. For example, each gate line 500 is configured to receive a gate signal, thereby enabling the active structure 204 to be turned on and forming a conductive path between the first source / drain electrode 201 and the second source / drain electrode 202 in the thin film transistor 200.

[0078] Figure 5 is a partial schematic diagram of another array substrate provided in at least one embodiment of the present disclosure.

[0079] For example, the connection method of the pixel electrodes in the array substrate shown in Figure 5 is different from that in the array substrate shown in Figure 4. Other features can be found in the relevant descriptions of the above embodiments, and will not be repeated here.

[0080] For example, as shown in FIG5, the plurality of pixel electrodes 300 includes a plurality of pixel electrode pairs 3000, and each pixel electrode pair 3000 includes a first pixel electrode 301 and a second pixel electrode 302. The first pixel electrode 301 and the second pixel electrode 302 are respectively located in adjacent pixel electrode rows 310. For example, there are at least two columns of pixel electrodes 320 between the first pixel electrode 301 and the second pixel electrode 302. For example, there may be 3 to 4 columns of pixel electrodes 320 between the first pixel electrode 301 and the second pixel electrode 302, and the embodiments of this disclosure are not limited thereto.

[0081] For example, as shown in FIG5, in the first direction X, the first pixel electrode 301 and the second pixel electrode 302 in the pixel electrode pair 3000 are located on both sides of the data line 100 connected to the first transistor 210 and the second transistor 220 in the transistor pair 2000, and there are two columns of pixel electrodes 320 between the first pixel electrode 301 and the second pixel electrode 302. For example, in the second direction Y, the first pixel electrode 301 and the second pixel electrode 302 in the pixel electrode pair 3000 are located on both sides of the transistor pair 2000.

[0082] For example, as shown in FIG5, each pixel electrode 300 includes an electrode body portion 330 and an electrode connection portion 340 connected to each other. The electrode connection portion 340 of the first pixel electrode 301 is electrically connected to the second source / drain electrode 202 of the first transistor 210, and the electrode connection portion 340 of the second pixel electrode 302 is electrically connected to the second source / drain electrode 202 of the second transistor 220. For example, the orthogonal projection area of ​​the electrode body portion 330 on the substrate is larger than the orthogonal projection area of ​​the electrode connection portion 340 on the substrate, and the electrode body portion 330 is electrically connected to the second source / drain electrode 202 of the corresponding transistor through the electrode connection portion 340.

[0083] For example, as shown in FIG5, at least one pixel electrode 300 has an electrode connection portion 340 including a plurality of sub-connection portions 3410, each sub-connection portion 3410 including a first end 3411 and a second end 3412. The first end 3411 of each sub-connection portion 3410 is connected to the electrode body portion 330, and the second end 3412 of each sub-connection portion 3410 is electrically connected to the second source / drain electrode 202 of the corresponding transistor. For example, the sub-connection portion 3410 can serve as an electrostatic discharge path. By including a plurality of sub-connection portions 3410 in the electrode connection portion 340, an electrostatic discharge path can be added while ensuring the electrical connection between the electrode body portion 330 and the second source / drain electrode 202 of the corresponding transistor. For example, when one sub-connection portion 3410 of the electrode connection portion 340 is disconnected due to electrostatic discharge or other reasons, the other sub-connection portions 3410 in the electrode connection portion 340 can still ensure the electrical connection between the electrode body portion 330 and the second source / drain electrode 202 of the corresponding transistor and continue to serve as an electrostatic discharge path.

[0084] For example, as shown in FIG5, each sub-connection portion 3410 extends in a direction from the first end 3411 to the second end 3412, and the width of at least one sub-connection portion 3410 of the electrode connection portion 340 gradually decreases in the direction perpendicular to its extension. For example, the width of the first end 3411 of the sub-connection portion 3410 connected to the electrode body portion 330 is greater than the width of the second end 3412. This arrangement can reduce the transmission resistance between the electrode body portion 330 and the first end 3411 of the sub-connection portion 3410, thereby improving the uniformity of signal transmission.

[0085] For example, as shown in FIG5, the extension direction of the sub-connection portion 3410 intersects with the first direction X and the second direction Y. For example, the extension direction of the sub-connection portion 3410 has a first angle with the first direction X, and the extension direction of the sub-connection portion 3410 has a second angle with the second direction Y. The first angle and the second angle can be approximately equal, for example, both can be 45 degrees, but the embodiments of this disclosure are not limited to this. FIG5 illustrates an example where the electrode connection portion 340 of the pixel electrode 300 includes two sub-connection portions 3410, and the width of the first end 3411 of either of the two sub-connection portions 3410 connected to the electrode body portion 330 is greater than the width of the second end 3412. This can effectively reduce the transmission resistance between the electrode body portion 330 and the first end 3411 of the sub-connection portion 3410, thereby improving the uniformity of signal transmission.

[0086] This configuration helps to shorten the length of the sub-connection section, thereby facilitating the effective connection between the electrode body and the second source / drain electrode of the corresponding transistor, reducing the transmission resistance of the sub-connection section, and ultimately enabling efficient signal transmission.

[0087] Figure 6 is a partial schematic diagram of another array substrate provided in at least one embodiment of the present disclosure; Figure 7 is a schematic diagram of a portion of the film layer in the array substrate shown in Figure 6.

[0088] For example, compared with the array substrate shown in FIG5, the array substrate shown in FIG6 includes multiple transmission lines 600 arranged along the first direction X, and the positions of the pixel electrodes are different, but the rest of the structure is the same. For details, please refer to the relevant description of the above embodiments, which will not be repeated here.

[0089] For example, as shown in Figures 6 and 7, the array substrate also includes a common electrode 800, which is located on the side of the multiple data lines 100 and multiple thin film transistors 200 away from the substrate. The common electrode 800 is configured to form an electric field with the pixel electrode 300.

[0090] For example, as shown in Figures 6 and 7, in the first direction X, there are multiple transmission lines 600 between adjacent transistor pairs 2000, and the transmission lines 600 are electrically connected to the common electrode 800. The array substrate can be used for touch display. For example, the transmission lines 600 can serve as drive electrode lines (e.g., they can be called TX lines). For example, when a finger or other conductor touches the array substrate, the capacitance change between the common electrode 800 and the finger can be captured by the transmission lines 600, and then converted into an electrical signal.

[0091] By setting multiple transmission lines between adjacent transistor pairs, the sensing sensitivity of the array substrate to conductors (e.g., fingers) can be enhanced, thereby improving the response speed to capacitance changes and enabling more accurate conversion of capacitance changes into electrical signals.

[0092] Figure 8 is a schematic diagram of a first transistor in an array substrate provided in at least one embodiment of the present disclosure.

[0093] For example, as shown in Figure 8, the first transistor 210 includes a first source / drain electrode 201, a second source / drain electrode 202, and a gate 203. The first source / drain electrode 201 and the second source / drain electrode 202 of the first transistor 210 are located on the same layer. The array substrate also includes a plurality of active structures 204, each active structure 204 being located between the second source / drain electrode 202 and the gate 203 of the first transistor 210. The orthographic projection of the active structure 204 on the substrate falls into the orthographic projection of the gate 203 of the first transistor 210 on the substrate.

[0094] For example, as shown in Figure 8, the edge of the curved portion 2021 of the second source / drain electrode 202 of the first transistor 210 away from the first source / drain electrode 201 has a preset distance from the edge of the active structure 204, and the preset distance satisfies: D≤(f1) 2 +d1 2 +f22 +d2 2 ) 0.5

[0095] In the formula, D represents the preset distance, f1 represents the process fluctuation value of the active structure 204, d1 represents the alignment deviation of the active structure 204, f2 represents the process fluctuation value of the second source / drain electrode 202, and d2 represents the alignment deviation of the second source / drain electrode 202.

[0096] For example, as shown in Figure 8, the process fluctuation value f1 of the active structure 204 and the process fluctuation value f2 of the second source-drain electrode 202 are both 0.5–5 micrometers. For example, the process fluctuation value f1 of the active structure 204 and the process fluctuation value f2 of the second source-drain electrode 202 can be equal or different. For example, the process fluctuation value f1 of the active structure 204 can be 0.5–2.5 micrometers, 1.5–3.0 micrometers, 2.0–3.5 micrometers, 4.0–4.5 micrometers, or 4.5–5.0 micrometers. For example, the process fluctuation value f2 of the second source-drain electrode 202 can be 0.5–2.5 micrometers, 1.5–3.0 micrometers, 2.0–3.5 micrometers, 4.0–4.5 micrometers, or 4.5–5.0 micrometers. For example, the alignment deviation d1 of the active structure 204 and the alignment deviation d2 of the second source-drain electrode 202 can be equal or different. For example, the alignment deviation d1 of the active structure 204 can be 1.0–1.5 μm, 2.0–2.5 μm, 3.0–3.5 μm, 2.0–3.5 μm, or 1.5–3.0 μm. For example, the alignment deviation d2 of the second source / drain electrode 202 can be 1.0–1.5 μm, 2.0–2.5 μm, 3.0–3.5 μm, 2.0–3.5 μm, or 1.5–3.0 μm. For example, the preset distance D can be 1.7–2.6 μm, for example, 1.7–2.0 μm, 1.8–2.1 μm, 1.9–2.2 μm, or 2.0–2.4 μm.

[0097] By ensuring that the preset distance meets the above range, the orthographic projection of the curved portion of the second source / drain electrode of the first transistor on the substrate can be located in the orthographic projection of the active structure on the substrate, and there is a gap between the curved portion and the edge of the active structure, thereby enabling the first transistor to have good conduction performance, which is beneficial for signal transmission.

[0098] It should be noted that Figure 8 is only illustrated using the first transistor as an example. For example, the first source-drain electrode of the second transistor in the array substrate may also include a bent portion, and the distance between the bent portion and the edge of the active structure may also satisfy the above-mentioned preset distance. The embodiments of this disclosure do not limit this.

[0099] Figure 9 is a cross-sectional schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0100] For example, as shown in Figure 9, the thin-film transistor 200 includes a first source / drain electrode 201, a second source / drain electrode 202, and a gate 203. A gate insulating layer 1011 is disposed on the gate 203, and an active structure 204 is disposed on the gate insulating layer 1011. An organic insulating layer 1022 is disposed on the first source / drain electrode 201 and the second source / drain electrode 202. A common electrode 800 is disposed on the insulating structure 1022 and is covered by an insulating structure 1033. A pixel electrode 300 is located on the insulating structure 1033, and the pixel electrode 400 is electrically connected to the second electrode 202 through a connecting via N penetrating the insulating structure 1033. For example, the insulating structure 1022 can be made of an organic material, and the insulating structure 1033 can be represented as a passivation layer PVX, but is not limited thereto.

[0101] Figure 10 is a schematic diagram of the structure of a display device provided in at least one embodiment of the present disclosure.

[0102] As shown in Figure 10, at least one embodiment of this disclosure also provides a display device 1000, which includes the array substrate described in any of the above embodiments. Therefore, since the display device includes the array substrate, the technical effects of the array substrate can also be reflected in the display device, and will not be elaborated further here.

[0103] As shown in Figure 10, the display panel 1000 includes an array substrate 01, an opposing substrate 02, and a liquid crystal layer 03. The opposing substrate 02 and the array substrate 01 are disposed opposite each other to form a cell. The liquid crystal layer 03 is located between the array substrate 01 and the opposing substrate 02, and the liquid crystal molecules in the liquid crystal layer 03 are deflected under the action of the array substrate 01 and the opposing substrate 02, thereby performing display. For example, the array substrate 01 can be the array substrate described in any of the above embodiments.

[0104] For example, as shown in FIG10, the liquid crystal layer 03 includes a plurality of liquid crystal molecules 031. In some embodiments, a filter layer may be provided on the side of the opposing substrate 02 facing the array substrate 01 to achieve color display. For example, the filter layer includes a plurality of filter units, each filter unit corresponding to a display electrode. For example, the plurality of filter units may include a plurality of red filter units, a plurality of green filter units, and a plurality of blue filter units, but is not limited thereto.

[0105] In embodiments of this disclosure, components located in the same layer may be fabricated from the same film layer using the same patterning process. For example, components located in the same layer may be located on the surface of the same component away from the substrate.

[0106] It should be noted that, for clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "below" another element, the element may be located "directly" on or "below" the other element, or there may be intermediate elements present.

[0107] In the embodiments of this disclosure, the patterning or patterning process may include only photolithography, or it may include both photolithography and etching steps, or it may include other processes such as printing or inkjet printing to form a predetermined pattern. Photolithography refers to processes including film formation, exposure, and development, using photoresist, photomasks, and exposure machines to form patterns. The appropriate patterning process can be selected based on the structure formed in the embodiments of this disclosure.

[0108] In the embodiments of this disclosure, components located in different layers are formed from different film layers through different patterning processes.

[0109] The following points also need to be explained:

[0110] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0111] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0112] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended rights.

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