Dimming panel, display panel, display apparatus and liquid crystal lens

Abstract

The present disclosure relates to the technical field of liquid crystals. Provided in the embodiments of the present disclosure are a dimming panel, a display panel, a display apparatus and a liquid crystal lens, which are at least used for solving the problem of functional partition implementation of dimming panels. The dimming panel comprises a first substrate, a second substrate and a plurality of conductive portions. The first substrate comprises a plurality of first electrodes, the plurality of first electrodes being arranged in a functional area. The second substrate is arranged opposite to the first substrate and comprises a plurality of second electrodes, the plurality of second electrodes being arranged in the functional area. The plurality of conductive portions are arranged between the first substrate and the second substrate and located in a peripheral area. The first substrate further comprises a plurality of second voltage signal lines arranged in the peripheral area, one second electrode being electrically connected to one second voltage signal line by means of at least one conductive portion, and the plurality of second voltage signal lines being configured to independently provide second voltage signals to respective corresponding second electrodes. The dimming panel is applied to the display apparatus or the liquid crystal lens.

Description

Dimming panel, display panel, display device and liquid crystal lens Technical Field

[0001] This disclosure relates to the field of liquid crystal technology, and in particular to a dimming panel, a display panel, a display device, and a liquid crystal lens. Background Technology

[0002] Liquid crystal (LC) molecules can rotate under the influence of an electric field, and the rotation angle changes with the driving voltage. Based on this property of liquid crystal molecules, liquid crystal technology is widely used in fields such as light modulation, for example, in dimming panels, which are used in display devices, liquid crystal lenses, and other similar devices. Summary of the Invention

[0003] On one hand, a dimming panel is provided. The dimming panel includes a functional area and a peripheral area surrounding the functional area. The dimming panel includes a first substrate, a second substrate, and a plurality of conductive portions. The first substrate includes a plurality of first electrodes disposed in the functional area. The second substrate is disposed opposite to the first substrate and includes a plurality of second electrodes disposed in the functional area. The orthographic projection of one second electrode on the first substrate overlaps with at least one first electrode, and the plurality of second electrodes are disposed independently of each other. The plurality of conductive portions are disposed between the first substrate and the second substrate and are located in the peripheral area. The first substrate further includes a plurality of second voltage signal lines disposed in the peripheral area; one second electrode is electrically connected to one second voltage signal line through at least one conductive portion, and the plurality of second voltage signal lines are configured to provide a second voltage signal to their respective corresponding second electrodes relatively independently.

[0004] In some embodiments, the functional area includes a first display area and a second display area. A plurality of second electrodes include a first partition electrode and a second partition electrode, the first partition electrode being disposed in the first display area and the second partition electrode being disposed in the second display area. A plurality of conductive portions include a first conductive portion and a second conductive portion. A plurality of second voltage signal lines include a first partition voltage signal line and a second partition voltage signal line, the first conductive portion being electrically connected to the first partition voltage signal line and the second conductive portion being electrically connected to the second partition voltage signal line. The second substrate further includes a first connecting portion and a second connecting portion. The first connecting portion is disposed on one side of the first partition electrode and is electrically connected to the first partition electrode and also electrically connected to the first conductive portion. The second connecting portion is disposed on one side of the second partition electrode and is electrically connected to the second partition electrode and also electrically connected to the second conductive portion.

[0005] In some embodiments, the first substrate further includes a first pad and a second pad. The orthographic projection of the first connection portion onto the first substrate overlaps with the first pad. A first conductive portion is located between the first connection portion and the first pad, and is electrically connected to the first pad. The first pad is electrically connected to a first partition voltage signal line. The orthographic projection of the second connection portion onto the first substrate overlaps with the second pad. A second conductive portion is located between the second connection portion and the second pad, and is electrically connected to the second pad. The second pad is electrically connected to a second partition voltage signal line.

[0006] In some embodiments, the first substrate further includes a first pattern and a second pattern. The first pattern is disposed below and electrically connected to the first pad; the first pattern is also electrically connected to a first partition voltage signal line. The second pattern is disposed below and electrically connected to the second pad; the second pattern is also electrically connected to a second partition voltage signal line.

[0007] In some embodiments, the peripheral region includes a first sub-region, a second sub-region, a third sub-region, and a fourth sub-region. The first and second sub-regions are located on opposite sides of the functional region in a second direction, and the third and fourth sub-regions are located on opposite sides of the functional region in a first direction. The first direction is the arrangement direction of the first partition electrode and the second partition electrode, and the first direction intersects the second direction. Both the first connecting portion and the second connecting portion are located in the first sub-region.

[0008] In some embodiments, the first connecting portion, the second connecting portion, the first partition electrode, and the second partition electrode are made of the same material. The first connecting portion is integrally disposed with the first partition electrode and extends along the side of the first partition electrode in which it is located. The second connecting portion is integrally disposed with the second partition electrode and extends along the side of the second partition electrode in which it is located.

[0009] In some embodiments, along the first direction, the distance between the first connecting portion and the second connecting portion is greater than the distance between the first partition electrode and the second partition electrode.

[0010] In some embodiments, the second sub-region includes a first bonding area and a second bonding area, the first bonding area being located on one side of the first display area and the second bonding area being located on one side of the second display area. A first partition voltage signal line extends along a third sub-region and extends to the first bonding area. A second partition voltage signal line extends along a fourth sub-region and extends to the second bonding area.

[0011] In some embodiments, the second substrate further includes a third connection portion and a fourth connection portion located in the second sub-region. The third connection portion is located on one side of the first partition electrode and electrically connected to the first partition electrode, and the fourth connection portion is located on one side of the second partition electrode and electrically connected to the second partition electrode. Multiple conductive portions further include a third conductive portion and a fourth conductive portion located in the second sub-region. The third connection portion is electrically connected to the third conductive portion, and the fourth connection portion is electrically connected to the fourth conductive portion. Multiple second voltage signal lines further include a third partition voltage signal line and a fourth partition voltage signal line located in the second sub-region. The third partition voltage signal line extends to the first bonding region, and the fourth partition voltage signal line extends to the second bonding region. The third conductive portion is electrically connected to the third partition voltage signal line, and the fourth conductive portion is electrically connected to the fourth partition voltage signal line.

[0012] In some embodiments, the third connecting portion, the fourth connecting portion, the first partition electrode, and the second partition electrode are made of the same material. The third connecting portion is integrally disposed with the first partition electrode and extends along the side of the first partition electrode in which it is located. The fourth connecting portion is integrally disposed with the second partition electrode and extends along the side of the second partition electrode in which it is located.

[0013] In some embodiments, along the second direction, the spacing between the third connecting portion and the fourth connecting portion is greater than the spacing between the first partition electrode and the second partition electrode.

[0014] In some embodiments, the first substrate further includes a first pin, a second pin, a third pin, and a fourth pin. The first pin and the third pin are disposed in a first bonding region and are spaced apart along a first direction, with the first pin being further away from the centerline of the dimming panel along a second direction than the third pin. A first partition voltage signal line is electrically connected to the first pin, and a third partition voltage signal line is electrically connected to the third pin. The second pin and the fourth pin are disposed in a second bonding region and are spaced apart along the first direction, with the second pin being further away from the centerline of the dimming panel along the second direction than the fourth pin. A second partition voltage signal line is electrically connected to the second pin, and a fourth partition voltage signal line is electrically connected to the fourth pin.

[0015] In some embodiments, the first substrate further includes a first scan line, a second scan line, a first fan-out line, and a second fan-out line. The first scan line extends along a first direction within the first display area, and a plurality of first scan lines are spaced apart along a second direction. The second scan line extends along the first direction within the second display area, and a plurality of second scan lines are spaced apart along the second direction. The first scan line and the second scan line are spaced apart in the first direction. The first fan-out line is electrically connected to the first scan line, extends along a third sub-region, and extends to a first bonding region. The second fan-out line is electrically connected to the second scan line, extends along a fourth sub-region, and extends to a second bonding region.

[0016] In some embodiments, the second substrate further includes a first regulating electrode and a second regulating electrode. The orthographic projection of the first regulating electrode on the first substrate covers the first fan-out line. The orthographic projection of the second regulating electrode on the first substrate covers the second fan-out line. The voltages of both the first and second regulating electrodes are configured to switch between a first regulating voltage and a second regulating voltage, and the non-operating voltages of both the first and second fan-out lines are greater than the first regulating voltage and less than the second regulating voltage.

[0017] In some embodiments, the plurality of conductive portions further include a fifth conductive portion and a sixth conductive portion disposed in the peripheral region. The first substrate further includes a first adjustment signal line and a second adjustment signal line. The first adjustment signal line extends along a third sub-region and extends to a first bonding region; a first adjustment electrode is electrically connected to the first adjustment signal line through at least one fifth conductive portion. The second adjustment signal line extends along a fourth sub-region and extends to a second bonding region; a second adjustment electrode is electrically connected to the second adjustment signal line through at least one sixth conductive portion.

[0018] In some embodiments, the second substrate further includes a fifth connecting portion and a sixth connecting portion, the fifth connecting portion being electrically connected to the first adjusting electrode, and the sixth connecting portion being electrically connected to the second adjusting electrode. The first substrate further includes a third pad and a fourth pad, the third pad being electrically connected to the first adjusting signal line, and the fourth pad being electrically connected to the second adjusting signal line. The orthographic projection of the fifth connecting portion on the first substrate overlaps with the third pad, and a fifth conductive portion is located between the fifth connecting portion and the third pad and is electrically connected to both. The orthographic projection of the sixth connecting portion on the first substrate overlaps with the fourth pad, and a sixth conductive portion is located between the sixth connecting portion and the fourth pad and is electrically connected to both.

[0019] In some embodiments, the first substrate further includes a third pattern and a fourth pattern. The third pattern is disposed below and electrically connected to the third pad; the third pattern is also electrically connected to the first adjustment signal line. The fourth pattern is disposed below and electrically connected to the fourth pad; the fourth pattern is also electrically connected to the second adjustment signal line.

[0020] In some embodiments, the fifth connection portion is located on the outer side of the corner of the first partition electrode near the first sub-region and the third sub-region, and the sixth connection portion is located on the outer side of the corner of the second partition electrode near the first sub-region and the fourth sub-region.

[0021] In some embodiments, the fifth and sixth connecting portions are L-shaped. The side of the fifth connecting portion is opposite to the side of the first connecting portion in a first direction, and there is a gap between them. The side of the sixth connecting portion is opposite to the side of the second connecting portion in a first direction, and there is a gap between them.

[0022] In some embodiments, the first regulating electrode and the second regulating electrode are L-shaped. Both the first and second regulating electrodes include a first portion and a second portion connected to each other. The first portion of the first regulating electrode extends along a third sub-region, and the first portion of the second regulating electrode extends along a fourth sub-region. Along the direction from the first sub-region to the second sub-region, the width of the first portions of both the first and second regulating electrodes gradually increases. The second portions of both the first and second regulating electrodes extend along the second sub-region. Along the direction from the third sub-region to the fourth sub-region, the width of the second portion of the first regulating electrode gradually decreases. Along the direction from the fourth sub-region to the third sub-region, the width of the second portion of the second regulating electrode also gradually decreases.

[0023] In some embodiments, the second substrate further includes a seventh connection portion and an eighth connection portion. The seventh connection portion is disposed on the side of the first adjustment electrode away from the first partition electrode. The eighth connection portion is disposed on the side of the second adjustment electrode away from the second partition electrode. The first substrate further includes a fifth pad and a sixth pad. The orthographic projection of the seventh connection portion on the first substrate overlaps with the fifth pad, and the seventh connection portion and the fifth pad are electrically connected through a conductive portion, and the fifth pad is electrically connected to the first partition voltage signal line. The orthographic projection of the eighth connection portion on the first substrate overlaps with the sixth pad, and the eighth connection portion and the sixth pad are electrically connected through a conductive portion, and the sixth pad is electrically connected to the second partition voltage signal line.

[0024] In some embodiments, the widths of the seventh and eighth connecting portions gradually decrease along the direction from the first sub-region to the second sub-region.

[0025] In some embodiments, a first adjustment signal line is located on the side of the first partition voltage signal line away from the first partition electrode, and a fifth pad is located between the first adjustment signal line and the first partition voltage signal line. A second adjustment signal line is located on the side of the second partition voltage signal line away from the second partition electrode, and a sixth pad is located between the second adjustment signal line and the second partition voltage signal line.

[0026] In some embodiments, the first substrate further includes a first shielding line extending along a second direction. The orthographic projection of the first shielding line on the second substrate is located between the first partition electrode and the second partition electrode, and has a gap with both the first partition electrode and the second partition electrode.

[0027] In some embodiments, the first substrate further includes a second shielding line. The second shielding line extends at least along a first sub-region, a third sub-region, and a fourth sub-region, and its two ends extend to a first bonding region and a second bonding region, respectively. One end of the first shielding line is electrically connected to a portion of the second shielding line located within the first sub-region.

[0028] In some embodiments, the first substrate further includes a fifth pattern disposed in the first sub-region. The first substrate includes a gate conductive layer and a source / drain conductive layer stacked together. The second shielding line and the fifth pattern are located in the gate conductive layer, and the fifth pattern is electrically connected to the second shielding line in the same layer. The first shielding line is located in the source / drain conductive layer, and one end of the first shielding line is electrically connected to the fifth pattern through a via.

[0029] In some embodiments, the fifth pattern is located between the first pad and the second pad.

[0030] In some embodiments, the second shielding line is located on the side of the first pad, the second pad, the first partition voltage signal line, and the second partition voltage signal line away from the second electrode.

[0031] In some embodiments, the first substrate further includes a third pad, a fourth pad, a first adjustment signal line, and a second adjustment signal line. A second shielding line is also located on the side of the third pad, the fourth pad, the first adjustment signal line, and the second adjustment signal line away from the second electrode.

[0032] In some embodiments, the first substrate further includes a third shielding line. The third shielding line extends along the second sub-region, and its two ends extend to the first bonding region and the second bonding region, respectively. The other end of the first shielding line is electrically connected to the third shielding line.

[0033] In some embodiments, the first substrate further includes a third partition voltage signal line and a fourth partition voltage signal line located in the second sub-region. The third shielding line is located on the side of the third partition voltage signal line and the fourth partition voltage signal line away from the second electrode.

[0034] In some embodiments, the first substrate further includes a fifth pin, a sixth pin, a seventh pin, and an eighth pin. The fifth pin is disposed in a first bonding region, the sixth pin is disposed in a second bonding region, and both ends of a second shielding wire are electrically connected to the fifth pin and the sixth pin, respectively. The seventh pin is disposed in the first bonding region, the eighth pin is disposed in the second bonding region, and both ends of a third shielding wire are electrically connected to the seventh pin and the eighth pin, respectively. The fifth pin and the seventh pin are arranged at intervals along a first direction, and the fifth pin is further away from the centerline of the dimming panel along the second direction than the seventh pin. The sixth pin and the eighth pin are arranged at intervals along the first direction, and the sixth pin is further away from the centerline of the dimming panel along the second direction than the eighth pin.

[0035] In some embodiments, the first sub-region includes a first bonding area and a second bonding area. The first bonding area is located on one side of the first display area, and the second bonding area is located on one side of the second display area. Both the first partition voltage signal line and the second partition voltage signal line are located in the first sub-region, with the first partition voltage signal line extending to the first bonding area and the second partition voltage signal line extending to the second bonding area.

[0036] The functional area also includes a third display area and a fourth display area arranged side-by-side along a first direction. The first display area, the third display area, the second display area, and the fourth display area are all arranged side-by-side along a second direction. Multiple second electrodes also include third partition electrodes and fourth partition electrodes, with the third partition electrodes located in the third display area and the fourth partition electrodes located in the fourth display area. A third bonding area and a fourth bonding area are provided in the second sub-area. The third bonding area is located on one side of the third display area, and the fourth bonding area is located on one side of the fourth display area. Multiple second voltage signal lines also include third partition voltage signal lines and fourth partition voltage signal lines located in the second sub-area, with the third partition voltage signal lines extending to the third bonding area and the fourth partition voltage signal lines extending to the fourth bonding area. The third partition electrodes are electrically connected to the third partition voltage signal lines via conductive parts, and the fourth partition electrodes are electrically connected to the fourth partition voltage signal lines via conductive parts.

[0037] In some embodiments, the first substrate further includes a first scan line, a second scan line, a third scan line, a fourth scan line, a first fan-out line, a second fan-out line, a third fan-out line, and a fourth fan-out line. The first scan line extends along a first direction within the first display area, and multiple first scan lines are arranged at intervals along a second direction. The second scan line extends along the first direction within the second display area, and multiple second scan lines are arranged at intervals along the second direction; the first scan line and the second scan line are spaced apart in the first direction. The third scan line extends along the first direction within the third display area, and multiple third scan lines are arranged at intervals along the second direction. The fourth scan line extends along the first direction within the fourth display area, and multiple fourth scan lines are arranged at intervals along the second direction; the third scan line and the fourth scan line are spaced apart in the first direction.

[0038] The first sector line is electrically connected to the first scan line, extends along the third sub-region, and extends to the first bonding area. The second sector line is electrically connected to the second scan line, extends along the fourth sub-region, and extends to the second bonding area. The third sector line is electrically connected to the third scan line, extends along the third sub-region, and extends to the third bonding area. The fourth sector line is electrically connected to the fourth scan line, extends along the fourth sub-region, and extends to the fourth bonding area.

[0039] In some embodiments, the second substrate further includes a first regulating electrode, a second regulating electrode, a third regulating electrode, and a fourth regulating electrode. The orthographic projection of the first regulating electrode onto the first substrate covers the first fan-out line. The orthographic projection of the second regulating electrode onto the first substrate covers the second fan-out line. The orthographic projection of the third regulating electrode onto the first substrate covers the third fan-out line. The orthographic projection of the fourth regulating electrode onto the first substrate covers the fourth fan-out line. The voltages of the first, second, third, and fourth regulating electrodes are all configured to switch between a first regulating voltage and a second regulating voltage. The non-operating voltages of the first, second, third, and fourth fan-out lines are all greater than the first regulating voltage and less than the second regulating voltage.

[0040] In some embodiments, the first substrate further includes a first adjustment signal line, a second adjustment signal line, a third adjustment signal line, and a fourth adjustment signal line. The first adjustment signal line extends along a third sub-region and to a first bonding region. A first adjustment electrode is electrically connected to the first adjustment signal line via a conductive portion. The second adjustment signal line extends along a fourth sub-region and to a second bonding region. A second adjustment electrode is electrically connected to the second adjustment signal line via a conductive portion. The third adjustment signal line extends along a third sub-region and to a third bonding region. A third adjustment electrode is electrically connected to the third adjustment signal line via a conductive portion. The fourth adjustment signal line extends along a fourth sub-region and to a fourth bonding region. A fourth adjustment electrode is electrically connected to the fourth adjustment signal line via a conductive portion.

[0041] In some embodiments, the second substrate further includes a ninth connection portion, a tenth connection portion, an eleventh connection portion, and a twelfth connection portion. A first adjustment electrode is electrically connected to the ninth connection portion, and the ninth connection portion is electrically connected to a first adjustment signal line via a conductive portion. A second adjustment electrode is electrically connected to the tenth connection portion, and the tenth connection portion is electrically connected to a second adjustment signal line via a conductive portion. A third adjustment electrode is electrically connected to the eleventh connection portion, and the eleventh connection portion is electrically connected to a third adjustment signal line via a conductive portion. A fourth adjustment electrode is electrically connected to the twelfth connection portion, and the twelfth connection portion is electrically connected to a fourth adjustment signal line via a conductive portion. The ninth and eleventh connection portions are spaced apart along a second direction between the first and third adjustment electrodes. The tenth and twelfth connection portions are spaced apart along a second direction between the second and fourth adjustment electrodes.

[0042] In some embodiments, the first substrate further includes a fourth shielding line and a fifth shielding line. The fourth shielding line extends along a second direction; its orthographic projection on the second substrate lies between the first and second partition electrodes, and between the third and fourth partition electrodes, and is spaced from all three partition electrodes. The fifth shielding line extends along a first direction; its orthographic projection on the second substrate lies between the first and third partition electrodes, and between the second and fourth partition electrodes, and is spaced from all three.

[0043] In some embodiments, the first substrate further includes a sixth shielding line and a seventh shielding line. The sixth shielding line extends at least along a third sub-region, and its two ends extend to a first bonding region and a third bonding region, respectively. The seventh shielding line extends at least along a fourth sub-region, and its two ends extend to a second bonding region and a fourth bonding region, respectively. The two ends of the fifth shielding line are electrically connected to the sixth shielding line and the seventh shielding line, respectively.

[0044] In some embodiments, the dimming panel includes a source-drain conductive layer, and the fifth shielding line, the sixth shielding line, and the seventh shielding line are all located in the source-drain conductive layer.

[0045] In some embodiments, the first substrate further includes an eighth shielding line and a ninth shielding line. The eighth shielding line extends along the first sub-region, and its two ends extend to the first bonding region and the second bonding region, respectively. The ninth shielding line extends along the second sub-region, and its two ends extend to the third bonding region and the fourth bonding region, respectively. The two ends of the fourth shielding line are electrically connected to the eighth shielding line and the ninth shielding line, respectively.

[0046] In some embodiments, the dimming panel includes a gate conductive layer, and the fourth shielding line, the eighth shielding line, and the ninth shielding line are all located in the gate conductive layer.

[0047] In some embodiments, the difference between the first regulated voltage and the non-operating voltage of the first fan-out line is equal to or approximately equal to the difference between the second regulated voltage and the non-operating voltage of the first fan-out line.

[0048] In some embodiments, the switching frequency of the first adjustment voltage and the second adjustment voltage is N times the display frequency of the dimming panel, where N is an integer greater than or equal to 1.

[0049] In some embodiments, the second substrate further includes a black matrix layer having a plurality of openings, wherein at least a portion of a first electrode has its orthographic projection onto the second substrate located within one opening. The black matrix layer includes a first black matrix line, and the orthographic projection of a first shielding line onto the second substrate overlaps with the first black matrix line. The dimming panel is a transmissive display panel, wherein the width of the first shielding line is smaller than the width of the first black matrix line; or, the dimming panel is a transflective display panel, wherein the width of the first shielding line is greater than or equal to the width of the first black matrix line.

[0050] In some embodiments, there are multiple first partition electrodes and multiple second partition electrodes, with multiple first partition electrodes arrayed in a first display area and multiple second partition electrodes arrayed in a second display area. There are multiple first connection portions and multiple second connection portions, which are spaced apart in a peripheral area. The second substrate also includes multiple first transmission lines and multiple second transmission lines. A first partition electrode is electrically connected to a first connection portion via a first transmission line, and a second partition electrode is electrically connected to a second connection portion via a second transmission line. There are multiple first partition voltage signal lines and multiple second partition voltage signal lines. A first connection portion is electrically connected to a first partition voltage signal line via a conductive portion, and a second connection portion is electrically connected to a second partition voltage signal line via a conductive portion. The first partition voltage signal lines are configured to provide, in a time-division multiplexing manner, a first common voltage signal required for display and a touch driving signal required for touch sensing to the corresponding first partition electrode; the second partition voltage signal lines are configured to provide, in a time-division multiplexing manner, a second common voltage signal required for display and a touch driving signal required for touch sensing to the corresponding second partition electrode.

[0051] In some embodiments, the peripheral area includes a first sub-area, a second sub-area, a third sub-area, and a fourth sub-area. The first and second sub-areas are located on opposite sides of the functional area in a second direction, and the third and fourth sub-areas are located on opposite sides of the functional area in the first direction. The first direction is the row direction of the plurality of second electrodes, and the second direction is the column direction of the plurality of second electrodes. A plurality of first connecting portions and a plurality of second connecting portions are disposed in the first sub-area and arranged along the first direction. The second sub-area includes a first binding area and a second binding area. The first binding area is located on one side of the first display area, and the second binding area is located on one side of the second display area. A first partition voltage signal line extends along the third sub-area and extends to the first binding area. A second partition voltage signal line extends along the fourth sub-area and extends to the second binding area.

[0052] In some embodiments, the second substrate further includes a second substrate and a black matrix layer disposed on the substrate, the black matrix layer comprising a plurality of interwoven black matrix lines. The gap between two adjacent second electrodes is located on the side of the black matrix lines away from the second substrate, and the width of the gap is smaller than the width of the black matrix lines.

[0053] In some embodiments, the second substrate further includes a plurality of light-filtering sections and a protective layer. Multiple black matrix lines interweave to form multiple openings, with one light-filtering section located within one opening. The protective layer covers the black matrix layer and the plurality of light-filtering sections on the side away from the second substrate. A plurality of second electrodes are located on the side of the protective layer away from the second substrate.

[0054] In some embodiments, the plurality of first electrodes and the plurality of second electrodes are all strip electrodes, and the orthographic projections of the plurality of second electrodes on the first substrate intersect with the plurality of first electrodes. The second substrate further includes a thirteenth connecting portion and a fourteenth connecting portion, respectively located on both sides of the functional region in a third direction, which is the extending direction of the second electrodes. A portion of the plurality of second electrodes is electrically connected to the thirteenth connecting portion, and another portion of the plurality of second electrodes is electrically connected to the fourteenth connecting portion.

[0055] In some embodiments, the second electrodes in odd-numbered rows are electrically connected to the thirteenth connection portion, and the second electrodes in even-numbered rows are electrically connected to the fourteenth connection portion.

[0056] On the other hand, a display panel is provided. The display panel includes: a dimming panel as described in any of the above embodiments, and at least two driver chips electrically connected to the dimming panel.

[0057] In another aspect, a display device is provided. The display device includes: a display panel as described in any of the above embodiments, and a backlight module disposed on one side of a first substrate of the display panel.

[0058] In another aspect, a liquid crystal lens is provided. The liquid crystal lens includes a dimming panel as described in any of the above embodiments. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0060] Figure 1A is a structural diagram of a dimming panel according to some embodiments;

[0061] Figure 1B is a cross-sectional view of a portion of the dimming panel in Figure 1A along section line C-C';

[0062] Figure 1C is a partial cross-sectional view of the dimming panel in Figure 1A along section line D-D';

[0063] Figure 2 is a structural diagram of a dimming panel according to some other embodiments;

[0064] Figure 3 is a structural diagram of a second substrate according to some other embodiments;

[0065] Figure 4 is a structural diagram of the second substrate according to some other embodiments;

[0066] Figure 5A is a structural diagram of a second substrate according to some other embodiments;

[0067] Figure 5B is a partial structural diagram of the second substrate according to some embodiments;

[0068] Figure 5C is a partial structural diagram of the second substrate according to some other embodiments;

[0069] Figure 5D is a partial structural diagram of the second substrate according to some other embodiments;

[0070] Figure 5E is a partial structural diagram of the second substrate according to some other embodiments;

[0071] Figure 6 is a structural diagram of a first substrate according to some embodiments;

[0072] Figure 7 is a structural diagram of a dimming panel according to some other embodiments;

[0073] Figure 8 is a structural diagram of the first substrate according to some other embodiments;

[0074] Figure 9A is a diagram of the adjusted voltage signal according to some embodiments;

[0075] Figure 9B is a diagram of the adjusted voltage signal according to some other embodiments;

[0076] Figure 10 is a structural diagram of a dimming panel according to some other embodiments;

[0077] Figure 11A is a structural diagram of a dimming panel according to some other embodiments;

[0078] Figure 11B is a partial cross-sectional view of the dimming panel in Figure 11A along section line A-A';

[0079] Figure 12A is a structural diagram of a dimming panel according to some other embodiments;

[0080] Figure 12B is a sectional view of a portion of the dimming panel in Figure 12A along section line B-B'.

[0081] Figure 13A is a structural diagram of a first substrate according to some other embodiments;

[0082] Figure 13B is a structural diagram of the first substrate according to some other embodiments;

[0083] Figure 14 is a structural diagram of the first substrate according to some other embodiments;

[0084] Figure 15A is a structural diagram of a second substrate according to some other embodiments;

[0085] Figure 15B is a structural diagram of a second substrate according to some other embodiments;

[0086] Figure 16 is a structural diagram of a first substrate according to some other embodiments;

[0087] Figure 17 is a structural diagram of a second substrate according to some other embodiments;

[0088] Figure 18 is a structural diagram of a first substrate according to some other embodiments;

[0089] Figure 19 is a structural diagram of a mask template according to some embodiments;

[0090] Figure 20 is a structural diagram of a dimming panel according to some other embodiments;

[0091] Figure 21 is a structural diagram of a first substrate according to some other embodiments;

[0092] Figure 22A is a structural diagram of a first substrate according to some other embodiments;

[0093] Figure 22B is a structural diagram of a first substrate according to some other embodiments. Detailed Implementation

[0094] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0095] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0096] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0097] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0098] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0099] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0100] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0101] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0102] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0103] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0104] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0105] As shown in Figures 1A-1C and 12A-12B, in some embodiments, the dimming panel 1000 includes a functional area AA and a peripheral area BB surrounding the functional area AA. The dimming panel 1000 includes a first substrate 100 and a second substrate 200. The first substrate 100 includes a plurality of first electrodes 110 disposed in the functional area AA. The second substrate 200 is disposed opposite to the first substrate 100 and includes a second electrode 210 disposed in the functional area AA.

[0106] For example, when the dimming panel 1000 is applied in a display device, the functional area AA can be a display area, the first substrate 100 can be an array substrate, the first electrode 110 can be a pixel electrode, and the second substrate 200 can be a color filter substrate.

[0107] In some examples, as shown in FIG1B, the first substrate 100 further includes a first substrate 100C, and a plurality of first electrodes 110 are disposed on the side of the first substrate 100C near the second substrate 200. For example, the plurality of first electrodes 110 are arrayed on the side of the first substrate 100C near the second substrate 200.

[0108] In some examples, as shown in FIG1C, the second substrate 200 further includes a second substrate 200C, and the second electrode 210 is disposed on the side of the second substrate 200C near the first substrate 100.

[0109] For example, the first substrate 100C and the second substrate 200C may be made of the same material, such as glass, but they may also be different, and this disclosure does not limit this.

[0110] For example, the materials of the first electrode 110 and the second electrode 210 are the same, for example, both are indium tin oxide (ITO) or indium zinc oxide (IZO), but of course they can be different, and this disclosure does not limit them.

[0111] In some embodiments, as shown in Figures 1B and 1C, a liquid crystal layer 400 is filled between the first substrate 100 and the second substrate 200. As shown in Figure 2, the dimming panel 1000 further includes a sealing structure 300 disposed around the liquid crystal layer 400. The sealing structure 300 is used to align the first substrate 100 and the second substrate 200 and to prevent liquid crystal molecules in the liquid crystal layer 400 from flowing out of the dimming panel 1000. The material of the sealing structure 300 is, for example, a sealant.

[0112] The aforementioned liquid crystal layer 400 comprises liquid crystal molecules. Liquid crystal molecules belong to the category of single-optical-axis crystals, possessing only one optical axis. Here, the optical axis, also known as the optic axis, is the direction in which two orthogonal waves have equal propagation velocities when light propagates within the crystal; light in this direction does not exhibit any change in optical properties. For example, anisotropic crystals exhibit birefringence for light propagating within them; however, when light propagates along the optical axis of the anisotropic crystal, birefringence does not occur. Therefore, the optical axis of anisotropic crystals can also be defined as the direction in which light can propagate without birefringence. Furthermore, anisotropic crystals can be further classified into single-optical-axis crystals and dual-optical-axis crystals. Single-optical-axis crystals have only one optical axis, while dual-optical-axis crystals have two optical axes.

[0113] Liquid crystal molecules can be classified into rod-type and disc-type liquid crystal molecules based on their shape. In rod-type liquid crystal molecules, the long axis is aligned with the optical axis; in disc-type liquid crystal molecules, the short axis is aligned with the optical axis. In a three-dimensional coordinate system, a material with at least two different refractive indices along the three coordinate axes is called a birefringent material, and liquid crystal molecules are all birefringent materials.

[0114] In some examples, the first substrate 100 further includes pixel driving circuits, each pixel driving circuit being electrically connected to a first electrode 110, and the pixel driving circuits being configured to at least provide a voltage signal to the first electrode 110.

[0115] In some embodiments, as shown in FIG6, the first substrate 100 further includes a source / drain conductive layer 100B and a gate conductive layer 100A disposed between the first substrate 100C and the layer containing the first electrode 110. The source / drain conductive layer 100B and the gate conductive layer 100A form a plurality of pixel driving circuits electrically connected to the plurality of first electrodes 110. Exemplarily, the gate conductive layer 100A is closer to the first substrate 100C than the source / drain conductive layer 100B.

[0116] In some embodiments, the gate conductive layer 100A includes a plurality of scan lines 160 spaced apart along the column direction of the plurality of first electrodes 110, the scan lines 160 being configured to turn on or off a plurality of pixels arranged along the row direction of the plurality of first electrodes 110.

[0117] Based on the above structure, the pixel driving circuit, the first electrode 110, and the second electrode 210 can be used to drive the rotation of liquid crystal molecules at corresponding positions in the liquid crystal layer 400 based on the driving signal. That is, the pixel driving circuit, the first electrode 110, and the second electrode 210 can be used to apply an electric field to the liquid crystal layer 400 based on the driving signal. The different rotation states of the liquid crystal molecules corresponding to different pixels can transmit light with different polarization states to achieve the effect of light modulation.

[0118] In some examples, a first alignment film (not shown) is disposed between the liquid crystal layer 400 and the layer containing the first electrode 110. The first alignment film is configured to anchor liquid crystal molecules in the liquid crystal layer 400 that are close to it, causing the liquid crystal molecules close to the first alignment film to generate a first pretilt angle. A second alignment film (not shown) is disposed between the liquid crystal layer 400 and the layer containing the second electrode 210. The second alignment film is configured to anchor liquid crystal molecules in the liquid crystal layer 400 that are close to it, causing the liquid crystal molecules close to the second alignment film to generate a second pretilt angle according to the second pretilt angle. The alignment direction of the first alignment film is, for example, perpendicular to the alignment direction of the second alignment film. The pretilt angle allows the liquid crystal molecules to be in a pre-tilted state, meaning that the liquid crystal molecules near the alignment film are tilted in a specific direction relative to the plane containing the alignment film.

[0119] In some implementations, referring to FIG1B and as shown in FIG3, the second electrode 210 included in the second substrate 200 is an electrode that is fully connected (e.g., an ITO electrode), which prevents the liquid crystal molecules in the liquid crystal layer 400 from being controlled by partitions, thus enabling the functional partitioning of the dimming panel 1000. For example, when the dimming panel 1000 is applied to an LCD (Liquid Crystal Display) (e.g., a TN-type LCD), since the second electrode 210 included in the second substrate 200 is an electrode that is fully connected, the LCD cannot perform partitioned display.

[0120] Based on this, some embodiments of this disclosure provide a dimming panel 1000. Referring to FIG2, and as shown in FIG5A-5E and FIG6, the dimming panel 1000 further includes a plurality of conductive portions 310. The second substrate 200 includes a plurality of second electrodes 210, which are disposed in functional area AA. The orthographic projection of one second electrode 210 on the first substrate 100 overlaps with at least one first electrode 110, and the plurality of second electrodes 210 are independently disposed. The plurality of conductive portions 310 are disposed between the first substrate 100 and the second substrate 200, and are located in peripheral area BB. The first substrate 100 also includes a plurality of second voltage signal lines 120 disposed in peripheral area BB; one second electrode 210 is electrically connected to one second voltage signal line 120 through at least one conductive portion 310, and the plurality of second voltage signal lines 120 are configured to provide a second voltage signal to their respective corresponding second electrode 210 relatively independently.

[0121] As exemplarily shown in FIG2, a plurality of conductive parts 310 are disposed inside the sealing structure 300. The conductive parts 310 are, for example, gold balls.

[0122] In some examples, a second electrode 210 is electrically connected to a second voltage signal line 120 via a conductive part 310; in other examples, as shown in FIG2, a second electrode 210 is electrically connected to a second voltage signal line 120 via multiple conductive parts 310 (e.g., two), thereby improving the reliability of the electrical connection between the second electrode 210 and the second voltage signal line 120 and improving the transmission stability of the signal from the second electrode 210.

[0123] For example, among the plurality of second electrodes 210, the spacing between two adjacent second electrodes 210 is greater than 30 μm, such as 31 μm, 34 μm, 37 μm, 40 μm, 42 μm or 50 μm.

[0124] When the orthographic projection of a second electrode 210 on the first substrate 100 overlaps with at least one first electrode 110, the second electrode 210 and the at least one first electrode 110 are arranged opposite each other along the thickness direction of the dimming panel 1000. In this way, by controlling the voltage on the second electrode 210 and the plurality of first electrodes 110 respectively, an electric field can be formed to drive the liquid crystal molecules located between the second electrode 210 and the plurality of first electrodes 110 to rotate to a set angle, thereby realizing the control of the rotation of the liquid crystal molecules at the position corresponding to the second electrode 210.

[0125] For example, the voltage signal transmitted from the second voltage signal line 120 to the second electrode 210 includes at least the second common voltage signal required to drive the liquid crystal molecules.

[0126] Understandably, when multiple second electrodes 210 are independently arranged and multiple second voltage signal lines 120 are configured to provide second voltage signals to their respective corresponding second electrodes 210 relatively independently, the liquid crystal molecules at the corresponding positions of each second electrode 210 can rotate under the control of the corresponding second voltage signal. Moreover, the rotation of the liquid crystal molecules at the corresponding positions of multiple second electrodes 210 can be different. In this way, it is possible to achieve zoned control of the liquid crystal molecules in the liquid crystal layer 400, thereby realizing the functional zoning of the dimming panel 1000. For example, when the dimming panel 1000 is applied to an LCD, it enables the LCD to display in zones.

[0127] The following description will be based on an example of a second substrate 200 including two second electrodes 210.

[0128] Figure 6 is a structural diagram of the first substrate 100 according to some embodiments. It should be noted that Figure 6 includes six partially enlarged substructure diagrams, and these six substructure diagrams are arranged according to their relative positions on the first substrate 100. For example, the first substructure diagram located in the upper right corner corresponds to the structural diagram of the portion of the first substrate 100 located near the corner of the first sub-region BB1 and the third sub-region BB3. The meanings of the first sub-region BB1 and the third sub-region BB3 can be found in the following description.

[0129] In some embodiments, as shown in Figures 2, 5A-5E, and 6, the functional area AA includes a first display area AA1 and a second display area AA2. A plurality of second electrodes 210 include a first partition electrode 211 and a second partition electrode 212, with the first partition electrode 211 disposed in the first display area AA1 and the second partition electrode 212 disposed in the second display area AA2. A plurality of conductive portions 310 include a first conductive portion 311 and a second conductive portion 312. A plurality of second voltage signal lines 120 include a first partition voltage signal line 121 and a second partition voltage signal line 122, with the first conductive portion 311 electrically connected to the first partition voltage signal line 121 and the second conductive portion 312 electrically connected to the second partition voltage signal line 122. The second substrate 200 also includes a first connecting portion 2201 and a second connecting portion 2202. The first connecting portion 2201 is disposed on one side of the first partition electrode 211 and is electrically connected to both the first partition electrode 211 and the first conductive portion 311. The second connection part 2202 is provided on one side of the second partition electrode 212 and is electrically connected to the second partition electrode 212 and also electrically connected to the second conductive part 312.

[0130] For example, the first connecting part 2201 and the second connecting part 2202 are disposed in the same layer as the second electrode 210.

[0131] Here, there are no further limitations on the placement of the first connecting part 2201 and the second connecting part 2202. In some examples, the first connecting part 2201 and the second connecting part 2202 are located in functional area AA. In still other examples, the first connecting part 2201 and the second connecting part 2202 are located in peripheral area BB.

[0132] With the above configuration, the first partition electrode 211 and the first conductive part 311 can be electrically connected through the first connecting part 2201, and the second partition electrode 212 and the second conductive part 312 can be electrically connected through the second connecting part 2202. In this way, the first partition voltage signal line 121 can be electrically connected to the first partition electrode 211 at least through the first conductive part 311 and the first connecting part 2201; the second partition voltage signal line 122 can be electrically connected to the second partition electrode 212 at least through the second conductive part 312 and the second connecting part 2202, so that the first partition voltage signal line 121 and the second partition voltage signal line 122 provide second voltage signals to the first partition electrode 211 and the second partition electrode 212 relatively independently, so that the second voltage signals of the first partition electrode 211 and the second partition electrode 212 can be different.

[0133] In some examples, the first partition voltage signal line 121 is electrically connected to the first conductive part 311 through electrical contact, and the second partition voltage signal line 122 is electrically connected to the second conductive part 312 through electrical contact.

[0134] In some other examples, other film layers (e.g., the layer where the first partition voltage signal line 121 and the second partition voltage line are located, such as the gate conductive layer 100A) are provided between the ends of the first conductive portion 311 and the second conductive portion 312 that are away from the second substrate 200, so that the first partition voltage signal line 121 and the first conductive portion 311, and the second partition voltage signal line 122 and the second conductive portion 312 cannot directly contact each other.

[0135] Therefore, in some embodiments, as shown in Figures 5A, 6, and 7, the first substrate 100 further includes a first pad 1301 and a second pad 1302. The orthographic projection of the first connecting portion 2201 onto the first substrate 100 overlaps with the first pad 1301. A first conductive portion 311 is located between the first connecting portion 2201 and the first pad 1301, and is electrically connected to the first pad 1301. The first pad 1301 is electrically connected to the first partition voltage signal line 121. The orthographic projection of the second connecting portion 2202 onto the first substrate 100 overlaps with the second pad 1302. A second conductive portion 312 is located between the second connecting portion 2202 and the second pad 1302, and is electrically connected to the second pad 1302. The second pad 1302 is electrically connected to the second partition voltage signal line 122.

[0136] For example, the spacing between the first pad 1301 and the second pad 1302 is greater than 30 μm, such as 31 μm, 34 μm, 37 μm, 40 μm, 42 μm or 49 μm.

[0137] For example, as shown in FIG6, the first pad 1301 and the second pad 1302 are disposed in the same layer as the first electrode 110, and the material of both is ITO.

[0138] With the above configuration, the first conductive part 311 and the first partition voltage signal line 121 can be electrically connected through the first pad 1301, and the second conductive part 312 and the second partition voltage signal line 122 can be electrically connected through the second pad 1302. In this way, the transmission of the first partition voltage signal between the first partition voltage signal line 121 and the first conductive part 311 can be realized, and the transmission of the second partition voltage signal between the second partition voltage signal line 122 and the second conductive part 312 can be realized. Moreover, the first partition voltage signal and the second partition voltage signal can be transmitted relatively independently.

[0139] It should be understood that, as shown in Figures 2 and 6, when the first conductive part 311 is located between the first connecting part 2201 and the first pad 1301, and the second conductive part 312 is located between the second connecting part 2202 and the second pad 1302, the first pad 1301 and the second pad 1302 are located in the peripheral area BB.

[0140] In some examples, in the peripheral area BB of the dimming panel 1000, the first pad 1301 is in vertical contact with at least a portion of the first zone voltage signal line 121, and the second pad 1302 is in vertical contact with at least a portion of the second zone voltage signal line 122.

[0141] In some other examples, the first pad 1301 is located in a sub-region of the peripheral area BB (e.g., the first sub-region BB1 described in detail below), and the first partition voltage signal line 121 is located in another sub-region of the peripheral area BB (e.g., the third sub-region BB3 described in detail below), so that the first pad 1301 and the first partition voltage signal line 121 cannot make contact. Similarly, the second pad 1302 is located in a sub-region of the peripheral area BB (e.g., the first sub-region BB1 described in detail below), and the second partition voltage signal line 122 is located in another sub-region of the peripheral area BB (e.g., the fourth sub-region BB4 described in detail below), so that the second pad 1302 and the second partition voltage signal line 122 cannot make contact.

[0142] Therefore, in some embodiments, as shown in FIG6, the first substrate 100 further includes a first pattern 141 and a second pattern 142. The first pattern 141 is disposed below the first pad 1301 and electrically connected to the first pad 1301; the first pattern 141 is also electrically connected to the first partition voltage signal line 121. The second pattern 142 is disposed below the second pad 1302 and electrically connected to the second pad 1302; the second pattern 142 is also electrically connected to the second partition voltage signal line 122.

[0143] For example, as shown in FIG6, the first pattern 141 and / or the second pattern 142 are mesh patterns.

[0144] For example, as shown in FIG6, the first pattern 141, the second pattern 142, the first partition voltage signal line 121 and the second partition voltage signal line 122 are disposed on the same layer, for example, all located in the gate conductive layer 100A.

[0145] In some examples, as shown in Figure 6, the first pattern 141 and the second pattern 142 are located in the peripheral area BB and below the sealing structure 300 (see Figure 2).

[0146] With the above configuration, on the one hand, the first gasket 1301 and the first partition voltage signal line 121 can be electrically connected through the first pattern 141, and the second gasket 1302 and the second partition voltage signal line 122 can be electrically connected through the second pattern 142. Moreover, the first partition voltage signal and the second partition voltage signal can be transmitted relatively independently. On the other hand, when the first pattern 141 and the second pattern 142 are located below the sealing structure 300, the adhesive material may be photocured in the preparation method of the sealing structure 300. With the above configuration, both the first pattern 141 and the second pattern 142 are patterned structures, which allows light in the photocuring process to pass through the first pattern 141 and the second pattern 142. Thus, the process feasibility of forming the sealing structure 300 can be improved.

[0147] In some embodiments, as shown in FIG5A, the peripheral area BB includes a first sub-area BB1, a second sub-area BB2, a third sub-area BB3, and a fourth sub-area BB4. The first sub-area BB1 and the second sub-area BB2 are located on opposite sides of the functional area AA in the second direction Y, and the third sub-area BB3 and the fourth sub-area BB4 are located on opposite sides of the functional area AA in the first direction X. The first direction X is the arrangement direction of the first partition electrode 211 and the second partition electrode 212, and the first direction X intersects the second direction Y. The first connecting portion 2201 and the second connecting portion 2202 are both located in the first sub-area BB1.

[0148] For example, the first direction X is perpendicular to the second direction Y.

[0149] For example, the first connecting portion 2201 has a dimension greater than 100 μm in the second direction Y, such as 101 μm, 110 μm, 120 μm, 130 μm, or 140 μm. For example, the second connecting portion 2202 has a dimension greater than 100 μm in the second direction Y, such as 102 μm, 110 μm, 125 μm, 130 μm, or 150 μm.

[0150] In some examples, the source / drain conductor layer includes data lines, and fan-out lines connected to the data lines are arranged in the second sub-region BB2.

[0151] In some examples, the size of function area AA along the first direction X is greater than the size of function area AA along the second direction Y.

[0152] With this configuration, the areas of the first connecting part 2201 and the second connecting part 2202 can be larger, which is beneficial to the stable transmission of the first partition voltage signal and the second partition voltage signal, and makes the uniformity of the second voltage signal better and the attenuation less.

[0153] In some examples, the first connecting portion 2201 and the first partition electrode 211 are not integrally formed, and the second connecting portion 2202 and the second partition electrode 212 are not integrally formed, so that the first connecting portion 2201 and the first partition electrode 211 are formed in different steps, and the second connecting portion 2202 and the second partition electrode 212 are formed in different steps.

[0154] In some embodiments, as shown in FIG5A, the first connecting portion 2201, the second connecting portion 2202, the first partition electrode 211, and the second partition electrode 212 are made of the same material. The first connecting portion 2201 is integrally disposed with the first partition electrode 211 and extends along the side of the first partition electrode 211 to which it is located. The second connecting portion 2202 is integrally disposed with the second partition electrode 212 and extends along the side of the second partition electrode 212 to which it is located.

[0155] With the above configuration, on the one hand, the first connecting portion 2201 and the first partition electrode 211 can be formed in the same step, and the second connecting portion 2202 and the second partition electrode 212 can be formed in the same step. This simplifies the process of forming the first connecting portion 2201, the first partition electrode 211, the second connecting portion 2202, and the second partition electrode 212. On the other hand, when the first connecting portion 2201 extends along the side of the first partition electrode 211 where it is located, and the second connecting portion 2202 extends along the side of the second partition electrode 212 where it is located, the area of ​​the first connecting portion 2201 and the second connecting portion 2202 can be larger. As mentioned above, this can improve the transmission stability of the first partition voltage signal and the second partition voltage signal, making the second voltage signal more uniform and less attenuated.

[0156] In some examples, along the first direction X, the distance between the first connecting portion 2201 and the second connecting portion 2202 is equal to the distance between the first partition electrode 211 and the second partition electrode 212.

[0157] In some embodiments, as shown in FIG5C, along the first direction X, the distance D2 between the first connecting portion 2201 and the second connecting portion 2202 is greater than the distance D1 between the first partition electrode 211 and the second partition electrode 212.

[0158] Understandably, when the distance D2 between the first connecting portion 2201 and the second connecting portion 2202 is small, there is a certain coupling effect between them, which may cause crosstalk between the first partition voltage signal and the second partition voltage signal. Furthermore, when the distance D1 between the first partition electrode 211 and the second partition electrode 212 is large, there may be a noticeable display interface between the first display area AA1 and the second display area AA2, which may affect the display effect. Therefore, through the above arrangement, at least at the gap between the first connecting portion 2201 and the second connecting portion 2202, the distance between the first partition electrode 211 and the second partition electrode 212 can be made larger. This reduces the coupling effect between the first partition electrode 211 and the second partition electrode 212, weakening the mutual influence between the first partition voltage signal and the second partition voltage signal.

[0159] The arrangement of the first partition voltage signal line 121 and the second partition voltage signal line 122 in this embodiment is not limited, as long as the first partition voltage signal and the second partition voltage signal can be transmitted to the first partition electrode 211 and the second partition electrode 212 respectively.

[0160] In some embodiments, as shown in FIG6, the second sub-region BB2 is provided with a first binding area CC1 and a second binding area CC2. The first binding area CC1 is located on one side of the first display area AA1, and the second binding area CC2 is located on one side of the second display area AA2. The first partition voltage signal line 121 extends along the third sub-region BB3 and extends to the first binding area CC1. The second partition voltage signal line 122 extends along the fourth sub-region BB4 and extends to the second binding area CC2.

[0161] With the above settings, on the one hand, the spatial positions of the first partition voltage signal line 121, the second partition voltage signal line 122, the first binding area CC1, and the second binding area CC2 can be optimized, making the size of the dimming panel 1000 smaller; on the other hand, the first partition voltage signal line 121 and the second partition voltage signal line 122 can be arranged along both sides of the functional area AA, reducing the mutual influence between the first partition voltage signal and the second partition voltage signal.

[0162] In some examples, the first partition voltage signal is transmitted to the first partition electrode 211 only through the first partition voltage signal line 121, the first conductive part 311, and the first connection part 2201; the second partition voltage signal is transmitted to the second partition electrode 212 only through the second partition voltage signal line 122, the second conductive part 312, and the second connection part 2202, so that the second voltage signal on the second electrode 210 (the first partition electrode 211 and / or the second partition electrode 212) is attenuated.

[0163] Therefore, in some embodiments, as shown in Figures 5A and 6, the second substrate 200 further includes a third connection portion 2203 and a fourth connection portion 2204 located in the second sub-region BB2. The third connection portion 2203 is located on one side of the first partition electrode 211 and is electrically connected to the first partition electrode 211, and the fourth connection portion 2204 is located on one side of the second partition electrode 212 and is electrically connected to the second partition electrode 212. The plurality of conductive portions 310 also include a third conductive portion 313 and a fourth conductive portion 314 located in the second sub-region BB2. The third connection portion 2203 is electrically connected to the third conductive portion 313, and the fourth connection portion 2204 is electrically connected to the fourth conductive portion 314. The plurality of second voltage signal lines 120 also include a third partition voltage signal line 123 and a fourth partition voltage signal line 124 located in the second sub-region BB2. The third partition voltage signal line 123 extends to the first bonding region CC1, and the fourth partition voltage signal line 124 extends to the second bonding region CC2. The third conductive part 313 is electrically connected to the third partition voltage signal line 123, and the fourth conductive part 314 is electrically connected to the fourth partition voltage signal line 124.

[0164] For example, as shown in FIG5A, the third connecting part 2203 and the fourth connecting part 2204 are disposed in the same layer as the second electrode 210.

[0165] For example, the dimension of the third connecting portion 2203 in the second direction Y is greater than 100 μm, such as 101 μm, 110 μm, 120 μm, 130 μm, or 145 μm. For example, the dimension of the fourth connecting portion 2204 in the second direction Y is greater than 100 μm, such as 103 μm, 110 μm, 125 μm, 130 μm, or 150 μm.

[0166] With the above configuration, the first partition voltage signal can be transmitted to the first partition electrode 211 not only through the first partition voltage signal line 121, the first conductive part 311, and the first connecting part 2201, but also through the third partition voltage signal line 123, the third conductive part 313, and the third connecting part 2203. Similarly, the second partition voltage signal can be transmitted to the second partition electrode 212 not only through the second partition voltage signal line 122, the second conductive part 312, and the second connecting part 2202, but also through the fourth partition voltage signal line 124, the fourth conductive part 314, and the fourth connecting part 2204. In other words, the second voltage signal can be simultaneously accessed on both sides of the second electrode 210 in the second direction Y, which can reduce signal attenuation and improve the uniformity of the transmission of the second voltage signal on the second electrode 210.

[0167] In some embodiments, as shown in Figures 6 and 7, the first substrate 100 further includes a seventh pad 1307 and an eighth pad 1308. The orthographic projection of the third connection portion 2203 onto the first substrate 100 overlaps with the seventh pad 1307. A third conductive portion 313 is located between the third connection portion 2203 and the seventh pad 1307, and is electrically connected to the seventh pad 1307. The seventh pad 1307 is electrically connected to the third partition voltage signal line 123. The orthographic projection of the fourth connection portion 2204 onto the first substrate 100 overlaps with the eighth pad 1308. A fourth conductive portion 314 is located between the fourth connection portion 2204 and the eighth pad 1308, and is electrically connected to the eighth pad 1308. The eighth pad 1308 is electrically connected to the fourth partition voltage signal line 124.

[0168] For example, as shown in FIG6, the seventh pad 1307 and the eighth pad 1308 are disposed in the same layer as the first electrode 110, and the material of both is ITO.

[0169] With the above configuration, the third conductive part 313 and the third partition voltage signal line 123 can be electrically connected through the seventh pad 1307, and the fourth conductive part 314 and the fourth partition voltage signal line 124 can be electrically connected through the eighth pad 1308. Moreover, the third partition voltage signal and the fourth partition voltage signal can be transmitted relatively independently.

[0170] In some embodiments, as shown in FIG5A, the third connecting portion 2203, the fourth connecting portion 2204, the first partition electrode 211, and the second partition electrode 212 are made of the same material. The third connecting portion 2203 is integrally disposed with the first partition electrode 211 and extends along the side of the first partition electrode 211 to which it is located. The fourth connecting portion 2204 is integrally disposed with the second partition electrode 212 and extends along the side of the second partition electrode 212 to which it is located.

[0171] Similar to the aforementioned first connecting portion 2201 and second connecting portion 2202, the above-mentioned arrangement simplifies the process of forming the third connecting portion 2203, the first partition electrode 211, the fourth connecting portion 2204, and the second partition electrode 212. Furthermore, it allows for a larger area for the third connecting portion 2203 and the fourth connecting portion 2204, thereby improving the transmission stability of the first partition voltage signal and the second partition voltage signal, resulting in better uniformity and less attenuation of the second voltage signal.

[0172] In some examples, along the first direction X, the distance D3 between the third connecting portion 2203 and the fourth connecting portion 2204 is equal to the distance D1 between the first partition electrode 211 and the second partition electrode 212.

[0173] In some embodiments, as shown in FIG5D, along the second direction Y, the distance D3 between the third connecting portion 2203 and the fourth connecting portion 2204 is greater than the distance D1 between the first partition electrode 211 and the second partition electrode 212.

[0174] Similar to the aforementioned first connecting portion 2201 and second connecting portion 2202, the above arrangement can make the distance between the first partition electrode 211 and the second partition electrode 212 larger, at least in the gap between the third connecting portion 2203 and the fourth connecting portion 2204. In this way, the coupling effect between the first partition electrode 211 and the second partition electrode 212 can be reduced, and the mutual influence between the first partition voltage signal and the second partition voltage signal can be weakened.

[0175] The following provides examples illustrating the pin configurations connected to the first partition voltage signal line 121, the second partition voltage signal line 122, the third partition voltage signal line 123, and the fourth partition voltage signal line 124.

[0176] In some embodiments, as shown in FIG6, the first substrate 100 further includes a first pin 151, a second pin 152, a third pin 153, and a fourth pin 154. The first pin 151 and the third pin 153 are located in a first bonding region CC1 and are spaced apart along a first direction X. The first pin 151 is further away from the centerline of the dimming panel 1000 along the second direction Y than the third pin 153. A first partition voltage signal line 121 is electrically connected to the first pin 151, and a third partition voltage signal line 123 is electrically connected to the third pin 153. The second pin 152 and the fourth pin 154 are located in a second bonding region CC2 and are spaced apart along the first direction X. The second pin 152 is further away from the centerline of the dimming panel 1000 along the second direction Y than the fourth pin 154. A second partition voltage signal line 122 is electrically connected to the second pin 152, and a fourth partition voltage signal line 124 is electrically connected to the fourth pin 154.

[0177] For example, the first pin 151, the second pin 152, the third pin 153 and the fourth pin 154 can be pins of an integrated circuit (IC) or pins of a flexible printed circuit board (FPC).

[0178] For example, the first pin 151 and the third pin 153 are configured to transmit the first partition voltage signal to the first partition voltage signal line 121 and the third partition voltage signal line 123, respectively; the second pin 152 and the fourth pin 154 are configured to transmit the second partition voltage signal to the second partition voltage signal line 122 and the fourth partition voltage signal line 124, respectively.

[0179] For example, the number of any one of the first pin 151, the second pin 152, the third pin 153, and the fourth pin 154 can be one or more. For instance, as shown in Figure 6, the number of the first pin 151 and the third pin 153 are both three, while the number of the second pin 152 and the fourth pin 154 are both multiple. This improves the transmission stability of the first partition voltage signal and the second partition voltage signal.

[0180] For example, the first pin 151, the second pin 152, the third pin 153 and the fourth pin 154 are arranged side by side.

[0181] For example, the first pin 151 and the second pin 152 are symmetrically arranged, and the third pin 153 and the fourth pin 154 are symmetrically arranged.

[0182] With the above settings, the first pin 151 can be closer to the first partition voltage signal line 121, the second pin 152 can be closer to the second partition voltage signal line 122, the third pin 153 can be closer to the third partition voltage signal line 123, and the fourth pin 154 can be closer to the fourth partition voltage signal line 124. In this way, the spatial position of the second voltage signal line 120 and the pins electrically connected to it is optimized, and the size of the peripheral area BB can be smaller.

[0183] In some embodiments, as shown in FIG8, the first substrate 100 further includes a first scan line 161, a second scan line 162, a first fan-out line 171, and a second fan-out line 172. The first scan line 161 extends along a first direction X within the first display area AA1, and multiple first scan lines 161 are spaced apart along a second direction Y. The second scan line 162 extends along the first direction X within the second display area AA2, and multiple second scan lines 162 are spaced apart along the second direction Y. The first scan line 161 and the second scan line 162 are spaced apart along the first direction X. The first fan-out line 171 is electrically connected to the first scan line 161, extends along a third sub-region BB3, and extends to a first bonding area CC1. The second fan-out line 172 is electrically connected to the second scan line 162, extends along a fourth sub-region BB4, and extends to a second bonding area CC2.

[0184] It should be noted that Figure 8 omits the structure of the first substrate 100 other than the first scan line 161, the second scan line 162, the first fan-out line 171, and the second fan-out line 172.

[0185] For example, the first scan line 161, the second scan line 162, the first fan-out line 171, and the second fan-out line 172 are located in the gate conductive layer 100A.

[0186] With the first scan line 161 and the second scan line 162 spaced apart in the first direction X, and the first fan-out line 171 extending to the first binding area CC1 and the second fan-out line 172 extending to the second binding area CC2, the signals transmitted by the first scan line 161 and the second scan line 162 may be different, so that the pixels of the first display area AA1 and the pixels of the second display area AA2 can be controlled relatively independently.

[0187] In some implementations, as shown in Figures 8 and 9A, the non-operating voltage V3 on the first fan-out line 171 and the second fan-out line 172 is relatively high. This causes impurity ions in the liquid crystal layer 400 located on one side of the first fan-out line 171 and the second fan-out line 172 to be adsorbed onto the substrate on one side due to the high voltage, resulting in polarization of the liquid crystal molecules. Consequently, the edges of the functional area AA (i.e., the display area) flicker or exhibit edge whitening. Furthermore, the distribution density of the first fan-out line 171 in the third sub-region BB3 and the distribution density of the second fan-out line 172 in the fourth sub-region BB4 are relatively high. Even when the polarization of the liquid crystal molecules is reduced by setting a conductor layer between the first fan-out line 171 and the second fan-out line 172 and the liquid crystal layer 400, coupling may occur between the conductor layer and the first fan-out line 171, and between the conductor layer and the second fan-out line 172, potentially affecting the transmission of voltage signals.

[0188] In some embodiments, as shown in Figures 5A, 8, and 9A, the second substrate 200 further includes a first regulating electrode 231 and a second regulating electrode 232. The orthographic projection of the first regulating electrode 231 onto the first substrate 100 covers the first fan-out line 171. The orthographic projection of the second regulating electrode 232 onto the first substrate 100 covers the second fan-out line 172. The voltages of both the first regulating electrode 231 and the second regulating electrode 232 are configured to switch between a first regulating voltage V1 and a second regulating voltage V2. The non-operating voltage V3 of both the first fan-out line 171 and the second fan-out line 172 is greater than the first regulating voltage V1 and less than the second regulating voltage V2.

[0189] For example, as shown in FIG5A, the first adjustment electrode 231 and the second adjustment electrode 232 are disposed in the same layer as the plurality of second electrodes 210 and are made of the same material, such as ITO.

[0190] Here, the non-operating voltage V3 of the first fan-out line 171 refers to the voltage transmitted by the first fan-out line 171 during periods other than the period for transmitting the scan voltage. In some examples, the scan voltage of the first fan-out line 171 is used to turn off the transistors in the pixel driving circuit, and can also be referred to as VGH; the non-operating voltage V3 of the first fan-out line 171 is used to turn on the transistors in the pixel driving circuit, and can also be referred to as VGL. For an understanding of the non-operating voltage V3 of the second fan-out line 172, please refer to the above description, which will not be repeated here.

[0191] When the non-working voltage V3 of the first fan-out line 171 and the second fan-out line 172 is greater than the first regulating voltage V1 and less than the second regulating voltage V2, the absolute value of the voltage difference between the non-working voltage V3 of the first fan-out line 171 and the second fan-out line 172 and the first regulating voltage V1, and the absolute value of the voltage difference between the non-working voltage V3 of the first fan-out line 171 and the second fan-out line 172 and the second regulating voltage V2, are both less than the absolute value of the non-working voltage V3 of the first fan-out line 171 and the second fan-out line 172. In this way, the voltage acting on the liquid crystal molecules can be lower, which can reduce the polarization degree of the liquid crystal molecules located on the side of the first fan-out line 171 and the second fan-out line 172, and avoid flickering or edge whitening of the functional area AA (i.e., the display area).

[0192] In some examples, the difference between the first regulated voltage V1 and the non-operating voltage V3 of the first fan-out line 171 is greater than the difference between the second regulated voltage V2 and the non-operating voltage V3 of the first fan-out line 171. In still other examples, the difference between the first regulated voltage V1 and the non-operating voltage V3 of the first fan-out line 171 is less than the difference between the second regulated voltage V2 and the non-operating voltage V3 of the first fan-out line 171.

[0193] In this case, the voltage applied to the liquid crystal molecules when the voltage of the first regulating electrode 231 and the second regulating electrode 232 is the first regulating voltage V1 is different from the voltage applied to the liquid crystal molecules when the voltage of the first regulating electrode 231 and the second regulating electrode 232 is the second regulating voltage V2. This makes the polarization state of the liquid crystal molecules when the voltage of the first regulating electrode 231 and the second regulating electrode 232 is the same as the polarization state of the liquid crystal molecules when the voltage of the first regulating electrode 231 and the second regulating electrode 232 is the second regulating voltage V2. At this time, the effect of the first regulating electrode 231 and the second regulating electrode 232 in reducing the polarization degree of the liquid crystal molecules is relatively poor.

[0194] Therefore, in some embodiments, in conjunction with FIG8, as shown in FIG9A and FIG9B, the difference between the first regulating voltage V1 and the non-working voltage V3 of the first fan-out line 171 is equal to or approximately equal to the difference between the second regulating voltage V2 and the non-working voltage V3 of the first fan-out line 171.

[0195] For example, the difference between the first regulating voltage V1 and the non-working voltage V3 of the first fan-out line, and the difference between the second regulating voltage V2 and the non-working voltage V3 of the first fan-out line 171 are both 5V.

[0196] With the above settings, the polarization state of the liquid crystal molecules when the voltage of the first regulating electrode 231 and the second regulating electrode 232 is the first regulating voltage V1 is the same as or approximately the same as the polarization state of the liquid crystal molecules when the voltage of the first regulating electrode 231 and the second regulating electrode 232 is the second regulating voltage V2. At this time, compared with the case where the difference between the first regulating voltage V1 and the non-working voltage V3 of the first fan-out line 171 is not equal to the difference between the second regulating voltage V2 and the non-working voltage V3 of the first fan-out line 171, the effect of the first regulating electrode 231 and the second regulating electrode 232 in reducing the polarization degree of the liquid crystal molecules can be improved.

[0197] In some examples, the switching frequency of the first regulating voltage V1 and the second regulating voltage V2 is less than the display frequency of the dimming panel 1000, which increases the burden on the control structure (e.g., IC) of the dimming panel 1000.

[0198] Therefore, in some embodiments, as shown in Figures 9A and 9B, the switching frequency of the first adjustment voltage V1 and the second adjustment voltage V2 is N times the display frequency of the dimming panel 1000, where N is an integer greater than or equal to 1.

[0199] For example, N can be 1, 2, 3, 5, or 7, etc.

[0200] For example, as shown in Figure 9A, the switching frequency of the first adjustment voltage V1 and the second adjustment voltage V2 is equal to the display frequency of the dimming panel 1000.

[0201] For example, as shown in Figure 9B, the switching frequency of the first adjustment voltage V1 and the second adjustment voltage V2 is twice the display frequency of the dimming panel 1000.

[0202] With the above settings, the switching time of the first regulating voltage V1 and the second regulating voltage V2 is at least partially the same as or approximately the same as the switching time of the display frame of the dimming panel 1000. In this way, the burden on the control structure (e.g., IC) of the dimming panel 1000 can be reduced.

[0203] In some embodiments, as shown in Figures 6 and 10, the plurality of conductive portions 310 further include a fifth conductive portion 315 and a sixth conductive portion 316 disposed in the peripheral region BB. The first substrate 100 also includes a first adjustment signal line 181 and a second adjustment signal line 182. The first adjustment signal line 181 extends along the third sub-region BB3 and extends to the first bonding region CC1; the first adjustment electrode 231 is electrically connected to the first adjustment signal line 181 through at least one fifth conductive portion 315. The second adjustment signal line 182 extends along the fourth sub-region BB4 and extends to the second bonding region CC2; the second adjustment electrode 232 is electrically connected to at least one second adjustment signal line 182 through the sixth conductive portion 316.

[0204] For example, as shown in FIG6, the first adjustment signal line 181 and the second adjustment signal line 182 are located in the gate conductive layer 100A.

[0205] With the above configuration, the first adjustment electrode 231 can be connected to the control structure located in the first binding area CC1 at least through the fifth conductive part 315 and the first adjustment signal line 181, and the second adjustment electrode 232 can be connected to the control structure located in the second binding area CC2 at least through the sixth conductive part 316 and the second adjustment signal line 182, so that the first adjustment electrode 231 and the second adjustment electrode 232 can be connected to the adjustment voltage signal relatively independently, and the independent transmission of the adjustment voltage signal of the first display area AA1 and the second display area AA2 can be realized.

[0206] In some embodiments, one end of the fifth conductive part 315 is in contact with the first regulating electrode 231 and the other end is in contact with the first regulating signal line 181, and one end of the sixth conductive part 316 is in contact with the second regulating electrode 232 and the other end is in contact with the second regulating signal line 182, so as to realize the transmission of the regulating voltage signal.

[0207] In some embodiments, as shown in Figures 5A, 6, and 10, the second substrate 200 further includes a fifth connecting portion 2205 and a sixth connecting portion 2206. The fifth connecting portion 2205 is electrically connected to the first adjusting electrode 231, and the sixth connecting portion 2206 is electrically connected to the second adjusting electrode 232. The first substrate 100 further includes a third pad 1303 and a fourth pad 1304. The third pad 1303 is electrically connected to the first adjusting signal line 181, and the fourth pad 1304 is electrically connected to the second adjusting signal line 182. The orthographic projection of the fifth connecting portion 2205 on the first substrate 100 overlaps with the third pad 1303. A fifth conductive portion 315 is located between the fifth connecting portion 2205 and the third pad 1303 and is electrically connected to both. The orthographic projection of the sixth connecting portion 2206 on the first substrate 100 overlaps with the fourth pad 1304. A sixth conductive portion 316 is located between the sixth connecting portion 2206 and the fourth pad 1304 and is electrically connected to both.

[0208] For example, as shown in FIG5A, the fifth connecting part 2205 and the sixth connecting part 2206 are disposed in the same layer as the second electrode 210, and the material of both is ITO.

[0209] For example, as shown in FIG6, the third pad 1303 and the fourth pad 1304 are disposed in the same layer as the first electrode 110, and the material of both is ITO.

[0210] With the above configuration, the fifth conductive part 315 and the first adjustment signal line 181 can be electrically connected through the third pad 1303, and the sixth conductive part 316 and the second adjustment signal line 182 can be electrically connected through the fourth pad 1304. In this way, the adjustment voltage can be transmitted between the first adjustment signal line 181 and the fifth conductive part 315, and the adjustment voltage can be transmitted between the second adjustment signal line 182 and the sixth conductive part 316. Moreover, the signals of the first adjustment electrode 231 and the second adjustment electrode 232 can be transmitted relatively independently.

[0211] In some examples, in the peripheral area BB of the dimming panel 1000, the third pad 1303 is in vertical contact with at least a portion of the first adjustment signal line 181, and the fourth pad 1304 is in vertical contact with at least a portion of the second adjustment signal line 182.

[0212] In some other examples, the third pad 1303 is located in a sub-section of the peripheral area BB (e.g., at the corner of the first sub-section BB1 and the third sub-section BB3), and the first adjustment signal line 181 is located in another sub-section of the peripheral area BB (e.g., the third sub-section BB3), and the third pad 1303 and the first adjustment signal line 181 are not in contact. Similarly, the fourth pad 1304 is located in a sub-section of the peripheral area BB (e.g., at the corner of the first sub-section BB1 and the fourth sub-section BB4), and the second adjustment signal line 182 is located in another sub-section of the peripheral area BB (e.g., the fourth sub-section BB4), and the fourth pad 1304 and the second adjustment signal line 182 are not in contact.

[0213] Therefore, in some embodiments, as shown in FIG6, the first substrate 100 further includes a third pattern 143 and a fourth pattern 144. The third pattern 143 is disposed below and electrically connected to the third pad 1303; the third pattern 143 is also electrically connected to the first adjustment signal line 181. The fourth pattern 144 is disposed below and electrically connected to the fourth pad 1304; the fourth pattern 144 is also electrically connected to the second adjustment signal line 182.

[0214] For example, as shown in FIG6, the third pattern 143 and / or the fourth pattern 144 are mesh patterns.

[0215] For example, as shown in FIG6, the third pattern 143, the fourth pattern 144, the first adjustment signal line 181 and the second adjustment signal line 182 are disposed in the same layer, for example, all located in the gate conductive layer 100A.

[0216] In some examples, as shown in Figure 6, the third pattern 143 and the fourth pattern 144 are located in the peripheral area BB and below the sealing structure 300.

[0217] With the above configuration, on the one hand, the third gasket 1303 and the first adjustment signal line 181 can be electrically connected through the third pattern 143, and the fourth gasket 1304 and the second adjustment signal line 182 can be electrically connected through the fourth pattern 144. Moreover, the signals of the first adjustment electrode 231 and the second adjustment electrode 232 can be transmitted relatively independently. On the other hand, with the above configuration, both the third pattern 143 and the fourth pattern 144 are patterned structures, which allows light in the photocuring process of the sealing structure 300 to pass through the third pattern 143 and the fourth pattern 144, thereby improving the process feasibility of forming the sealing structure 300.

[0218] Here, there are no limitations on the placement of the fifth connecting part 2205 and / or the sixth connecting part 2206. For example, the fifth connecting part 2205 can be located in the third sub-region BB3 near the first sub-region BB1, and the sixth connecting part 2206 can be located in the fourth sub-region BB4 near the first sub-region BB1.

[0219] In some embodiments, as shown in FIG5A, the fifth connection portion 2205 is located on the outer side of the corner of the first partition electrode 211 near the first sub-region BB1 and the third sub-region BB3, and the sixth connection portion 2206 is located on the outer side of the corner of the second partition electrode 212 near the first sub-region BB1 and the fourth sub-region BB4.

[0220] When the fifth connection portion 2205 is located on the outer side of the corner of the first sub-region BB1 and the third sub-region BB3 near the first partition electrode 211, compared to when the fifth connection portion 2205 is only located in the first sub-region BB1 or only in the third sub-region BB3, the area of ​​the fifth connection portion 2205 can be larger. This results in a larger connection area between the fifth connection portion 2205 and the third pad 1303, improving the connection reliability between the fifth connection portion 2205 and the third pad 1303, and consequently improving the connection reliability between the first adjustment electrode 231 and the first adjustment signal line 181. The beneficial effects of the sixth connection portion 2206 being located on the outer side of the corner of the second partition electrode 212 near the corner of the first sub-region BB1 and the fourth sub-region BB4 can be found above and will not be repeated here.

[0221] The shapes of the fifth connecting portion 2205 and the sixth connecting portion 2206 are not limited here. For example, the shapes of the fifth connecting portion 2205 and the sixth connecting portion 2206 can be rectangular, rhomboid, or circular, etc.

[0222] In some embodiments, as shown in FIG5A, the fifth connecting portion 2205 and the sixth connecting portion 2206 are L-shaped.

[0223] Through the above arrangement, the shape of the fifth connection portion 2205 can be matched with the spatial shape of the outer side of the corner of the first partition electrode 211 near the first sub-region BB1 and the third sub-region BB3, making the area of ​​the fifth connection portion 2205 larger. Thus, similarly to the previous part, the connection reliability between the first adjustment electrode 231 and the first adjustment signal line 181 can be improved. Regarding the beneficial effects of the L-shaped shape of the sixth connection portion 2206, please refer to the above content, and it will not be repeated here.

[0224] In some embodiments, as shown in FIG5A, the side of the fifth connecting portion 2205 is opposite to the side of the first connecting portion 2201 in the first direction X, and there is a gap between them. The side of the sixth connecting portion 2206 is opposite to the side of the second connecting portion 2202 in the first direction X, and there is a gap between them.

[0225] For example, the side of the fifth connecting portion 2205 is parallel to the side of the first connecting portion 2201; the side of the sixth connecting portion 2206 is parallel to the side of the second connecting portion 2202.

[0226] For example, the distance between the side of the fifth connecting portion 2205 and the side of the first connecting portion 2201 is greater than 30 μm, such as 31 μm, 34 μm, 35 μm, 40 μm, 45 μm, or 49 μm. The distance between the side of the sixth connecting portion 2206 and the side of the second connecting portion 2202 is greater than 30 μm, such as 31 μm, 34 μm, 35 μm, 40 μm, 45 μm, or 55 μm.

[0227] When there is a gap between the side of the fifth connecting portion 2205 and the side of the first connecting portion 2201, the coupling effect between the fifth connecting portion 2205 and the first connecting portion 2201 can be reduced, preventing crosstalk between the signal of the first regulating electrode 231 and the first partition voltage signal, which is beneficial to improving the reliability of signal transmission of the dimming panel 1000. Regarding the beneficial effects of having a gap between the side of the sixth connecting portion 2206 and the side of the second connecting portion 2202, please refer to the above content, and it will not be repeated here.

[0228] The shape of the first regulating electrode 231 and / or the second regulating electrode 232 is not limited here. For example, the shape of the first regulating electrode 231 and / or the second regulating electrode 232 can be rectangular or elliptical, etc.

[0229] In some embodiments, as shown in FIG5A, the first regulating electrode 231 and the second regulating electrode 232 are L-shaped. Both the first regulating electrode 231 and the second regulating electrode 232 include a first portion and a second portion connected together. The first portion 2311 of the first regulating electrode 231 extends along a third sub-region BB3, and the first portion 2321 of the second regulating electrode 232 extends along a fourth sub-region BB4. Along the direction from the first sub-region BB1 to the second sub-region BB2, the width of the first portion 2311 of the first regulating electrode 231 and the width of the first portion 2321 of the second regulating electrode 232 both gradually increase. The second portions of both the first regulating electrode 231 and the second regulating electrode 232 extend along the second sub-region BB2. Along the direction from the third sub-region BB3 to the fourth sub-region BB4, the width of the second portion 2312 of the first regulating electrode 231 gradually decreases. Along the direction from the fourth sub-region BB4 to the third sub-region BB3, the width of the second portion 2322 of the second regulating electrode 232 also gradually decreases.

[0230] With the above configuration, the width of the first regulating electrode 231 can correspond to the distribution density of the multiple first fan-out lines 171. That is, the width of the first regulating electrode 231 is larger at positions with higher distribution density of the multiple first fan-out lines 171, and smaller at positions with lower distribution density of the multiple first fan-out lines 171. In this way, the first regulating electrode 231 can cover the multiple first fan-out lines 171 to a greater extent, so that more liquid crystal molecules on one side of the multiple first fan-out lines 171 are located between the first regulating electrode 231 and the multiple first fan-out lines 171, thereby improving the effect of the first regulating electrode 231 in reducing the polarization of liquid crystal molecules. Similarly, with the above configuration, the width of the second regulating electrode 232 can correspond to the distribution density of the multiple second fan-out lines 172, thereby improving the effect of the second regulating electrode 232 in reducing the polarization of liquid crystal molecules.

[0231] In some embodiments, as shown in FIG5A, the second substrate 200 further includes a seventh connection portion 2207 and an eighth connection portion 2208. The seventh connection portion 2207 is disposed on the side of the first adjustment electrode 231 away from the first partition electrode 211. The eighth connection portion 2208 is disposed on the side of the second adjustment electrode 232 away from the second partition electrode 212. The first substrate 100 further includes a fifth pad 1305 and a sixth pad 1306. The orthographic projection of the seventh connection portion 2207 on the first substrate 100 overlaps with the fifth pad 1305, and the seventh connection portion 2207 and the fifth pad 1305 are electrically connected through a conductive portion 310. The fifth pad 1305 is electrically connected to the first partition voltage signal line 121. The orthographic projection of the eighth connection portion 2208 on the first substrate 100 overlaps with the sixth pad 1306, and the eighth connection portion 2208 and the sixth pad 1306 are electrically connected through a conductive portion 310. The sixth pad 1306 is electrically connected to the second partition voltage signal line 122.

[0232] For example, as shown in FIG5A, the seventh connecting part 2207 and the eighth connecting part 2208 are disposed in the same layer as the second electrode 210, and the material of both is ITO.

[0233] For example, as shown in FIG6, the fifth pad 1305 and the sixth pad 1306 are disposed in the same layer as the first electrode 110, and the material of both is ITO.

[0234] With the above configuration, the first partition electrode 211 and the first partition voltage signal line 121 can be electrically connected not only through the first connecting part 2201, the first conductive part 311, and the first pad 1301, but also through the seventh connecting part 2207 and the fifth pad 1305. This reduces the attenuation of the first partition voltage signal and improves the uniformity of the transmission of the first partition voltage signal on the first partition electrode 211. Similarly, the second partition electrode 212 and the second partition voltage signal line 122 can be electrically connected not only through the second connecting part 2202, the second conductive part 312, and the second pad 1302, but also through the eighth connecting part 2208 and the sixth pad 1306. This improves the uniformity of the transmission of the second partition voltage signal on the second partition electrode 212.

[0235] In some embodiments, as shown in Figures 5A to 5E, the widths of the seventh connecting portion 2207 and the eighth connecting portion 2208 gradually decrease along the direction from the first sub-region BB1 to the second sub-region BB2.

[0236] With the above configuration, the width H5 of the seventh connection portion 2207 can change in the opposite direction to the width change of the first adjustment electrode 231, and the width H6 of the eighth connection portion 2208 can change in the opposite direction to the width change of the second adjustment electrode 232. In this way, the space utilization rate of the third sub-region BB3 and the fourth sub-region BB4 in the first substrate 100 can be improved, and the size of the dimming panel 1000 can be reduced.

[0237] In some embodiments, as shown in FIG6, the first adjustment signal line 181 is located on the side of the first partition voltage signal line 121 away from the first partition electrode 211, and the fifth pad 1305 is located between the first adjustment signal line 181 and the first partition voltage signal line 121. The second adjustment signal line 182 is located on the side of the second partition voltage signal line 122 away from the second partition electrode 212, and the sixth pad 1306 is located between the second adjustment signal line 182 and the second partition voltage signal line 122.

[0238] In some embodiments, as shown in FIG6, the first substrate 100 further includes a sixth pattern 146 and a seventh pattern 147. The sixth pattern 146 is disposed below and electrically connected to the fifth pad 1305; the sixth pattern 146 is also electrically connected to the first partition voltage signal line 121. The seventh pattern 147 is disposed below and electrically connected to the sixth pad 1306; the seventh pattern 147 is also electrically connected to the second partition voltage signal line 122.

[0239] For example, as shown in FIG6, the sixth pattern 146 and / or the seventh pattern 147 are mesh patterns.

[0240] For example, as shown in FIG6, the sixth pattern 146, the seventh pattern 147, the first partition voltage signal line 121 and the second partition voltage signal line 122 are disposed on the same layer, for example, all located in the gate conductive layer 100A.

[0241] With the above arrangement, the fifth pad 1305 and the first partition voltage signal line 121 are arranged adjacently, which facilitates the connection between the fifth pad 1305 and the first partition voltage signal line 121. For example, the fifth pad 1305 is electrically connected to the first partition voltage signal line 121 through the sixth pattern 146. Moreover, the signal of the first partition voltage signal line 121 can be led out from the fifth pad 1305 side and the first pad 1301 side respectively, and connected to the side of the first partition electrode 211 near the third sub-region BB3 and the side of the first partition electrode 211 near the first sub-region BB1 respectively. This reduces signal attenuation and improves the uniformity of the transmission of the first partition voltage signal on the first partition electrode 211. Similarly, with the above arrangement, the sixth pad 1306 and the second partition voltage signal line 122 are arranged adjacently. This facilitates the connection between the sixth pad 1306 and the second partition voltage signal line 122 and improves the uniformity of the transmission of the second partition voltage signal on the first partition electrode 211.

[0242] In some implementations, the spacing between the first partition electrode 211 and the second partition electrode 212 is small, so that a certain coupling effect is generated between the first partition electrode 211 and the second partition electrode 212.

[0243] Therefore, in some embodiments, as shown in FIG6, FIG13A and FIG13B, the first substrate 100 further includes a first shielding line 1901 extending along the second direction Y. The orthographic projection of the first shielding line 1901 on the second substrate 200 is located between the first partition electrode 211 and the second partition electrode 212, and has a distance from both the first partition electrode 211 and the second partition electrode 212.

[0244] For example, the first shield 1901 is configured to transmit a constant voltage signal.

[0245] For example, the constant voltage signal transmitted by the first shield 1901 is less than or equal to the threshold voltage, which is, for example, 2V.

[0246] For example, the constant voltage signal transmitted by the first shield 1901 can be a ground signal (GND).

[0247] For example, the first shielding line 1901 is located in the source-drain conductive layer 100B.

[0248] For example, the distance between the orthographic projection of the first shielding line 1901 on the second substrate 200 and the first partition electrode 211, and the distance between the orthographic projection of the first shielding line 1901 on the second substrate 200 and the second partition electrode 212 are equal or approximately equal.

[0249] With the above settings, the constant voltage signal transmitted by the first shielding line 1901 can form a shielding effect between the first partition electrode 211 and the second partition electrode 212, thereby reducing the coupling effect between the first partition voltage and the second partition voltage and reducing the mutual influence between the first partition voltage signal and the second partition voltage signal.

[0250] In some examples, the first shield 1901 is directly connected to a control structure (e.g., an IC) to receive a constant voltage signal.

[0251] In some embodiments, as shown in Figures 11B and 12B, the second substrate 200 further includes a black matrix layer 240, which has a plurality of openings Q1. At least a portion of a first electrode 110 has its orthographic projection onto the second substrate 200 located within one opening Q1. The black matrix layer 240 includes a first black matrix line 241, and the orthographic projection of a first shielding line 1901 onto the second substrate 200 overlaps with the first black matrix line 241.

[0252] For example, the black matrix layer 240 includes a light-absorbing material.

[0253] When the second substrate 200 includes a black matrix layer 240, the black matrix layer 240 can separate multiple pixel areas and absorb large-angle light emitted from each pixel area, thereby improving color mixing between adjacent pixel areas.

[0254] In some embodiments, as shown in Figures 11A and 11B, the dimming panel 1000 is a transmissive display panel, and the width H8 of the first shielding line 1901 is smaller than the width H9 of the first black matrix line 241.

[0255] In some examples, the material of the first shielding wire 1901 includes a metallic material, which has a certain reflective effect on light, causing light leakage at the first shielding wire 1901.

[0256] In some examples, there may be an electric field between the first shielding line 1901 and the second electrode 210, which will drive the liquid crystal molecules to rotate, causing light to leak out around the first shielding line 1901.

[0257] By setting the width H8 of the first shielding line 1901 to be smaller than the width H9 of the first black matrix line 241, the first black matrix line 241 can absorb the light leaking out around the first shielding line 1901, which can improve the display effect of the dimming panel 1000.

[0258] In some embodiments, as shown in Figures 12A and 12B, the dimming panel 1000 is a transflective display panel, and the width H8 of the first shielding line 1901 is greater than or equal to the width H9 of the first black matrix line 241.

[0259] By configuring it in this way, the width H8 of the first shielding line 1901 can be wider, resulting in stronger light reflection between the first electrode 110 (e.g., a reflective electrode) and the first shielding line 1901, thus improving the light emission effect of the dimming panel 1000. Furthermore, when the width H8 of the first shielding line 1901 is greater than or equal to the width H9 of the first black matrix line 241, the reflected light from the first shielding line 1901 can exit through the opening Q1, further enhancing the light emission effect of the dimming panel 1000.

[0260] In some embodiments, as shown in Figures 11B and 12B, the width of the first shielding line 1901 in the transmissive display panel is smaller than the width of the first shielding line 1901 in the semi-transparent display panel. This is because in the transmissive display panel, the first black matrix line 241 needs to block the first shielding line 1901. If the width of the first shielding line 1901 is wider, then the width of the first black matrix line 241 will be wider; and a wider first black matrix line 241 will cause the boundary between adjacent display areas to appear black when the display panel is displayed, affecting the display effect.

[0261] In some embodiments, as shown in FIG6, the first substrate 100 further includes a second shielding line 1902. The second shielding line 1902 extends at least along the first sub-region BB1, the third sub-region BB3, and the fourth sub-region BB4, and both ends of the second shielding line 1902 extend to the first bonding region CC1 and the second bonding region CC2, respectively. One end of the first shielding line 1901 is electrically connected to the portion of the second shielding line 1902 located in the first sub-region BB1.

[0262] For example, as shown in FIG6, the second shielding line 1902 is located in the gate conductive layer 100A.

[0263] With the above configuration, the first shielding line 1901 can be connected to the first bonding area CC1 and the second bonding area CC2 via the second shielding line 1902 for receiving constant voltage signals. Moreover, the second shielding line 1902 can transmit the same constant voltage signal as the first shielding line 1901. With the second shielding line 1902 extending at least along the first sub-area BB1, the third sub-area BB3 and the fourth sub-area BB4, the coverage of the constant voltage signal can be expanded, thereby improving the anti-static performance of the dimming panel 1000.

[0264] In some examples, the first shield 1901 and the second shield 1902 are electrically connected in the same layer.

[0265] In some embodiments, as shown in FIG6, FIG13A and FIG13B, the first substrate 100 further includes a fifth pattern 145 disposed in the first sub-region BB1. The first substrate 100 includes a gate conductive layer 100A and a source / drain conductive layer 100B stacked together. The second shielding line 1902 and the fifth pattern 145 are located in the gate conductive layer 100A, and the fifth pattern 145 and the second shielding line 1902 are electrically connected in the same layer. The first shielding line 1901 is located in the source / drain conductive layer 100B, and one end of the first shielding line 1901 is electrically connected to the fifth pattern 145 through a transition hole Q2.

[0266] For example, as shown in Figures 6, 13A and 13B, the fifth pattern 145 is a mesh pattern.

[0267] For example, the adapter hole Q2 can be a rectangular hole, a circular hole, or a diamond-shaped hole, etc.

[0268] With the above configuration, the first shielding wire 1901 and the second shielding wire 1902 can be electrically connected to the fifth pattern 145 through the adapter hole Q2, so that the second shielding wire 1902 can transmit the same constant voltage signal as the first shielding wire 1901. Moreover, when the fifth pattern 145 is located below the sealing structure 300, the light in the photocuring process can pass through the fifth pattern 145, which can improve the process feasibility of forming the sealing structure 300.

[0269] As mentioned above, along the first direction X, the distance between the first connecting portion 2201 and the second connecting portion 2202 is greater than the distance between the first partition electrode 211 and the second partition electrode 212, that is, the distance between the first pad 1301 and the second pad 1302 is larger.

[0270] In some embodiments, as shown in FIG6, FIG13A and FIG13B, the fifth pattern 145 is located between the first pad 1301 and the second pad 1302.

[0271] For example, the fifth pattern 145 is located between the first pattern 141 and the second pattern 142.

[0272] With this arrangement, the fifth pattern 145 can be set in the portion of the first sub-area BB1 located between the first pad 1301 and the second pad 1302, which can optimize the spatial position. Compared with the case where the first pad 1301 and the second pad 1302 are arranged with the fifth pattern 145 along the second direction Y, the size of the dimming panel 1000 along the second direction Y can be smaller.

[0273] In some examples, at least one of the first pad 1301, the second pad 1302, the first partition voltage signal line 121, and the second partition voltage signal line 122 is located on the side of the second shield line 1902 away from the second electrode 210. In this case, the constant voltage signal transmitted on the first shield line 1901 and the second shield line 1902 covers a relatively small area.

[0274] In some embodiments, as shown in FIG6, the second shielding line 1902 is located on the side of the first pad 1301, the second pad 1302, the first partition voltage signal line 121, and the second partition voltage signal line 122 away from the second electrode 210.

[0275] With this configuration, compared to the case where at least one of the first pad 1301, the second pad 1302, the first partition voltage signal line 121, and the second partition voltage signal line 122 is located on the side of the second shielding line 1902 away from the second electrode 210, the constant voltage signal transmitted on the first shielding line 1901 and the second shielding line 1902 can cover a relatively large area, which is beneficial to improving the anti-static performance of the dimming panel 1000.

[0276] In some examples, at least one of the third pad 1303, the fourth pad 1304, the first adjustment signal line 181, and the second adjustment signal line 182 is located on the side of the second shield line 1902 away from the second electrode 210. In this case, the constant voltage signal transmitted on the first shield line 1901 and the second shield line 1902 covers a relatively small area.

[0277] In some embodiments, as shown in FIG6, the first substrate 100 further includes a third pad 1303, a fourth pad 1304, a first adjustment signal line 181, and a second adjustment signal line 182. The second shielding line 1902 is also located on the side of the third pad 1303, the fourth pad 1304, the first adjustment signal line 181, and the second adjustment signal line 182 away from the second electrode 210.

[0278] With this configuration, compared to the case where at least one of the third pad 1303, the fourth pad 1304, the first adjustment signal line 181, and the second adjustment signal line 182 is located on the side of the second shielding line 1902 away from the second electrode 210, the constant voltage signal transmitted on the first shielding line 1901 and the second shielding line 1902 can cover a relatively large area, which is beneficial to improving the anti-static performance of the dimming panel 1000.

[0279] In some examples, the other end of the first shielding line 1901 is not connected to other lines. In this case, the constant voltage signal transmitted on the first shielding line 1901 and the second shielding line 1902 is weaker in the part of the second sub-region BB2 located between the first binding region CC1 and the second binding region CC2.

[0280] In some embodiments, as shown in Figures 6 and 14, the first substrate 100 further includes a third shielding line 1903. The third shielding line 1903 extends along the second sub-region BB2, and its two ends extend to the first bonding region CC1 and the second bonding region CC2, respectively. The other end of the first shielding line 1901 is electrically connected to the third shielding line 1903.

[0281] For example, the third shielding wire 1903 is electrically connected to the first shielding wire 1901 in the same layer, and both are located in the source-drain conductive layer 100B.

[0282] With the above settings, the portion of the second sub-area BB2 located between the first bonding area CC1 and the second bonding area CC2 can be covered by the constant voltage signal transmitted on the third shielding line 1903. In this way, the constant voltage signals transmitted on the first shielding line 1901, the second shielding line 1902 and the third shielding line 1903 can more comprehensively cover the dimming panel 1000, thereby improving the anti-static performance of the dimming panel 1000.

[0283] In some examples, the first substrate 100 also includes a third partition voltage signal line 123 and a fourth partition voltage signal line 124 located in the second sub-region BB2, and the third partition voltage signal line 123 or the fourth partition voltage signal line 124 is located on the side of the third shield line 1903 away from the second electrode 210. In this case, the constant voltage signal transmitted on the third shield line 1903 covers a relatively small range.

[0284] In some embodiments, as shown in Figures 6 and 14, the first substrate 100 further includes a third partition voltage signal line 123 and a fourth partition voltage signal line 124 located in the second sub-region BB2. A third shielding line 1903 is located on the side of the third partition voltage signal line 123 and the fourth partition voltage signal line 124 away from the second electrode 210.

[0285] With this configuration, compared to the case where the third zone voltage signal line 123 or the fourth zone voltage signal line 124 is located on the side of the third shield line 1903 away from the second electrode 210, the constant voltage signal transmitted on the third shield line 1903 can cover a relatively large area, which is beneficial to improving the anti-static performance of the dimming panel 1000.

[0286] The following example illustrates the pin configuration connected to the second shield 1902 and the third shield 1903.

[0287] In some embodiments, as shown in Figures 6 and 14, the first substrate 100 further includes a fifth pin 155, a sixth pin 156, a seventh pin 157, and an eighth pin 158. The fifth pin 155 is located in the first bonding region CC1, and the sixth pin 156 is located in the second bonding region CC2. The two ends of the second shielding wire 1902 are electrically connected to the fifth pin 155 and the sixth pin 156, respectively. The seventh pin 157 is located in the first bonding region CC1, and the eighth pin 158 is located in the second bonding region CC2. The two ends of the third shielding wire 1903 are electrically connected to the seventh pin 157 and the eighth pin 158, respectively. The fifth pin 155 and the seventh pin 157 are arranged at intervals along the first direction X, and the fifth pin 155 is further away from the centerline of the dimming panel 1000 along the second direction Y than the seventh pin 157. The sixth pin 156 and the eighth pin 158 are arranged at intervals along the first direction X, and the sixth pin 156 is further away from the centerline of the dimming panel 1000 along the second direction Y than the eighth pin 158.

[0288] For example, pin 155, pin 156, pin 157 and pin 158 can be pins of the IC, or they can be pins of the FPC.

[0289] For example, the fifth pin 155 and the sixth pin 156 are configured to transmit a constant voltage signal to the second shield 1902; the seventh pin 157 and the eighth pin 158 are configured to transmit a constant voltage signal to the third shield 1903.

[0290] For example, the number of any one of the fifth pin 155, the sixth pin 156, the seventh pin 157 and the eighth pin 158 can be one or more, and there is no limitation here.

[0291] For example, the fifth pin 155, the sixth pin 156, the seventh pin 157, and the eighth pin 158 are arranged side by side (e.g., side by side along the second direction Y). In some examples, the first pin 151 to the eighth pin 158 are arranged side by side.

[0292] For example, the fifth pin 155 and the sixth pin 156 are symmetrically arranged, and the seventh pin 157 and the eighth pin 158 are symmetrically arranged.

[0293] With the above settings, the fifth pin 155 and the sixth pin 156 can be placed closer to the two ends of the second shielding line 1902, and the seventh pin 157 and the eighth pin 158 can be placed closer to the two ends of the third shielding line 1903. In this way, the spatial position of the second shielding line 1902, the third shielding line 1903, and the pins electrically connected to them are optimized, which can make the size of the peripheral area BB smaller.

[0294] In some embodiments, in addition to the first partition electrode 211 and the second partition electrode 212, the plurality of second electrodes 210 also include other partition electrodes. That is, in addition to the first display area AA1 and the second display area AA2, the functional area AA also includes other display areas, thus enabling a larger number of split screens.

[0295] The following example illustrates the concept of multiple second electrodes 210 including a third partition electrode 213 and a fourth partition electrode 214.

[0296] Figure 16 is a structural diagram of the first substrate 100 according to some embodiments. It should be noted that Figure 16 includes nine partially enlarged substructure diagrams, and these nine substructure diagrams are arranged according to their relative positions on the first substrate 100. For example, the first substructure diagram located in the upper right corner corresponds to the structural diagram of the portion of the first substrate 100 located near the corner between the first sub-region BB1 and the third sub-region BB3.

[0297] In some embodiments, as shown in FIG16, a first binding area CC1 and a second binding area CC2 are provided in the first sub-region BB1. The first binding area CC1 is located on one side of the first display area AA1, and the second binding area CC2 is located on one side of the second display area AA2. The first partition voltage signal line 121 and the second partition voltage signal line 122 are both provided in the first sub-region BB1, the first partition voltage signal line 121 extends to the first binding area CC1, and the second partition voltage signal line 122 extends to the second binding area CC2.

[0298] As shown in Figure 15A, the functional area AA also includes a third display area AA3 and a fourth display area AA4 arranged side by side along the first direction X. The first display area AA1 and the third display area AA3, as well as the second display area AA2 and the fourth display area AA4, are all arranged side by side along the second direction Y. The plurality of second electrodes 210 also include a third partition electrode 213 and a fourth partition electrode 214, with the third partition electrode 213 located in the third display area AA3 and the fourth partition electrode 214 located in the fourth display area AA4.

[0299] Referring to Figure 15A, as shown in Figure 16, the second sub-region BB2 includes a third binding area CC3 and a fourth binding area CC4. The third binding area CC3 is located on one side of the third display area AA3, and the fourth binding area CC4 is located on one side of the fourth display area AA4. The multiple second voltage signal lines 120 also include a third partition voltage signal line 123 and a fourth partition voltage signal line 124 located in the second sub-region BB2. The third partition voltage signal line 123 extends to the third binding area CC3, and the fourth partition voltage signal line 124 extends to the fourth binding area CC4.

[0300] As shown in Figures 15A and 16, the third partition electrode 213 is electrically connected to the third partition voltage signal line 123 through the conductive part 310 (see Figure 2), and the fourth partition electrode 214 is electrically connected to the fourth partition voltage signal line 124 through the conductive part 310.

[0301] For example, as shown in FIG16, the third partition voltage signal line 123 and the fourth partition voltage signal line 124 are located in the gate conductive layer 100A.

[0302] For example, as shown in FIG16, the first binding area CC1 and the third binding area CC3 are symmetrically arranged on both sides of the center line of the dimming panel 1000 along the first direction X; the second binding area CC2 and the fourth binding area CC4 are symmetrically arranged on both sides of the center line of the dimming panel 1000 along the first direction X.

[0303] For example, as shown in FIG16, the first binding area CC1 and the second binding area CC2 are symmetrically arranged on both sides of the center line of the dimming panel 1000 along the second direction Y; the third binding area CC3 and the fourth binding area CC4 are symmetrically arranged on both sides of the center line of the dimming panel 1000 along the second direction Y.

[0304] With the above configuration, the first partition electrode 211, the second partition electrode 212, the third partition electrode 213, and the fourth partition electrode 214 are independently configured. The first partition voltage signal line 121, the second partition voltage signal line 122, the third partition voltage signal line 123, and the fourth partition voltage signal line 124 can provide second voltage signals to their respective second electrodes 210 relatively independently. The liquid crystal molecules located in the first display area AA1, the second display area AA2, the third display area AA3, and the fourth display area AA4 can rotate under the control of the corresponding second voltage signals to achieve partition control of the liquid crystal molecules in the liquid crystal layer 400, thereby realizing the function of partition display.

[0305] In some embodiments, as shown in FIG16, the first substrate 100 further includes a first scan line 161, a second scan line 162, a third scan line 163, a fourth scan line 164, a first fan-out line, a second fan-out line, a third fan-out line, and a fourth fan-out line. The first scan line 161 extends along a first direction X within the first display area AA1, and multiple first scan lines 161 are spaced apart along a second direction Y. The second scan line 162 extends along the first direction X within the second display area AA2, and multiple second scan lines 162 are spaced apart along the second direction Y; the first scan line 161 and the second scan line 162 are spaced apart along the first direction X. The third scan line 163 extends along the first direction X within the third display area AA3, and multiple third scan lines 163 are spaced apart along the second direction Y. The fourth scan line 164 extends along the first direction X within the fourth display area AA4, and multiple fourth scan lines 164 are spaced apart along the second direction Y; the third scan line 163 and the fourth scan line 164 are spaced apart along the first direction X.

[0306] As shown in Figure 16, the first sector output line is electrically connected to the first scan line, extends along the third sub-region BB3, and extends to the first bonding region CC1. The second sector output line is electrically connected to the second scan line, extends along the fourth sub-region BB4, and extends to the second bonding region CC2. The third sector output line is electrically connected to the third scan line, extends along the third sub-region BB3, and extends to the third bonding region CC3. The fourth sector output line is electrically connected to the fourth scan line, extends along the fourth sub-region BB4, and extends to the fourth bonding region CC4.

[0307] For an understanding of the distribution of the first, second, third, and fourth outgoing lines, please refer to Figure 8.

[0308] For example, the first scan line 161, the second scan line 162, the third scan line 163, the fourth scan line 164, the first fan-out line, the second fan-out line, the third fan-out line, and the fourth fan-out line are all located in the gate conductive layer 100A.

[0309] It should be understood that when multiple first scan lines 161 are arranged at intervals along the second direction Y, and multiple third scan lines 163 are arranged at intervals along the second direction Y, the first scan lines 161 and the third scan lines 163 are spaced apart in the second direction Y. Similarly, the second scan lines 162 and the fourth scan lines 164 are spaced apart in the second direction Y.

[0310] Understandably, the first scan line 161 and the second scan line 162 are spaced apart in the first direction X, the third scan line 163 and the fourth scan line 164 are spaced apart in the first direction X, the first scan line 161 and the third scan line 163 are spaced apart in the second direction Y, and the second scan line 162 and the fourth scan line 164 are spaced apart in the second direction Y. When the four scan lines extend to the four binding areas respectively, the signals transmitted by the first scan line 161, the second scan line 162, the third scan line 163 and the fourth scan line 164 can be different, so that the pixels of the first display area AA1, the second display area AA2, the third display area AA3 and the fourth display area AA4 can be controlled relatively independently.

[0311] In some implementations, similar to the aforementioned parts, the liquid crystal molecules located on the first, second, third, and fourth fan-out lines are easily polarized by high voltage, which in turn causes the edges of the functional area AA (i.e., the display area) to flicker or produce a whitening effect at the edges.

[0312] In some embodiments, as shown in Figures 15A-15E and Figure 9A, the second substrate 200 further includes a first regulating electrode 231, a second regulating electrode 232, a third regulating electrode 233, and a fourth regulating electrode 234. The orthographic projection of the first regulating electrode 231 onto the first substrate 100 covers the first fan-out line. The orthographic projection of the second regulating electrode 232 onto the first substrate 100 covers the second fan-out line. The orthographic projection of the third regulating electrode 233 onto the first substrate 100 covers the third fan-out line. The orthographic projection of the fourth regulating electrode 234 onto the first substrate 100 covers the fourth fan-out line. The voltages of the first regulating electrode 231, the second regulating electrode 232, the third regulating electrode 233, and the fourth regulating electrode 234 are all configured to switch between a first regulating voltage V1 and a second regulating voltage V2. The non-operating voltage V3 of the first fan-out line, the second fan-out line, the third fan-out line, and the fourth fan-out line is greater than the first regulating voltage V1 and less than the second regulating voltage V2.

[0313] Regarding the understanding of the non-operating voltage V3 of the fan-out line, please refer to the description of the non-operating voltage V3 of the first fan-out line in the preceding section, which will not be repeated here. Regarding the understanding of the first regulating voltage V1 and the second regulating voltage V2, please refer to the exemplary description of the first regulating voltage V1 and the second regulating voltage V2 in the preceding section, which will not be repeated here. For example, the difference between the first regulating voltage V1 and the non-operating voltage V3 of the first fan-out line is equal to or approximately equal to the difference between the second regulating voltage V2 and the non-operating voltage V3 of the first fan-out line.

[0314] For example, the first regulating electrode 231, the second regulating electrode 232, the third regulating electrode 233 and the fourth regulating electrode 234 are disposed in the same layer as the plurality of second electrodes 210 and are made of the same material, such as ITO.

[0315] For example, the first regulating electrode 231, the second regulating electrode 232, the third regulating electrode 233, and the fourth regulating electrode 234 are L-shaped. Each of the first regulating electrode 231, the second regulating electrode 232, the third regulating electrode 233, and the fourth regulating electrode 234 includes a first portion and a second portion that are connected to each other.

[0316] The first portion of the first regulating electrode 231 extends along the third sub-region BB3, and the first portion of the second regulating electrode 232 extends along the fourth sub-region BB4. Along the direction from the first sub-region BB1 to the second sub-region BB2, the widths of the first portions of both the first regulating electrode 231 and the second regulating electrode 232 gradually decrease. The second portions of both the first regulating electrode 231 and the second regulating electrode 232 extend along the first sub-region BB1. Along the direction from the third sub-region BB3 to the fourth sub-region BB4, the width of the second portion of the first regulating electrode 231 gradually decreases. Along the direction from the fourth sub-region BB4 to the third sub-region BB3, the width of the second portion of the second regulating electrode 232 also gradually decreases.

[0317] The first portion of the third regulating electrode 233 extends along the third sub-region BB3, and the first portion of the fourth regulating electrode 234 extends along the fourth sub-region BB4. Along the direction from the first sub-region BB1 to the second sub-region BB2, the width of the first portions of both the third regulating electrode 233 and the fourth regulating electrode 234 gradually increases. The second portions of both the third regulating electrode 233 and the fourth regulating electrode 234 extend along the second sub-region BB2. Along the direction from the third sub-region BB3 to the fourth sub-region BB4, the width of the second portion of the third regulating electrode 233 gradually decreases. Along the direction from the fourth sub-region BB4 to the third sub-region BB3, the width of the second portion of the fourth regulating electrode 234 also gradually decreases.

[0318] The beneficial effects of the dimming panel 1000 including the first adjustment electrode 231, the second adjustment electrode 232, the third adjustment electrode 233 and the fourth adjustment electrode 234 described above are similar to the beneficial effects of the dimming panel 1000 including the first adjustment electrode 231 and the second adjustment electrode 232 described in some of the above embodiments, and will not be repeated here.

[0319] In some embodiments, the first substrate 100 further includes a first adjustment signal line 181, a second adjustment signal line 182, a third adjustment signal line 183, and a fourth adjustment signal line 184. The first adjustment signal line 181 extends along a third sub-region BB3 and to a first bonding region CC1. A first adjustment electrode 231 is electrically connected to the first adjustment signal line 181 via a conductive portion 310. The second adjustment signal line 182 extends along a fourth sub-region BB4 and to a second bonding region CC2. A second adjustment electrode 232 is electrically connected to the second adjustment signal line 182 via a conductive portion 310. The third adjustment signal line 183 extends along a third sub-region BB3 and to a third bonding region CC3. A third adjustment electrode 233 is electrically connected to the third adjustment signal line 183 via a conductive portion 310. The fourth adjustment signal line 184 extends along a fourth sub-region BB4 and to a fourth bonding region CC4. A fourth adjustment electrode 234 is electrically connected to the fourth adjustment signal line 184 via a conductive portion 310.

[0320] For example, as shown in FIG16, the first adjustment signal line 181, the second adjustment signal line 182, the third adjustment signal line 183 and the fourth adjustment signal line 184 are located in the gate conductive layer 100A.

[0321] Similarly, through the above settings, the first adjustment electrode 231, the second adjustment electrode 232, the third adjustment electrode 233 and the fourth adjustment electrode 234 can be connected to the adjustment voltage signal relatively independently, and the independent transmission of the adjustment voltage signal of the first display area AA1, the second display area AA2, the third display area AA3 and the fourth display area AA4 can be realized.

[0322] In some embodiments, the first regulating electrode 231, the second regulating electrode 232, the third regulating electrode 233 and the fourth regulating electrode 234 are in contact with their corresponding conductive parts 310 to realize the transmission of regulating voltage signals.

[0323] In some embodiments, as shown in Figures 15A-15E and Figure 16, the second substrate 200 further includes a ninth connection portion 2209, a tenth connection portion 2210, an eleventh connection portion 2211, and a twelfth connection portion 2212. A first adjustment electrode 231 is electrically connected to the ninth connection portion 2209, which is electrically connected to a first adjustment signal line 181 via a conductive portion 310. A second adjustment electrode 232 is electrically connected to the tenth connection portion 2210, which is electrically connected to a second adjustment signal line 182 via a conductive portion 310. A third adjustment electrode 233 is electrically connected to the eleventh connection portion 2211, which is electrically connected to a third adjustment signal line 183 via a conductive portion 310. A fourth adjustment electrode 234 is electrically connected to the twelfth connection portion 2212, which is electrically connected to a fourth adjustment signal line 184 via a conductive portion 310. The ninth connecting portion 2209 and the eleventh connecting portion 2211 are disposed at intervals along the second direction Y between the first adjusting electrode 231 and the third adjusting electrode 233. The tenth connecting portion 2210 and the twelfth connecting portion 2212 are disposed at intervals along the second direction Y between the second adjusting electrode 232 and the fourth adjusting electrode 234.

[0324] For example, as shown in Figures 15A to 15E, the ninth connecting part 2209, the tenth connecting part 2210, the eleventh connecting part 2211, and the twelfth connecting part 2212 are disposed in the same layer as the second electrode 210, and all of them are made of ITO.

[0325] For example, the ninth connecting part 2209, the tenth connecting part 2210, the eleventh connecting part 2211 and the twelfth connecting part 2212 are all rectangular in shape.

[0326] With the above arrangement, the signals of the first adjustment electrode 231, the second adjustment electrode 232, the third adjustment electrode 233, and the fourth adjustment electrode 234 can be transmitted relatively independently. Furthermore, the ninth connection portion 2209 and the eleventh connection portion 2211 are spaced apart along the second direction Y between the first adjustment electrode 231 and the third adjustment electrode 233, and the tenth connection portion 2210 and the twelfth connection portion 2212 are spaced apart along the second direction Y between the second adjustment electrode 232 and the fourth adjustment electrode 234. This optimizes the spatial layout of the above structure in the third sub-region BB3 and the fourth sub-region BB4, resulting in a smaller size for the dimming panel 1000.

[0327] In some embodiments, as shown in Figures 15A and 16, the first substrate 100 further includes a plurality of ninth pads 1309, which are respectively connected to the first adjustment signal line 181, the second adjustment signal line 182, the third adjustment signal line 183, and the fourth adjustment signal line 184. The orthographic projection of the ninth connection portion 2209 on the first substrate 100 overlaps with the ninth pad 1309 connected to the first adjustment signal line 181; the orthographic projection of the tenth connection portion 2210 on the first substrate 100 overlaps with the ninth pad 1309 connected to the second adjustment signal line 182; the orthographic projection of the eleventh connection portion 2211 on the first substrate 100 overlaps with the ninth pad 1309 connected to the third adjustment signal line 183; and the orthographic projection of the twelfth connection portion 2212 on the first substrate 100 overlaps with the ninth pad 1309 connected to the fourth adjustment signal line 184. Any one of the ninth connecting part 2209, the tenth connecting part 2210, the eleventh connecting part 2211 and the twelfth connecting part 2212 is electrically connected to a ninth pad 1309 via at least one conductive part 310.

[0328] For example, the material of the ninth liner 1309 is ITO.

[0329] In some embodiments, as shown in FIG16, the first substrate 100 further includes an eighth pattern 148. The eighth pattern 148 is disposed below and electrically connected to the ninth pad 1309; the eighth pattern 148 located below the ninth pad 1309 electrically connected to the ninth connection portion 2209 is also electrically connected to the first adjustment signal line 181; the eighth pattern 148 located below the ninth pad 1309 electrically connected to the tenth connection portion 2210 is also electrically connected to the second adjustment signal line 182; the eighth pattern 148 located below the ninth pad 1309 electrically connected to the eleventh connection portion 2211 is also electrically connected to the third adjustment signal line 183; the eighth pattern 148 located below the ninth pad 1309 electrically connected to the twelfth connection portion 2212 is also electrically connected to the fourth adjustment signal line 184.

[0330] For example, as shown in FIG16, the eighth pattern 148 is a mesh pattern.

[0331] For example, as shown in FIG16, the eighth pattern 148, the first adjustment signal line 181, the second adjustment signal line 182, the third adjustment signal line 183 and the fourth adjustment signal line 184 are disposed in the same layer, for example, all located in the gate conductive layer 100A.

[0332] In some examples, as shown in Figure 16, the eighth pattern 148 is located in the peripheral area BB and below the sealing structure 300.

[0333] The beneficial effects of the dimming panel 1000 including multiple eighth patterns 148 are similar to the beneficial effects of the dimming panel 1000 including third patterns 143 and fourth patterns 144 in some of the above embodiments, and will not be repeated here.

[0334] In some embodiments, as shown in Figures 15A to 15E, the second substrate 200 further includes a fifteenth connecting portion 2215, a sixteenth connecting portion 2216, a seventeenth connecting portion 2217, and an eighteenth connecting portion 2218. The fifteenth connecting portion 2215 is located on the side of the first adjustment electrode 231 away from the first partition electrode 211. The sixteenth connecting portion 2216 is located on the side of the second adjustment electrode 232 away from the second partition electrode 212. The seventeenth connecting portion 2217 is located on the side of the third adjustment electrode 233 away from the third partition electrode 213. The eighteenth connecting portion 2218 is located on the side of the fourth adjustment electrode 234 away from the fourth partition electrode 214.

[0335] For example, as shown in Figures 15A to 15E, the fifteenth connecting part 2215, the sixteenth connecting part 2216, the seventeenth connecting part 2217, and the eighteenth connecting part 2218 are disposed in the same layer as the second electrode 210, and the material of all of them is ITO.

[0336] Exemplarily, the first substrate 100 further includes a plurality of tenth pads 1310, which are respectively connected to the first partition voltage signal line 121, the second partition voltage signal line 122, the third partition voltage signal line 123, and the fourth partition voltage signal line 124. The orthographic projection of the fifteenth connection portion 2215 on the first substrate 100 overlaps with the tenth pad 1310 connected to the first partition voltage signal line 121; the orthographic projection of the sixteenth connection portion 2216 on the first substrate 100 overlaps with the tenth pad 1310 connected to the second partition voltage signal line 122; the orthographic projection of the seventeenth connection portion 2217 on the first substrate 100 overlaps with the tenth pad 1310 connected to the third partition voltage signal line 123; and the eighteenth connection portion 2218 on the first substrate 100 overlaps with the tenth pad 1310 connected to the fourth partition voltage signal line 124. Any one of the fifteenth connecting part 2215, the sixteenth connecting part 2216, the seventeenth connecting part 2217 and the eighteenth connecting part 2218 is electrically connected to a tenth pad 1310 via at least one conductive part 310.

[0337] For example, as shown in FIG16, the tenth gasket 1310 and the ninth gasket 1309 are disposed in the same layer and are both made of ITO.

[0338] In some embodiments, as shown in Figures 15A to 15E, along the direction from the first sub-region BB1 to the second sub-region BB2, the widths of the fifteenth connecting portion 2215 and the sixteenth connecting portion 2216 gradually decrease, while the widths of the seventeenth connecting portion 2217 and the eighteenth connecting portion 2218 gradually increase.

[0339] In some embodiments, as shown in FIG16, the first substrate 100 further includes a ninth pattern 149. The ninth pattern 149 is disposed below the tenth pad 1310 and electrically connected to the tenth pad 1310; the ninth pattern 149 is also electrically connected to one of the first partition voltage signal line 121, the second partition voltage signal line 122, the third partition voltage signal line 123, and the fourth partition voltage signal line 124 to realize the connection between the tenth pad 1310 and its corresponding partition voltage signal line.

[0340] For example, as shown in FIG16, the ninth pattern 149 is a mesh pattern.

[0341] For example, as shown in FIG16, the ninth pattern 149, the first adjustment signal line 181, the second adjustment signal line 182, the third adjustment signal line 183 and the fourth adjustment signal line 184 are disposed in the same layer, for example, all located in the gate conductive layer 100A.

[0342] In some examples, as shown in Figure 16, the ninth pattern 149 is located in the peripheral area BB and below the sealing structure 300.

[0343] In some embodiments, as shown in FIG16, the first adjustment signal line 181 is located on the side of the first partition voltage signal line 121 away from the first partition electrode 211, and the tenth pad 1310, electrically connected to the fifteenth connection portion 2215, is located between the first adjustment signal line 181 and the first partition voltage signal line 121. The second adjustment signal line 182 is located on the side of the second partition voltage signal line 122 away from the second partition electrode 212, and the tenth pad 1310, electrically connected to the sixteenth connection portion 2216, is located between the second adjustment signal line 182 and the second partition voltage signal line 122. The third adjustment signal line 183 is located on the side of the third partition voltage signal line 123 away from the third partition electrode 213, and the tenth pad 1310, electrically connected to the seventeenth connection portion 2217, is located between the third adjustment signal line 183 and the third partition voltage signal line 123. The fourth adjustment signal line 184 is located on the side of the fourth partition voltage signal line 124 away from the fourth partition electrode 214, and the tenth pad 1310, which is electrically connected to the eighteenth connection part 2218, is located between the fourth adjustment signal line 184 and the fourth partition voltage signal line 124.

[0344] In some implementations, the spacing between adjacent electrodes in the first partition electrode 211, the second partition electrode 212, the third partition electrode 213, and the fourth partition electrode 214 is small, resulting in a certain coupling effect between adjacent electrodes.

[0345] Therefore, in some embodiments, as shown in FIG16, the first substrate 100 further includes a fourth shielding line 1904 and a fifth shielding line 1905. The fourth shielding line 1904 extends along the second direction Y; its orthographic projection on the second substrate 200 is located between the first partition electrode 211 and the second partition electrode 212, and between the third partition electrode 213 and the fourth partition electrode 214, and has a distance from each of the first partition electrode 211, the second partition electrode 212, the third partition electrode 213, and the fourth partition electrode 214. The fifth shielding line 1905 extends along the first direction X; its orthographic projection on the second substrate 200 is located between the first partition electrode 211 and the third partition electrode 213, and between the second partition electrode 212 and the fourth partition electrode 214, and has a distance from each of the first partition electrode 211, the second partition electrode 212, the third partition electrode 213, and the fourth partition electrode 214. Both the fourth shield 1904 and the fifth shield 1905 are configured to transmit constant voltage signals.

[0346] For example, the constant voltage signal transmitted by the fourth shield 1904 and the fifth shield 1905 is less than or equal to the threshold voltage, which is, for example, 2V.

[0347] For example, the constant voltage signal transmitted by the fourth shield 1904 and the fifth shield 1905 can be a ground signal (GND).

[0348] With the above configuration, the constant voltage signal transmitted by the fourth shielding line 1904 can form a shielding effect between the first partition electrode 211 and the second partition electrode 212, and between the third partition electrode 213 and the fourth partition electrode 214; the constant voltage signal transmitted by the fifth shielding line 1905 can also form a shielding effect between the first partition electrode 211 and the third partition electrode 213, and between the second partition electrode 212 and the fourth partition electrode 214. In this way, the coupling effect between adjacent pairs of the first partition electrode 211, the second partition electrode 212, the third partition electrode 213, and the fourth partition electrode 214 can be reduced, and the mutual influence between the first partition voltage signal, the second partition voltage signal, the third partition voltage signal, and the fourth partition voltage signal can be reduced.

[0349] In some embodiments, as shown in FIG16, the first substrate 100 further includes a sixth shielding line 1906 and a seventh shielding line 1907. The sixth shielding line 1906 extends at least along the third sub-region BB3, and its two ends extend to the first bonding region CC1 and the third bonding region CC3, respectively. The seventh shielding line 1907 extends at least along the fourth sub-region BB4, and its two ends extend to the second bonding region CC2 and the fourth bonding region CC4, respectively. The two ends of the fifth shielding line 1905 are electrically connected to the sixth shielding line 1906 and the seventh shielding line 1907, respectively.

[0350] With the above configuration, the fifth shielding wire 1905 is connected to the first bonding area CC1 and the third bonding area CC3 respectively via the sixth shielding wire 1906 for receiving constant voltage signals, and is connected to the second bonding area CC2 and the fourth bonding area CC4 respectively via the seventh shielding wire 1907 for receiving constant voltage signals. Moreover, the sixth shielding wire 1906 and the seventh shielding wire 1907 can transmit the same constant voltage signal as the fifth shielding wire 1905, which can make the coverage of the constant voltage signal larger and improve the anti-static performance of the dimming panel 1000.

[0351] In some examples, as shown in Figure 16, the fifth shield 1905, the sixth shield 1906, and the seventh shield 1907 are electrically connected in the same layer.

[0352] In some embodiments, as shown in FIG16, the dimming panel 1000 includes a source-drain conductive layer 100B, and the fifth shielding line 1905, the sixth shielding line 1906 and the seventh shielding line 1907 are all located in the source-drain conductive layer 100B.

[0353] The above settings can improve the connection reliability between the fifth shield 1905 and the sixth shield 1906, as well as between the fifth shield 1905 and the seventh shield 1907, and simplify the formation process of the fifth shield 1905, the sixth shield 1906, and the seventh shield 1907.

[0354] In some embodiments, as shown in FIG16, the first substrate 100 further includes an eighth shielding line 1908 and a ninth shielding line 1909. The eighth shielding line 1908 extends along the first sub-region BB1, and its two ends extend to the first bonding region CC1 and the second bonding region CC2, respectively. The ninth shielding line 1909 extends along the second sub-region BB2, and its two ends extend to the third bonding region CC3 and the fourth bonding region CC4, respectively. The two ends of the fourth shielding line 1904 are electrically connected to the eighth shielding line 1908 and the ninth shielding line 1909, respectively.

[0355] With the above configuration, the fourth shielding wire 1904 is connected to the first bonding area CC1 and the third bonding area CC3 respectively via the eighth shielding wire 1908 for receiving constant voltage signals, and is connected to the second bonding area CC2 and the fourth bonding area CC4 respectively via the ninth shielding wire 1909 for receiving constant voltage signals. Moreover, the eighth shielding wire 1908 and the ninth shielding wire 1909 can transmit the same constant voltage signal as the fourth shielding wire 1904, which can make the coverage of the constant voltage signal larger and improve the anti-static performance of the dimming panel 1000.

[0356] In some examples, as shown in Figure 16, the fourth shield 1904, the eighth shield 1908, and the ninth shield 1909 are electrically connected in the same layer.

[0357] In some embodiments, as shown in FIG16, the dimming panel 1000 includes a gate conductive layer 100A, and the fourth shielding line 1904, the eighth shielding line 1908 and the ninth shielding line 1909 are all located on the gate conductive layer 100A.

[0358] The above settings can improve the connection reliability between the fourth shield 1904 and the eighth shield 1908, and between the fourth shield 1904 and the ninth shield 1909, and simplify the formation process of the fourth shield 1904, the eighth shield 1908 and the ninth shield 1909.

[0359] In some implementations, as shown in Figure 3, the second electrode 120 included in the second substrate 200 is an electrode that is fully connected (e.g., an ITO electrode), so that the touch structure of the dimming panel 1000 adopts a structure with a touch sensor on the dimming panel (i.e., an on-cell touch structure) or an external touch structure, which increases the structural complexity of the dimming panel 1000.

[0360] Figure 17 is a structural diagram of a first substrate 100 according to some embodiments. Figure 18 is a structural diagram of a second substrate 200 according to some embodiments. In Figure 18, DD1 represents the distribution area of ​​a plurality of eleventh pads and a plurality of twelfth pads; DD2 represents the distribution area of ​​a plurality of first partition voltage signal lines 121 and a plurality of second partition voltage signal lines 122; DD3 represents the distribution area of ​​a plurality of first fan-out lines; DD4 represents the distribution area of ​​a plurality of second fan-out lines; and DD5 represents the distribution area of ​​a plurality of anti-static circuits.

[0361] In some embodiments, as shown in FIG17, there are multiple first partition electrodes 211 and multiple second partition electrodes 212. The multiple first partition electrodes 211 are arrayed in the first display area AA1, and the multiple second partition electrodes 212 are arrayed in the second display area AA2. There are multiple first connection portions 2201 and multiple second connection portions 2202. The multiple first connection portions 2201 and the multiple second connection portions 2202 are disposed at intervals in the peripheral area BB.

[0362] As shown in Figures 17 and 20, the second substrate 200 further includes multiple first transmission lines 251 and multiple second transmission lines 251. A first partition electrode 211 is electrically connected to a first connection portion 2201 through a first transmission line 251, and a second partition electrode 212 is electrically connected to a second connection portion 2202 through a second transmission line 251. There are multiple first partition voltage signal lines 121 and multiple second partition voltage signal lines 122. A first connection portion 2201 is electrically connected to a first partition voltage signal line 121 through a conductive portion 310, and a second connection portion 2202 is electrically connected to a second partition voltage signal line 122 through a conductive portion 310.

[0363] As shown in Figures 17 and 18, the first partition voltage signal line 121 is configured to provide the first common voltage signal required for display and the touch driving signal required for touch sensing to the corresponding first partition electrode 211 in a time-division manner; the second partition voltage signal line 122 is configured to provide the second common voltage signal required for display and the touch driving signal required for touch sensing to the corresponding second partition electrode 212 in a time-division manner.

[0364] For example, the first transmission line 251, the second transmission line 251, the first partition electrode 211 and the second partition electrode 212 are disposed in the same layer, and all are made of ITO.

[0365] For example, in the plurality of first connecting portions 2201 and the plurality of second connecting portions 2202, the spacing between any two adjacent portions is greater than 30 μm, for example, 31 μm, 33 μm, 35 μm, 40 μm, 45 μm or 53 μm.

[0366] When the first partition voltage signal line 121 provides the touch driving signal required for touch sensing to the corresponding first partition electrode 211, and the second partition voltage signal line 122 provides the touch driving signal required for touch sensing to the corresponding second partition electrode 212, the multiple first partition electrodes 211 and the multiple second partition electrodes 212 are multiplexed as touch electrodes. The multiple first partition electrodes 211, the multiple second partition electrodes 212, the multiple first transmission lines 251, the multiple second transmission lines 251, the multiple first connection parts 2201, the multiple second connection parts 2202, the multiple first partition voltage signal lines 121 and the multiple second partition voltage signal lines 122 can constitute an in-cell touch structure of the display panel (e.g., a TN LCD) (i.e., the touch panel function is embedded in the pixel). Compared with the use of an on-cell touch structure or an external touch structure, the structural complexity of the display panel can be reduced.

[0367] In some examples, as shown in FIG19, a plurality of first partition electrodes 211 and a plurality of second partition electrodes 212 are formed by photolithography, and the photolithography mask 500 includes a plurality of mask patterns 510, the shapes of the plurality of mask patterns 510 being matched with the shapes of the plurality of first partition electrodes 211 and the plurality of second partition electrodes 212.

[0368] In some implementations, the distribution density of multiple first partition electrodes 211 and multiple second partition electrodes 212 in functional area AA is high, resulting in a small spacing between two adjacent mask patterns 510 (e.g., 30 μm). As a result, during the formation of multiple first connection portions 2201 and multiple second connection portions 2202 by photolithography, electrostatic interaction (MASK ESD) occurs between two adjacent mask patterns 510, causing the mask patterns 510 to adsorb surrounding particles (e.g., metal particles). The increase in particles will cause two adjacent mask patterns 510 on the mask template 500 to connect, thereby connecting the two adjacently arranged connection portions (first connection portion 2201 or second connection portion 2202), causing crosstalk in the partition voltage signals corresponding to the two adjacent connection portions.

[0369] Based on this, in some embodiments, as shown in FIG19, the mask template 500 includes a connecting line 520 disposed between two adjacent mask patterns 510, and the width of the connecting line 520 is in the range of 0.5μm to 0.7μm.

[0370] For example, the width of the connecting line 520 can be 0.50μm, 0.55μm, 0.60μm, 0.65μm or 0.70μm, etc.

[0371] Through the above configuration, multiple mask patterns 510 can be connected into one unit using the connecting line 520, thereby reducing the electrostatic interaction between two adjacent mask patterns 510 and preventing the mask patterns 510 from adsorbing surrounding particles. Furthermore, by connecting two adjacent mask patterns 510, the multiple first connecting portions 2201 and multiple second connecting portions 2202 are spaced apart, preventing crosstalk between the corresponding partition voltage signals. Moreover, when the width of the connecting line 520 is in the range of 0.5μm to 0.7μm, the relatively narrow width prevents patterns from forming at positions corresponding to the connecting line 520 during the formation of multiple first partition electrodes 211 and multiple second partition electrodes 212.

[0372] In some embodiments, as shown in Figures 17 and 18, the peripheral area BB includes a first sub-area BB1, a second sub-area BB2, a third sub-area BB3, and a fourth sub-area BB4. The first sub-area BB1 and the second sub-area BB2 are located on opposite sides of the functional area AA in the second direction Y, and the third sub-area BB3 and the fourth sub-area BB4 are located on opposite sides of the functional area AA in the first direction X. The first direction X is the row direction in which the plurality of second electrodes 210 are arranged, and the second direction Y is the column direction in which the plurality of second electrodes 210 are arranged. A plurality of first connecting portions 2201 and a plurality of second connecting portions 2202 are disposed in the first sub-area BB1 and arranged along the first direction X.

[0373] As shown in Figure 18, the second sub-region BB2 has a first binding area CC1 and a second binding area CC2. The first binding area CC1 is located on one side of the first display area AA1, and the second binding area CC2 is located on one side of the second display area AA2. The first partition voltage signal line 121 extends along the third sub-region BB3 and extends to the first binding area CC1. The second partition voltage signal line 122 extends along the fourth sub-region BB4 and extends to the second binding area CC2.

[0374] With the above configuration, multiple first partition electrodes 211 can be electrically connected to multiple pins of the first bonding area CC1 through multiple first partition voltage signal lines 121, and multiple second partition electrodes 212 can be electrically connected to multiple pins of the second bonding area CC2 through multiple second partition voltage signal lines 122. In this way, multiple first partition voltage signals and multiple second partition voltage signals can be transmitted relatively independently.

[0375] In some embodiments, as shown in FIG18, the first substrate 100 further includes a plurality of eleventh pads and a plurality of twelfth pads located in the first sub-region BB1. A first connection portion 2201 has its orthographic projection on the first substrate 100 overlapping with an eleventh pad, and the first connection portion 2201 and the eleventh pad are electrically connected through a conductive portion 310; a second connection portion 2202 has its orthographic projection on the first substrate 100 overlapping with a twelfth pad, and the second connection portion 2202 and the twelfth pad are electrically connected through a conductive portion 310.

[0376] In some embodiments, the first substrate 100 further includes a first scan line (not shown in FIG. 18), a second scan line (not shown in FIG. 18), a first fan-out line, and a second fan-out line. The first scan line extends along a first direction X within the first display area AA1, and multiple first scan lines are spaced apart along a second direction Y. The second scan line extends along the first direction X within the second display area AA2, and multiple second scan lines are spaced apart along the second direction Y. The first scan line and the second scan line are spaced apart along the first direction X. The first fan-out line is electrically connected to the first scan line, extends along a third sub-region BB3, and extends to a first bonding area CC1. The second fan-out line is electrically connected to the second scan line, extends along a fourth sub-region BB4, and extends to a second bonding area CC2.

[0377] As shown in Figure 17, the second substrate 200 also includes a fifth adjustment electrode 235 and a sixth adjustment electrode 236. The fifth adjustment electrode 235 extends along the third sub-region BB3 and the second sub-region BB2, and the sixth adjustment electrode 236 extends along the second sub-region BB2 and the fourth sub-region BB4. The voltages of the fifth adjustment electrode 235 and the sixth adjustment electrode 236 are both configured to switch between a first adjustment voltage V1 and a second adjustment voltage V2. The non-working voltage V3 of the first fan-out line and the second fan-out line is greater than the first adjustment voltage V1 and less than the second adjustment voltage V2.

[0378] As shown in FIG18, the first substrate 100 further includes a thirteenth pad 1313 and a fourteenth pad 1314 located on both sides of the distribution area DD1 of the plurality of eleventh pads and the plurality of twelfth pads. The thirteenth pad 1313 is electrically connected to the fifth adjustment electrode 235 through the conductive part 310; the fourteenth pad 1314 is electrically connected to the sixth adjustment electrode 236 through the conductive part 310.

[0379] As shown in FIG18, the first substrate 100 further includes a fifth adjustment signal line extending along the third sub-region BB3 and a sixth adjustment signal line extending along the fourth sub-region BB4. The fifth adjustment signal line extends to the first bonding region CC1 and the sixth adjustment signal line extends to the second bonding region CC2.

[0380] In some embodiments, as shown in FIG18, the second substrate 200 further includes a tenth shielding line 1910 located on the side of the fifth adjustment signal line and the sixth adjustment signal line away from the functional area AA, and the two ends of the tenth shielding line 1910 extend to the first bonding area CC1 and the second bonding area CC2, respectively.

[0381] In some embodiments, as shown in FIG18, the second substrate 200 further includes a plurality of anti-static circuits.

[0382] In some examples, as shown in FIG21, the first substrate 100 further includes a fifteenth pad 1315 and a plurality of sixteenth pads. The fifteenth pad 1315 and the plurality of sixteenth pads are disposed in the first sub-region BB1, wherein the distribution area of ​​the sixteenth pads is shown as DD6 in FIG21. The fifteenth pad 1315 is used to provide the second common voltage signal required for display to the corresponding second partition electrode 212, that is, the voltage signal transmitted by the fifteenth pad 1315 may not undergo abrupt changes. The sixteenth pads are used to provide the second common voltage signal required for display and the touch driving signal required for touch sensing to the corresponding second partition electrode 212 in a time-division manner, that is, the voltage signal transmitted by the sixteenth pad undergoes abrupt changes as needed.

[0383] In this case, the positional relationship between the distribution areas DD1 of the multiple eleventh pads and the multiple twelfth pads, the distribution area DD5 of the multiple antistatic circuits, the distribution area DD6 of the sixteenth pad, and the fifteenth pad 1315 is shown in Figure 21. This arrangement allows the sixteenth pad to avoid the placement of the antistatic circuits.

[0384] In some embodiments, as shown in Figures 1A to 1C, the second substrate 200 further includes a second substrate 200C and a black matrix layer 240 disposed on the substrate. The black matrix layer 240 includes a plurality of interwoven black matrix lines 242. The gap H10 between two adjacent second electrodes 210 is located on the side of the black matrix line 242 away from the second substrate 200C, and the width of the gap is smaller than the width of the black matrix line 242.

[0385] When the gap H10 between two adjacent second electrodes 210 is located on the side of the black matrix line 242 away from the second substrate 200C, the portion of the light emitted from one display area that is directed towards adjacent display areas can be absorbed by the black matrix line 242, thus preventing crosstalk between adjacent display areas and improving the display effect. Furthermore, when the width of the gap H10 is smaller than the width H9 of the black matrix line 242, the anti-crosstalk effect on light from adjacent display areas is even better, further enhancing the display effect.

[0386] In some embodiments, as shown in Figures 3 and 4, the second substrate 200 further includes a plurality of filter portions 260. A plurality of black matrix lines 242 interweave to form a plurality of openings Q1, and a filter portion 260 is located within one opening Q1.

[0387] When a filter section 260 is located within an opening Q1, multiple black matrix lines 242 can separate multiple filter sections 260.

[0388] The aforementioned filter unit 260 can be configured to allow light of the same color to pass through and filter out light of a different color, thereby improving the color purity of the emitted light. Exemplarily, the plurality of filter units 260 include at least one red filter unit 261, at least one green filter unit 262, and at least one blue filter unit 263. The red filter unit 261 is used to allow red light to pass through and filter out other light besides red light.

[0389] For example, the filter portion 260 is connected to the second substrate 200C by an adhesive.

[0390] In some implementations, multiple second electrodes 210 are formed by an etching process. During the process of forming multiple second electrodes 210 on the side away from the second substrate 200C of multiple black matrix lines 242 and multiple filter sections 260, adhesive may detach from the second substrate 200C, and the detached adhesive may enter the display area, causing display defects and adverse effects on subsequent processes of the display panel.

[0391] Based on this, in some embodiments, as shown in FIG4, the second substrate 200 further includes a protective layer 270, which covers the black matrix layer 240 and the plurality of filter portions 260 on the side away from the second substrate 200C. The plurality of second electrodes 210 are located on the side of the protective layer 270 away from the second substrate 200C.

[0392] For example, the protective layer 270 is a thermosetting material. For instance, the material of the protective layer 270 can be a cured acrylic polymer (ACR) film.

[0393] With the above configuration, the protective layer 270 can at least provide protection for the adhesive, reduce the impact of the etching process that forms multiple second electrodes 210 on the adhesive, and prevent the adhesive from falling off during the etching process, so as to avoid display defects.

[0394] When the second substrate 200 also includes a protective layer 270 and a plurality of filter portions 260, the method for preparing the dimming panel 1000 includes, for example, S1 to S4.

[0395] S1: Provide a second substrate 200C.

[0396] S2: A black matrix layer 240 and multiple filter sections 260 are formed. The black matrix layer 240 includes multiple interwoven black matrix lines 242. The multiple black matrix lines 242 interweave to form multiple openings Q1, and a filter section 260 is located within one opening Q1.

[0397] S3: A protective layer 270 is formed on the side of the black matrix layer 240 and the plurality of filter sections 260 away from the second substrate 200C, and the protective layer 270 is cured.

[0398] For example, an annealing process (oven process) can be used to cure the protective layer 270.

[0399] S4: Using an etching process, a plurality of second electrodes 210 are formed on the side of the protective layer 270 away from the second substrate 200C. The material of the second electrodes 210 is, for example, ITO.

[0400] On the other hand, some embodiments of this disclosure provide a display panel. The display panel includes: a dimming panel 1000 as described in any of the above embodiments, and a plurality of driver chips electrically connected to the dimming panel 1000.

[0401] For example, multiple driver chips are electrically connected to multiple second electrodes 210 in a one-to-one correspondence. The driver chips are configured to provide a second voltage signal to their corresponding second electrodes 210 to drive the display panel to display.

[0402] The aforementioned display panel is a liquid crystal display (LCD), such as a TN LCD, which features high transmittance, large size, low power consumption, and low cost, and is a widely used type of display.

[0403] In some examples, the display panel further includes a first polarizer disposed on the side of the first substrate 100 away from the second substrate 200, and a second polarizer disposed on the side of the second substrate 200 away from the first substrate 100. The first and second polarizers may be linear polarizers, which allow light with the same polarization direction as the transmission axis (i.e., the transmission direction) of the linear polarizer to pass through (i.e., to exit); the polarization directions of the first and second polarizers are perpendicular or substantially perpendicular to each other.

[0404] The beneficial effects of the above-mentioned display panel are the same as those of the dimming panel 1000 described in some of the above embodiments, and will not be repeated here.

[0405] In another aspect, a display device is provided. The display device includes: a display panel as described in any of the above embodiments, and a backlight module disposed on one side of a first substrate 100 of the display panel.

[0406] A backlight module is used to provide a light source for the display panel. A backlight module can be an edge-lit backlight module, and may include, for example, a light source, a light guide plate, a reflector, and optical elements.

[0407] For example, a display device can be any device that displays images, whether moving (e.g., video) or stationary (e.g., still images), and whether text or pictures. The display device can be a variety of display devices, including but not limited to mobile phones, wireless devices, portable Android devices (PADs), handheld or portable computers, GPS (Global Positioning System) receivers / navigators, cameras, MP4 (MPEG-4 Part 14) video players, camcorders, game consoles, flat panel displays, computer monitors, automotive displays (e.g., car dashcams or rearview cameras), etc.

[0408] The beneficial effects of the above-described display device are the same as those of the display panel described in some of the above embodiments, and will not be repeated here.

[0409] In some embodiments, the dimming panel 1000 is a dimming panel 1000 in a liquid crystal transparent.

[0410] In some implementations, as shown in Figure 3, the second electrode 210 included in the second substrate 200 is an electrode with the entire surface connected (e.g., an ITO electrode), and the plurality of first electrodes 110 included in the first substrate 100 are strip electrodes. By transmitting a driving voltage to the first electrode 110 and a common voltage to the second electrode 210, the liquid crystal at the corresponding position is deflected to achieve dimming. However, in the above case, the liquid crystal molecules in the liquid crystal layer 400 are only subjected to an edge field along one direction, resulting in a poor light emission viewing angle of the dimming panel 1000. When the dimming panel 1000 includes an alignment film, the initial state of the liquid crystal molecules is determined by the alignment direction, so the deflection direction of the liquid crystal molecules under the action of the electric field is also affected by the alignment direction, making the dimming panel 1000 have a better lower viewing angle effect, further degrading the light emission viewing angle.

[0411] Based on this, in some embodiments, as shown in Figures 22A and 22B, the plurality of first electrodes 110 and the plurality of second electrodes 210 are all strip electrodes, and the orthographic projections of the plurality of second electrodes 210 on the first substrate 100 intersect with the plurality of first electrodes 110. The second substrate 200 also includes a thirteenth connecting portion 2213 and a fourteenth connecting portion 2214, respectively located on both sides of the functional area AA in the third direction Z, where the third direction Z is the extending direction of the second electrodes 210. A portion of the plurality of second electrodes 210 is electrically connected to the thirteenth connecting portion 2213, and another portion of the plurality of second electrodes 210 is electrically connected to the fourteenth connecting portion 2214.

[0412] For example, the orthographic projection of the plurality of second electrodes 210 on the first substrate 100 is perpendicular to the plurality of first electrodes 110.

[0413] When a portion of the second electrodes 210 is electrically connected to the thirteenth connection portion 2213, the thirteenth connection portion 2213 can be configured to provide a common voltage signal to the second electrodes 210 electrically connected thereto; when another portion of the second electrodes 210 is electrically connected to the fourteenth connection portion 2214, the thirteenth connection portion 2213 can be configured to provide a common voltage signal to the second electrodes 210 electrically connected thereto.

[0414] With the above configuration, the edge field experienced by the liquid crystal molecules of the liquid crystal layer 400 includes at least the edge field along the third direction Z and the edge field along the extension direction of the first electrode 110. In this way, the liquid crystal molecules can be subjected to edge fields in multiple directions, enabling the liquid crystal to rotate at multiple angles and improving the light emission angle of the dimming panel 1000.

[0415] Here, there are no limitations on the connection methods between the thirteenth connecting part 2213, the fourteenth connecting part 2214 and the plurality of second electrodes 210. For example, the plurality of second electrodes 210 can be divided into two groups of second electrodes 210 arranged along the fourth direction, one group of second electrodes 210 connected to the thirteenth connecting part 2213 and the other group of second electrodes 210 connected to the fourteenth connecting part 2214, with the fourth direction perpendicular to the third direction Z.

[0416] In some embodiments, as shown in Figures 22A and 22B, the second electrode 210 in the odd-numbered rows is electrically connected to the thirteenth connection portion 2213, and the second electrode 210 in the even-numbered rows is electrically connected to the fourteenth connection portion 2214.

[0417] For example, the number of multiple second electrodes 210 is ten extending along the rows, with the second electrodes 210 in the first, third, fifth, seventh, and ninth rows electrically connected to the thirteenth connecting portion 2213; and the second electrodes 210 in the second, fourth, sixth, eighth, and tenth rows electrically connected to the thirteenth connecting portion 2213.

[0418] With the above settings, the voltage signals of any two adjacent rows of second electrodes 210 can be different, so that an electric field can be formed between any two rows of second electrodes 210, and a grating structure can be formed on the dimming panel 1000 to realize the function of a liquid crystal lens.

[0419] In another aspect, a liquid crystal lens is provided. The liquid crystal lens includes a dimming panel 1000 as described in any of the above embodiments.

[0420] In some examples, liquid crystal lenses can achieve the effect of converging light; in other examples, liquid crystal lenses can achieve the effect of diverging light.

[0421] The beneficial effects of the above-mentioned display panel are the same as those of the dimming panel 1000 described in some of the above embodiments, and will not be repeated here.

[0422] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A dimming panel, comprising a functional area and a peripheral area surrounding the functional area; the dimming panel comprising: A first substrate includes a plurality of first electrodes, the plurality of first electrodes being disposed in the functional area; The second substrate is disposed opposite to the first substrate and includes a plurality of second electrodes. The plurality of second electrodes are disposed in the functional area. The orthographic projection of one second electrode on the first substrate overlaps with at least one first electrode. The plurality of second electrodes are disposed independently of each other. Multiple conductive portions are disposed between the first substrate and the second substrate, and are located in the peripheral region; The first substrate further includes multiple second voltage signal lines disposed in the peripheral area; a second electrode is electrically connected to a second voltage signal line through at least one of the conductive parts, and the multiple second voltage signal lines are configured to provide a second voltage signal to their respective corresponding second electrodes relatively independently.

2. The dimming panel according to claim 1, wherein, The functional area includes a first display area and a second display area; the plurality of second electrodes include a first partition electrode and a second partition electrode, wherein the first partition electrode is disposed in the first display area and the second partition electrode is disposed in the second display area; The plurality of conductive parts include a first conductive part and a second conductive part, and the plurality of second voltage signal lines include a first partition voltage signal line and a second partition voltage signal line. The first conductive part is electrically connected to the first partition voltage signal line, and the second conductive part is electrically connected to the second partition voltage signal line. The second substrate further includes: The first connecting part is disposed on one side of the first partition electrode, and is electrically connected to the first partition electrode and also electrically connected to the first conductive part. The second connecting part is provided on one side of the second partition electrode and is electrically connected to the second partition electrode and also electrically connected to the second conductive part.

3. The dimming panel according to claim 2, wherein, The first substrate further includes: The first pad, the orthographic projection of the first connecting portion on the first substrate overlaps with the first pad, the first conductive portion is located between the first connecting portion and the first pad, and the first conductive portion is electrically connected to the first pad, and the first pad is electrically connected to the first partition voltage signal line. The second pad, the orthographic projection of the second connecting portion on the first substrate overlaps with the second pad, the second conductive portion is located between the second connecting portion and the second pad, and the second conductive portion is electrically connected to the second pad, and the second pad is electrically connected to the second partition voltage signal line.

4. The dimming panel according to claim 3, wherein, The first substrate further includes: A first pattern is disposed below the first pad and electrically connected to the first pad; the first pattern is also electrically connected to the first partition voltage signal line. The second pattern is disposed below the second pad and electrically connected to the second pad; the second pattern is also electrically connected to the second partition voltage signal line.

5. The dimming panel according to any one of claims 2 to 4, wherein, The peripheral area includes a first sub-area, a second sub-area, a third sub-area, and a fourth sub-area. The first sub-area and the second sub-area are located on both sides of the functional area in the second direction, and the third sub-area and the fourth sub-area are located on both sides of the functional area in the first direction. The first direction is the arrangement direction of the first partition electrode and the second partition electrode, and the first direction intersects the second direction. Both the first connecting portion and the second connecting portion are located in the first sub-region.

6. The dimming panel according to claim 5, wherein, The first connecting part, the second connecting part, the first partition electrode, and the second partition electrode are made of the same material; The first connecting portion is integrally formed with the first partition electrode, and the first connecting portion extends along the side of the first partition electrode where it is located; The second connecting portion is integrally formed with the second partition electrode, and the second connecting portion extends along the side of the second partition electrode where it is located.

7. The dimming panel according to claim 5 or 6, wherein, Along the first direction, the distance between the first connecting portion and the second connecting portion is greater than the distance between the first partition electrode and the second partition electrode.

8. The dimming panel according to any one of claims 5 to 7, wherein, The second sub-area is provided with a first binding area and a second binding area, the first binding area is located on one side of the first display area, and the second binding area is located on one side of the second display area; The first partition voltage signal line extends along the third sub-region and extends to the first bonding region; The second partition voltage signal line extends along the fourth sub-region and extends to the second bonding region.

9. The dimming panel according to claim 8, wherein, The second substrate further includes a third connection portion and a fourth connection portion located in the second sub-region. The third connection portion is located on one side of the first partition electrode and is electrically connected to the first partition electrode. The fourth connection portion is located on one side of the second partition electrode and is electrically connected to the second partition electrode. The plurality of conductive parts further include a third conductive part and a fourth conductive part located in the second sub-region, the third connecting part being electrically connected to the third conductive part, and the fourth connecting part being electrically connected to the fourth conductive part; The plurality of second voltage signal lines also include a third partition voltage signal line and a fourth partition voltage signal line located in the second sub-region. The third partition voltage signal line extends to the first bonding region, and the fourth partition voltage signal line extends to the second bonding region. The third conductive part is electrically connected to the third partition voltage signal line, and the fourth conductive part is electrically connected to the fourth partition voltage signal line.

10. The dimming panel according to claim 9, wherein, The third connecting part, the fourth connecting part, the first partition electrode, and the second partition electrode are made of the same material; The third connecting portion is integrally formed with the first partition electrode, and the third connecting portion extends along the side of the first partition electrode where it is located. The fourth connecting portion is integrally formed with the second partition electrode, and the fourth connecting portion extends along the side of the second partition electrode where it is located.

11. The dimming panel according to claim 9 or 10, wherein, Along the second direction, the distance between the third connecting portion and the fourth connecting portion is greater than the distance between the first partition electrode and the second partition electrode.

12. The dimming panel according to any one of claims 9 to 11, wherein, The first substrate further includes a first pin, a second pin, a third pin, and a fourth pin; The first pin and the third pin are located in the first bonding area and are spaced apart along the first direction. The first pin is further away from the center line of the dimming panel along the second direction than the third pin. The first partition voltage signal line is electrically connected to the first pin, and the third partition voltage signal line is electrically connected to the third pin. The second pin and the fourth pin are located in the second bonding area and are spaced apart along the first direction. The second pin is farther away from the center line of the dimming panel along the second direction than the fourth pin. The second partition voltage signal line is electrically connected to the second pin, and the fourth partition voltage signal line is electrically connected to the fourth pin.

13. The dimming panel according to any one of claims 8 to 12, wherein, The first substrate further includes: The first scan line extends along the first direction within the first display area, and multiple first scan lines are arranged at intervals along the second direction. The second scan line extends along the first direction within the second display area, and multiple second scan lines are arranged at intervals along the second direction; the first scan line and the second scan line are arranged at intervals along the first direction. The first sector output line is electrically connected to the first scan line, extends along the third sub-region, and extends to the first bonding region; The second fan-out line is electrically connected to the second scan line, extends along the fourth sub-region, and extends to the second bonding region.

14. The dimming panel according to claim 13, wherein, The second substrate further includes: A first regulating electrode, the orthographic projection of the first regulating electrode on the first substrate covers the first fan-out line; The second adjustment electrode, the orthogonal projection of the second adjustment electrode on the first substrate covers the second fan-out line; The voltages of the first regulating electrode and the second regulating electrode are both configured to switch between a first regulating voltage and a second regulating voltage. The non-operating voltages of the first fan-out line and the second fan-out line are both greater than the first regulating voltage and less than the second regulating voltage.

15. The dimming panel according to claim 14, wherein, The plurality of conductive parts further includes a fifth conductive part and a sixth conductive part, which are disposed in the peripheral area; The first substrate further includes: A first adjustment signal line extends along the third sub-region and to the first bonding region; the first adjustment electrode is electrically connected to the first adjustment signal line through at least one of the fifth conductive parts; The second adjustment signal line extends along the fourth sub-region and extends to the second bonding region; the second adjustment electrode is electrically connected to the second adjustment signal line through at least one of the sixth conductive parts.

16. The dimming panel according to claim 15, wherein, The second substrate further includes a fifth connection portion and a sixth connection portion, wherein the fifth connection portion is electrically connected to the first adjustment electrode and the sixth connection portion is electrically connected to the second adjustment electrode; The first substrate further includes a third pad and a fourth pad, wherein the third pad is electrically connected to the first adjustment signal line and the fourth pad is electrically connected to the second adjustment signal line; The orthographic projection of the fifth connecting portion on the first substrate overlaps with the third pad, and the fifth conductive portion is located between the fifth connecting portion and the third pad and is electrically connected to both of them respectively; The orthographic projection of the sixth connecting portion on the first substrate overlaps with the fourth pad, and the sixth conductive portion is located between the sixth connecting portion and the fourth pad and is electrically connected to both of them.

17. The dimming panel according to claim 16, wherein, The first substrate further includes: The third pattern is disposed below the third pad and electrically connected to the third pad; the third pattern is also electrically connected to the first adjustment signal line. The fourth pattern is disposed below the fourth pad and electrically connected to the fourth pad; the fourth pattern is also electrically connected to the second adjustment signal line.

18. The dimming panel according to claim 16 or 17, wherein, The fifth connection is located on the outer side of the corner of the first partition electrode near the first sub-region and the third sub-region, and the sixth connection is located on the outer side of the corner of the second partition electrode near the first sub-region and the fourth sub-region.

19. The dimming panel according to claim 18, wherein, The fifth connecting part and the sixth connecting part are L-shaped; The side of the fifth connecting part is opposite to the side of the first connecting part in the first direction, and there is a gap between them; The side of the sixth connecting part is opposite to the side of the second connecting part in the first direction, and there is a gap between them.

20. The dimming panel according to any one of claims 14 to 19, wherein, The first regulating electrode and the second regulating electrode are L-shaped, and both the first regulating electrode and the second regulating electrode include a first part and a second part that are connected to each other. The first portion of the first regulating electrode extends along the third sub-region, and the first portion of the second regulating electrode extends along the fourth sub-region; the width of the first portion of both the first regulating electrode and the second regulating electrode gradually increases along the direction from the first sub-region to the second sub-region. The second portions of both the first regulating electrode and the second regulating electrode extend along the second sub-region; the width of the second portion of the first regulating electrode gradually decreases along the direction from the third sub-region to the fourth sub-region, and the width of the second portion of the second regulating electrode also gradually decreases along the direction from the fourth sub-region to the third sub-region.

21. The dimming panel according to claim 20, wherein, The second substrate further includes a seventh connection portion and an eighth connection portion, wherein the seventh connection portion is disposed on the side of the first adjustment electrode away from the first partition electrode, and the eighth connection portion is disposed on the side of the second adjustment electrode away from the second partition electrode; The first substrate further includes a fifth pad and a sixth pad; The orthographic projection of the seventh connection portion on the first substrate overlaps with the fifth pad, and the seventh connection portion and the fifth pad are electrically connected through the conductive portion, and the fifth pad is electrically connected to the first partition voltage signal line; The orthographic projection of the eighth connection portion on the first substrate overlaps with the sixth pad, and the eighth connection portion and the sixth pad are electrically connected through the conductive portion. The sixth pad is electrically connected to the second partition voltage signal line.

22. The dimming panel according to claim 21, wherein, Along the direction from the first sub-region to the second sub-region, the widths of both the seventh connecting portion and the eighth connecting portion gradually decrease.

23. The dimming panel according to claim 21 or 22, wherein, The first adjustment signal line is located on the side of the first partition voltage signal line away from the first partition electrode, and the fifth pad is located between the first adjustment signal line and the first partition voltage signal line; The second adjustment signal line is located on the side of the second partition voltage signal line away from the second partition electrode, and the sixth pad is located between the second adjustment signal line and the second partition voltage signal line.

24. The dimming panel according to any one of claims 8 to 23, wherein, The first substrate further includes a first shielding line, which extends along the second direction; The orthographic projection of the first shielding line on the second substrate is located between the first partition electrode and the second partition electrode, and has a gap with both the first partition electrode and the second partition electrode.

25. The dimming panel according to claim 24, wherein, The first substrate also includes a second shielding line; The second shielding line extends at least along the first sub-region, the third sub-region, and the fourth sub-region, and both ends of the second shielding line extend to the first bonding area and the second bonding area, respectively; One end of the first shielding wire is electrically connected to the portion of the second shielding wire located within the first sub-region.

26. The dimming panel according to claim 25, wherein, The first substrate further includes a fifth pattern disposed in the first sub-region; The first substrate includes a gate conductive layer and a source / drain conductive layer stacked together; the second shielding line and the fifth pattern are located on the gate conductive layer, and the fifth pattern is electrically connected to the second shielding line on the same layer; the first shielding line is located on the source / drain conductive layer, and one end of the first shielding line is electrically connected to the fifth pattern through an adapter hole; The fifth pattern is located between the first pad and the second pad.

27. The dimming panel according to claim 25 or 26, wherein, The second shielding line is located on the side of the first pad, the second pad, the first partition voltage signal line, and the second partition voltage signal line away from the second electrode; and / or, The first substrate further includes a third pad, a fourth pad, a first adjustment signal line, and a second adjustment signal line; the second shielding line is also located on the side of the third pad, the fourth pad, the first adjustment signal line, and the second adjustment signal line away from the second electrode.

28. The dimming panel according to any one of claims 25 to 27, wherein, The first substrate also includes a third shielding line; The third shielding line extends along the second sub-region, and both ends of the third shielding line extend to the first binding region and the second binding region, respectively; The other end of the first shielding wire is electrically connected to the third shielding wire.

29. The dimming panel according to claim 28, wherein, The first substrate further includes a third partition voltage signal line and a fourth partition voltage signal line located in the second sub-region; The third shielding line is located on the side of the third partition voltage signal line and the fourth partition voltage signal line away from the second electrode.

30. The dimming panel according to claim 28 or 29, wherein, The first substrate further includes a fifth pin, a sixth pin, a seventh pin, and an eighth pin; The fifth pin is located in the first bonding area, the sixth pin is located in the second bonding area, and the two ends of the second shielding wire are electrically connected to the fifth pin and the sixth pin, respectively. The seventh pin is located in the first bonding area, the eighth pin is located in the second bonding area, and the two ends of the third shielding wire are electrically connected to the seventh pin and the eighth pin, respectively. The fifth pin and the seventh pin are arranged at intervals along the first direction, and the fifth pin is farther away from the center line of the dimming panel along the second direction than the seventh pin; the sixth pin and the eighth pin are arranged at intervals along the first direction, and the sixth pin is farther away from the center line of the dimming panel along the second direction than the eighth pin.

31. The dimming panel according to any one of claims 5 to 7, wherein, The first sub-area is provided with a first binding area and a second binding area. The first binding area is located on one side of the first display area, and the second binding area is located on one side of the second display area. The first partition voltage signal line and the second partition voltage signal line are both provided in the first sub-area. The first partition voltage signal line extends to the first binding area, and the second partition voltage signal line extends to the second binding area. The functional area further includes a third display area and a fourth display area arranged side by side along the first direction, wherein the first display area and the third display, as well as the second display area and the fourth display area, are all arranged side by side along the second direction; the plurality of second electrodes further include a third partition electrode and a fourth partition electrode, wherein the third partition electrode is disposed in the third display area and the fourth partition electrode is disposed in the fourth display area; The second sub-area is provided with a third binding area and a fourth binding area. The third binding area is located on one side of the third display area, and the fourth binding area is located on one side of the fourth display area. The plurality of second voltage signal lines also include a third partition voltage signal line and a fourth partition voltage signal line provided in the second sub-area. The third partition voltage signal line extends to the third binding area, and the fourth partition voltage signal line extends to the fourth binding area. The third partition electrode is electrically connected to the third partition voltage signal line through the conductive part, and the fourth partition electrode is electrically connected to the fourth partition voltage signal line through the conductive part.

32. The dimming panel according to claim 31, wherein, The first substrate further includes: The first scan line extends along the first direction within the first display area, and multiple first scan lines are arranged at intervals along the second direction. The second scan line extends along the first direction within the second display area, and multiple second scan lines are arranged at intervals along the second direction; the first scan line and the second scan line are arranged at intervals along the first direction. The third scan line is provided extending along the first direction within the third display area, and multiple third scan lines are arranged at intervals along the second direction. The fourth scan line extends along the first direction within the fourth display area, and multiple fourth scan lines are arranged at intervals along the second direction; the third scan line and the fourth scan line are arranged at intervals in the first direction; The first sector output line is electrically connected to the first scan line, extends along the third sub-region, and extends to the first bonding region; The second fan-out line is electrically connected to the second scan line, extends along the fourth sub-region, and extends to the second bonding region; The third fan-out line is electrically connected to the third scan line, extends along the third sub-region, and extends to the third binding region; The fourth fan-out line is electrically connected to the fourth scan line, extends along the fourth sub-region, and extends to the fourth binding region.

33. The dimming panel according to claim 32, wherein, The second substrate further includes: A first regulating electrode, the orthographic projection of the first regulating electrode on the first substrate covers the first fan-out line; The second adjustment electrode, the orthogonal projection of the second adjustment electrode on the first substrate covers the second fan-out line; The third adjustment electrode, the orthographic projection of the third adjustment electrode on the first substrate covers the third fan-out line; The fourth adjustment electrode, the orthographic projection of which is on the first substrate covers the fourth fan-out line; The voltages of the first regulating electrode, the second regulating electrode, the third regulating electrode, and the fourth regulating electrode are all configured to switch between a first regulating voltage and a second regulating voltage. The non-operating voltages of the first fan-out line, the second fan-out line, the third fan-out line, and the fourth fan-out line are all greater than the first regulating voltage and less than the second regulating voltage.

34. The dimming panel according to claim 33, wherein, The first substrate further includes: A first adjustment signal line extends along the third sub-region and to the first bonding region; the first adjustment electrode is electrically connected to the first adjustment signal line through the conductive part; The second adjustment signal line extends along the fourth sub-region and extends to the second bonding region; the second adjustment electrode is electrically connected to the second adjustment signal line through the conductive part; The third adjustment signal line extends along the third sub-region and to the third bonding region; the third adjustment electrode is electrically connected to the third adjustment signal line through the conductive part; A fourth adjustment signal line extends along the fourth sub-region and to the fourth binding region; the fourth adjustment electrode is electrically connected to the fourth adjustment signal line through the conductive part.

35. The dimming panel according to claim 34, wherein, The second substrate further includes a ninth connecting portion, a tenth connecting portion, an eleventh connecting portion, and a twelfth connecting portion; The first adjustment electrode is electrically connected to the ninth connection portion, and the ninth connection portion is electrically connected to the first adjustment signal line through the conductive portion; The second adjustment electrode is electrically connected to the tenth connection portion, and the tenth connection portion is electrically connected to the second adjustment signal line through the conductive portion; The third adjustment electrode is electrically connected to the eleventh connection part, and the eleventh connection part is electrically connected to the third adjustment signal line through the conductive part; The fourth adjustment electrode is electrically connected to the twelfth connection portion, and the twelfth connection portion is electrically connected to the fourth adjustment signal line through the conductive portion; The ninth connecting portion and the eleventh connecting portion are disposed at intervals between the first adjusting electrode and the third adjusting electrode along the second direction; The tenth connecting portion and the twelfth connecting portion are disposed at intervals along the second direction between the second adjusting electrode and the fourth adjusting electrode.

36. The dimming panel according to any one of claims 31 to 35, wherein, The first substrate also includes a fourth shielding line and a fifth shielding line; The fourth shielding line extends along the second direction; the orthographic projection of the fourth shielding line on the second substrate is located between the first partition electrode and the second partition electrode, and between the third partition electrode and the fourth partition electrode, and has a distance from the first partition electrode, the second partition electrode, the third partition electrode, and the fourth partition electrode; The fifth shielding line extends along the first direction; the orthographic projection of the fifth shielding line on the second substrate is located between the first partition electrode and the third partition electrode, and between the second partition electrode and the fourth partition electrode, and has a gap with the first partition electrode, the second partition electrode, the third partition electrode, and the fourth partition electrode.

37. The dimming panel according to claim 36, wherein, The first substrate also includes a sixth shielding line and a seventh shielding line; The sixth shielding line extends at least along the third sub-region, and both ends of the sixth shielding line extend to the first bonding region and the third bonding region, respectively; The seventh shielding line extends at least along the fourth sub-region, and both ends of the seventh shielding line extend to the second bonding region and the fourth bonding region, respectively. The two ends of the fifth shielding wire are electrically connected to the sixth shielding wire and the seventh shielding wire, respectively.

38. The dimming panel according to claim 36 or 37, wherein, The first substrate also includes an eighth shielding line and a ninth shielding line; The eighth shielding line extends along the first sub-region, and both ends of the eighth shielding line extend to the first bonding region and the second bonding region, respectively; The ninth shielding line extends along the second sub-region, and both ends of the ninth shielding line extend to the third bonding region and the fourth bonding region, respectively; The two ends of the fourth shielding wire are electrically connected to the eighth shielding wire and the ninth shielding wire, respectively.

39. The dimming panel according to claim 38, wherein, The dimming panel includes a gate conductive layer, and the fourth shielding line, the eighth shielding line, and the ninth shielding line are all located in the gate conductive layer; and / or, The first substrate further includes a sixth shielding line and a seventh shielding line; the dimming panel includes a source-drain conductive layer, and the fifth shielding line, the sixth shielding line and the seventh shielding line are all located in the source-drain conductive layer.

40. The dimming panel according to any one of claims 14-23 and 33-35, wherein, The difference between the first regulated voltage and the non-operating voltage of the first fan-out line is equal to or approximately equal to the difference between the second regulated voltage and the non-operating voltage of the first fan-out line.

41. The dimming panel according to any one of claims 14-23, 33-35, wherein, The switching frequency of the first adjustment voltage and the second adjustment voltage is N times the display frequency of the dimming panel, where N is an integer greater than or equal to 1.

42. The dimming panel according to any one of claims 24-30 and 36-39, wherein, The second substrate further includes a black matrix layer having a plurality of openings, wherein at least a portion of the first electrode is projected onto the second substrate through one of the openings; The black matrix layer includes a first black matrix line, and the orthogonal projection of the first shielding line on the second substrate overlaps with the first black matrix line. The dimming panel is a transmissive display panel, and the width of the first shielding line is smaller than the width of the first black matrix line; or... The dimming panel is a semi-transparent and semi-reflective display panel, and the width of the first shielding line is greater than or equal to the width of the first black matrix line.

43. The dimming panel according to any one of claims 2 to 5, wherein, The number of first partition electrodes and second partition electrodes are both multiple, with multiple first partition electrodes arrayed in the first display area and multiple second partition electrodes arrayed in the second display area; The number of the first connecting portion and the number of the second connecting portions are both multiple, and the multiple first connecting portions and the multiple second connecting portions are disposed at intervals between each other in the peripheral area; The second substrate further includes multiple first transmission lines and multiple second transmission lines. A first partition electrode is electrically connected to a first connection portion via a first transmission line, and a second partition electrode is electrically connected to a second connection portion via a second transmission line. The number of the first partition voltage signal line and the second partition voltage signal line are both multiple. One first connection part is electrically connected to one first partition voltage signal line through the conductive part, and one second connection part is electrically connected to one second partition voltage signal line through the conductive part. The first partition voltage signal line is configured to provide the first common voltage signal required for display and the touch driving signal required for touch sensing to the corresponding first partition electrode in a time-division manner; the second partition voltage signal line is configured to provide the second common voltage signal required for display and the touch driving signal required for touch sensing to the corresponding second partition electrode in a time-division manner.

44. The dimming panel according to claim 43, wherein, The peripheral area includes a first sub-area, a second sub-area, a third sub-area, and a fourth sub-area. The first sub-area and the second sub-area are located on both sides of the functional area in the second direction, and the third sub-area and the fourth sub-area are located on both sides of the functional area in the first direction. The first direction is the row direction in which the plurality of second electrodes are arranged, and the second direction is the column direction in which the plurality of second electrodes are arranged. A plurality of the first connecting portions and a plurality of the second connecting portions are disposed in the first sub-region and arranged along the first direction; The second sub-area is provided with a first binding area and a second binding area, the first binding area is located on one side of the first display area, and the second binding area is located on one side of the second display area; Multiple first partition voltage signal lines extend along the third sub-region and extend to the first bonding region; multiple second partition voltage signal lines extend along the fourth sub-region and extend to the second bonding region.

45. The dimming panel according to any one of claims 1 to 44, wherein, The second substrate further includes a second substrate and a black matrix layer disposed on the substrate, the black matrix layer including a plurality of interwoven black matrix lines; The gap between two adjacent second electrodes is located on the side of the black matrix line away from the second substrate, and the width of the gap is smaller than the width of the black matrix line.

46. ​​The dimming panel according to claim 45, wherein, The second substrate further includes: Multiple filter sections, with multiple black matrix lines interwoven to form multiple openings, and one filter section located within one of the openings; A protective layer covers the black matrix layer and the plurality of filter sections on the side away from the second substrate; The plurality of second electrodes are located on the side of the protective layer away from the second substrate.

47. The dimming panel according to claim 1, wherein, The plurality of first electrodes and the plurality of second electrodes are all strip electrodes, and the orthographic projections of the plurality of second electrodes on the first substrate intersect with the plurality of first electrodes; The second substrate further includes a thirteenth connection portion and a fourteenth connection portion, which are located on both sides of the functional area in a third direction, the third direction being the extension direction of the second electrode; A portion of the plurality of second electrodes is electrically connected to the thirteenth connection portion, and another portion of the plurality of second electrodes is electrically connected to the fourteenth connection portion.

48. The dimming panel according to claim 47, wherein, The second electrode in the odd-numbered row is electrically connected to the thirteenth connection part, and the second electrode in the even-numbered row is electrically connected to the fourteenth connection part.

49. A display panel comprising a dimming panel as described in claims 1 to 46, and at least two driver chips electrically connected to the dimming panel.

50. A display device comprising a display panel as claimed in claim 49, and a backlight module disposed on one side of a first substrate of the display panel.

51. A liquid crystal lens, comprising the dimming panel as described in claims 1, 47, and 48.

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