Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a base substrate, a light-shielding layer, a buffer layer, an active layer, a gate insulating layer and a gate layer, which are stacked in sequence, wherein the light-shielding layer comprises a plurality of light-shielding portions arranged at intervals; the active layer comprises a first active portion, the first active portion comprises a first conductor portion, a first channel portion and a second conductor portion, which are connected in sequence, and the orthographic projection of at least the first channel portion on the base substrate is located within the orthographic projection of the light-shielding portions on the base substrate; and the gate layer comprises a first gate and a gate line connected to each other, the orthographic projection of the first channel portion on the base substrate is located within the orthographic projection of the first gate on the base substrate, and the gate line extends in a first direction. The array substrate has a relatively small parasitic capacitance.

Description

Array substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0002] In recent years, electronic devices have been widely used in people's daily lives. Display panels are an important component of electronic devices and serve as a crucial window for human-computer interaction. Display panels are generally driven by an array substrate. Low cost and high display performance are consistent goals for manufacturers.

[0003] However, the performance of current array substrates cannot meet many of the requirements.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate and a display device.

[0006] According to one aspect of this disclosure, an array substrate is provided, comprising:

[0007] Substrate;

[0008] A light-shielding layer is disposed on one side of the substrate, and the light-shielding layer includes a plurality of light-shielding portions disposed at intervals;

[0009] A buffer layer is disposed on the side of the light-shielding layer opposite to the substrate.

[0010] An active layer is disposed on the side of the buffer layer away from the substrate. The active layer includes a first active portion, which includes a first conductor portion, a first channel portion, and a second conductor portion connected in sequence. At least the orthographic projection of the first channel portion on the substrate is located within the orthographic projection of the light-shielding portion on the substrate.

[0011] A gate insulating layer is disposed on the side of the active layer opposite to the substrate.

[0012] A gate layer is disposed on the side of the gate insulating layer opposite to the substrate. The gate layer includes a first gate and a gate line that are interconnected. The orthogonal projection of the first channel portion on the substrate is located within the orthogonal projection of the first gate on the substrate. The gate line extends along a first direction.

[0013] In one exemplary embodiment of this disclosure, the first gate is electrically connected to the light-shielding portion.

[0014] In one exemplary embodiment of this disclosure, the light-shielding layer further includes:

[0015] The data cable extends along a second direction, which intersects with the first direction;

[0016] The first connecting part is connected to the data line;

[0017] The gate layer further includes:

[0018] The second connection portion is disposed at a distance from the first gate and the gate line. The second connection portion is connected to the second conductor portion and also connected to the first connection portion.

[0019] In an exemplary embodiment of this disclosure, a first via is provided on the buffer layer, the first via communicating with the first connecting portion; a second via is provided on the gate insulating layer, the second via including a first sub-via and a second sub-via communicating with each other, the first sub-via communicating with the first via, and the second via communicating with the second conductor portion; the second connecting portion includes:

[0020] The first sub-connecting part passes through the first sub-via and the first via and is connected to the first connecting part;

[0021] The second sub-connection portion passes through the second sub-via and is connected to the second conductor portion. The second sub-connection portion is connected to the first sub-connection portion.

[0022] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0023] An insulating layer group is disposed on the side of the gate layer opposite to the substrate.

[0024] The first electrode is disposed on the side of the insulating layer group away from the substrate.

[0025] A third insulating layer is disposed on the side of the first electrode away from the substrate.

[0026] The second electrode is disposed on the side of the third insulating layer opposite to the substrate.

[0027] The first electrode or the second electrode is electrically connected to the first conductor portion.

[0028] In an exemplary embodiment of this disclosure, the light-shielding portion is configured as a strip extending along a second direction, the first gate is configured as a strip extending along a second direction, the orthographic projection of the first gate on the substrate is located within the orthographic projection of the light-shielding portion on the substrate, the first active portion is configured as a strip extending along the first direction, and the orthographic projection of the first active portion on the substrate is located on the side of the orthographic projection of the gate line on the substrate closer to the second electrode.

[0029] In an exemplary embodiment of this disclosure, a first gate connection via is provided on the buffer layer, and the first gate connection via is connected to the light-shielding portion; a second gate connection via is provided on the gate insulating layer, and the second gate connection via communicates with the first gate connection via; the first gate is connected to the light-shielding portion through the first gate connection via and the second gate connection via.

[0030] In one exemplary embodiment of this disclosure, the first gate connection via and the second gate connection via are connected to one end of the first gate near the gate line.

[0031] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0032] An interlayer dielectric layer is disposed on the side of the gate layer opposite to the substrate, and a third via, a fourth via, a fifth via, and a sixth via are disposed on the interlayer dielectric layer;

[0033] A first connection conductor layer is disposed on the side of the interlayer dielectric layer facing away from the substrate. The first connection conductor layer includes a data line, a first connection conductor portion, a second connection conductor portion, and a third connection conductor portion. The data line extends along a second direction, which intersects with the first direction. The data line and the gate line divide the array substrate into multiple pixel regions. The first connection conductor portion is electrically connected to the first conductor portion through the third via. The second connection conductor portion is electrically connected to the second conductor portion through the fourth via 72. The second connection conductor portion is connected to the data line. The first end of the third connection conductor portion is connected to the first gate through the fifth via. The second end of the third connection conductor portion is connected to the light-shielding portion through the sixth via and the first gate connection via on the buffer layer.

[0034] A first electrode is disposed on the side of the first connecting conductor layer opposite to the substrate, and the first electrode is connected to the first conductor portion;

[0035] A first insulating layer is disposed on the side of the first electrode away from the substrate.

[0036] The second electrode is disposed on the side of the first insulating layer away from the substrate.

[0037] In an exemplary embodiment of this disclosure, the second electrode is a common electrode, and a plurality of slits arranged along the first direction are provided on the second electrode. The slits have first edge lines, which are the edge lines of the end of the slit near the first active portion. The plurality of first edge lines located in the same pixel area are not located on the same straight line extending along the first direction.

[0038] In one exemplary embodiment of this disclosure, within a pixel region, the distance between the first edge line and the gate line in the second direction decreases as the distance between the slit and the data line in the first direction increases, wherein the gate line and the data line are connected to a thin-film transistor controlling the pixel electrode of the pixel region.

[0039] In one exemplary embodiment of this disclosure, the distance between two adjacent first edge lines in the second direction is greater than or equal to 1 micrometer.

[0040] In one exemplary embodiment of this disclosure, the orthographic projection of the gate layer on the substrate does not overlap with the orthographic projection of the first electrode on the substrate.

[0041] In one exemplary embodiment of this disclosure, the orthographic projection of the slit on the substrate overlaps with the orthographic projection of the first gate on the substrate.

[0042] In one exemplary embodiment of this disclosure, the minimum distance between the orthographic projection of the gate layer on the substrate and the orthographic projection of the first electrode on the substrate is greater than or equal to 1 micrometer.

[0043] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0044] An interlayer dielectric layer is disposed on the side of the gate layer opposite to the substrate, and a plurality of third vias, fourth vias, fifth vias and sixth vias are disposed on the interlayer dielectric layer;

[0045] A first connection conductor layer is disposed on the side of the interlayer dielectric layer facing away from the substrate. The first connection conductor layer includes a data line, a first connection conductor portion, a second connection conductor portion, and a third connection conductor portion. The data line extends along a second direction, which intersects with the first direction. The data line and the gate line divide the array substrate into multiple pixel regions. The first connection conductor portion is electrically connected to the first conductor portion through the third via. The second connection conductor portion is electrically connected to the second conductor portion through the fourth via. The second connection conductor portion is connected to the data line. The first end of the third connection conductor portion is connected to the first gate through the fifth via. The second end of the third connection conductor portion is connected to the light-shielding portion through the sixth via and the first gate connection via on the buffer layer.

[0046] An insulating layer group is disposed on the side of the first connecting conductor layer opposite to the substrate.

[0047] The first electrode is disposed on the side of the insulating layer group away from the substrate.

[0048] A third insulating layer is disposed on the side of the first electrode away from the substrate.

[0049] The second electrode is disposed on the side of the third insulating layer opposite to the substrate.

[0050] The first electrode or the second electrode is electrically connected to the first connecting conductor portion.

[0051] In an exemplary embodiment of this disclosure, the first active portion, the first gate, the first connecting conductor portion, and the second connecting conductor portion constitute a first thin-film transistor, and the extending direction of the third connecting conductor portion is consistent with the extending direction of the first thin-film transistor.

[0052] In an exemplary embodiment of this disclosure, the first active portion is configured as a strip extending along a first direction, the first gate is configured as a strip extending along a second direction, the third connecting conductor portion is configured as a strip extending along the first direction, and the orthographic projection of the third connecting conductor portion on the substrate is located on the side of the orthographic projection of the first active portion on the substrate that is close to the orthographic projection of the gate line on the substrate. The light-shielding portion includes:

[0053] The first sub-shielding part is configured as a strip extending along a first direction, and the orthographic projection of the first active part on the substrate is located within the orthographic projection of the first sub-shielding part on the substrate.

[0054] The second sub-shielding part is connected to the side of the first sub-shielding part near the gate line. The orthographic projection of the second sub-shielding part on the substrate overlaps with the orthographic projection of the third connecting conductor on the substrate. The orthographic projection of the second sub-shielding part on the substrate does not overlap with the orthographic projection of the first gate on the substrate.

[0055] In an exemplary embodiment of this disclosure, the first active portion is configured as a strip extending along a first direction, the first gate is configured as a strip extending along a second direction, the third connecting conductor portion is configured as a strip extending along the first direction, and the orthographic projection of the third connecting conductor portion on the substrate is located on the side of the orthographic projection of the first active portion on the substrate that is close to the orthographic projection of the gate line on the substrate. The light-shielding portion includes:

[0056] The first sub-shielding portion is configured as a strip extending along the second direction. The orthographic projection of the first channel portion on the substrate is located within the orthographic projection of the first sub-shielding portion on the substrate. The orthographic projection of the first sub-shielding portion on the substrate does not overlap with the orthographic projections of the first connecting conductor portion and the second connecting conductor portion on the substrate.

[0057] The second sub-shielding part is connected to the side of the first sub-shielding part near the gate line. The orthographic projection of the second sub-shielding part on the substrate overlaps at least with the orthographic projection of the second end of the third connecting conductor on the substrate. The second sub-shielding part is electrically connected to the second end of the third connecting conductor.

[0058] In an exemplary embodiment of this disclosure, a portion of the gate line serves as a first gate, and the orthographic projections of the first and second connecting conductor portions on the substrate are located on opposite sides of a second direction in which the orthographic projection of the gate line on the substrate is directed, with the second connecting conductor portion being closer to the data line than the first connecting conductor portion; the third connecting conductor portion is configured as a strip extending along the second direction, and the third connecting conductor portion is located on the side of the first active portion opposite to the data line, the first active portion comprising:

[0059] The first part is configured as a strip extending in a second direction, and the first part includes the first conductor portion and the first channel portion;

[0060] The second part is connected to the side of the first part near the data line. The second part includes a second conductor portion. The orthographic projections of the first conductor portion and the second conductor portion on the substrate are located on opposite sides of the second direction of the orthographic projection of the gate line on the substrate.

[0061] The light-shielding part includes:

[0062] The first sub-shielding portion is configured as a strip extending along the second direction, and the orthographic projection of the first portion on the substrate is located within the orthographic projection of the first sub-shielding portion on the substrate.

[0063] The second sub-shielding part is connected to the side of the first sub-shielding part away from the data line. The orthographic projection of the second sub-shielding part on the substrate overlaps at least with the orthographic projection of the second end of the third connecting conductor on the substrate, but does not overlap with the orthographic projection of the gate line on the substrate. The second sub-shielding part is electrically connected to the second end of the third connecting conductor.

[0064] In one exemplary embodiment of this disclosure, the light-shielding portion further includes:

[0065] The third sub-shielding part is connected to the side of the first sub-shielding part near the data line. The orthographic projection of the second part on the substrate is located within the orthographic projection of the third sub-shielding part on the substrate, so that the orthographic projections of the third sub-shielding part and a part of the first sub-shielding part on the substrate are located on opposite sides of the second direction of the orthographic projection of the gate line on the substrate.

[0066] In one exemplary embodiment of this disclosure, the width of the first gate in the second direction is greater than the width of the gate line in the second direction.

[0067] In an exemplary embodiment of this disclosure, the first gate includes a gate functional portion and a gate connection portion connected sequentially in a first direction, wherein the width of the gate connection portion in the second direction is greater than the width of the gate functional portion in the second direction.

[0068] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0069] An interlayer dielectric layer is disposed on the side of the gate layer opposite to the substrate, and a third via and a fourth via are disposed on the interlayer dielectric layer;

[0070] A first connecting conductor layer is disposed on the side of the interlayer dielectric layer facing away from the substrate. The first connecting conductor layer includes a data line, a first connecting conductor portion, and a second connecting conductor portion. The data line extends along a second direction, which intersects with the first direction. The data line and the gate line divide the array substrate into multiple pixel regions. The first connecting conductor portion is electrically connected to the first conductor portion through the third via. The second connecting conductor portion is electrically connected to the second conductor portion through the fourth via. The second connecting conductor portion is connected to the data line.

[0071] A first electrode is disposed on the side of the first connecting conductor layer opposite to the substrate, and the first electrode is connected to the first conductor portion;

[0072] A first insulating layer is disposed on the side of the first electrode away from the substrate.

[0073] The second electrode is disposed on the side of the first insulating layer away from the substrate.

[0074] In an exemplary embodiment of this disclosure, the first active portion, the first gate, the first connecting conductor portion, and the second connecting conductor portion constitute a first thin-film transistor, wherein the extension direction of the first thin-film transistor is consistent with the extension direction of the gate line.

[0075] In an exemplary embodiment of this disclosure, the first active portion includes a first portion, a second portion, and a third portion connected sequentially in a first direction. The width of the first portion in the second direction is greater than the width of the second portion in the second direction, and the width of the third portion in the second direction is greater than the width of the second portion in the second direction. The edges of the first portion, the second portion, and the third portion near the gate line are collinear. The first gate is configured as a strip extending in the second direction. The first end of the first gate in the second direction protrudes from the first channel portion, and the second end of the first gate in the second direction is connected to the gate line.

[0076] In one exemplary embodiment of this disclosure, the light-shielding portion includes:

[0077] The first sub-shielding part is configured as a strip extending along a first direction, and the orthographic projection of the first active part on the substrate is located within the orthographic projection of the first sub-shielding part on the substrate.

[0078] The second sub-shielding part is connected to the side of the first sub-shielding part near the gate line. The orthographic projection of the second sub-shielding part on the substrate overlaps with the orthographic projection of the data line on the substrate and also overlaps with the orthographic projection of the gate line on the substrate, so that the corner of the shielding part away from the data line and near the gate line is provided with a cutout.

[0079] In one exemplary embodiment of this disclosure, the first connection conductor layer further includes:

[0080] The signal trace extends along the second direction and is located on one side of the data line in the first direction. One signal trace is provided in each of the pixel regions, or one signal trace is provided in two or more pixel regions.

[0081] In one exemplary embodiment of this disclosure, the array substrate has a non-display area, and in the non-display area, the array substrate further includes:

[0082] The second transistor includes a second gate, a second source, and a second drain. The second source is electrically connected to the functional traces in the display area and is also electrically connected to the second gate.

[0083] An electrostatic discharge trace is electrically connected to the second drain electrode;

[0084] The third transistor includes a third gate, a third source, and a third drain. The second source is electrically connected to the third source, the second drain is electrically connected to the third drain, and the third gate is electrically connected to the electrostatic discharge line.

[0085] In an exemplary embodiment of this disclosure, the active layer includes a second active portion and a third active portion. The second active portion includes a third conductor portion, a second channel portion, and a fourth conductor portion connected in sequence. The third active portion includes a fifth conductor portion, a third channel portion, and a sixth conductor portion connected in sequence.

[0086] The gate layer includes a second gate and a third gate, and an electrostatic discharge line. The orthographic projection of the second channel portion on the substrate is located within the orthographic projection of the second gate portion on the substrate. The orthographic projection of the third channel portion on the substrate is located within the orthographic projection of the third gate portion on the substrate.

[0087] The first connection conductor layer includes a second drain and a second source, a third drain and a third source, the third source and the second source being directly connected to the data line as a whole, the second drain and the third drain being directly connected as a whole, and the third gate being directly connected to the electrostatic discharge trace as a whole.

[0088] According to another aspect of this disclosure, a display device is provided, comprising:

[0089] The array substrate is any one of the array substrates described above.

[0090] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0091] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0092] Figure 1 is a schematic diagram of the structure of a first example embodiment of the array substrate disclosed herein.

[0093] Figure 2 is a schematic diagram of the structure of a second exemplary embodiment of the array substrate disclosed herein.

[0094] Figure 3 is a schematic diagram of the structure of a third exemplary embodiment of the array substrate disclosed herein.

[0095] Figure 4 is a top view of the array substrate in Figure 1.

[0096] Figure 5 is a schematic diagram of the structure of the light-shielding layer in Figure 4.

[0097] Figure 6 is a schematic diagram of the gate layer in Figure 4.

[0098] Figure 7 is a top view of an example embodiment of the array substrate in Figure 2.

[0099] Figure 8 is a schematic diagram of the structure after removing the first and second electrodes from the schematic diagram in Figure 7.

[0100] Figure 9 is a schematic diagram of the structure of the light-shielding layer in Figure 7.

[0101] Figure 10 is a schematic diagram of the active layer in Figure 7.

[0102] Figure 11 is a schematic diagram of the gate layer in Figure 7.

[0103] Figure 12 is a schematic diagram of the structure of the first connecting conductor layer in Figure 7.

[0104] Figure 13 is a schematic cross-sectional view of the section cut according to section AA in Figure 8.

[0105] Figure 14 is a schematic diagram of the structure of the first electrode in Figure 7.

[0106] Figure 15 is a schematic diagram of the structure of the second electrode in Figure 7.

[0107] Figure 16 is a top view of another example embodiment of the array substrate in Figure 2.

[0108] Figure 17 is a schematic diagram of the structure after removing the first and second electrodes from the schematic diagram in Figure 16.

[0109] Figure 18 is a schematic diagram of the structure of the light-shielding layer in Figure 16.

[0110] Figure 19 is a schematic diagram of the active layer in Figure 16.

[0111] Figure 20 is a schematic diagram of the gate layer in Figure 16.

[0112] Figure 21 is a schematic diagram of the structure of the first connecting conductor layer in Figure 16.

[0113] Figure 22 is a top view of another exemplary embodiment of the array substrate in Figure 2 after removing the first and second electrodes.

[0114] Figure 23 is a top view of the array substrate in Figure 3.

[0115] Figure 24 is a schematic diagram of the structure after removing the first and second electrodes from the schematic diagram in Figure 23.

[0116] Figure 25 is a schematic diagram of the structure of the light-shielding layer in Figure 23.

[0117] Figure 26 is a schematic diagram of the active layer in Figure 23.

[0118] Figure 27 is a schematic diagram of the gate layer in Figure 23.

[0119] Figure 28 is a schematic diagram of the structure of the first connecting conductor layer in Figure 23.

[0120] Figure 29 is a schematic diagram of the structure of the first electrode in Figure 23.

[0121] Figure 30 is a schematic diagram of the structure of the second electrode in Figure 23.

[0122] Figure 31 is a schematic diagram of a first example embodiment of the equivalent circuit of the array substrate in the non-display area of ​​this disclosure.

[0123] Figure 32 is a schematic diagram of a second example embodiment of the equivalent circuit of the array substrate in the non-display area of ​​this disclosure.

[0124] Figure 33 is a schematic diagram of the structure of the array substrate of this disclosure in the non-display area.

[0125] Figure 34 is a top view of Figure 33.

[0126] Figure 35 is a schematic diagram of the active layer in Figure 34.

[0127] Figure 36 is a schematic diagram of the gate layer in Figure 34.

[0128] Figure 37 is a schematic diagram of the structure of the first connecting conductor layer in Figure 34.

[0129] Figure 38 is a comparison curve of the transfer characteristics of the first thin-film transistor in the array substrate of this disclosure and the thin-film transistor in the prior art.

[0130] Figure 39 is a top view of another example embodiment of the array substrate in Figure 2 after removing the first and second electrodes.

[0131] Figure 40 is a schematic diagram of the structure of the light-shielding part in Figure 39.

[0132] Figure 41 is a schematic diagram of the structure of the first active part in Figure 39.

[0133] Figure 42 is a top view of another example embodiment of the array substrate in Figure 2 after removing the first and second electrodes.

[0134] Figure 43 is a schematic diagram of the structure of the light-shielding part in Figure 42.

[0135] Explanation of reference numerals in the attached drawings: 1. Substrate; 2. Light-shielding layer; 21. Light-shielding portion; 211. First sub-light-shielding portion; 212. Second sub-light-shielding portion; 213. Third sub-light-shielding portion; 22. First connecting portion; 3. Buffer layer; 31. First via; 32. First gate connection via; 4. Active layer; 41. First active portion; 41a. First part; 41b. Second part; 41c. Third part; 411. First conductor part; 412. First channel part; 413. Second conductor part; 42. Second active portion; 421. Third conductor part; 422. Second channel part; 423. Fourth conductor part; 43. Third active portion; 431. Fifth conductor part; 432. Third channel part; 433. Sixth conductor part; 5. Gate insulating layer; 51. Second via; 511. First sub-via; 512. Second sub-via; 52. 6. Gate layer; 61. First gate; 611. Gate functional part; 612. Gate connection part; 62. Second connection part; 621. First sub-connection part; 622. Second sub-connection part; 63. Second gate; 64. Third gate; 7. Interlayer dielectric layer; 71. Third via; 72. Fourth via; 73. Fifth via; 74. Sixth via; 8. First connecting conductor layer; 81. First connecting conductor part; 82. Second connecting conductor part; 83. Third connecting conductor part; 84. Signal trace; 85. Second source; 86. Second drain; 87. Third source; 88. Third drain; 9. Insulating layer group; 91. First insulating layer; 911. Seventh via; 92. Second insulating layer; 921. Eighth via; 10. First electrode; 11. Third insulating layer; 12. Second electrode; 121. Slit; 1211. First edge line; Data; Gate; COM; TFT1. First transistor; TFT2. Second transistor; TFT3. Third transistor; X. First direction; Y. Second direction. Detailed Implementation

[0136] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0137] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0138] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0139] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0140] This disclosure provides an array substrate, as shown in Figures 1-38. The array substrate may include a substrate 1, a light-shielding layer 2, a buffer layer 3, an active layer 4, a gate insulating layer 5, and a gate layer 6. The light-shielding layer 2 is disposed on one side of the substrate 1 and includes a plurality of spaced-apart light-shielding portions 21. The buffer layer 3 is disposed on the side of the light-shielding layer 2 away from the substrate 1. The active layer 4 is disposed on the side of the buffer layer 3 away from the substrate 1 and includes a first active portion 41. The first active portion 41 includes a first conductor portion 411 and a second active portion 411 connected in sequence. A channel portion 412 and a second conductor portion 413 are provided, and at least the orthographic projection of the first channel portion 412 on the substrate 1 is located within the orthographic projection of the light-shielding portion 21 on the substrate 1. A gate insulating layer 5 is disposed on the side of the active layer 4 away from the substrate 1. A gate layer 6 is disposed on the side of the gate insulating layer 5 away from the substrate 1. The gate layer 6 includes a first gate 61 and a gate line that are interconnected. The orthographic projection of the first channel portion 412 on the substrate 1 is located within the orthographic projection of the first gate 61 on the substrate 1. The gate line extends along the first direction X.

[0141] The array substrate disclosed herein includes, on the one hand, a light-shielding layer 2 that may include a plurality of spaced-apart light-shielding portions 21, meaning that adjacent light-shielding portions 21 are not connected and are separated by gaps; this prevents signals from communicating between the various light-shielding portions 21, thereby ensuring that the thin-film transistors do not interfere with each other. On the other hand, it minimizes the overlap area between the light-shielding portions 21 and other conductive film layers, thereby minimizing the parasitic capacitance between the light-shielding portions 21 and other conductive film layers, thus ensuring the electrical performance of the thin-film transistors.

[0142] In this exemplary embodiment, the material of the substrate 1 may include inorganic materials, such as glass, quartz, or metal. The material of the substrate 1 may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed from multiple material layers; for example, the substrate 1 may include multiple substrate layers, and the substrate layers may be made of any of the materials described above. Of course, the substrate 1 may also be a single layer, and may be any of the materials described above.

[0143] Referring to Figures 1-3, a light-shielding layer 2 can be disposed on one side of the substrate 1. Light rays entering the active layer 4 from the substrate 1 will generate photogenerated carriers in the active layer 4, which will have a significant impact on the characteristics of the thin-film transistor and ultimately affect the display quality of the display device. The light-shielding layer 2 can block the light rays entering from the substrate 1, thereby avoiding the impact on the characteristics of the thin-film transistor and the display quality of the display device. The thickness of the light-shielding layer 2 is greater than or equal to 2500 angstroms and less than or equal to 4500 angstroms. For example, the thickness of the light-shielding layer 2 can be 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, etc.

[0144] Referring to Figures 5, 9, 18, and 25, the light-shielding layer 2 may include a plurality of spaced-apart light-shielding portions 21, that is, there is no connection between adjacent light-shielding portions 21 and a gap is provided; so that the signals between each light-shielding portion 21 will not be interconnected, thereby ensuring that the thin-film transistors will not interfere with each other; and the overlap area between the light-shielding portion 21 and other conductive film layers is minimized, thereby minimizing the parasitic capacitance between the light-shielding portion 21 and other conductive film layers, so as to ensure the electrical performance of the thin-film transistors.

[0145] The light-shielding part 21 may be provided with a hollow part, thereby further reducing the overlap area between the light-shielding part 21 and other conductive film layers, and further reducing the parasitic capacitance between the light-shielding part 21 and other conductive film layers, so as to ensure the electrical performance of the thin film transistor.

[0146] It should be noted that the cutout portion can be a hole or opening extending from one surface of the light-shielding portion 21 to another. That is, the cutout portion can be a hole whose outer perimeter is surrounded by the light-shielding portion 21. The cutout portion can also be an opening, notch, or recessed structure that is not surrounded by the light-shielding portion 21 on one or both sides. These cutout portions can be regular geometric shapes, such as circles or squares, or they can be complex patterns or irregular patterns.

[0147] Referring to Figures 1-3, a buffer layer 3 can be formed on the side of the light-shielding layer 2 facing away from the substrate 1. The buffer layer 3 serves to block water vapor and impurity ions in the substrate 1 (especially organic materials) and to increase hydrogen ions for the subsequently formed active layer 4. The buffer layer 3 is made of an insulating material to insulate the light-shielding layer 2 from the active layer 4. The buffer layer 3 may include silicon nitride, silicon oxide, or silicon oxynitride. The thickness of the buffer layer 3 is greater than or equal to 2000 angstroms and less than or equal to 4500 angstroms. For example, the thickness of the buffer layer 3 may be 2200 angstroms, 2500 angstroms, 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, etc.

[0148] Referring to Figures 1-3, an active layer 4 is provided on the side of the buffer layer 3 facing away from the substrate 1. The active layer 4 may include a first active portion 41. The first active portion 41 may include a first conductor portion 411, a first channel portion 412, and a second conductor portion 413 connected in sequence. At least the orthographic projection of the first channel portion 412 on the substrate 1 is located within the orthographic projection of the light-shielding portion 21 on the substrate 1. For example, it may be that only the orthographic projection of the first channel portion 412 on the substrate 1 is located within the orthographic projection of the light-shielding portion 21 on the substrate 1, or it may be that not only the orthographic projection of the first channel portion 412 on the substrate 1 is located within the orthographic projection of the light-shielding portion 21 on the substrate 1, but also part or all of the orthographic projections of the first conductor portion 411 and the second conductor portion 413 on the substrate 1 are located within the orthographic projection of the light-shielding portion 21 on the substrate 1. The light-shielding part 21 can block the first channel part 412, preventing light from entering the first channel part 412 from the substrate 1, thereby avoiding affecting the characteristics of the thin film transistor and ensuring the display quality of the display device.

[0149] The active layer 4 can be made of IGZO (Indium Gallium Zinc Oxide). The thickness of the active layer 4 is greater than or equal to 800 angstroms and less than or equal to 1500 angstroms. For example, the thickness of the active layer 4 can be 850 angstroms, 900 angstroms, 950 angstroms, 1000 angstroms, 1050 angstroms, 1100 angstroms, 1150 angstroms, 1200 angstroms, 1250 angstroms, 1300 angstroms, 1350 angstroms, 1400 angstroms, 1450 angstroms, etc.

[0150] The main types of thin-film transistors are LTPS (Low Temperature Poly-Silicon), Oxide, and a-Si (amorphous silicon), primarily distinguished by the material of the active layer 4. They correspond to different electron mobilities, with the former generally being 10 times higher than the latter, to accommodate different product specifications. See Table 1 for the main characteristics of the three types of thin-film transistors.

[0151] Table 1

[0152] IGZO is an amorphous oxide containing indium, gallium, and zinc. It can greatly improve the charging and discharging rate of the pixel electrode in thin-film transistors (TFTs), improve the pixel response speed, and achieve a faster refresh rate. At the same time, the faster response also greatly improves the pixel's line scan rate, making ultra-high resolution possible in liquid crystal display panels.

[0153] Based on the overall performance of various displays, oxide thin-film transistor (OTT) technology exhibits the best performance, offering relatively high resolution while maintaining both low refresh rates and high refresh frequencies, as well as a wide frequency range (10Hz–480Hz). Furthermore, OTT technology boasts advantages such as fewer mask etching processes and lower costs, giving it a significant competitive edge in the market and making it a key area for future development.

[0154] However, as can be seen from the table above, the mobility of these three thin-film transistors is within 1 cm⁻¹. 2 / vs to 10cm 2 / vs, then to 100cm 2 / vs, The span is too large, lacking the middle 50cm 2 The left and right transitions of / vs result in obvious defects in product display performance, failing to meet various needs.

[0155] Referring to Figures 1-3, a gate insulating layer 5 is provided on the side of the active layer 4 away from the substrate 1. The thickness of the gate insulating layer 5 is greater than or equal to 1500 angstroms and less than or equal to 3000 angstroms. For example, the thickness of the gate insulating layer 5 can be 1800 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms, 2700 angstroms, etc.

[0156] Referring to Figures 1-3, a gate layer 6 is disposed on the side of the gate insulating layer 5 facing away from the substrate 1. The gate layer 6 may include a first gate 61 and a gate line connected to each other. The gate line extends along a first direction X. The thickness of the gate layer 6 is greater than or equal to 3000 angstroms and less than or equal to 4500 angstroms. For example, the thickness of the gate layer 6 may be 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, etc.

[0157] The orthographic projection of the first channel portion 412 on the substrate 1 lies within the orthographic projection of the first gate 61 on the substrate 1. The active layer 4 is fabricated by doping the active material layer using the first gate 61 as a shield. The portion shielded by the first gate 61 remains undoped and is still a semiconductor, forming the first channel portion 412. The portion not shielded by the first gate 61 is doped to form a conductor, forming the first conductor portion 411 and the second conductor portion 413.

[0158] The first gate 61 can be electrically connected to the light-shielding part 21, so that the gate signal transmitted through the gate line can be transmitted not only to the first gate 61, but also to the light-shielding part 21. This results in a gate signal on the side of the first channel part 412 closest to the substrate 1, and a gate signal on the side of the first channel part 412 away from the substrate 1. That is, the first gate 61 and the light-shielding part 21 form a dual-gate structure. When the thin film transistor (TFT) is working, the gate turn-on capability can be greatly improved, and the on-state current Ion of the thin film transistor can be greatly improved. The measured mobility can reach 50 cm⁻¹. 2 / v·s is five times that of ordinary oxide thin film transistors, thus filling the mobility gap between oxide thin film transistors and low-temperature polycrystalline silicon thin film transistors, enabling thin film transistors to be used in conjunction with other thin film transistors to meet different product specification requirements.

[0159] In some exemplary embodiments of this disclosure, referring to Figures 1, 4 and 5, where the first electrode 10 is not shown in Figure 4, the light-shielding layer 2 may also include a data line Data and a first connection portion 22; the data line Data extends along the second direction Y, and the first connection portion 22 is connected to the data line Data. The first connection portion 22 may be a part of the data line Data, except that the width of the first connection portion 22 in the first direction X is greater than the width of the data line Data in the first direction X, so as to facilitate the connection between the first connection portion 22 and the second connection portion 62.

[0160] It should be noted that both the first direction X and the second direction Y are parallel to the side of the substrate 1 where the light-shielding layer 2 is disposed, and the second direction Y intersects with the first direction X. For example, the second direction Y is perpendicular to the first direction X.

[0161] In this case, referring to Figures 1, 4, and 6, the gate layer 6 may further include a second connection portion 62. The second connection portion 62 is spaced apart from the first gate 61 and the gate line, meaning that the second connection portion 62 is not connected to either the first gate 61 or the gate line, and gaps are provided between the second connection portion 62 and both the first gate 61 and the gate line. The second connection portion 62 is connected to the second conductor portion 413 and also to the first connection portion 22. That is, the second conductor portion 413 is connected to the first connection portion 22 through the second connection portion 62, and the first connection portion 22 is connected to the data line Data. Thus, the second conductor portion 413 is connected to the data line Data through the second connection portion 62 and the first connection portion 22, and the data signal transmitted through the data line Data can be transmitted to the second conductor portion 413 through the first connection portion 22 and the second connection portion 62.

[0162] By setting the data cable Data and the first connecting part 22 and the light-shielding part 21 in the same layer and with the same material, that is, the data cable Data and the first connecting part 22 and the light-shielding part 21 are made of the same material, and the data cable Data and the first connecting part 22 and the light-shielding part 21 are formed through the same patterning process, one patterning process can be reduced, thereby reducing costs and improving efficiency.

[0163] Alternatively, as shown in Figures 1 and 4, a first through hole 31 is provided on the buffer layer 3, and the first through hole 31 is connected to the first connecting part 22, that is, the first connecting part 22 is not covered by the buffer layer 3 at the position of the first through hole 31.

[0164] A second via 51 is provided on the gate insulating layer 5. The second via 51 may include a first sub-via 511 and a second sub-via 512 that are interconnected. The first sub-via 511 is connected to the first via 31, meaning that the first connecting portion 22 is not covered by the gate insulating layer 5 at the locations of the first sub-via 511 and the first via 31. The orthographic projection of the first via 31 on the substrate 1 does not overlap with the orthographic projection of the active layer 4 on the substrate 1. The first via 31 may be provided along the edge of the second conductor portion 413. The second sub-via 512 is connected to the second conductor portion 413, meaning that the second conductor portion 413 is not covered by the gate insulating layer 5 at the location of the second sub-via 512. In other words, the second via 51 is located at the edge of the second conductor portion 413, with a portion of the second via 51 exposing the second conductor portion 413 and another portion exposing the first connecting portion 22. This configuration avoids the need for vias on the active layer 4, reducing one patterning process and thus lowering costs and improving efficiency. Furthermore, as the active layer 4 is a critical component of the thin-film transistor, avoiding vias on it prevents damage to the structure and electrical performance of the active layer 4 during via formation, thereby ensuring the electrical performance of the thin-film transistor.

[0165] Referring to Figures 1 and 4, the second connecting portion 62 may include a first sub-connecting portion 621 and a second sub-connecting portion 622; the first sub-connecting portion 621 passes through the first sub-via 511 and the first via 31 and is connected to the first connecting portion 22; the second sub-connecting portion 622 passes through the second sub-via 512 and is connected to the second conductor portion 413, and the second sub-connecting portion 622 is connected to the first sub-connecting portion 621. That is, a part of the second connecting portion 62 overlaps with the second conductor portion 413, and another part of the second connecting portion 62 overlaps with the first connecting portion 22, thereby enabling the second conductor portion 413 to be electrically connected to the first connecting portion 22.

[0166] The length of the second via 51 in the first direction X is greater than or equal to 6 micrometers, and the width of the second via 51 in the second direction Y is greater than or equal to 4 micrometers.

[0167] Of course, in some other exemplary embodiments of this disclosure, a via may also be provided on the second conductor portion 413, so that the second connecting portion 62 is connected to the second conductor portion 413 through the second via 51, and the second connecting portion 62 is then connected to the first connecting portion 22 through the via on the second conductor portion 413 and the first via 31 on the gate insulating layer 5, which can also enable the second conductor portion 413 and the first connecting portion 22 to be electrically connected.

[0168] The light-shielding part 21, the active layer 4, and the first gate 61 constitute a dual-gate thin-film transistor.

[0169] Referring to Figures 1 and 4, in this exemplary embodiment, the array substrate may further include an insulating layer group 9, a first electrode 10, a third insulating layer 11, and a second electrode 12. The insulating layer group 9 is disposed on the side of the gate layer 6 facing away from the substrate 1. The insulating layer group 9 may include a first insulating layer 91 and a second insulating layer 92. The thickness of the first insulating layer 91 is greater than or equal to 1500 angstroms and less than or equal to 3500 angstroms; for example, the thickness of the first insulating layer 91 may be 1800 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms, 2700 angstroms, 3000 angstroms, 3300 angstroms, etc. The material of the first insulating layer 91 may be an inorganic material; for example, the material of the first insulating layer 91 may be silicon nitride, silicon oxide, silicon oxynitride, etc. The thickness of the second insulating layer 92 is greater than or equal to 20,000 angstroms and less than or equal to 30,000 angstroms. For example, the thickness of the second insulating layer 92 can be 22,000 angstroms, 23,500 angstroms, 25,000 angstroms, 27,000 angstroms, 28,500 angstroms, etc. The material of the second insulating layer 92 can be an organic material, such as resin materials like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate.

[0170] The first electrode 10 is disposed on the side of the insulating layer group 9 facing away from the substrate 1. The first electrode 10 is made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The thickness of the first electrode 10 is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms. For example, the thickness of the first electrode 10 can be 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, etc.

[0171] The third insulating layer 11 is disposed on the side of the first electrode 10 facing away from the substrate 1. The material of the third insulating layer 11 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The thickness of the third insulating layer 11 is greater than or equal to 2000 angstroms and less than or equal to 4500 angstroms. For example, the thickness of the third insulating layer 11 can be 2200 angstroms, 2500 angstroms, 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4300 angstroms, etc.

[0172] The second electrode 12 is disposed on the side of the third insulating layer 11 facing away from the substrate 1. The material of the second electrode 12 is a transparent conductive material. For example, the material of the second electrode 12 can be indium-tin-oxide (ITO), indium-zinc oxide (IZO), etc. The thickness of the second electrode 12 is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms. For example, the thickness of the second electrode 12 can be 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, etc.

[0173] The second electrode 12 is a pixel electrode, and the first electrode 10 is a common electrode. The second electrode 12 is electrically connected to the first conductor portion 411. Specifically, the second electrode 12 is electrically connected to the first conductor portion 411 through the third insulating layer 11, the second insulating layer 92, the first insulating layer 91, and vias on the gate insulating layer 5, so that the second electrode 12 can be energized by the dual-gate thin-film transistor composed of the light-shielding portion 21, the active layer 4, and the first gate 61. The first electrode 10 is electrically connected to the common line COM.

[0174] The vias on the gate insulating layer 5 have a side length or diameter greater than or equal to 4 micrometers and are formed through a single patterning process. The vias on the first insulating layer 91 and the third insulating layer 11 have a side length or diameter 1 micrometer larger than the vias on the gate insulating layer 5, and the vias on the first insulating layer 91 and the third insulating layer 11 are formed into the seventh via 911 through the same patterning process. The vias on the second insulating layer 92 have a side length or diameter 1.5 micrometers larger than the vias on the first insulating layer 91, and the vias on the second insulating layer 92 are formed into the eighth via 921 through a single patterning process.

[0175] The above describes the situation where the gate insulating layer 5 is basically a full-layer coverage. In the case where the gate insulating layer 5 is not a full-layer coverage, that is, when the gate insulating layer 5 is only provided on the side of the first gate 61 close to the substrate 1, it is not necessary to provide a via for connecting the second electrode 12 on the gate insulating layer 5.

[0176] Of course, in other exemplary embodiments of this disclosure, the first electrode 10 may be a pixel electrode, the second electrode 12 may be a common electrode, and the first electrode 10 may be electrically connected to the first conductor portion 411. Specifically, the first electrode 10 is electrically connected to the first conductor portion 411 through the second insulating layer 92 and vias on the first insulating layer 91, so that the dual-gate thin-film transistor composed of the light-shielding portion 21, the active layer 4, and the first gate 61 can control whether the first electrode 10 is energized. The second electrode 12 is electrically connected to the common line COM.

[0177] Alternatively, referring to Figures 4, 5, and 6, the light-shielding portion 21 is configured as a strip extending along the second direction Y, and the light-shielding portion 21 is disposed substantially parallel to the data line Data. The first gate 61 is configured as a strip extending along the second direction Y, and the first gate 61 is substantially perpendicularly connected to the gate line Gate. The orthographic projection of the first gate 61 on the substrate 1 is located within the orthographic projection of the light-shielding portion 21 on the substrate 1. Specifically, in the first direction X, the two edges of the orthographic projection of the first gate 61 on the substrate 1 correspond one-to-one with the two edges of the orthographic projection of the light-shielding portion 21 on the substrate 1, and the distance between them is greater than or equal to 2 micrometers. On the side of the second direction Y near the second electrode 12, the edges of the orthographic projection of the first gate 61 on the substrate 1 and the edges of the orthographic projection of the light-shielding portion 21 on the substrate 1 are substantially coincident. On the side of the second direction Y near the gate line, the orthographic projection of the light-shielding portion 21 on the substrate 1 overlaps with the orthographic projection of the gate line on the substrate 1, that is, the light-shielding portion 21 extends to the side of the gate line near the substrate 1, that is, the light-shielding portion 21 extends to the lower side of the gate line.

[0178] Referring to FIG4, the first active portion 41 is configured as a strip extending along the first direction X. The length of the first channel portion 412 in the first direction X is greater than or equal to 5 micrometers, and the width of the first channel portion 412 in the second direction Y is greater than or equal to 4 micrometers. The width of the first gate 61 in the first direction X is substantially the same as the width of the first channel portion 412 in the first direction X; therefore, the width of the first gate 61 in the first direction X is also greater than or equal to 5 micrometers. The first gate 61 protrudes beyond the first channel portion 412 in the second direction Y, and the protrusion of the first gate 61 beyond the first channel portion 412 in the second direction Y is greater than or equal to 2.5 micrometers. Furthermore, combining the above dimensions, the width of the light-shielding portion 21 in the first direction X is greater than or equal to 9 micrometers. The orthographic projection of the first active portion 41 on the substrate 1 is located on the side of the orthographic projection of the gate line on the substrate 1 closest to the second electrode 12. That is, in the top view, the first active portion 41 is located between the second electrode 12 (excluding the portion connected to the first active portion 41) and the gate line.

[0179] In this example embodiment, referring to FIG4, a first gate connection via 32 is provided on the buffer layer 3, which is connected to the light-shielding part 21. That is, at the location of the first gate connection via 32, the buffer layer 3 does not cover the light-shielding part 21, leaving the light-shielding part 21 exposed. A second gate connection via 52 is provided on the gate insulating layer 5, which connects to the first gate connection via 32. That is, at the locations of the first gate connection via 32 and the second gate connection via 52, the light-shielding part 21 is not covered by the gate insulating layer 5. The first gate 61 is connected to the light-shielding part 21 through the first gate connection via 32 and the second gate connection via 52, thereby realizing the electrical connection between the first gate 61 and the light-shielding part 21. That is, the first gate 61 and the light-shielding part 21 are directly connected to realize a dual-gate structure, which greatly improves the on-state current Ion of the thin-film transistor and reduces the transmission path of the gate signal, thus reducing the attenuation of the gate signal.

[0180] Alternatively, referring to FIG4, the first gate connection via 32 and the second gate connection via 52 are connected to the end of the first gate 61 near the gate line, that is, the orthogonal projection of the first gate connection via 32 and the second gate connection via 52 on the substrate 1 is located at the end of the orthogonal projection of the first gate 61 on the substrate 1 near the gate line. This avoids opening a hole on the side near the second electrode 12, which would affect the planarization of the base layer forming the second electrode 12, thus ensuring the planarization of the base layer forming the second electrode 12.

[0181] The first gate 61 is directly connected to the light-shielding portion 21, eliminating the need for connection via the third connecting conductor portion 83 in the first connecting conductor layer 8. This reduces the width of the black matrix to be subsequently formed in the second direction Y by more than 50%, effectively improving the pixel aperture ratio and thus increasing pixel transmittance. Furthermore, the absence of the first connecting conductor layer 8 allows the second electrode 12 to be directly connected to the first conductor portion 411, significantly reducing the overlap capacitance between the gate layer 6 and other layers, saving over 50% of the load, improving charging capability, and significantly reducing the overall power consumption of the array substrate.

[0182] Referring to Figures 2 and 8, in some exemplary embodiments of this disclosure, the array substrate may further include an interlayer dielectric layer 7, a first interconnect conductor layer 8, a first electrode 10, a first insulating layer 91, and a second electrode 12. The interlayer dielectric layer 7 is disposed on the side of the gate layer 6 facing away from the substrate 1, and a third via 71, a fourth via 72, a fifth via 73, and a sixth via 74 are disposed on the interlayer dielectric layer 7; the thickness of the interlayer dielectric layer 7 is greater than or equal to 3000 angstroms and less than or equal to 4500 angstroms, for example, the thickness of the interlayer dielectric layer 7 may be 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, etc.

[0183] The first connecting conductor layer 8 is disposed on the side of the interlayer dielectric layer 7 away from the substrate 1. The thickness of the first connecting conductor layer 8 is greater than or equal to 3000 angstroms and less than or equal to 4500 angstroms. For example, the thickness of the first connecting conductor layer 8 can be 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, etc.

[0184] Referring to Figures 2, 7, 8, 12, and 13, the first connecting conductor layer 8 may include a data line Data, a first connecting conductor portion 81, a second connecting conductor portion 82, and a third connecting conductor portion 83. The data line Data extends along the second direction Y, and the data line Data and the gate line Gate divide the array substrate into multiple pixel regions. The first connecting conductor portion 81 is electrically connected to the first conductor portion 411 through a third via 71, and the second connecting conductor portion 82 is electrically connected to the second conductor portion 413 through a fourth via 72. The second connecting conductor portion 82 is connected to the data line Data; data signals can be transmitted to the second connecting conductor portion 82 through the data line Data. The second connecting conductor portion 82 may also be a part of the data line Data. The first end of the third connecting conductor portion 83 is connected to the first gate 61 through the fifth via 73. The second end of the third connecting conductor portion 83 is connected to the light-shielding portion 21 through the sixth via 74 and the first gate connection via 32 on the buffer layer 3. When the gate insulating layer 5 is basically a full layer coverage, the second end of the third connecting conductor portion 83 also needs to be connected to the light-shielding portion 21 through the via on the gate insulating layer 5. This allows the light-shielding portion 21 and the first gate 61 to be indirectly connected through the third connecting conductor portion 83, thereby realizing a dual-gate structure to significantly improve the on-state current Ion of the thin-film transistor.

[0185] The spacing between the fifth via 73 and the sixth via 74 is greater than or equal to 4 micrometers. The third connecting conductor portion 83 completely covers the fifth via 73 and the sixth via 74. The spacing between the edge of the third connecting conductor portion 83 and the edge of the fifth via 73 and the sixth via 74 is greater than or equal to 1.5 micrometers. Even if the third connecting conductor portion 83 is offset, it can still be ensured that the third connecting conductor portion 83 is connected to the first gate 61 through the fifth via 73 and connected to the light-shielding portion 21 through the sixth via 74 and the first gate connection via 32 on the buffer layer 3.

[0186] Furthermore, the first gate 61 completely covers the fifth via 73, and the distance between the edge line of the first gate 61 and the edge line of the fifth via 73 is greater than or equal to 3 micrometers. Even if the fifth via 73 is offset, the third connecting conductor portion 83 can be connected to the first gate 61 through the fifth via 73.

[0187] Referring to FIG2, the first electrode 10 is disposed on the side of the first connecting conductor layer 8 facing away from the substrate 1. The material and thickness of the first electrode 10 can be the same as those in the above example embodiment, and will not be repeated here. The first electrode 10 is connected to the first conductor portion 411, and the first electrode 10 is directly connected to the first conductor portion 411.

[0188] A first insulating layer 91 is disposed on the side of the first electrode 10 facing away from the substrate 1. The material of the first insulating layer 91 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The thickness of the first insulating layer 91 is greater than or equal to 2500 angstroms and less than or equal to 4500 angstroms. For example, the thickness of the first insulating layer 91 can be 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, etc.

[0189] The second electrode 12 is disposed on the side of the first insulating layer 91 away from the substrate 1. The material and thickness of the second electrode 12 can be the same as those in the above example embodiment, and will not be repeated here.

[0190] Alternatively, the first electrode 10 is a pixel electrode, and the second electrode 12 is a common electrode. Referring to Figures 7 and 15, the second electrode 12 is provided with a plurality of slits 121 arranged along the first direction X. The slits 121 have a first edge line 1211, which is the edge line of the slit 121 near the end of the first active portion 41. The plurality of first edge lines 1211 located in the same pixel area are not located on the same straight line extending along the first direction X, thereby making the lengths of the plurality of slits 121 located in the same pixel area different in the second direction Y.

[0191] For example, within a pixel region, the distance between the first edge line 1211 and the gate line in the second direction Y decreases as the distance between the slit 121 and the data line Data in the first direction X increases. The gate line and the data line Data are connected to the thin-film transistor controlling the pixel electrode of the pixel region. Specifically, the gate line is connected to the first gate 61 of the thin-film transistor controlling the pixel electrode of the pixel region, and the data line Data is connected to the second connection conductor portion 82 of the thin-film transistor controlling the pixel electrode of the pixel region.

[0192] The light effect at the corner of the slit 121 is relatively poor. This setting ensures that the black matrix to be set later can block the corner of the slit 121. That is, the orthographic projection of the corner of the slit 121 on the substrate 1 is within the orthographic projection of the black matrix on the substrate 1, thus ensuring the light effect of the entire pixel.

[0193] Optionally, the distance between two adjacent first edge lines 1211 in the second direction Y is greater than or equal to 1 micrometer. For example, the distance between two adjacent first edge lines 1211 in the second direction Y can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, etc.

[0194] Of course, in some other example embodiments of this disclosure, the distance between two adjacent first edge lines 1211 in the second direction Y may be less than 1 micrometer.

[0195] Referring to FIG7, the orthographic projection of the gate layer 6 on the substrate 1 does not overlap with the orthographic projection of the first electrode 10 on the substrate 1. That is, the orthographic projections of the gate line Gate and the first gate 61 on the substrate 1 do not overlap with the orthographic projection of the first electrode 10 on the substrate 1, thereby avoiding interference of the gate signal to the signal of the first electrode 10.

[0196] Alternatively, the orthographic projection of the slit 121 on the substrate 1 overlaps with the orthographic projection of the first gate 61 on the substrate 1, that is, the slit 121 can extend to the side of the first gate 61 away from the substrate 1.

[0197] Optionally, the minimum distance between the orthographic projection of the gate layer 6 on the substrate 1 and the orthographic projection of the first electrode 10 on the substrate 1 is greater than or equal to 1 micrometer. For example, the minimum distance between the orthographic projection of the gate layer 6 on the substrate 1 and the orthographic projection of the first electrode 10 on the substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, 2.5 micrometers, 2.8 micrometers, etc.

[0198] During the fabrication of the gate layer 6 and the first electrode 10, there will be certain deviations. If the minimum distance between the orthographic projection of the gate layer 6 on the substrate 1 and the orthographic projection of the first electrode 10 on the substrate 1 is too small, it will still cause the orthographic projection of the gate layer 6 on the substrate 1 and the orthographic projection of the first electrode 10 on the substrate 1 to overlap, thereby causing the gate signal to interfere with the signal of the first electrode 10.

[0199] Referring to FIG3, in some exemplary embodiments of this disclosure, the array substrate may further include an interlayer dielectric layer 7, a first interconnect conductor layer 8, an insulating layer group 9, a first electrode 10, a third insulating layer 11, and a second electrode 12. The interlayer dielectric layer 7 is disposed on the side of the gate layer 6 facing away from the substrate 1, and a plurality of third vias 71, fourth vias 72, fifth vias 73, and sixth vias 74 are disposed on the interlayer dielectric layer 7; the thickness of the interlayer dielectric layer 7 is greater than or equal to 3000 angstroms and less than or equal to 4500 angstroms, for example, the thickness of the interlayer dielectric layer 7 may be 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, etc.

[0200] The first connecting conductor layer 8 is disposed on the side of the interlayer dielectric layer 7 away from the substrate 1. The thickness of the first connecting conductor layer 8 is greater than or equal to 3000 angstroms and less than or equal to 4500 angstroms. For example, the thickness of the first connecting conductor layer 8 can be 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, etc.

[0201] Referring to Figures 3 and 13, the first connecting conductor layer 8 may include a data line Data, a first connecting conductor portion 81, a second connecting conductor portion 82, and a third connecting conductor portion 83. The data line Data extends along the second direction Y, and the data line Data and the gate line Gate divide the array substrate into multiple pixel regions. The first connecting conductor portion 81 is electrically connected to the first conductor portion 411 through a third via 71, and the second connecting conductor portion 82 is electrically connected to the second conductor portion 413 through a fourth via 72. The second connecting conductor portion 82 is connected to the data line Data; data signals can be transmitted to the second connecting conductor portion 82 through the data line Data. The second connecting conductor portion 82 may also be part of the data line Data. The first end of the third connecting conductor portion 83 is connected to the first gate 61 through a fifth via 73, and the second end of the third connecting conductor portion 83 is connected to the light-shielding portion 21 through a sixth via 74 and a first gate connection via 32 on the buffer layer 3. When the gate insulating layer 5 is basically a full layer coverage, the second end of the third connecting conductor portion 83 also needs to be connected to the light-shielding portion 21 through a via on the gate insulating layer 5. This allows the light-shielding part 21 and the first gate 61 to be indirectly connected through the third connecting conductor part 83, thereby realizing a dual-gate structure to significantly improve the on-state current Ion of the thin-film transistor.

[0202] Referring to Figure 3, the insulating layer group 9 is disposed on the side of the first connecting conductor layer 8 facing away from the substrate 1. The insulating layer group 9 may include a first insulating layer 91 and a second insulating layer 92. The thickness of the first insulating layer 91 is greater than or equal to 2500 angstroms and less than or equal to 4500 angstroms. For example, the thickness of the first insulating layer 91 may be 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, etc. The material of the first insulating layer 91 may be an inorganic material. For example, the material of the first insulating layer 91 may be silicon nitride, silicon oxide, silicon oxynitride, etc. The thickness of the second insulating layer 92 is greater than or equal to 20000 angstroms and less than or equal to 30000 angstroms. For example, the thickness of the second insulating layer 92 may be 22000 angstroms, 23500 angstroms, 25000 angstroms, 27000 angstroms, 28500 angstroms, etc. The material of the second insulating layer 92 can be an organic material, such as resin materials like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate.

[0203] Referring to FIG3, the first electrode 10 is disposed on the side of the insulating layer group 9 away from the substrate 1. The material and thickness of the first electrode 10 can be the same as those in the above example embodiment, and will not be described again here.

[0204] The third insulating layer 11 is disposed on the side of the first electrode 10 facing away from the substrate 1. The material of the third insulating layer 11 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The thickness of the third insulating layer 11 is greater than or equal to 1500 angstroms and less than or equal to 4500 angstroms. For example, the thickness of the third insulating layer 11 can be 1800 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms, 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4300 angstroms, etc.

[0205] The second electrode 12 is disposed on the side of the third insulating layer 11 away from the substrate 1; the material and thickness of the second electrode 12 can be the same as those in the above example embodiment, and will not be repeated here.

[0206] The second electrode 12 is a pixel electrode, and the first electrode 10 is a common electrode. The second electrode 12 is electrically connected to the first connecting conductor portion 81. Specifically, the second electrode 12 is electrically connected to the first connecting conductor portion 81 through vias on the third insulating layer 11, the second insulating layer 92, and the first insulating layer 91 gate insulating layer 5. This allows the second electrode 12 to be energized by a dual-gate thin-film transistor composed of the light-shielding portion 21, the active layer 4, the first connecting conductor portion 81, the second connecting conductor portion 82, and the first gate 61. The first electrode 10 is electrically connected to the common line COM.

[0207] The vias on the first insulating layer 91 and the third insulating layer 11 have a side length or diameter greater than or equal to 4 micrometers, and are formed as the seventh via 911 through the same patterning process. The vias on the second insulating layer 92 have a side length or diameter 1 micrometer larger than the vias on the first insulating layer 91, and are formed as the eighth via 921 through the same patterning process.

[0208] Of course, in other exemplary embodiments of this disclosure, the first electrode 10 may be a pixel electrode, the second electrode 12 may be a common electrode, and the first electrode 10 may be electrically connected to the first connecting conductor portion 81. Specifically, the first electrode 10 is electrically connected to the first connecting conductor portion 81 through the third insulating layer 11, the second insulating layer 92, and vias on the first insulating layer 91, so that the dual-gate thin-film transistor composed of the light-shielding portion 21, the active layer 4, the first connecting conductor portion 81, the second connecting conductor portion 82, and the first gate 61 can control whether the first electrode 10 is energized. The second electrode 12 is electrically connected to the common line COM.

[0209] The above describes the film layer stacking structure of the array substrate in detail. The following describes the planar layout of the array substrate in detail.

[0210] The first active portion 41, the first gate 61, the first connecting conductor portion 81, and the second connecting conductor portion 82 constitute the first thin film transistor TFT1. The extension direction of the third connecting conductor portion 83 is consistent with the extension direction of the first thin film transistor TFT1, thereby greatly saving the arrangement space and improving the pixel transmittance.

[0211] In some exemplary embodiments of this disclosure, referring to Figures 8 and 9, 23, 24 and 25, the light-shielding portion 21 may include a first sub-light-shielding portion 211 and a second sub-light-shielding portion 212. The first sub-light-shielding portion 211 is configured as a strip extending along a first direction X, and the orthographic projection of the first active portion 41 on the substrate 1 may be located within the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1. Specifically, in the first direction X, the edge line of the orthographic projection of the first active portion 41 on the substrate 1 coincides with the edge line of the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1. In the second direction Y, the minimum distance between the edge line of the orthographic projection of the first active portion 41 on the substrate 1 and the edge line of the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1 is greater than or equal to 1.5 micrometers, such that the minimum distance by which the light-shielding portion 21 protrudes from the first active portion 41 is greater than or equal to 1.5 micrometers.

[0212] The second sub-shielding part 212 is connected to the side of the first sub-shielding part 211 near the gate line. The orthographic projection of the second sub-shielding part 212 on the substrate 1 overlaps with the orthographic projection of the third connecting conductor part 83 on the substrate 1, so that the second sub-shielding part 212 can be electrically connected to the second end of the third connecting conductor part 83 through the sixth via 74 on the interlayer dielectric layer 7 and the first gate connecting via 32 on the buffer layer 3. The orthographic projection of the second sub-shielding part 212 on the substrate 1 does not overlap with the orthographic projection of the first gate 61 on the substrate 1, thereby reducing the overlap area of ​​the shielding part 21, the first gate 61 and the third connecting conductor part 83, and thus reducing the overlap capacitance.

[0213] The orthographic projection of the second sub-shielding portion 212 on the substrate 1 does not overlap with the orthographic projection of the gate line on the substrate 1. Similarly, by reducing the overlap area between the shielding portion 212 and the gate line, the overlap capacitance is reduced. Furthermore, the distance between the orthographic projection of the second sub-shielding portion 212 on the substrate 1 and the orthographic projection of the gate line on the substrate 1 is greater than 2 micrometers. Even if the gate line is offset, it can be ensured that the orthographic projection of the second sub-shielding portion 212 on the substrate 1 does not overlap with the orthographic projection of the gate line on the substrate 1.

[0214] Referring to FIG24, a portion of the orthographic projection of the second sub-shielding portion 212 on the substrate 1 may overlap with a portion of the orthographic projection of the gate line on the substrate 1, that is, the second sub-shielding portion 212 may extend to the side of the gate line near the substrate 1. The edge of the orthographic projection of the first sub-shielding portion 211 on the substrate 1 near the data line Data may be located within the orthographic projection of the data line Data on the substrate 1.

[0215] Of course, the edge of the first sub-shielding part 211 projected onto the substrate 1 near the data line Data can also coincide with the edge of the data line Data projected onto the substrate 1 away from the first gate 61.

[0216] Referring to Figures 8, 10, 24, and 26, the first active portion 41 is configured as a strip extending along the first direction X. The width of the first channel portion 412 in the first direction X is greater than or equal to 5 micrometers, and the length of the first channel portion 412 in the second direction Y is greater than or equal to 4 micrometers. The width of the first gate 61 in the first direction X is substantially the same as the width of the first channel portion 412 in the first direction X; therefore, the width of the first gate 61 in the first direction X is also greater than or equal to 5 micrometers. The first gate 61 protrudes beyond the first channel portion 412 in the second direction Y, and the dimension of the first gate 61 protruding beyond the first channel portion 412 in the second direction Y is greater than or equal to 2.5 micrometers.

[0217] Referring to Figures 8 and 11, and Figures 24 and 27, the first gate 61 is configured as a strip extending along the second direction Y, and the first gate 61 is substantially perpendicularly connected to the gate line. Referring to Figures 8 and 12, and Figures 24 and 28, the third connecting conductor portion 83 is configured as a strip extending along the first direction X, such that the extending direction of the third connecting conductor portion 83 is consistent with the extending direction of the first active portion 41, that is, the third connecting conductor portion 83 and the first active portion 41 are substantially parallel, thereby making the extending direction of the third connecting conductor portion 83 consistent with the extending direction of the first thin-film transistor TFT1. This configuration can significantly save layout space and improve pixel transmittance. The orthographic projection of the third connecting conductor portion 83 on the substrate 1 is located on the side of the orthographic projection of the first active portion 41 on the substrate 1 that is close to the orthographic projection of the gate line Gate on the substrate 1. That is, in the second direction Y, the third connecting conductor portion 83 is closer to the gate line Gate than the first active portion 41, so that the third connecting conductor portion 83 is closer to the gate line Gate than the first connecting conductor portion 81 and the second connecting conductor portion 82.

[0218] Correspondingly, the fifth via 73 and the sixth via 74 are provided on the side of the first active part 41 near the gate line.

[0219] The orthographic projection of the first connecting conductor portion 81 on the substrate 1 does not overlap with the orthographic projection of the gate layer 6 on the substrate 1, and the distance in the first direction X between the orthographic projection of the first connecting conductor portion 81 on the substrate 1 and the orthographic projection of the first gate 61 on the substrate 1 is greater than or equal to 2 micrometers. The orthographic projection of the second connecting conductor portion 82 on the substrate 1 does not overlap with the orthographic projection of the gate layer 6 on the substrate 1, and the distance in the first direction X between the orthographic projection of the second connecting conductor portion 82 on the substrate 1 and the orthographic projection of the first gate 61 on the substrate 1 is greater than or equal to 2 micrometers.

[0220] With this configuration, even if the first connecting conductor portion 81 and the second connecting conductor portion 82 are offset, the orthographic projection of the first connecting conductor portion 81 on the substrate 1 does not overlap with the orthographic projection of the gate layer 6 on the substrate 1, and the orthographic projection of the second connecting conductor portion 82 on the substrate 1 does not overlap with the orthographic projection of the gate layer 6 on the substrate 1, thereby avoiding an increase in pixel load.

[0221] The distance in the second direction Y between the orthographic projection of the first connecting conductor portion 81 on the substrate 1 and the orthographic projection of the third connecting conductor portion 83 on the substrate 1 is greater than or equal to 3.5 micrometers. To ensure this dimension, referring to Figures 8 and 11, the distance between the edge line of the first connecting conductor portion 81 near the gate line and the gate line in the second direction Y is greater than the distance between the edge line of the second connecting conductor portion 82 near the gate line and the gate line in the second direction Y.

[0222] Referring to FIG29, when the first electrode 10 is a common electrode, the first electrode 10 is formed as a single layer, and an opening is provided on the first electrode 10. The orthographic projection of the opening on the substrate 1 overlaps with the orthographic projection of the first thin-film transistor TFT 1 on the substrate 1. When the second electrode 12 is a pixel electrode, a slit 121 may also be provided on the second electrode 12.

[0223] In some exemplary embodiments of this disclosure, referring to FIG22, the structure of the light-shielding part 21 in this exemplary embodiment is different from the structure of the light-shielding part 21 shown in FIG8, but the other structures are the same. Therefore, the other structures will not be described in detail here.

[0224] Specifically, the light-shielding portion 21 may include a first sub-light-shielding portion 211 and a second sub-light-shielding portion 212. The first sub-light-shielding portion 211 is configured as a strip extending along the second direction Y, and the orthographic projection of the first channel portion 412 on the substrate 1 is located within the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1. In the first direction X, the first sub-light-shielding portion 211 protrudes beyond the first gate 61, and the distance between the edge line of the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1 and the edge line of the orthographic projection of the first gate 61 on the substrate 1 is greater than or equal to 2 micrometers. The orthographic projection of the first sub-light-shielding portion 211 on the substrate 1 does not overlap with the orthographic projections of the first connecting conductor portion 81 and the second connecting conductor portion 82 on the substrate 1, that is, in the first direction X, the width of the first sub-light-shielding portion 211 in this example embodiment is smaller than the length of the first sub-light-shielding portion 211 in the example embodiment shown in FIG8.

[0225] The second sub-shielding portion 212 is connected to the side of the first sub-shielding portion 211 near the gate line. The orthographic projection of the second sub-shielding portion 212 on the substrate 1 overlaps at least with the orthographic projection of the second end of the third connecting conductor portion 83 on the substrate 1. The second sub-shielding portion 212 is electrically connected to the second end of the third connecting conductor portion 83. Specifically, the second sub-shielding portion 212 is configured as a strip extending along the first direction X. The orthographic projection of the second end of the third connecting conductor portion 83 on the substrate 1 is located within the orthographic projection of the second sub-shielding portion 212 on the substrate 1. The orthographic projection of the first end of the third connecting conductor portion 83 on the substrate 1 also overlaps with the orthographic projection of the second sub-shielding portion 212 on the substrate 1. That is, in the first direction X, the length of the second sub-shielding portion 212 in this example embodiment is greater than the width of the second sub-shielding portion 212 in the example embodiment shown in FIG8. This configuration ensures the connection width between the first sub-shielding part 211 and the second sub-shielding part 212, preventing the connection between the first sub-shielding part 211 and the second sub-shielding part 212 from being too narrow, which would lead to increased resistance and easy breakage.

[0226] Referring to Figures 16-21, in some exemplary embodiments of this disclosure, and referring to Figure 20, a portion of the gate line Gate can be used as a first gate 61. The width of the first gate 61 in the second direction Y is greater than the width of the gate line Gate in the second direction Y, that is, the width of the portion of the gate line Gate used as the first gate 61 in the second direction Y is greater than the width of the gate line Gate in the second direction Y.

[0227] Alternatively, the first gate 61 may include a gate function portion 611 and a gate connection portion 612 connected sequentially in the first direction X. The gate function portion 611, which implements the gate function, is disposed opposite to the first channel portion 412. The gate connection portion 612 is used to connect with the third connection conductor portion 83, that is, the gate connection portion 612 is electrically connected to the third connection conductor portion 83. The width of the gate connection portion 612 in the second direction Y is greater than the width of the gate function portion 611 in the second direction Y.

[0228] For example, the width of the gate line in the second direction Y is greater than or equal to 3.5 micrometers, and the width of the gate functional portion 611 of the first gate 61 in the second direction Y is greater than or equal to 5 micrometers. This arrangement ensures that the width of the first channel portion 412 in the second direction Y meets the requirements of a thin-film transistor. The width of the gate connection portion 612 of the first gate 61 in the second direction Y is greater than or equal to 3 micrometers. This arrangement ensures sufficient space for the fifth via 73 to guarantee the electrical connection between the gate connection portion 612 and the third connecting conductor portion 83.

[0229] Referring to Figures 16, 17, and 21, the orthographic projections of the first connecting conductor portion 81 and the second connecting conductor portion 82 on the substrate 1 are located on opposite sides of the second direction Y of the orthographic projection of the gate line on the substrate 1. For example, the orthographic projection of the first connecting conductor portion 81 on the substrate 1 is located on the side of the orthographic projection of the gate line on the substrate 1 that is closer to the first electrode 10, which facilitates the connection between the first electrode 10 and the first connecting conductor portion 81. That is, the first electrode 10 and the first connecting conductor portion 81 can be directly connected without crossing the gate line. The orthographic projection of the second connecting conductor portion 82 on the substrate 1 is located on the side of the orthographic projection of the gate line on the substrate 1 that is away from the first electrode 10.

[0230] The first connecting conductor portion 81 and the second connecting conductor portion 82 are offset in the second direction Y. Specifically, the second connecting conductor portion 82 is closer to the data line Data than the first connecting conductor portion 81. Since the second connecting conductor portion 82 is connected to the data line Data, this arrangement makes the length of the second connecting conductor portion 82 extending in the first direction X shorter, which can avoid the first gate 61. This can reduce the width of the black matrix subsequently set in the second direction Y, effectively improve the pixel aperture ratio and thus improve the pixel transmittance. Moreover, it can ensure the width of the gap between the first connecting conductor portion 81 and the data line Data in the first direction X, and avoid the overlapping capacitance caused by the overlap between the light-shielding portion 21 and the data line Data.

[0231] In this case, referring to Figures 17 and 19, the first active portion 41 may include a first portion 41a and a second portion 41b; the first portion 41a is configured as a strip extending along the second direction Y, and the first portion 41a may include a first conductor portion 411 and a first channel portion 412. The orthographic projection of the first conductor portion 411 on the substrate 1 is located on the side of the orthographic projection of the gate line on the substrate 1 close to the first electrode 10, which facilitates the connection between the first connecting conductor portion 81 and the first conductor portion 411; the portion of the first active portion 41 that is directly opposite to the first gate 61 is the first channel portion 412, and the width of the first channel portion 412 in the first direction X is greater than or equal to 4 micrometers.

[0232] The second part 41b is connected to the side of the first part 41a near the data line Data. The second part 41b may include a second conductor part 413. The orthographic projections of the first conductor part 411 and the second conductor part 413 on the substrate 1 are located on opposite sides of the second direction Y of the orthographic projection of the gate line Gate on the substrate 1. The orthographic projection of the second conductor part 413 on the substrate 1 is located on the side of the orthographic projection of the gate line Gate on the substrate 1 away from the first electrode 10, which facilitates the connection between the second connecting conductor part 82 and the second conductor part 413.

[0233] In addition, in some other exemplary embodiments of this disclosure, when the second connecting conductor portion 82 extends a long length along the first direction X, the first active portion 41 can be configured as a rectangle extending along the second direction Y, that is, the first portion 41a extends along the second direction Y until it overlaps with the second connecting conductor portion 82.

[0234] Referring to Figures 16, 17, and 21, the third connecting conductor portion 83 is configured as a strip extending along the second direction Y. The extension direction of the third connecting conductor portion 83 is consistent with the extension direction of the first active portion 41, that is, the third connecting conductor portion 83 and the first active portion 41 are arranged substantially parallel to each other. This makes the extension direction of the third connecting conductor portion 83 consistent with the extension direction of the first thin-film transistor TFT1. This arrangement can significantly save layout space and improve pixel transmittance. In this example embodiment, the width of the area where the black matrix is ​​set in the second direction Y can be reduced by more than 18% compared with the prior art, which can effectively improve the pixel aperture ratio and thus improve the pixel transmittance.

[0235] The third connecting conductor portion 83 is located on the side of the first active portion 41 away from the data line Data, that is, in the first direction X, the third connecting conductor portion 83 is further away from the data line Data relative to the first active portion 41, so that the third connecting conductor portion 83 is further away from the data line Data relative to the first connecting conductor portion 81 and the second connecting conductor portion 82.

[0236] Correspondingly, the fifth via 73 and the sixth via 74 are located on the side of the first active part 41 away from the data line Data.

[0237] In this case, referring to Figures 16, 17, and 18, the light-shielding portion 21 may include a first sub-light-shielding portion 211 and a second sub-light-shielding portion 212. The first sub-light-shielding portion 211 is configured as a strip extending along the second direction Y. The orthographic projection of the first portion 41a on the substrate 1 is located within the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1, that is, the orthographic projections of the first conductor portion 411 and the first channel portion 412 on the substrate 1 are located within the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1. Specifically, at both ends of the extension direction of the first portion 41a, the edge line of the orthographic projection of the first portion 41a on the substrate 1 substantially coincides with the edge line of the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1. On both sides of the width direction of the first portion 41a, the first sub-light-shielding portion 211 protrudes from the first portion 41a.

[0238] Of course, in some other example embodiments of this disclosure, it is also possible that only the orthogonal projection of the first channel portion 412 on the substrate 1 is located within the orthogonal projection of the first sub-shielding portion 211 on the substrate 1.

[0239] The second sub-shielding portion 212 is connected to the side of the first sub-shielding portion 211 away from the data line Data. The orthographic projection of the second sub-shielding portion 212 on the substrate 1 overlaps at least with the orthographic projection of the second end of the third connecting conductor portion 83 on the substrate 1, so that the second sub-shielding portion 212 can be electrically connected to the second end of the third connecting conductor portion 83 through the sixth via 74 on the interlayer dielectric layer 7 and the first gate connection via 32 on the buffer layer 3. For example, the orthographic projection of the second sub-shielding portion 212 on the substrate 1 may only overlap with the orthographic projection of the second end of the third connecting conductor portion 83 on the substrate 1, so that the orthographic projection of the second sub-shielding portion 212 on the substrate 1 does not overlap with the orthographic projection of the first gate 61 on the substrate 1, thereby reducing the overlap area of ​​the shielding portion 21, the first gate 61 and the third connecting conductor portion 83, and thus reducing the overlap capacitance.

[0240] The orthographic projection of the second sub-shielding portion 212 on the substrate 1 does not overlap with the orthographic projection of the gate line on the substrate 1. Similarly, reducing the overlap area between the shielding portion 212 and the gate line reduces the overlap capacitance. Furthermore, the distance between the orthographic projection of the second sub-shielding portion 212 on the substrate 1 and the orthographic projection of the gate line on the substrate 1 is greater than 2 micrometers. Even if the gate line is offset, it can be ensured that the orthographic projection of the second sub-shielding portion 212 on the substrate 1 does not overlap with the orthographic projection of the gate line on the substrate 1.

[0241] Referring to Figures 42 and 43, in some other example embodiments of this disclosure, the light-shielding portion may further include a third sub-light-shielding portion 213, which is connected to the side of the first sub-light-shielding portion 211 near the data line Data. The orthographic projection of the second portion 41b on the substrate 1 is located within the orthographic projection of the third sub-light-shielding portion 213 on the substrate 1, so that the orthographic projections of the third sub-light-shielding portion 213 and a portion of the first sub-light-shielding portion 211 on the substrate 1 are located on opposite sides of the second direction Y of the orthographic projection of the gate line Gate on the substrate 1.

[0242] Referring to Figures 2 and 39-41, in some exemplary embodiments of this disclosure, the array substrate may further include an interlayer dielectric layer 7, a first interconnect conductor layer 8, a first electrode 10, a first insulating layer 91, and a second electrode 12. The interlayer dielectric layer 7 is disposed on the side of the gate layer 6 facing away from the substrate 1, and a third via 71 and a fourth via 72 are provided on the interlayer dielectric layer 7.

[0243] The first connection conductor layer 8 is disposed on the side of the interlayer dielectric layer 7 facing away from the substrate 1. Referring to Figures 2 and 39-41, the first connection conductor layer 8 may include a data line Data, a first connection conductor portion 81, and a second connection conductor portion 82. The data line Data extends along the second direction Y, and the data line Data and the gate line Gate divide the array substrate into multiple pixel regions. The first connection conductor portion 81 is electrically connected to the first conductor portion 411 through a third via 71, and the second connection conductor portion 82 is electrically connected to the second conductor portion 413 through a fourth via 72. The second connection conductor portion 82 is connected to the data line Data; data signals can be transmitted to the second connection conductor portion 82 through the data line Data. The second connection conductor portion 82 may also be a part of the data line Data.

[0244] Referring to FIG2, the first electrode 10 is disposed on the side of the first connecting conductor layer 8 facing away from the substrate 1. The material and thickness of the first electrode 10 can be the same as those in the above example embodiment, and will not be repeated here. The first electrode 10 is connected to the first conductor portion 411, and the first electrode 10 is directly connected to the first conductor portion 411.

[0245] The first insulating layer 91 is disposed on the side of the first electrode 10 away from the substrate 1; the material of the first insulating layer 91 can be an inorganic material, for example, the material of the first insulating layer 91 can be silicon nitride, silicon oxide, silicon oxynitride, etc.

[0246] The second electrode 12 is disposed on the side of the first insulating layer 91 away from the substrate 1. The material and thickness of the second electrode 12 can be the same as those in the above example embodiment, and will not be repeated here.

[0247] Referring to FIG39, the first active portion 41, the first gate 61, the first connecting conductor portion 81, and the second connecting conductor portion 82 constitute the first thin film transistor TFT1. The extension direction of the first thin film transistor TFT1 is consistent with the extension direction of the gate line, thereby greatly saving the arrangement space and improving the pixel transmittance.

[0248] The first gate 61 is configured as a strip extending along the second direction Y. Since the active layer 4 is fabricated by doping the active material layer using the first gate 61 as a shield, the portion shielded by the first gate 61 remains undoped and is still a semiconductor, forming the first channel portion 412. The portion not shielded by the first gate 61 is doped to form conductors, forming the first conductor portion 411 and the second conductor portion 413. Therefore, in order to ensure the shielding effect of the first gate 61 even with process errors, and to form a first channel portion 412 with better performance, the first gate 61 needs to protrude sufficiently from both sides of the first channel portion 412 in the second direction Y. This results in the first thin-film transistor TFT1 occupying a large area, which is detrimental to improving the aperture ratio and light extraction efficiency.

[0249] Alternatively, referring to FIG41, the first active portion 41 may include a first portion 41a, a second portion 41b, and a third portion 41c connected sequentially in the first direction X. The first portion 41a is included in the first conductor portion 411, that is, the end of the first conductor portion 411 away from the first channel portion 412 is the first portion 41a; the second portion 41b may include the first channel portion 412; and the third portion 41c is included in the second conductor portion 413, that is, the end of the second conductor portion 413 away from the first channel portion 412 is the third portion 41c.

[0250] The width of the first part 41a in the second direction Y is greater than the width of the second part 41b in the second direction Y, and the width of the third part 41c in the second direction Y is greater than the width of the second part 41b in the second direction Y. The width of the first part 41a in the second direction Y can be the same as the width of the third part 41c in the second direction Y. The first part 41a, the second part 41b and the third part 41c are collinear near the edge of the gate line, so that the first active part 41 is configured as a structure that is approximately "U" shaped.

[0251] The first gate 61 protrudes from the first end of the first channel portion 412 in the second direction Y, so that the shielding effect of the first end of the first gate 61 can be guaranteed even if there are errors in the process. The second end of the first gate 61 in the second direction Y is connected to the gate line, that is, the end of the first gate 61 close to the gate line in the second direction Y is connected to the gate line. Therefore, even if there are errors in the process, the shielding effect of the second end of the first gate 61 can be guaranteed by the gate line, so as to form a first channel portion 412 with better performance.

[0252] The first active portion 41 is configured with a roughly "U"-shaped structure, so that the recessed structure formed by the first active portion 41 can accommodate the first end of the first gate 61, so that the first end of the first gate 61 in the second direction Y will not protrude from the first active portion 41, thereby reducing the length of the first gate 61 in the second direction Y, and further reducing the occupied area of ​​the first thin film transistor TFT1, which is beneficial to improving the aperture ratio and light extraction efficiency. Specifically, the width of the subsequently set black matrix in the second direction Y can be reduced by about 30%, that is, the width of the black matrix in the second direction Y in this example embodiment is about 70% of the width of the black matrix in the second direction Y in the prior art.

[0253] Furthermore, the first gate 61 is not connected to the light-shielding part 21, thereby saving the space for setting the via connecting the first gate 61 and the light-shielding part 21, further reducing the width of the black matrix set subsequently in the second direction Y, and further improving the aperture ratio and light extraction efficiency.

[0254] Alternatively, referring to FIG40, the light-shielding portion 21 may include a first sub-light-shielding portion 211 and a second sub-light-shielding portion 212; the first sub-light-shielding portion 211 is configured as a strip extending along the first direction X, and the orthographic projection of the first active portion 41 on the substrate 1 may be located within the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1; specifically, in the first direction X, the minimum distance between the edge line of the orthographic projection of the first active portion 41 on the substrate 1 and the edge line of the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1 is greater than or equal to 1.5 micrometers, and in the second direction Y, the minimum distance between the edge line of the orthographic projection of the first active portion 41 on the substrate 1 and the edge line of the orthographic projection of the first sub-light-shielding portion 211 on the substrate 1 is greater than or equal to 1.5 micrometers, such that the minimum distance by which the light-shielding portion 21 protrudes from the first active portion 41 is greater than or equal to 1.5 micrometers.

[0255] The second sub-shielding part 212 is connected to the side of the first sub-shielding part 211 near the gate line. The orthographic projection of the second sub-shielding part 212 on the substrate 1 overlaps with the orthographic projection of the data line Data on the substrate 1, and also overlaps with the orthographic projection of the gate line Gate on the substrate, so that the cutout part is located at the corner of the shielding part 21 away from the data line Data and close to the gate line Gate.

[0256] To ensure the light-shielding effect of the light-shielding part 21, the area of ​​the light-shielding part 21 needs to be set to a large size; however, such a setting will increase parasitic capacitance. Setting a hollow part can reduce parasitic capacitance while ensuring the light-shielding effect of the light-shielding part 21.

[0257] Alternatively, referring to Figures 7 and 8, 16 and 17, and 23 and 24, the first connecting conductor layer 8 may further include a signal trace 84. The signal trace 84 extends along the second direction Y, and its extension direction is consistent with that of the data line Data. Furthermore, the shape of the signal trace 84 is substantially consistent with the shape of the data line Data, ensuring that the signal trace 84 is substantially parallel to the data line Data at various points. The signal trace 84 is located on one side of the data line Data in the first direction X, and one signal trace 84 is provided in each pixel region, thus meeting the touch panel size requirements of large-size products. The signal trace 84 can be used as a touch trace, through which touch signals can be transmitted.

[0258] In this case, the common electrode can be reused as a touch electrode; that is, when implementing the display function, the common electrode is used as a common electrode; when implementing the touch function, the common electrode is used as a touch electrode. The block size of the common electrode is less than or equal to 5mm. The signal trace 84 can be connected to the common electrode through touch vias on the first insulating layer 91 and the second insulating layer 92, and the touch vias can be located between two thin-film transistors. Of course, a single signal trace 84 can also be provided in two or more pixel areas.

[0259] Of course, in some other exemplary embodiments of this disclosure, the signal trace 84 may also be a dummy trace. A dummy trace may not be powered on; it is only set up to ensure process consistency. In this case, the signal trace 84 does not need to be connected to other parts. The signal trace 84 can also be used as a common electrode line.

[0260] The thin-film transistors on the array substrate disclosed herein can achieve an electron mobility of 50 cm⁻¹. 2With a resolution of 1920*1080 to 3840*2400 and a frequency of 10Hz to 600Hz, the pixel density (PPI) can reach 500.

[0261] Referring to Figure 38, L1 is the transfer characteristic curve of a thin-film transistor in the prior art, and L2 is the transfer characteristic curve of the first thin-film transistor TFT1 in the array substrate of this disclosure. The horizontal axis is the gate voltage Vg, in volts (V); the vertical axis is the drain current Id, in amperes (A). When the gate voltage Vg is greater than or equal to 5V, the drain current Id of the first thin-film transistor TFT1 in this disclosure is greater than the drain current Id of the thin-film transistor in the prior art at the same gate voltage Vg. Moreover, the gate voltage Vg in normal use is 15V, thereby ensuring that the drain current Id of the first thin-film transistor TFT1 in this disclosure is greater than the drain current Id of the thin-film transistor in the prior art in the use state.

[0262] The above describes the display area of ​​the array substrate in detail. The array substrate also has a non-display area. Referring to Figures 31-37, the array substrate may further include a second transistor TFT2 and electrostatic discharge (ESD) traces. The second transistor TFT2 may include a second gate 63, a second source 85, and a second drain 86. The second source 85 is electrically connected to the functional traces in the display area and to the second gate 63. The second drain 86 is electrically connected to the ESD traces. The functional traces may be data lines (Data), gate lines (Gate), signal lines of GOA circuits, etc. The ESD traces may be common lines (COM), ground lines (GND), etc.

[0263] When the functional trace is the data line Data and the electrostatic discharge trace is the common line COM, the data line Data extends to the non-display area. When there is a large current on the data line Data, the second transistor TFT2 will be turned on through the second gate 63, so that the large current of the data line Data flows to the common line COM through the second source 85 and the second drain 86, thereby achieving the purpose of releasing static electricity.

[0264] Specifically, referring to Figures 33-37, the active layer 4 may further include a second active portion 42, which may include a third conductor portion 421, a second channel portion 422, and a fourth conductor portion 423 connected in sequence. The gate layer 6 may further include a second gate 63 and a common line COM. The orthographic projection of the second channel portion 422 on the substrate 1 lies within the orthographic projection of the second gate 63 on the substrate 1. The first connecting conductor layer 8 may include a second drain 86 and a second source 85. The second source 85 is disposed on the same layer and with the same material as the data line Data, and the second source 85 and the data line Data can be directly connected as one unit. The data line Data can be connected to the second gate 63 through vias on the interlayer dielectric layer 7. The second drain 86 can be connected to the common line COM through vias on the interlayer dielectric layer 7.

[0265] Alternatively, as shown in Figures 32–37, the array substrate may further include a third transistor TFT3. The third transistor TFT3 may include a third gate 64, a third source 87, and a third drain 88. A second source 85 is electrically connected to the third source 87, a second drain 86 is electrically connected to the third drain 88, and the third gate 64 is electrically connected to an electrostatic discharge trace.

[0266] Specifically, the active layer 4 may further include a third active portion 43, which may include a fifth conductor portion 431, a third channel portion 432, and a sixth conductor portion 433 connected in sequence; the gate layer 6 may further include a third gate 64. The orthographic projection of the third channel portion 432 on the substrate 1 is located within the orthographic projection of the third gate 64 on the substrate 1. The first connecting conductor layer 8 may include a third drain 88 and a third source 87. The third source 87 and the second source 85 are disposed on the same layer and with the same material as the data line Data, and the third source 87 and the second source 85 can be directly connected to the data line Data as a whole; the second drain 86 and the third drain 88 are disposed on the same layer and with the same material, and the second drain 86 and the third drain 88 can be directly connected as a whole. The third gate 64 is disposed on the same layer and with the same material as the common line COM, and the third gate 64 can be directly connected to the common line COM as a whole.

[0267] When there is a large current on the data line Data, the second transistor TFT2 is turned on through the second gate 63, allowing the large current on the data line Data to flow to the common line COM through the second source 85 and the second drain 86, thereby releasing static electricity. When a large amount of static electricity accumulates on the common line COM, resulting in a large current on the common line COM, the third transistor TFT3 is turned on through the third gate 64, allowing the large current on the data line Data to flow to the common line COM through the third source 87 and the third drain 88, further releasing static electricity.

[0268] The maximum width of the second active portion 42 in the first direction X is greater than or equal to 3.5 micrometers and less than or equal to 6 micrometers. For example, the maximum width of the second active portion 42 in the first direction X can be 4 micrometers, 4.5 micrometers, 5 micrometers, 5.5 micrometers, etc. That is, the maximum width of the second transistor TFT2 in the first direction X is greater than or equal to 3.5 micrometers and less than or equal to 6 micrometers.

[0269] The maximum width of the third active portion 43 in the first direction X is greater than or equal to 3.5 micrometers and less than or equal to 6 micrometers. For example, the maximum width of the third active portion 43 in the first direction X can be 4 micrometers, 4.5 micrometers, 5 micrometers, 5.5 micrometers, etc. That is, the maximum width of the third transistor TFT3 in the first direction X is greater than or equal to 3.5 micrometers and less than or equal to 6 micrometers.

[0270] The distance between the second drain 86 and the second source 85 of the second transistor TFT2 in the second direction Y is greater than or equal to 40 micrometers and less than or equal to 60 micrometers. For example, the distance between the second drain 86 and the second source 85 of the second transistor TFT2 in the second direction Y can be 45 micrometers, 50 micrometers, 55 micrometers, etc.

[0271] The distance between the third source 87 and the third drain 88 of the third transistor TFT3 in the second direction Y is greater than or equal to 40 micrometers and less than or equal to 60 micrometers. For example, the distance between the third source 87 and the third drain 88 of the third transistor TFT3 in the second direction Y can be 45 micrometers, 50 micrometers, 55 micrometers, etc.

[0272] Based on the same inventive concept, this disclosure provides a display device that may include the array substrate described in any of the above-described embodiments. The specific structure of the array substrate has been described in detail above, and therefore will not be repeated here.

[0273] The display device can be a liquid crystal display panel, an OLED (Organic Light-Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, and so on.

[0274] When the display device can be a liquid crystal display panel, the display device may also include a color filter substrate, and the color filter substrate and the array substrate are bonded together by a frame.

[0275] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated further here.

[0276] It should be noted that, in addition to the array substrate, the display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0277] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiments, and will not be repeated here.

[0278] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein, include: Substrate; A light-shielding layer is disposed on one side of the substrate, and the light-shielding layer includes a plurality of light-shielding portions disposed at intervals; A buffer layer is disposed on the side of the light-shielding layer opposite to the substrate. An active layer is disposed on the side of the buffer layer away from the substrate. The active layer includes a first active portion, which includes a first conductor portion, a first channel portion, and a second conductor portion connected in sequence. At least the orthographic projection of the first channel portion on the substrate is located within the orthographic projection of the light-shielding portion on the substrate. A gate insulating layer is disposed on the side of the active layer opposite to the substrate. A gate layer is disposed on the side of the gate insulating layer opposite to the substrate. The gate layer includes a first gate and a gate line that are interconnected. The orthogonal projection of the first channel portion on the substrate is located within the orthogonal projection of the first gate on the substrate. The gate line extends along a first direction.

2. The array substrate according to claim 1, wherein, The first gate is electrically connected to the light-shielding portion.

3. The array substrate according to claim 2, wherein, The light-shielding layer also includes: The data cable extends along a second direction, which intersects with the first direction; The first connecting part is connected to the data line; The gate layer further includes: The second connection portion is disposed at a distance from the first gate and the gate line. The second connection portion is connected to the second conductor portion and also connected to the first connection portion.

4. The array substrate according to claim 3, wherein, A first via is provided on the buffer layer, and the first via communicates with the first connecting portion; a second via is provided on the gate insulating layer, the second via including a first sub-via and a second sub-via that communicate with each other, the first sub-via communicating with the first via, and the second via communicating with the second conductor portion; the second connecting portion includes: The first sub-connecting part passes through the first sub-via and the first via and is connected to the first connecting part; The second sub-connection portion passes through the second sub-via and is connected to the second conductor portion. The second sub-connection portion is connected to the first sub-connection portion.

5. The array substrate according to claim 3, wherein, The array substrate further includes: An insulating layer group is disposed on the side of the gate layer opposite to the substrate. The first electrode is disposed on the side of the insulating layer group away from the substrate. A third insulating layer is disposed on the side of the first electrode away from the substrate. The second electrode is disposed on the side of the third insulating layer opposite to the substrate. The first electrode or the second electrode is electrically connected to the first conductor portion.

6. The array substrate according to claim 5, wherein, The light-shielding portion is configured as a strip extending along the second direction, the first gate is configured as a strip extending along the second direction, the orthographic projection of the first gate on the substrate is located within the orthographic projection of the light-shielding portion on the substrate, the first active portion is configured as a strip extending along the first direction, and the orthographic projection of the first active portion on the substrate is located on the side of the orthographic projection of the gate line on the substrate closer to the second electrode.

7. The array substrate according to claim 5, wherein, The buffer layer is provided with a first gate connection via, which is connected to the light-shielding part; the gate insulating layer is provided with a second gate connection via, which is connected to the first gate connection via; the first gate is connected to the light-shielding part through the first gate connection via and the second gate connection via.

8. The array substrate according to claim 7, wherein, The first gate connection via and the second gate connection via are connected to one end of the first gate near the gate line.

9. The array substrate according to claim 2, wherein, The array substrate further includes: An interlayer dielectric layer is disposed on the side of the gate layer opposite to the substrate, and a third via, a fourth via, a fifth via, and a sixth via are disposed on the interlayer dielectric layer; A first connection conductor layer is disposed on the side of the interlayer dielectric layer facing away from the substrate. The first connection conductor layer includes a data line, a first connection conductor portion, a second connection conductor portion, and a third connection conductor portion. The data line extends along a second direction, which intersects with the first direction. The data line and the gate line divide the array substrate into multiple pixel regions. The first connection conductor portion is electrically connected to the first conductor portion through the third via. The second connection conductor portion is electrically connected to the second conductor portion through the fourth via. The second connection conductor portion is connected to the data line. The first end of the third connection conductor portion is connected to the first gate through the fifth via. The second end of the third connection conductor portion is connected to the light-shielding portion through the sixth via and the first gate connection via on the buffer layer. A first electrode is disposed on the side of the first connecting conductor layer opposite to the substrate, and the first electrode is connected to the first conductor portion; A first insulating layer is disposed on the side of the first electrode away from the substrate. The second electrode is disposed on the side of the first insulating layer away from the substrate.

10. The array substrate according to claim 9, wherein, The second electrode is a common electrode, and multiple slits arranged along the first direction are provided on the second electrode. Each slit has a first edge line, which is the edge line of the end of the slit near the first active part. Multiple first edge lines located in the same pixel area do not lie on the same straight line extending along the first direction.

11. The array substrate according to claim 10, wherein, Within a pixel region, the distance between the first edge line and the gate line in the second direction decreases as the distance between the slit and the data line in the first direction increases, wherein the gate line and the data line are connected to a thin-film transistor that controls the pixel electrode of the pixel region.

12. The array substrate according to claim 11, wherein, The distance between two adjacent first edge lines in the second direction is greater than or equal to 1 micrometer.

13. The array substrate according to claim 10, wherein, The orthographic projection of the gate layer on the substrate does not overlap with the orthographic projection of the first electrode on the substrate.

14. The array substrate according to claim 13, wherein, The orthographic projection of the slit on the substrate overlaps with the orthographic projection of the first gate on the substrate.

15. The array substrate according to claim 13, wherein, The minimum distance between the orthographic projection of the gate layer on the substrate and the orthographic projection of the first electrode on the substrate is greater than or equal to 1 micrometer.

16. The array substrate according to claim 2, wherein, The array substrate further includes: An interlayer dielectric layer is disposed on the side of the gate layer opposite to the substrate, and a plurality of third vias, fourth vias, fifth vias and sixth vias are disposed on the interlayer dielectric layer; A first connection conductor layer is disposed on the side of the interlayer dielectric layer facing away from the substrate. The first connection conductor layer includes a data line, a first connection conductor portion, a second connection conductor portion, and a third connection conductor portion. The data line extends along a second direction, which intersects with the first direction. The data line and the gate line divide the array substrate into multiple pixel regions. The first connection conductor portion is electrically connected to the first conductor portion through the third via. The second connection conductor portion is electrically connected to the second conductor portion through the fourth via. The second connection conductor portion is connected to the data line. The first end of the third connection conductor portion is connected to the first gate through the fifth via. The second end of the third connection conductor portion is connected to the light-shielding portion through the sixth via and the first gate connection via on the buffer layer. An insulating layer group is disposed on the side of the first connecting conductor layer opposite to the substrate. The first electrode is disposed on the side of the insulating layer group away from the substrate. A third insulating layer is disposed on the side of the first electrode away from the substrate. The second electrode is disposed on the side of the third insulating layer opposite to the substrate. The first electrode or the second electrode is electrically connected to the first connecting conductor portion.

17. The array substrate according to claim 9 or 16, wherein, The first active portion, the first gate, the first connecting conductor portion, and the second connecting conductor portion constitute a first thin-film transistor, and the extension direction of the third connecting conductor portion is consistent with the extension direction of the first thin-film transistor.

18. The array substrate according to claim 17, wherein, The first active portion is configured as a strip extending along a first direction, the first gate is configured as a strip extending along a second direction, and the third connecting conductor portion is configured as a strip extending along the first direction. The orthographic projection of the third connecting conductor portion on the substrate is located on the side of the orthographic projection of the first active portion on the substrate that is close to the orthographic projection of the gate line on the substrate. The light-shielding portion includes: The first sub-shielding part is configured as a strip extending along a first direction, and the orthographic projection of the first active part on the substrate is located within the orthographic projection of the first sub-shielding part on the substrate. The second sub-shielding part is connected to the side of the first sub-shielding part near the gate line. The orthographic projection of the second sub-shielding part on the substrate overlaps with the orthographic projection of the third connecting conductor on the substrate. The orthographic projection of the second sub-shielding part on the substrate does not overlap with the orthographic projection of the first gate on the substrate.

19. The array substrate according to claim 17, wherein, The first active portion is configured as a strip extending along a first direction, the first gate is configured as a strip extending along a second direction, and the third connecting conductor portion is configured as a strip extending along the first direction. The orthographic projection of the third connecting conductor portion on the substrate is located on the side of the orthographic projection of the first active portion on the substrate that is close to the orthographic projection of the gate line on the substrate. The light-shielding portion includes: The first sub-shielding portion is configured as a strip extending along the second direction. The orthographic projection of the first channel portion on the substrate is located within the orthographic projection of the first sub-shielding portion on the substrate. The orthographic projection of the first sub-shielding portion on the substrate does not overlap with the orthographic projections of the first connecting conductor portion and the second connecting conductor portion on the substrate. The second sub-shielding part is connected to the side of the first sub-shielding part near the gate line. The orthographic projection of the second sub-shielding part on the substrate overlaps at least with the orthographic projection of the second end of the third connecting conductor on the substrate. The second sub-shielding part is electrically connected to the second end of the third connecting conductor.

20. The array substrate according to claim 17, wherein, A portion of the gate line serves as a first gate. The orthographic projections of the first and second connecting conductor portions on the substrate are located on opposite sides of a second direction in which the gate line is projected onto the substrate. The second connecting conductor portion is closer to the data line than the first connecting conductor portion. The third connecting conductor portion is configured as a strip extending along the second direction. The third connecting conductor portion is located on the side of the first active portion opposite to the data line. The first active portion includes: The first part is configured as a strip extending in a second direction, and the first part includes the first conductor portion and the first channel portion; The second part is connected to the side of the first part near the data line. The second part includes a second conductor portion. The orthographic projections of the first conductor portion and the second conductor portion on the substrate are located on opposite sides of the second direction of the orthographic projection of the gate line on the substrate. The light-shielding part includes: The first sub-shielding portion is configured as a strip extending along the second direction, and the orthographic projection of the first portion on the substrate is located within the orthographic projection of the first sub-shielding portion on the substrate. The second sub-shielding part is connected to the side of the first sub-shielding part away from the data line. The orthographic projection of the second sub-shielding part on the substrate overlaps at least with the orthographic projection of the second end of the third connecting conductor on the substrate, but does not overlap with the orthographic projection of the gate line on the substrate. The second sub-shielding part is electrically connected to the second end of the third connecting conductor.

21. The array substrate according to claim 20, wherein, The light-shielding part also includes: The third sub-shielding part is connected to the side of the first sub-shielding part near the data line. The orthographic projection of the second part on the substrate is located within the orthographic projection of the third sub-shielding part on the substrate, so that the orthographic projections of the third sub-shielding part and a part of the first sub-shielding part on the substrate are located on opposite sides of the second direction of the orthographic projection of the gate line on the substrate.

22. The array substrate according to claim 20, wherein, The width of the first gate in the second direction is greater than the width of the gate line in the second direction.

23. The array substrate according to claim 22, wherein, The first gate includes a gate functional portion and a gate connecting portion connected sequentially in a first direction, wherein the width of the gate connecting portion in the second direction is greater than the width of the gate functional portion in the second direction.

24. The array substrate according to claim 1, wherein, The array substrate further includes: An interlayer dielectric layer is disposed on the side of the gate layer opposite to the substrate, and a third via and a fourth via are disposed on the interlayer dielectric layer; A first connecting conductor layer is disposed on the side of the interlayer dielectric layer facing away from the substrate. The first connecting conductor layer includes a data line, a first connecting conductor portion, and a second connecting conductor portion. The data line extends along a second direction, which intersects with the first direction. The data line and the gate line divide the array substrate into multiple pixel regions. The first connecting conductor portion is electrically connected to the first conductor portion through the third via. The second connecting conductor portion is electrically connected to the second conductor portion through the fourth via. The second connecting conductor portion is connected to the data line. A first electrode is disposed on the side of the first connecting conductor layer opposite to the substrate, and the first electrode is connected to the first conductor portion; A first insulating layer is disposed on the side of the first electrode away from the substrate. The second electrode is disposed on the side of the first insulating layer away from the substrate.

25. The array substrate according to claim 24, wherein, The first active portion, the first gate, the first connecting conductor portion, and the second connecting conductor portion constitute a first thin-film transistor, and the extension direction of the first thin-film transistor is consistent with the extension direction of the gate line.

26. The array substrate according to claim 25, wherein, The first active portion includes a first part, a second part, and a third part connected sequentially in a first direction. The width of the first part in the second direction is greater than the width of the second part in the second direction, and the width of the third part in the second direction is greater than the width of the second part in the second direction. The edges of the first part, the second part, and the third part near the gate line are collinear. The first gate is configured as a strip extending along a second direction, the first gate protrudes from the first channel portion at a first end in the second direction, and the first gate is connected to the gate line at a second end in the second direction.

27. The array substrate according to claim 26, wherein, The light-shielding part includes: The first sub-shielding part is configured as a strip extending along a first direction, and the orthographic projection of the first active part on the substrate is located within the orthographic projection of the first sub-shielding part on the substrate. The second sub-shielding part is connected to the side of the first sub-shielding part near the gate line. The orthographic projection of the second sub-shielding part on the substrate overlaps with the orthographic projection of the data line on the substrate and also overlaps with the orthographic projection of the gate line on the substrate, so that the corner of the shielding part away from the data line and near the gate line is provided with a cutout.

28. The array substrate according to claim 9, 16, or 24, wherein, The first connecting conductor layer further includes: The signal trace extends along the second direction and is located on one side of the data line in the first direction. One signal trace is provided in each of the pixel regions, or one signal trace is provided in two or more pixel regions.

29. The array substrate according to claim 9, 16 or 24, wherein, The array substrate has a non-display area, and in the non-display area, the array substrate further includes: The second transistor includes a second gate, a second source, and a second drain. The second source is electrically connected to the functional traces in the display area and is also electrically connected to the second gate. An electrostatic discharge trace is electrically connected to the second drain electrode; The third transistor includes a third gate, a third source, and a third drain. The second source is electrically connected to the third source, the second drain is electrically connected to the third drain, and the third gate is electrically connected to the electrostatic discharge line.

30. The array substrate according to claim 29, wherein, The active layer includes a second active portion and a third active portion. The second active portion includes a third conductor portion, a second channel portion and a fourth conductor portion connected in sequence. The third active portion includes a fifth conductor portion, a third channel portion and a sixth conductor portion connected in sequence. The gate layer includes a second gate and a third gate, and an electrostatic discharge line. The orthographic projection of the second channel portion on the substrate is located within the orthographic projection of the second gate portion on the substrate. The orthographic projection of the third channel portion on the substrate is located within the orthographic projection of the third gate portion on the substrate. The first connection conductor layer includes a second drain and a second source, a third drain and a third source, the third source and the second source being directly connected to the data line as a whole, the second drain and the third drain being directly connected as a whole, and the third gate being directly connected to the electrostatic discharge trace as a whole.

31. A display device, wherein, include: The array substrate is the array substrate as described in any one of claims 1 to 30.

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