Display panel and display apparatus

Abstract

The present application relates to a display panel and a display apparatus. The side surface of the side of each bank close to a pixel opening comprises a first sub-surface and a second sub-surface, wherein the first sub-surface is located between an array substrate and the second sub-surface, and the contact angle of the first sub-surface is less than that of the second sub-surface; and the first sub-surface has a first height in the direction of thickness of the display panel, the bank has a second height in the direction of thickness of the display panel, and the ratio of the first height to the second height is greater than or equal to 0.5.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202510096004.2, filed with the Chinese Patent Office on January 21, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] Organic light-emitting diode (OLED) display panels have advantages such as low cost, wide viewing angle, high contrast and flexibility, and have achieved remarkable results in both small and large-size applications.

[0004] Inkjet printing technology can be used in the preparation of organic functional layers in OLED display panels. Inkjet printing technology involves directly dropping ink containing OLED materials onto a pre-made pixel definition layer. After the solvent evaporates, the desired pattern is formed. For example, hole injection layers, hole transport layers, and light-emitting layers can all be prepared using inkjet printing technology.

[0005] Typically, a hydrophobic surface is formed on the upper side of the dam in the pixel definition layer to make it easier for ink to flow into the pixel opening. The film ramp cutoff points of the hole injection layer, hole transport layer, and light-emitting layer on the side wall of the dam are all located below the hydrophobic surface, and the ramp heights are not much different. As a result, the hole injection layer is easily exposed and not covered at the side wall of the dam, which makes it easy for the hole injection layer to come into contact with the cathode layer above the light-emitting layer, thus causing leakage current and affecting device performance and display effect. Invention Overview

[0006] This application provides a display panel and display device that can extend the leakage path between short-circuit film layers, increase resistance, and reduce leakage current.

[0007] This application provides a display panel, which includes:

[0008] Array substrate;

[0009] A pixel definition layer is disposed on the array substrate. The pixel definition layer has multiple pixel openings. The pixel definition layer includes a barrier wall disposed between adjacent pixel openings. The side surface of the barrier wall near the pixel opening includes a first sub-surface and a second sub-surface. The first sub-surface is located between the array substrate and the second sub-surface. The contact angle of the first sub-surface is smaller than the contact angle of the second sub-surface.

[0010] The first sub-surface has a first height along the thickness direction of the display panel, and the barrier wall has a second height along the thickness direction of the display panel, wherein the ratio of the first height to the second height is greater than or equal to 0.5.

[0011] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display device, the display device including a display panel, the display panel comprising:

[0012] Array substrate;

[0013] A pixel definition layer is disposed on the array substrate. The pixel definition layer has multiple pixel openings. The pixel definition layer includes a barrier wall disposed between adjacent pixel openings. The side surface of the barrier wall near the pixel opening includes a first sub-surface and a second sub-surface. The first sub-surface is located between the array substrate and the second sub-surface. The contact angle of the first sub-surface is smaller than the contact angle of the second sub-surface.

[0014] The first sub-surface has a first height along the thickness direction of the display panel, and the barrier wall has a second height along the thickness direction of the display panel, wherein the ratio of the first height to the second height is greater than or equal to 0.5. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0017] Figure 1 is a schematic diagram of the structure of a display panel provided in one embodiment;

[0018] Figure 2 is an enlarged structural diagram of point a in Figure 1;

[0019] Figure 3 is a schematic diagram of a first structure of a display panel provided in an embodiment of this application;

[0020] Figure 4 is an enlarged structural diagram of A in Figure 3 provided in an embodiment of this application;

[0021] Figure 5 is a schematic diagram of the detection of hydrophobic materials on the side surface of the retaining wall provided in the embodiment of this application;

[0022] Figure 6 is a schematic diagram of a second structure of the display panel provided in an embodiment of this application;

[0023] Figure 7 is a schematic diagram of a pixel definition layer provided in an embodiment of this application;

[0024] Figure 8 is a schematic diagram of another structure of the pixel definition layer provided in an embodiment of this application;

[0025] Figure 9 is a schematic diagram of a third structure of the display panel provided in an embodiment of this application;

[0026] Figure 10 is a schematic diagram of the planar distribution of the pixel definition layer provided in an embodiment of this application;

[0027] Figures 11 and 12 are schematic diagrams of the fabrication process of the pixel definition layer provided in the embodiments of this application.

[0028] Explanation of reference numerals in the attached figures:

[0029] 1. Anode; 2. Pixel confinement layer; 3. Hole injection film; 4. Hole transport film; 5. Organic light-emitting layer; 6. Cathode;

[0030] 10. Array substrate;

[0031] 20. Pixel definition layer; 21. Barrier; 211. First sub-part; 212. Second sub-part; 201. Pixel opening; 202. Top surface; 203. Side surface; 2031. First sub-surface; 2032. Second sub-surface; 23. Barrier intermediate body; 204. First surface; 205. Second surface;

[0032] 30. Anode layer; 31. Anode;

[0033] 40. Hole injection layer; 41. Hole injection section;

[0034] 50. Light-emitting layer; 51. Light-emitting part;

[0035] 60. Functional electrode layer; 61. Cathode layer; 62. Hole transport layer;

[0036] 70. Hole transport layer; 71. Hole transport unit. Embodiments of the present invention

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0038] Referring to Figures 1 and 2, the display panel includes a positive electrode 1, a pixel defining layer 2 disposed on the positive electrode 1, a hole injection film layer 3, a hole transport film layer 4, an organic light-emitting layer 5, and a negative electrode 6 disposed on the pixel defining layer 2 and the organic light-emitting layer 5. The pixel defining layer 2 has pixel openings, and the hole injection film layer 3, the hole transport film layer 4, and the organic light-emitting layer 5 can all be located within the pixel openings. Typically, inkjet printing is used to fabricate the hole injection film layer 3, the hole transport film layer 4, and the organic light-emitting layer 5. In inkjet printing, the pixel defining layer 2 is often... A hydrophobic surface is formed on the upper side of the dam to facilitate the flow of ink from the hole injection film 3, hole transport film 4, and organic light-emitting layer 5 into the pixel opening. The film ramp cutoff points of the hole injection film 3, hole transport film 4, and organic light-emitting layer 5 on the sidewall of the dam are all located below the hydrophobic surface, and the ramp heights are not significantly different. Consequently, at the sidewall of the dam, the hole injection film 3 is easily exposed and not enclosed, making it easy for the hole injection film 3 to come into contact with the cathode 6 above the light-emitting layer, as shown at leakage current a in Figure 1, thus generating leakage current and affecting device performance and display effect.

[0039] Referring to Figures 3 and 4, this application embodiment provides a display panel, which includes an array substrate 10 and a pixel definition layer 20. The pixel definition layer 20 is disposed on the array substrate 10, and a plurality of pixel openings 201 are formed in the pixel definition layer 20. The pixel definition layer 20 includes a barrier wall 21 disposed between adjacent pixel openings 201. The side surface 203 of the barrier wall 21 near the pixel opening 201 includes a first sub-surface 2031 and a second sub-surface 2032. The first sub-surface 2031 is located between the array substrate 10 and the second sub-surface 2032, and the contact angle of the first sub-surface 2031 is smaller than the contact angle of the second sub-surface 2032.

[0040] The first sub-surface 2031 has a first height H1 along the thickness direction of the display panel, and the barrier 21 has a second height H2 along the thickness direction of the display panel. The ratio of the first height H1 to the second height H2 is greater than or equal to 0.5.

[0041] In the implementation process, by increasing the height of the first sub-surface 2031, this embodiment of the application can increase the proportion of the portion with a smaller contact angle in the side surface 203 of the baffle 21. Consequently, in the manufacturing process of the display panel, the climbing height of the ink on the side surface 203 increases, and the connection position of the short-circuit film layer also increases, which lengthens the leakage path, increases the resistance, reduces the leakage current, and thus helps to improve the performance and display effect of the display panel.

[0042] In one embodiment of this application, the display panel further includes:

[0043] A hole injection layer, including a hole injection portion disposed within the pixel opening;

[0044] The light-emitting layer includes a light-emitting portion disposed within the pixel opening and located on the side of the hole injection portion away from the array substrate;

[0045] A functional electrode layer is disposed on the pixel definition layer and extends into the pixel opening, and the functional electrode layer located in the pixel opening is located on the side of the light-emitting part away from the hole injection part;

[0046] The edge of the hole injection portion extends to the side surface, and the functional electrode layer extends to the side surface and connects with the hole injection portion.

[0047] In one embodiment of this application, the connection between the hole injection portion and the functional electrode layer is located on the first sub-surface, and on the side of the first sub-surface closer to the second sub-surface.

[0048] In one embodiment of this application, the orthogonal projection of the light-emitting portion on the array substrate is located within the orthogonal projection of the hole injection portion on the array substrate.

[0049] In one embodiment of this application, within the pixel opening, at least one edge of the light-emitting portion is spaced apart from the side surface, and the functional electrode layer covers the light-emitting portion and extends to the side surface to connect with the hole injection portion.

[0050] In one embodiment of this application, the functional electrode layer includes a cathode layer, and the hole injection portion is connected to the cathode layer at the side surface;

[0051] Alternatively, the functional electrode layer may include an electron transport layer and the cathode layer, with the electron transport layer located between the light-emitting portion and the cathode layer, and the hole injection portion connected to the electron transport layer at the side surface.

[0052] In one embodiment of this application, the display panel further includes a hole transport layer disposed between the hole injection layer and the light-emitting layer, the hole transport layer including a hole transport portion disposed between the hole injection portion and the light-emitting portion and located within the pixel opening;

[0053] Within the pixel opening, at least one edge of the hole transport section is spaced apart from the side surface, and the functional electrode layer covers the light-emitting section and the hole transport section and extends to the side surface to connect with the hole injection section.

[0054] In one embodiment of this application, the display panel further includes:

[0055] A hole injection layer, including a hole injection portion disposed within the pixel opening;

[0056] The light-emitting layer includes a light-emitting portion disposed within the pixel opening and located on the side of the hole injection portion away from the array substrate;

[0057] A functional electrode layer is disposed on the pixel definition layer and extends into the pixel opening, and the functional electrode layer located in the pixel opening is located on the side of the light-emitting part away from the hole injection part;

[0058] The hole injection section is spaced apart from the functional electrode layer.

[0059] In one embodiment of this application, the first sub-surface is connected to the second sub-surface, and the first sub-surface and the second sub-surface intersect at a preset angle at the connection point, wherein the preset angle is less than or equal to 180°.

[0060] In one embodiment of this application, the first sub-surface includes a first side close to the array substrate and a second side away from the array substrate, the second sub-surface includes a third side close to the array substrate and a fourth side away from the array substrate, a first distance is between the first side and the second side, a second distance is between the third side and the fourth side, and the ratio of the first distance to the second distance is greater than or equal to 1.

[0061] In one embodiment of this application, the first sub-surface is hydrophilic and the second sub-surface is hydrophobic.

[0062] In one embodiment of this application, a plurality of pixel openings are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect.

[0063] The barrier includes a first sub-part and a plurality of second sub-parts stacked together. The first sub-part is located between the array substrate and the second sub-parts. The first sub-part extends along the first direction and the second direction and is disposed around each of the pixel openings.

[0064] The second sub-part extends along the second direction, and a plurality of second sub-parts are arranged along the first direction. A plurality of pixel openings arranged along the second direction are provided between two adjacent second sub-parts. The side of the second sub-part near the pixel opening has a first sub-surface and a second sub-surface.

[0065] Specifically, please continue to refer to Figures 3 and 4. The display panel includes an array substrate 10, an anode layer 30 disposed on the array substrate 10, a pixel definition layer 20 disposed on the anode layer 30, a hole injection layer 40, a light-emitting layer 50, and a functional electrode layer 60.

[0066] In some embodiments, the array substrate 10 includes a substrate and a thin-film transistor layer disposed on the substrate.

[0067] In some embodiments, the substrate may be a rigid substrate, such as a glass substrate; or the substrate may be a flexible substrate, such as a substrate formed of polyimide. When the substrate is a flexible substrate, the substrate may be formed of multiple sub-substrates of the same material, such as polyimide, and adjacent sub-substrates may be bonded together by adhesive sub-layers.

[0068] In some embodiments, the thin-film transistor layer includes a thin-film transistor comprising a semiconductor located on the substrate, the semiconductor being formed of polycrystalline silicon or a metal oxide (such as indium gallium zinc oxide). The semiconductor is divided into a channel region and source and drain regions formed on either side of the channel region. The thin-film transistor layer further includes a first gate insulating layer covering the semiconductor. The thin-film transistor also includes a first gate formed on the first gate insulating layer, the first gate overlapping the channel region. The first gate may be formed as multiple layers or a single layer comprising a low-resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance. The thin-film transistor layer further includes a second gate insulating layer covering the first gate. The thin-film transistor also includes a second gate located on the second gate insulating layer, the second gate overlapping the first gate, the second gate being formed as multiple layers or a single layer comprising a low-resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance. The thin-film transistor layer further includes a first interlayer insulating layer formed on the second gate. The first interlayer insulating layer, the first gate insulating layer, and the second gate insulating layer include source contact holes and drain contact holes, and the source region and the drain region are exposed through the source contact holes and the drain contact holes, respectively.

[0069] The thin-film transistor further includes a source and a drain disposed on the same layer. Both the source and the drain are formed on the first interlayer insulating layer. The source is connected to the source region through a source contact hole, and the drain is connected to the drain region through a drain contact hole. The source and the drain can be multiple layers or a single layer formed of low-resistance materials such as Al, Ti, Mo, Cu, Ni, or their alloys, or materials with high corrosion resistance. For example, the source and the drain can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, or other single-layer or multi-layer structures.

[0070] In some embodiments, the thin-film transistor layer further includes a planarization layer located on the side of the first interlayer insulating layer away from the substrate, the planarization layer covering the source and the drain.

[0071] In some embodiments, the anode layer 30 is disposed on the planarization layer, and the anode layer 30 includes a plurality of anodes 31; the pixel definition layer 20 is disposed on the planarization layer, and the pixel definition layer 20 has a plurality of pixel openings 201, and the plurality of pixel openings 201 are correspondingly disposed with respect to the plurality of anodes 31; for example, the plurality of pixel openings 201 and the plurality of anodes 31 can be correspondingly disposed one-to-one, and each pixel opening 201 exposes the surface of the corresponding anode 31 on the side away from the array substrate 10.

[0072] Furthermore, the hole injection layer 40 is disposed on the pixel definition layer 20, and the hole injection layer 40 includes a hole injection portion 41 disposed within the pixel opening 201 and located on the side of the anode 31 away from the array substrate 10.

[0073] The light-emitting layer 50 is disposed on the hole injection layer 40, and the light-emitting layer 50 includes a light-emitting part 51 disposed in the pixel opening 201 and located on the side of the hole injection part 41 away from the anode 31.

[0074] The functional electrode layer 60 is disposed on the pixel definition layer 20, and the functional electrode layer 60 is further disposed on the side of the light-emitting layer 50 away from the hole injection layer 40. The functional electrode layer 60 extends into the pixel opening 201, and the functional electrode layer 60 located in the pixel opening 201 is located on the side of the light-emitting part 51 away from the hole injection part 41.

[0075] In some embodiments, the pixel definition layer 20 includes a barrier 21 disposed between adjacent pixel openings 201, and the barrier 21 includes a top surface 202 on the side away from the array substrate 10 and a side surface 203 on the side close to the pixel openings 201, and the side surface 203 is connected to the top surface 202; wherein, the side surface 203 includes a first sub-surface 2031 and a second sub-surface 2032, the first sub-surface 2031 is located between the second sub-surface 2032 and the array substrate 10, the contact angle of the first sub-surface 2031 is smaller than the contact angle of the second sub-surface 2032, and the contact angle of the first sub-surface 2031 is smaller than the contact angle of the top surface 202.

[0076] In some embodiments, the first sub-surface 2031 may be hydrophilic, the second sub-surface 2032 and the top surface 202 may be hydrophobic; further, the contact angle of the first sub-surface 2031 may be less than 90°, the contact angle of the second sub-surface 2032 may be greater than 90°, and the contact angle of the top surface 202 may be greater than 90°.

[0077] It should be noted that the hole injection layer 40 and the light-emitting layer 50 in the display panel provided in this application embodiment can be prepared using inkjet printing technology. During the manufacturing process of the display panel, since the top surface 202 and the second sub-surface 2032 are hydrophobic, ink will flow into the pixel opening 201 and form a film on the first sub-surface 2031. The hole injection layer 40 and the light-emitting layer 50 will form a ramp at the first sub-surface 2031. Because the ramp heights of the hole injection layer 40 and the light-emitting layer 50 are not significantly different, the hole injection layer 40 is easily exposed on the side surface 203 of the barrier 21 and is not covered by the light-emitting layer 50. Consequently, the hole injection layer 40 is likely to contact the functional electrode layer 60 above the light-emitting layer 50, resulting in leakage current and affecting device performance and display effect.

[0078] In some embodiments, the hydrophilicity and hydrophobicity of the top surface 202 and the side surface 203 can be achieved by forming a hydrophilic or hydrophobic film on the surface of the baffle 21; or, a hydrophobic material, such as fluorine, can be added to the material of the baffle 21, and the hydrophobic material is mainly distributed on the side of the baffle 21 away from the array substrate 10, for example, the concentration of the hydrophobic material on the side of the baffle 21 away from the array substrate 10 is greater than the concentration of the hydrophobic material on the side of the baffle 21 close to the array substrate 10, so that the top surface 202 and the second sub-surface 2032 on the side of the baffle 21 away from the array substrate 10 are hydrophobic, while the first sub-surface 2031 on the side of the baffle 21 close to the array substrate 10 is hydrophilic.

[0079] In some embodiments, the ratio of the concentration of the hydrophobic material at the second sub-surface 2032 to the concentration of the hydrophobic material at the first sub-surface 2031 is greater than or equal to 3; for example, as shown in FIG5, when the hydrophobic material is fluorine, the fluorine content at the first sub-surface 2031 and the second sub-surface 2032 can be detected.

[0080] In this embodiment, the first sub-surface 2031 has a first height H1 along the thickness direction of the display panel, and the baffle 21 has a second height H2 along the thickness direction of the display panel. The ratio of the first height H1 to the second height H2 is greater than or equal to 0.5. That is, by increasing the height of the first sub-surface 2031, this embodiment increases the climbing distance of the hole injection part 41 and the light-emitting part 51 on the side surface 203. Even if the hole injection part 41 is connected to the functional electrode layer 60 at the climbing point, the position where the hole injection part 41 and the functional electrode 60 are connected can be moved away from the anode 31, so that the short-circuit point is farther from the center of the hole injection part 41, extending the leakage path, increasing the resistance, and thus effectively reducing the leakage current and improving the performance and display effect of the display panel.

[0081] In some embodiments, the ratio of the first height H1 to the second height H2 can be 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, or 1.

[0082] In one embodiment of this application, referring to Figures 3 and 4, the edge of the hole injection section 41 extends to the side surface 203, and the functional electrode layer 60 extends to the side surface 203 and is connected to the hole injection section 41.

[0083] Since the contact angle of the first sub-surface 2031 is smaller than that of the second sub-surface 2032, for example, the first sub-surface 2031 is hydrophilic while the second sub-surface 2032 is hydrophobic, the ink will be confined to the first sub-surface 2031 during the process. Therefore, the ramp edges of the hole injection section 41 and the light-emitting section 51 should not extend beyond the range of the first sub-surface 2031.

[0084] In some embodiments, the connection between the hole injection portion 41 and the functional electrode layer 60 is located on the first sub-surface 2031, and on the side of the first sub-surface 2031 closer to the second sub-surface 2032. Furthermore, by increasing the height of the first sub-surface 2031, the connection point between the hole injection portion 41 and the functional electrode 60 can be effectively moved away from the anode 31, making the short-circuit point farther from the center of the hole injection portion 41, extending the leakage path, increasing the resistance, and thus effectively reducing the leakage current and improving the performance and display effect of the display panel.

[0085] In some embodiments, within the pixel opening 201, at least one edge of the light-emitting portion 51 is spaced apart from the side surface 203, and the functional electrode layer 60 covers the light-emitting portion 51 and extends to the side surface 203 to connect with the hole injection portion 41.

[0086] In some embodiments, the orthogonal projection of the light-emitting portion 51 on the array substrate 10 is located within the orthogonal projection of the hole injection portion 41 on the array substrate 10.

[0087] In some embodiments, the display panel further includes a hole transport layer 70 disposed between the hole injection layer 40 and the light-emitting layer 50. The hole transport layer 70 includes a hole transport portion 71 disposed between the hole injection portion 41 and the light-emitting portion 51 and located within the pixel opening 201. Within the pixel opening 201, at least one edge of the hole transport portion 71 is spaced apart from the side surface 203. The functional electrode layer 60 covers the light-emitting portion 51 and the hole transport portion 71 and extends to the side surface 203 to connect with the hole injection portion 41.

[0088] In some embodiments, the orthographic projection of the hole transport section 71 on the array substrate 10 is located within the orthographic projection of the hole injection section 41 on the array substrate 10.

[0089] In some embodiments, as shown in Figures 3 and 4, the functional electrode layer 60 includes a cathode layer 61, and the hole injection portion 41 is connected to the cathode layer 61 at the side surface 203.

[0090] In some other embodiments, as shown in FIG6, the functional electrode layer 60 includes an electron transport layer 62 and a cathode layer 61, and the electron transport layer 62 is located between the light-emitting part 51 and the cathode layer 61. At the side surface 203, the hole injection part 41 is connected to the electron transport layer 62.

[0091] It is understood that by increasing the height of the first sub-surface 2031, the leakage current between the hole injection section 41 and the cathode layer 61, or the leakage current between the hole injection section 41 and the electron transport layer 62, can be reduced in the embodiments of this application.

[0092] In some embodiments, referring to Figures 3 and 7, the first sub-surface 2031 is connected to the second sub-surface 2032, and the first sub-surface 2031 and the second sub-surface 2032 intersect at the connection point at a preset angle B, wherein the preset angle B is less than or equal to 180°.

[0093] Further, the first sub-surface 2031 includes a first side close to the array substrate 10 and a second side away from the array substrate 10, and the second sub-surface 2032 includes a third side close to the array substrate 10 and a fourth side away from the array substrate 10. There is a first distance L1 between the first side and the second side, and a second distance L2 between the third side and the fourth side. The ratio of the first distance L1 to the second distance L2 is greater than or equal to 1.

[0094] It should be noted that when the preset included angle B is equal to 180°, the first sub-surface 2031 and the second sub-surface 2032 are coplanar. At this time, the ratio of the first height H1 to the second height H2 is equal to the ratio of the first distance L1 to the sum of the first distance L1 and the second distance L2.

[0095] In some embodiments, the corner where the second sub-surface 2032 connects to the top surface 202 can be a rounded corner, as shown in Figure 8.

[0096] Furthermore, in this embodiment of the application, referring to Figures 9 and 10, the barrier 21 includes a first sub-part 211 and a second sub-part 212 stacked together, and the first sub-part 211 is located between the second sub-part 212 and the array substrate 10.

[0097] In some embodiments, the plurality of pixel openings 201 are arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y may be perpendicular.

[0098] In some embodiments, the first sub-part 211 extends along the first direction X and the second direction Y and is disposed around each of the pixel openings 201; the second sub-part 212 extends along the second direction Y, and a plurality of the second sub-parts 212 are arranged along the first direction X, that is, the second sub-parts 212 are located on the side of the first sub-part 211 extending along the second direction Y away from the array substrate 10.

[0099] Among them, a plurality of pixel openings 201 arranged along the second direction Y are provided between two adjacent second sub-parts 212, and the second sub-part 212 has a first sub-surface 2031 and a second sub-surface 2032 on the side near the pixel opening 201.

[0100] In this embodiment, a first sub-part 211 and a second sub-part 212 are stacked between two adjacent pixel openings 201 along the first direction X, and a first sub-part 211 is disposed between two adjacent pixel openings 201 along the second direction Y. That is, the height of the barrier 21 between two adjacent pixel openings 201 along the first direction X is greater than the height of the barrier 21 between two adjacent pixel openings 201 along the second direction Y. Therefore, in the inkjet printing process of the display panel, the hole injection layer 40 and the light-emitting layer 50 are continuously disposed along the second direction Y, and the hole injection layer 40 and the light-emitting layer 50 are spaced apart along the first direction X. That is, the hole injection layer 40 and the light-emitting layer 50 along the first direction X are separated by the second sub-part 212, and the hole injection part 41 and the light-emitting part 51 will generate a slope at the side surface 203 of the second sub-part 212.

[0101] Continuing from the above, by increasing the height of the first sub-surface 2031, the proportion of the portion with a smaller contact angle in the side surface 203 of the barrier 21 can be increased. Consequently, during the manufacturing process of the display panel, the climbing height of the ink on the side surface 203 increases, and the connection position between the hole injection part 41 and the functional electrode layer 60 also increases, thereby lengthening the leakage path, increasing resistance, and reducing leakage current, which in turn helps to improve the performance and display effect of the display panel.

[0102] In other embodiments of this application, the hole injection section 41 and the functional electrode layer 60 may also be spaced apart, that is, the hole injection section 41 and the functional electrode layer 60 are not short-circuited.

[0103] Wherein, the orthogonal projection of the hole injection section 41 on the array substrate 10 is located within the orthogonal projection of the light emission section 51 on the array substrate 10, and / or the orthogonal projection of the hole injection section 41 on the array substrate 10 is located within the orthogonal projection of the hole transmission section 71 on the array substrate 10.

[0104] In addition, this application embodiment also provides a method for manufacturing the display panel described in the above embodiments, specifically including how to control the height of the first sub-surface 2031.

[0105] Referring to Figures 3, 11, and 12, firstly, the barrier intermediate body 23 is formed on the anode layer 30, and the barrier intermediate body 23 has a first surface 204 on the side away from the anode layer 30 and a second surface 205 connected to the first surface 204, as shown in Figure 11.

[0106] In some embodiments, the contact angle of the first surface 204 is greater than the contact angle of the second surface 205; further, the first surface 204 is hydrophobic and the second surface 205 is hydrophilic, that is, the contact angle of the first surface 204 is greater than 90° and the contact angle of the second surface 205 is less than 90°.

[0107] In some embodiments, the hydrophilicity and hydrophobicity of the first surface 204 and the second surface 205 can be achieved by forming a hydrophilic or hydrophobic film on the surface of the retaining wall intermediate 23; or, a hydrophobic material, such as fluorine, can be added to the material of the retaining wall intermediate 23, and the hydrophobic material is mainly distributed on the side of the retaining wall intermediate 23 away from the anode layer 30, for example, the concentration of the hydrophobic material on the side of the retaining wall intermediate 23 away from the anode layer 30 is greater than the concentration of the hydrophobic material on the side of the retaining wall intermediate 23 close to the anode layer 30, so that the first surface 204 of the retaining wall intermediate 23 away from the anode layer 30 is hydrophobic, while the second surface 205 of the retaining wall intermediate 23 close to the anode layer 30 is hydrophilic.

[0108] Next, the intermediate barrier 23 is baked and cured. During the baking process, the intermediate barrier 23 softens and flows, causing a portion of the first surface 204 to flow to the side of the intermediate barrier 23, thereby making the portion of the side of the intermediate barrier 23 away from the anode layer 30 hydrophobic.

[0109] This leads to the structure of the pixel definition layer 20 shown in Figure 12, wherein in the barrier 21 of the pixel definition layer 20, the second sub-surface 2032 on the side away from the anode layer 30 of the top surface 202 and the side surface 203 is hydrophobic, while the first sub-surface 2031 on the side surface 203 near the anode layer 30 is hydrophilic.

[0110] It should be noted that the area of ​​the first surface 204 flowing to the side of the barrier intermediate body 23 can be controlled by controlling the baking time of the barrier intermediate body 23, thereby controlling the height or length ratio of the first sub-surface 2031. For example, the shorter the baking time, the smaller the height and length ratio of the second sub-surface 2032, and the larger the height or length ratio of the first sub-surface 2031. The leakage current generated between the hole injection part 41 and the functional electrode layer 60 is smaller, which is more beneficial to the performance improvement of the display panel.

[0111] In other embodiments of this application, the height or length ratio of the first sub-surface 2031 can also be controlled by controlling the height of the retaining wall 21. For example, the higher the height of the retaining wall 21, the greater the height or length ratio of the first sub-surface 2031. Specifically, the height of the second retaining wall 212 can be increased, and / or the height of the first retaining wall 211 can be increased.

[0112] In addition, this application embodiment also provides a display device, which includes the display panel described in the above embodiments.

[0113] It is understood that since the display device has the same beneficial effects as the display panel, it will not be elaborated further here.

[0114] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0115] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0116] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0117] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel comprising: Array substrate; A pixel definition layer is disposed on the array substrate. The pixel definition layer has multiple pixel openings. The pixel definition layer includes a barrier wall disposed between adjacent pixel openings. The side surface of the barrier wall near the pixel opening includes a first sub-surface and a second sub-surface. The first sub-surface is located between the array substrate and the second sub-surface. The contact angle of the first sub-surface is smaller than the contact angle of the second sub-surface. The first sub-surface has a first height along the thickness direction of the display panel, and the barrier wall has a second height along the thickness direction of the display panel, wherein the ratio of the first height to the second height is greater than or equal to 0.

5.

2. The display panel according to claim 1, wherein, The display panel also includes: Hole injection layer, including a hole injection portion disposed within the pixel opening; The light-emitting layer includes a light-emitting portion disposed within the pixel opening and located on the side of the hole injection portion away from the array substrate; A functional electrode layer is disposed on the pixel definition layer and extends into the pixel opening, and the functional electrode layer located in the pixel opening is located on the side of the light-emitting part away from the hole injection part; The edge of the hole injection portion extends to the side surface, and the functional electrode layer extends to the side surface and connects with the hole injection portion.

3. The display panel according to claim 2, wherein, The connection between the hole injection section and the functional electrode layer is located on the first sub-surface, and on the side of the first sub-surface closer to the second sub-surface.

4. The display panel according to claim 2, wherein, The orthogonal projection of the light-emitting part on the array substrate is located within the orthogonal projection of the hole injection part on the array substrate.

5. The display panel according to claim 2, wherein, Within the pixel opening, at least one edge of the light-emitting portion is spaced apart from the side surface, and the functional electrode layer covers the light-emitting portion and extends to the side surface to connect with the hole injection portion.

6. The display panel according to claim 2, wherein, The functional electrode layer includes a cathode layer, and the hole injection portion is connected to the cathode layer at the side surface; Alternatively, the functional electrode layer may include an electron transport layer and the cathode layer, with the electron transport layer located between the light-emitting portion and the cathode layer, and the hole injection portion connected to the electron transport layer at the side surface.

7. The display panel according to claim 2, wherein, The display panel further includes a hole transport layer disposed between the hole injection layer and the light-emitting layer, the hole transport layer including a hole transport portion disposed between the hole injection portion and the light-emitting portion and located within the pixel opening; Within the pixel opening, at least one edge of the hole transport section is spaced apart from the side surface, and the functional electrode layer covers the light-emitting section and the hole transport section and extends to the side surface to connect with the hole injection section.

8. The display panel according to claim 1, wherein, The display panel also includes: Hole injection layer, including a hole injection portion disposed within the pixel opening; The light-emitting layer includes a light-emitting portion disposed within the pixel opening and located on the side of the hole injection portion away from the array substrate; A functional electrode layer is disposed on the pixel definition layer and extends into the pixel opening, and the functional electrode layer located in the pixel opening is located on the side of the light-emitting part away from the hole injection part; The hole injection section is spaced apart from the functional electrode layer.

9. The display panel according to any one of claims 1 to 8, wherein, The first sub-surface is connected to the second sub-surface, and the first sub-surface and the second sub-surface intersect at a preset angle at the connection point, wherein the preset angle is less than or equal to 180°.

10. The display panel according to any one of claims 1 to 8, wherein, The first sub-surface includes a first side close to the array substrate and a second side away from the array substrate, the second sub-surface includes a third side close to the array substrate and a fourth side away from the array substrate, a first distance is between the first side and the second side, a second distance is between the third side and the fourth side, and the ratio of the first distance to the second distance is greater than or equal to 1.

11. The display panel according to any one of claims 1 to 8, wherein, The first sub-surface is hydrophilic, and the second sub-surface is hydrophobic.

12. The display panel according to any one of claims 1 to 8, wherein, The plurality of pixel openings are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect. The barrier includes a first sub-part and a plurality of second sub-parts stacked together. The first sub-part is located between the array substrate and the second sub-parts. The first sub-part extends along the first direction and the second direction and is disposed around each of the pixel openings. The second sub-part extends along the second direction, and a plurality of second sub-parts are arranged along the first direction. A plurality of pixel openings arranged along the second direction are provided between two adjacent second sub-parts. The side of the second sub-part near the pixel opening has a first sub-surface and a second sub-surface.

13. A display device, the display device comprising a display panel, the display panel comprising: Array substrate; A pixel definition layer is disposed on the array substrate. The pixel definition layer has multiple pixel openings. The pixel definition layer includes a barrier wall disposed between adjacent pixel openings. The side surface of the barrier wall near the pixel opening includes a first sub-surface and a second sub-surface. The first sub-surface is located between the array substrate and the second sub-surface. The contact angle of the first sub-surface is smaller than the contact angle of the second sub-surface. The first sub-surface has a first height along the thickness direction of the display panel, and the barrier wall has a second height along the thickness direction of the display panel, wherein the ratio of the first height to the second height is greater than or equal to 0.

5.

14. The display device according to claim 13, wherein, The display panel also includes: Hole injection layer, including a hole injection portion disposed within the pixel opening; The light-emitting layer includes a light-emitting portion disposed within the pixel opening and located on the side of the hole injection portion away from the array substrate; A functional electrode layer is disposed on the pixel definition layer and extends into the pixel opening, and the functional electrode layer located in the pixel opening is located on the side of the light-emitting part away from the hole injection part; The edge of the hole injection portion extends to the side surface, and the functional electrode layer extends to the side surface and connects with the hole injection portion.

15. The display device according to claim 14, wherein, The connection between the hole injection section and the functional electrode layer is located on the first sub-surface, and on the side of the first sub-surface closer to the second sub-surface.

16. The display device according to claim 14, wherein, The orthogonal projection of the light-emitting part on the array substrate is located within the orthogonal projection of the hole injection part on the array substrate.

17. The display device according to claim 14, wherein, Within the pixel opening, at least one edge of the light-emitting portion is spaced apart from the side surface, and the functional electrode layer covers the light-emitting portion and extends to the side surface to connect with the hole injection portion.

18. The display device according to claim 14, wherein, The functional electrode layer includes a cathode layer, and the hole injection portion is connected to the cathode layer at the side surface; Alternatively, the functional electrode layer may include an electron transport layer and the cathode layer, with the electron transport layer located between the light-emitting portion and the cathode layer, and the hole injection portion connected to the electron transport layer at the side surface.

19. The display device according to claim 14, wherein, The display panel further includes a hole transport layer disposed between the hole injection layer and the light-emitting layer, the hole transport layer including a hole transport portion disposed between the hole injection portion and the light-emitting portion and located within the pixel opening; Within the pixel opening, at least one edge of the hole transport section is spaced apart from the side surface, and the functional electrode layer covers the light-emitting section and the hole transport section and extends to the side surface to connect with the hole injection section.

20. The display device according to claim 13, wherein, The display panel also includes: Hole injection layer, including a hole injection portion disposed within the pixel opening; The light-emitting layer includes a light-emitting portion disposed within the pixel opening and located on the side of the hole injection portion away from the array substrate; A functional electrode layer is disposed on the pixel definition layer and extends into the pixel opening, and the functional electrode layer located in the pixel opening is located on the side of the light-emitting part away from the hole injection part; The hole injection section is spaced apart from the functional electrode layer.

Images