Display panel and display device

Abstract

The present invention relates to the technical field of display. Provided are a display panel and a display device, which are used to improve load uniformity of scan lines. The display panel comprises: an active area comprising a second active area, the second active area comprising a light-transmitting hole and sub-regions; and a first scan line located at least in the active area and comprising a wiring portion, the wiring portion comprising a first sub-wiring and a second sub-wiring that are electrically connected, wherein the first sub-wiring overlaps the second sub-wiring of the wiring portion. The first scan line comprises a second sub-scan line at least partially located in the second active area. The second sub-scan line comprises at least two wiring portions, each wiring portion corresponding to one sub-region. The second sub-scan line further comprises a first bypass wiring, wherein wiring portions located on two sides of the light-transmitting hole are connected via the first bypass wiring. At least one wiring portion of the second sub-scan line comprises a first wiring portion comprising a first side and a second side opposite each other, wherein the first sub-wiring and the second sub-wiring of the first wiring portion are connected at the first side and are not connected at the second side.

Description

Display panel and display device

[0001] This invention claims priority to Chinese Patent Application No. 202510103727.0, filed with the State Intellectual Property Office of China on January 22, 2025, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] The display panel includes pixel circuitry and scan lines electrically connected to the pixel circuitry. When the display area of ​​the display panel includes a light-transmitting aperture, the scan lines need to be wound around the light-transmitting aperture.

[0004] However, this winding design can lead to inconsistent loads on the scan lines in different display areas, thus affecting display uniformity. Summary of the Invention

[0005] This invention provides a display panel and a display device for improving the load uniformity of scan lines in the display panel.

[0006] In a first aspect, embodiments of the present invention provide a display panel, comprising:

[0007] Substrate;

[0008] The display area includes a first display area and a second display area arranged along a first direction. The second display area includes a light-transmitting hole and a sub-area arranged along the second direction. The sub-area is located on the opposite side of the light-transmitting hole. The first direction intersects the second direction. The display area includes the pixel circuit.

[0009] A first scan line is at least partially located in the display area and electrically connected to the pixel circuit. The first scan line includes at least one trace portion, and the trace portion includes a first sub-trace and a second sub-trace that are electrically connected. In a direction perpendicular to the plane of the substrate, the first sub-trace and the second sub-trace in the same trace portion at least partially overlap.

[0010] The first scan line includes a first sub-scan line and a second sub-scan line, wherein the first sub-scan line is at least partially located in the first display area and the second sub-scan line is at least partially located in the second display area;

[0011] The first sub-scan line includes a routing section, and the first sub-routes and the second sub-routes in the same routing section pass through the first display area along the second direction, and the first sub-routes and the second sub-routes are connected at both ends;

[0012] The second sub-scan line includes at least two of the said trace portions, and the second sub-scan line also includes a first winding around the light-transmitting aperture. In the same second sub-scan line, one of the trace portions corresponds to one of the said sub-regions, and the two trace portions on both sides of the light-transmitting aperture are connected by the first winding. Furthermore, the trace portion in at least one second sub-scan line includes a first trace portion, and the first trace portion includes a first side and a second side opposite to each other in the second direction. The first sub-trace and the second sub-trace in the first trace portion are connected on the first side and not connected on the second side.

[0013] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel.

[0014] The technical solution provided by the embodiments of the present invention has the following beneficial effects:

[0015] In this embodiment of the invention, the second sub-scan line includes a first routing section. The first sub-routes and second sub-routes in the first routing section are connected only on one side, and not on the other side. Compared to the prior art design where the first and second sub-routes in the routing section on the light-transmitting hole side are connected at both ends, the first and second sub-routes in the aforementioned first routing section do not form a parallel structure. Therefore, the overall load of the second sub-scan line is increased. The increased load on the second sub-scan line caused by the first routing section is used to offset the reduced load caused by the winding design, making the load of the second sub-scan line more consistent with the load of the first sub-scan line. This reduces the load difference between the first scan lines in different display areas and effectively improves the display uniformity of the display panel. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 is a schematic diagram of a display panel structure in the prior art;

[0018] Figure 2 is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of a signal transmission corresponding to Figures 3 and 4;

[0022] Figure 6 is another schematic diagram of signal transmission corresponding to Figures 3 and 4;

[0023] Figure 7 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0024] Figure 8 is a schematic diagram of a signal transmission corresponding to Figure 7;

[0025] Figure 9 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0026] Figure 10 is a schematic diagram of a signal transmission corresponding to Figure 9;

[0027] Figure 11 is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0028] Figure 12 is a timing diagram corresponding to Figure 11;

[0029] Figure 13 is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention;

[0030] Figure 14 is a cross-sectional view of Figure 9 along the A1-A2 direction;

[0031] Figure 15 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0032] Figure 16 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0033] Figure 17 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention;

[0034] Figure 18 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0035] Figure 19 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0036] Figure 20 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0037] Figure 21 is a schematic diagram of a structure of the second sub-scan line provided in an embodiment of the present invention;

[0038] Figure 22 is a cross-sectional view of Figure 21 along the B1-B2 direction;

[0039] Figure 23 is a schematic diagram of another structure of the second sub-scan line provided in an embodiment of the present invention;

[0040] Figure 24 is a cross-sectional view of Figure 23 along the C1-C2 direction;

[0041] Figure 25 is a schematic diagram of another structure of the second sub-scan line provided in an embodiment of the present invention;

[0042] Figure 26 is a cross-sectional view of Figure 25 along the D1-D2 direction;

[0043] Figure 27 is a schematic diagram of another structure of the second sub-scan line provided in an embodiment of the present invention;

[0044] Figure 28 is a cross-sectional view of Figure 27 along the E1-E2 direction;

[0045] Figure 29 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0046] Figure 30 is a cross-sectional view of Figure 29 along the F1-F2 direction;

[0047] Figure 31 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0048] Figure 32 is a cross-sectional view of Figure 31 along the G1-G2 direction;

[0049] Figure 33 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0050] Figure 34 is a cross-sectional view of Figure 33 along the H1-H2 direction;

[0051] Figure 35 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0052] Figure 36 is a cross-sectional view of Figure 35 along the I1-I2 direction;

[0053] Figure 37 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0054] Figure 38 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0055] Figure 39 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0056] Figure 40 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0057] Figure 41 is a schematic diagram of another structure of the second sub-scan line provided in an embodiment of the present invention;

[0058] Figure 42 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0059] Figure 43 is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0060] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0061] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0062] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0063] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0064] The display panel includes pixel circuitry and scan lines electrically connected to the pixel circuitry. Currently, at least one scan line can employ a double-layer routing design. The following describes one structural design used in this type of scan line in the prior art.

[0065] As shown in Figure 1, which is a schematic diagram of a display panel in the prior art, the display area of ​​the display panel includes a first display area 01 and a second display area 02 arranged along a first direction x. The second display area 02 includes a light-transmitting hole 03 and sub-areas 04 located on opposite sides of the light-transmitting hole 03 along a second direction y, where the second direction y intersects the first direction x.

[0066] The display panel also includes a substrate 05, a pixel circuit 06, and a first scan line 07. The first scan line 07 is electrically connected to the pixel circuit 06 and includes a first sub-line 08 and a second sub-line 09. In a direction perpendicular to the plane of the substrate 05, the first sub-line 08 and the second sub-line 09 at least partially overlap.

[0067] For the first scan line 07 in the first display area 01, since the first display area 01 does not have a light-transmitting hole 03, the first sub-line 08 and the second sub-line 09 in this part of the first scan line 07 both pass through the first display area 01 laterally, and the first sub-line 08 and the second sub-line 09 in the same first scan line 07 are connected at both ends.

[0068] For the first scan line 07 in the second display area 02, since a light-transmitting hole 03 is provided in the second display area 02, this part of the first scan line 07 needs to adopt a winding design at the light-transmitting hole 03. In the first scan line 07 of the second display area 02, the first sub-trace 08 in the same first scan line 07 is broken on both sides of the light-transmitting hole 03 to form a discontinuous trace. The first sub-trace 08 broken on one side of the light-transmitting hole 03 is connected to the second sub-trace 09 at both ends. Then, the second sub-trace 09 is connected to the second sub-trace 09 on the other side of the light-transmitting hole 03 through the winding 010 to form a continuous signal transmission path.

[0069] However, the inventors discovered that with the above design, the load on the first scan line 07 in different display areas will have significant differences:

[0070] To improve the transmittance of the light-transmitting aperture 03, sub-pixels are typically not set within the aperture 03, or the density of sub-pixels is very low. This results in the windings 010 in the first scan line 07 of the second display area 02 not being connected to, or only connecting to, a very small number of pixel circuits 06. Furthermore, the coupling between the windings 010 and the pixel circuits 06 is very small. Consequently, the load on the first scan line 07 in the second display area 02 is significantly lower than that in the first display area 01. This difference in load between the first scan lines 07 further leads to display differences between the second display area 02 and the first display area 01, causing a noticeable horizontal mura phenomenon on the display panel.

[0071] In this regard, the present invention provides a display panel, as shown in Figures 2 to 4. Figure 2 is a schematic diagram of one structure of the display panel provided in the present invention, Figure 3 is a schematic diagram of another structure of the display panel provided in the present invention, and Figure 4 is a schematic diagram of yet another structure of the display panel provided in the present invention. The display panel includes a substrate 1, which can be a rigid substrate such as glass or a flexible substrate such as polyimide.

[0072] The display panel also includes a display area AA, which includes a first display area AA1 and a second display area AA2 arranged along a first direction x. The second display area AA2 includes a light-transmitting hole 2 and a sub-area 3 arranged along a second direction y. Optical components such as a camera are correspondingly disposed at the light-transmitting hole 2, and the sub-area 3 is located on the opposite side of the light-transmitting hole 2. The first direction x and the second direction y intersect.

[0073] In other words, the second display area AA2 includes m light-transmitting holes 2 and m+1 sub-areas 3, where m ≥ 1, for example, m = 1, 2, 3, etc. The sub-areas 3 and the light-transmitting holes 2 are arranged alternately along the second direction y, and a sub-area 3 is provided on each side of the opposite side of each light-transmitting hole 2. This embodiment of the invention is illustrated by taking the second display area AA2 including one light-transmitting hole 2 as an example.

[0074] The display area AA also includes pixel circuits 4.

[0075] The display panel also includes a first scan line 5, at least a portion of which is located in the display area AA and electrically connected to the pixel circuit 4. The first scan line 5 includes at least one trace portion 6, which includes a first sub-trace 7 and a second sub-trace 8 that are electrically connected. In a direction perpendicular to the plane of the substrate 1, the first sub-trace 7 and the second sub-trace 8 in the same trace portion 6 at least partially overlap.

[0076] The first scan line 5 includes a first sub-scan line 5-1 and a second sub-scan line 5-2. The first sub-scan line 5-1 is at least partially located in the first display area AA1, and the second sub-scan line 5-2 is at least partially located in the second display area AA2.

[0077] For the first sub-scan line 5-1, the first sub-scan line 5-1 includes a routing section 6, the first sub-routing line 7 and the second sub-routing line 8 in the same routing section 6 pass through the first display area AA1 along the second direction y, and the first sub-routing line 7 and the second sub-routing line 8 in the same routing section 6 are connected at both ends.

[0078] For example, in a more specific structure, the display panel further includes a first non-display area NAA1 surrounding the display area AA. In the same routing section 6 of the first sub-scan line 5-1, both the first sub-routes 7 and 8 laterally penetrate the first display area AA1 and extend into the first non-display areas NAA1 on both sides of the first display area AA1. Specifically, the first sub-routes 7 and 8 in the routing section 6 are connected at both ends; that is, the first sub-routes 7 and 8 are connected in the first non-display area NAA1 on one side of the first display area AA1 and also connected in the first non-display area NAA1 on the other side of the first display area AA1.

[0079] For the second sub-scan line 5-2, the second sub-scan line 5-2 includes at least two routing portions 6, and the second sub-scan line 5-2 also includes a first winding 9 surrounding the light-transmitting aperture 2. In the same second sub-scan line 5-2, one routing portion 6 corresponds to one sub-region 3, and the two routing portions 6 on both sides of the light-transmitting aperture 2 are connected by the first winding 9. Among them, the routing portion 6 in at least one second sub-scan line 5-2 includes a first routing portion 10, the first routing portion 10 includes a first side fd and a second side sd opposite each other in the second direction y, and the first sub-routes 7 and the second sub-routes 8 in the first routing portion 10 are connected on the first side fd and not connected on the second side sd.

[0080] For example, in a more specific structure, the display panel further includes a first non-display area NAA1 surrounding the display area AA, and the display area AA also includes a second non-display area NAA2 surrounding the light-transmitting hole 2, the second non-display area NAA2 being located between the light-transmitting hole 2 and the sub-area 3. In the same first trace portion 10 of the second sub-scan line 5-2, both the first sub-trace 7 and the second sub-trace 8 laterally penetrate their respective sub-area 3 and extend to the first non-display area NAA1 and the second non-display area NAA2 on both sides of the sub-area 3. One side of the first side fd and the second side sd of the first trace portion 10 can be understood as the first non-display area NAA1 located on one side of the sub-area 3, and the other side can be understood as the second non-display area NAA2 located on the other side of the sub-area 3. The first sub-line 7 and the second sub-line 8 in the first wiring section 10 are connected on the first side fd and not connected on the second side sd. Specifically, the first sub-line 7 and the second sub-line 8 are connected in the first non-display area NAA1 on one side of the sub-area 3 and not connected in the second non-display area NAA2 on the other side of the sub-area 3, or the first sub-line 7 and the second sub-line 8 are connected in the second non-display area NAA2 on one side of the sub-area 3 and not connected in the first non-display area NAA1 on the other side of the sub-area 3.

[0081] In the technical solution provided in the embodiments of the present invention, the second sub-scan line 5-2 includes a first routing section 10. The first sub-routes 7 and 8 in the first routing section 10 are connected only on one side and not on the other side. The first sub-routes 7 and 8 in the first routing section 10 do not form a parallel structure. Compared with the structure shown in FIG1, this will increase the load of the second sub-scan line 5-2. The increased load of the second sub-scan line 5-2 caused by the first routing section 10 can be used to offset the reduced load of the second sub-scan line 5-2 caused by the winding design, so that the load of the second sub-scan line 5-2 is more consistent with the load of the first sub-scan line 5-1. This reduces the load difference between the first scan lines 5 in different display areas AA and effectively improves the display uniformity of the display panel.

[0082] In one feasible implementation, referring to Figures 3 and 4, the first side fd is the side of the first wiring section 10 closest to the light-transmitting hole 2. That is, the first sub-wiring line 7 and the second sub-wiring line 8 in the first wiring section 10 are connected on the side closest to the light-transmitting hole 2, and are not connected on the side furthest from the light-transmitting hole 2.

[0083] Referring to Figures 5 and 6, the display panel also includes a first shift register 12, which is electrically connected to the first sub-scan line 5-1 and the second sub-scan line 5-2, and is used to provide a first scan signal to the first sub-scan line 5-1 and the second sub-scan line 5-2.

[0084] In this embodiment of the invention, the first shift register 12 drives the first scan line 5 connected to it on one side only, that is, the first scan line 5 is electrically connected to only one first shift register 12 on one side. This part is described in detail in the embodiment related to FIG18.

[0085] Taking the connection between the first shift register 12 and the first trace 10 in the second sub-scan line 5-2 as an example.

[0086] When the first side fd is the side of the first trace section 10 closest to the light-transmitting hole 2, in one case, referring to Figures 3, 4, and 5 (Figure 5 is a signal transmission schematic corresponding to Figures 3 and 4), the first shift register 12 is connected to the first sub-trace 7 in the first trace section 10. The first scan signal provided by the first shift register 12 first flows to the first sub-trace 7 in the first trace section 10. When it is transmitted to the end of the first sub-trace 7 closest to the light-transmitting hole 2, it will continue to be transmitted to the trace section 6 on the other side of the light-transmitting hole 2 via the first winding 9, and to the second sub-trace 8 in the first trace section 10, thereby realizing that each first sub-trace 7 and each second sub-trace 8 in the second sub-scan line 5-2 normally receives the first scan signal.

[0087] In another scenario, referring to Figures 3, 4, and 6 (Figure 6 being a schematic diagram of another signal transmission corresponding to Figures 3 and 4), the first shift register 12 is connected to the second sub-trace 8 in the first trace section 10. The first scan signal provided by the first shift register 12 first flows to the second sub-trace 8 in the first trace section 10. When it reaches the end of the second sub-trace 8 near the light-transmitting hole 2, it continues to be transmitted via the first winding 9 to the trace section 6 on the other side of the light-transmitting hole 2, and to the first sub-trace 7 in the first trace section 10. This ensures that each first sub-trace 7 and each second sub-trace 8 in the second sub-scan lines 5-2 normally receives the first scan signal.

[0088] In the attached diagram, R1' represents the resistance of the first sub-line 7 of the routing section 6 in the first sub-scan line 5-1, R2' represents the resistance of the second sub-line 8 of the routing section 6 in the first sub-scan line 5-1, R1 represents the resistance of the first sub-line 7 of the routing section 6 in the second sub-scan line 5-2, R2 represents the resistance of the second sub-line 8 of the routing section 6 in the second sub-scan line 5-2, and R3 represents the resistance of the first winding 9 in the second sub-scan line 5-2.

[0089] It should be noted that, within the same second sub-scan line 5-2, the values ​​of resistor R1 corresponding to the first sub-line 7 in different routing sections 5 can be the same or different, and the values ​​of resistor R2 corresponding to the second sub-line 8 in different routing sections 5 can be the same or different.

[0090] For example, display area 1 includes a first side and a second side opposite to each other along the second direction y. In one case, along the second direction y, the distance between the light-transmitting hole 2 and the first side and the distance between the light-transmitting hole 2 and the second side are equal. In this case, within the same second sub-scan line 5-2, the resistance R1 values ​​corresponding to the first sub-trace 7 in different trace portions 5 can be equal, and the resistance R2 values ​​corresponding to the second sub-trace 8 in different trace portions 5 can also be equal. Alternatively, in another case, along the second direction y, the distance between the light-transmitting hole 2 and the first side and the distance between the light-transmitting hole 2 and the second side are not equal. In this case, within the same second sub-scan line 5-2, the resistance R1 values ​​corresponding to the first sub-trace 7 in different trace portions 5 can also be unequal, and the resistance R2 values ​​corresponding to the second sub-trace 8 in different trace portions 5 can also be unequal.

[0091] When the display panel includes at least two light-transmitting holes 2, it means that the same second sub-scan line 5-2 includes at least two first windings 9. Within the same second sub-scan line 5-2, the resistance R3 values ​​corresponding to different first windings 9 can be the same or different. For example, when the shape and area of ​​at least two light-transmitting holes 2 are the same, the resistance R3 values ​​corresponding to different first windings 9 within the same second sub-scan line 5-2 can be equal. Alternatively, when the shape and area of ​​at least two light-transmitting holes 2 are different, the resistance R3 values ​​corresponding to different first windings 9 within the same second sub-scan line 5-2 can also be unequal.

[0092] Alternatively, in another feasible implementation, as shown in Figures 7 to 10, Figure 7 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention, Figure 8 is a schematic diagram of a signal transmission corresponding to Figure 7, Figure 9 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention, and Figure 10 is a schematic diagram of a signal transmission corresponding to Figure 9. The first side fd is the side of the first wiring portion 10 away from the light-transmitting hole 2. That is, the first sub-wiring line 7 and the second sub-wiring line 8 in the first wiring portion 10 are connected on the side away from the light-transmitting hole 2, and are not connected on the side close to the light-transmitting hole 2.

[0093] Referring to Figures 8 and 10, the display panel includes a first shift register 12, which is electrically connected to the first sub-scan line 5-1 and the second sub-scan line 5-2, and is used to provide a first scan signal to the first sub-scan line 5-1 and the second sub-scan line 5-2.

[0094] Taking the connection between the first shift register 12 and the first trace 10 in the second sub-scan line 5-2 as an example.

[0095] When the first side fd is the side of the first trace section 10 furthest from the light-transmitting hole 2, in one case, referring to Figures 7 and 8, the first winding 9 is connected to the first sub-trace 7. The first scan signal provided by the first shift register 12 flows simultaneously to the first sub-trace 7 and the second sub-trace 8 in the first trace section 10. When the first scan signal is transmitted to the end of the second sub-trace 8 near the light-transmitting hole 2, it stops transmitting. However, when the first scan signal is transmitted to the end of the first sub-trace 7 near the light-transmitting hole 2, it continues to be transmitted to the trace section 6 on the other side of the light-transmitting hole 2 via the first winding 9. This ensures that each first sub-trace 7 and each second sub-trace 8 in the second sub-scan lines 5-2 normally receives the first scan signal.

[0096] In another scenario, referring to Figures 9 and 10, the first winding 9 is connected to the second sub-trace 8. The first scan signal provided by the first shift register 12 flows simultaneously to the first sub-trace 7 and the second sub-trace 8 in the first trace section 10. When the first scan signal is transmitted to the end of the first sub-trace 7 near the light-transmitting hole 2, it stops transmitting. However, when the first scan signal is transmitted to the end of the second sub-trace 8 near the light-transmitting hole 2, it continues to be transmitted to the trace section 6 on the other side of the light-transmitting hole 2 via the first winding 9. This ensures that each first sub-trace 7 and each second sub-trace 8 in the second sub-scan lines 5-2 receives the first scan signal normally.

[0097] The above two embodiments respectively illustrate the case where the first side fd is the side away from the light-transmitting hole 2, and the case where the first side fd is the side close to the light-transmitting hole 2.

[0098] It should be further noted that when the first side fd is the side closest to the light-transmitting hole 2, further effects can be achieved in the load design of the second sub-scan line 5-2.

[0099] Specifically, in the first sub-scan line 5-1, the first sub-line 7 and the second sub-line 8 included in its wiring section 6 both transversely run through the entire first display area AA1 and are relatively long. Therefore, the charging rate of the first sub-line 7 and the second sub-line 8 in the first sub-scan line 5-1 will be slightly slower.

[0100] In the second sub-scan line 5-2, referring to Figures 3-6, when the first side fd is the side closest to the light-transmitting hole 2, the first sub-line 7 and the second sub-line 8 in the first wiring section 10 are connected on the side closest to the light-transmitting hole 2. In Figures 3, 4, and 5, when the first scan signal is transmitted to the end of the first sub-line 7 in the first wiring section 10 near the light-transmitting hole 2, it will simultaneously continue to be transmitted backward via the first winding 9 and to the second sub-line 8 of the first wiring section 10. This can make the charging rate of the first sub-line 7 and the second sub-line 8 in the first wiring section 10 slightly slower, thereby making it more consistent with the charging rate of the first sub-line 7 and the second sub-line 8 in the first sub-scan line 5-1, which helps to improve the charging consistency of different sub-lines. Similarly, in Figures 3, 4, and 6, when the first scan signal is transmitted to the end of the second sub-trace 8 in the first trace section 10 near the light-transmitting hole 2, it will simultaneously continue to be transmitted backward via the first winding 9 and to the first sub-trace 7 in the first trace section 10. This will also make the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first trace section 10 slightly slower, so as to be consistent with the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first sub-scan line 5-1, thereby improving the charging consistency of different sub-traces.

[0101] In one feasible implementation, as shown in Figures 11 to 14, Figure 11 is a schematic diagram of a pixel circuit 4 provided in an embodiment of the present invention, Figure 12 is a timing diagram corresponding to Figure 11, Figure 13 is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention, and Figure 14 is a cross-sectional view along the A1-A2 direction of Figure 9. The pixel circuit 4 includes a first transistor T0, and the active layer ac of the first transistor T0 includes an oxide semiconductor material, that is, the active layer ac of the first transistor T0 is located in the oxide semiconductor layer oxy. This type of first transistor T0 has a smaller off-state leakage current, which helps to improve the stability of the node voltage in the pixel circuit 4.

[0102] In this embodiment of the invention, the active layer ac of the first transistor T0 may include indium gallium zinc oxide (IGZO) material, and in this case, the first transistor T0 is an IGZO transistor.

[0103] The gate of the first transistor T0 is electrically connected to the first scan line 5. The gate of the first transistor T0 includes a top gate g1 and a bottom gate g2. The top gate g1 is located in the first metal layer MG, and the bottom gate g2 is located in the second metal layer Mc. The first metal layer MG is located on the side of the active layer ac away from the substrate 1, that is, on the side of the oxide semiconductor layer oxy away from the substrate 1; the second metal layer Mc is located on the side of the active layer ac close to the substrate 1, that is, on the side of the oxide semiconductor layer oxy close to the substrate 1.

[0104] In the first scan line 5, the first sub-line 7 is located in the first metal layer MG and is partially multiplexed as the top gate g1, and the second sub-line 8 is located in the second metal layer Mc and is partially multiplexed as the bottom gate g2.

[0105] In this embodiment of the invention, referring to Figures 13 and 14, the active layer ac of the first transistor T0 can be electrically connected to other transistors or other signal lines via connecting leads 50. The connecting leads 50 are located in the third metal layer SD, which is located on the side of the first metal layer MG away from the substrate 1.

[0106] The first transistor T0 has a top-bottom dual-gate structure. The first sub-line 7 and the second sub-line 8 provide signal inputs to the top gate g1 and the bottom gate g2, respectively, which increases the channel control capability of the first transistor T0 and thus improves its operational reliability. Furthermore, the first sub-line 7 is located on the first metal layer MG and partially multiplexed as the top gate g1, while the second sub-line 8 is located on the second metal layer Mc and partially multiplexed as the bottom gate g2. This simplifies the wiring of the first scan line 5 and the gate of the first transistor T0, resulting in a more optimized layout design.

[0107] In one feasible implementation, as shown in FIG15, FIG15 is another structural schematic diagram of the display panel provided in the embodiment of the present invention, wherein the first side fd is the side of the first wiring portion 10 near the light-transmitting hole 2. That is, the first sub-wiring line 7 and the second sub-wiring line 8 in the first wiring portion 10 are connected on the side near the light-transmitting hole 2 and are not connected on the side away from the light-transmitting hole 2.

[0108] The display panel also includes a first shift register 12, which is electrically connected to the second sub-scan line 5-2 and is used to provide a first scan signal to the second sub-scan line 5-2. Simultaneously, the first shift register 12 is also electrically connected to the first sub-scan line 5-1 and is used to provide a first scan signal to the first sub-scan line 5-1.

[0109] The first shift register 12 is located on the side of the first sub-trace 7 in the second sub-scan line 5-2 that it is connected to, away from the light-transmitting hole 2. In the first trace 10, the second sub-trace 8 is connected to the first shift register 12 through the first sub-trace 7.

[0110] The first shift register 12 is electrically connected to the first scan line 5 via the first connection line 15.

[0111] The phrase "in the first routing section 10, the second sub-routes 8 are connected to the first shift register 12 via the first sub-routes 7" specifically means that in the first routing section 10, the first sub-routes 7 are connected to the first connection line 15, while the second sub-routes 8 are not connected to the first connection line 15. The first scan signal provided by the first shift register 12 is first transmitted to the first sub-routes 7 via the first connection line 15, and then transmitted to the second sub-routes 8. In other words, the first scan signal received by the second sub-routes 8 is transmitted from the first sub-routes 7.

[0112] First, based on the preceding explanation of Figures 3 to 6, when the first side fd is the side of the first trace section 10 closest to the light-transmitting hole 2, the charging rates of the first sub-trace 7 and the second sub-trace 8 in the first trace section 10 are relatively close to those of the first sub-trace 7 and the second sub-trace 8 in the first sub-scan line 5-1. This can improve the charging consistency of the top gate g1 and the bottom gate g2 of the first transistor T0 in different regions. Furthermore, in a transistor with a top-bottom dual-gate structure, the top gate g1 is more sensitive to the modulation of channel carriers than the bottom gate g2, thus having a greater impact on the transistor's switching characteristics. Since the first sub-trace 7 in the first scan line 5 is used to provide a signal to the top gate g1, connecting the first sub-trace 7 to the first shift register 12 allows the first sub-trace 7 to directly receive the first scan signal provided by the first shift register 12, thereby reducing the signal voltage drop across the top gate g1 of the first transistor T0 in that sub-region 3.

[0113] Alternatively, in another feasible implementation, as shown in FIG16, FIG16 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, wherein the first side fd is the side of the first wiring portion 10 near the light-transmitting hole 2. That is, the first sub-wiring line 7 and the second sub-wiring line 8 in the first wiring portion 10 are connected on the side near the light-transmitting hole 2 and are not connected on the side away from the light-transmitting hole 2.

[0114] The display panel also includes a first shift register 12, which is electrically connected to the second sub-scan line 5-2 and is used to provide a first scan signal to the second sub-scan line 5-2. Simultaneously, the first shift register 12 is also electrically connected to the first sub-scan line 5-1 and is used to provide a first scan signal to the first sub-scan line 5-1.

[0115] The first shift register 12 is located on the side of the first sub-line 7 in the second sub-scan line 5-2 that it is connected to, away from the light-transmitting hole 2. In the first line section 10, the first sub-line 7 is connected to the first shift register 12 through the second sub-line 8.

[0116] The first shift register 12 is electrically connected to the first scan line 5 via the first connection line 15.

[0117] The aforementioned "in the first routing section 10, the first sub-routes 7 are connected to the first shift register 12 via the second sub-routes 8" specifically means that in the first routing section 10, the second sub-routes 8 are connected to the first connection line 15, while the first sub-routes 7 are not connected to the first connection line 15. The first scan signal provided by the first shift register 12 is first transmitted to the second sub-routes 8 via the first connection line 15, and then transmitted to the first sub-routes 7. In other words, the first scan signal received by the first sub-routes 7 is transmitted from the second sub-routes 8.

[0118] As can be seen from the previous explanation of Figures 3 to 6, when the first side fd is the side of the first trace section 10 closest to the light-transmitting hole 2, the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first trace section 10 is close to the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first sub-scan line 5-1, which can improve the charging consistency of the top gate g1 and the bottom gate g2 of the first transistor T0 in different regions.

[0119] In this structure, although the first sub-line 7 in the first routing section 10 is not directly connected to the first shift register 12, the transmission path of the signal output by the first shift register 12 to the first sub-line 7 is still relatively short. Therefore, the signal voltage drop of the top gate g1 of the first transistor T0 in this partition will not be too large.

[0120] In one feasible implementation, referring again to Figure 13, the line width of the second sub-trace 8 is greater than the line width of the first sub-trace 7.

[0121] The second sub-trace 8 is partially reused as the bottom gate g2 of the first transistor T0 and is located below the active layer ac of the first transistor T0. The wider the second sub-trace 8, the flatter the active layer ac of the first transistor T0, the more regular the carrier transport path in the active layer ac, and the less resistance encountered by carriers when moving within the active layer ac. Therefore, designing a larger linewidth for the first sub-trace 7 helps to increase the conductivity of the first transistor T0, thereby achieving higher switching speeds and lower power consumption.

[0122] In one possible implementation, referring again to FIG11, the pixel circuit 4 includes a driving transistor T1.

[0123] The first transistor T0 includes a threshold compensation transistor T2, which is electrically connected between the second terminal of the driving transistor T1 and the gate of the driving transistor T1. The first scan line 5 includes a threshold compensation scan line S2N electrically connected to the threshold compensation transistor T2.

[0124] And / or, the first transistor T0 includes a gate reset transistor T3 electrically connected between the first reset line Ref1 and the gate of the driving transistor T1. The first scan line 5 includes a reset scan line S1N electrically connected to the gate reset transistor T3.

[0125] Both the threshold compensation transistor T2 and the gate reset transistor T3 are electrically connected to the gate of the driving transistor T1. Therefore, the off-state leakage current of these two transistors has a greater impact on the gate potential of the driving transistor T1. To address this, this embodiment of the invention designs the threshold compensation transistor T2 and / or the gate reset transistor T3 as a transistor structure with a top-bottom dual-gate configuration. This effectively reduces the impact of the off-state leakage current of these two transistors on the gate potential of the driving transistor T1, thereby ensuring the stability of the operating state of the driving transistor T1.

[0126] Furthermore, referring again to Figure 11, the pixel circuit 4 may also include:

[0127] The data writing transistor T4 has its gate electrically connected to the write scan line Sp, its first terminal electrically connected to the data line Data, and its second terminal electrically connected to the first terminal of the driving transistor T1.

[0128] The first light-emitting control transistor T5 has its gate electrically connected to the light-emitting control scan line Emit, its first electrode electrically connected to the power supply line PVDD, and its second electrode electrically connected to the first electrode of the driving transistor T1.

[0129] The second light-emitting control transistor T6 has its gate electrically connected to the light-emitting control scan line Emit, its first electrode electrically connected to the second electrode of the driving transistor T1, and its second electrode electrically connected to the light-emitting element 1616.

[0130] The anode reset transistor T7 has its gate electrically connected to the write scan line Sp, its first electrode electrically connected to the second reset line Ref2, and its second electrode electrically connected to the light-emitting element 16.

[0131] The storage capacitor Cst has its first plate electrically connected to the power supply line PVDD and its second plate electrically connected to the gate of the driving transistor T1.

[0132] The bias transistor T8 has its gate electrically connected to the bias scan line Sp*, its first terminal electrically connected to the bias signal line DVH, and its second terminal electrically connected to the first terminal of the drive transistor T1.

[0133] Among them, the light-emitting element 16 can be a variety of devices such as organic light-emitting diode (OLED) and light-emitting diode (LED).

[0134] In one feasible structure, referring to Figure 11, the first transistor T0 includes a threshold compensation transistor T2 and a gate reset transistor T3. The threshold compensation transistor T2 is turned on when a high level is provided by the threshold compensation scan line S2N and turned off when a low level is provided. The gate reset transistor T3 is turned on when a high level is provided by the reset scan line S1N and turned off when a low level is provided.

[0135] The pixel circuit also includes a second transistor T0', the active layer of which includes a silicon semiconductor material. For example, the active layer of the second transistor T0' includes a low-temperature polysilicon (LTPS) material, and the second transistor T0' is a low-temperature polysilicon (LTPS) transistor.

[0136] The second transistor T0' includes at least one of a driving transistor T1, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, and a bias transistor T8. The second transistor T0' is turned on when a low level is provided by the scan line to which it is connected, and turned off when a high level is provided.

[0137] The embodiment of the present invention is illustrated by taking the second transistor T0', which includes a driving transistor T1, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, and a bias transistor T8 as an example.

[0138] Referring to Figures 11 and 12, the driving cycle of pixel circuit 4 includes write frame F1 and hold frame F2.

[0139] The write frame F1 includes a first non-light-emitting period t11 and a first light-emitting period t21, wherein the first non-light-emitting period t11 includes a reset period t1 and a charging period t2. During the reset period t1, the gate reset transistor T3 is turned on to reset the gate of the driving transistor T1. During the charging period t2, the threshold compensation transistor T2, the data write transistor T4, and the anode reset transistor T7 are turned on. The threshold compensation transistor T2 and the data write transistor T4 are used to charge the driving transistor T1 and perform threshold compensation on the driving transistor T1, and the anode reset transistor T7 is used to reset the anode of the light-emitting element 16. During the first light-emitting period t21, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, transmitting the driving current converted by the driving transistor T1 to the light-emitting element 16.

[0140] The holding frame F2 includes a second non-light-emitting period t12 and a second light-emitting period t22, wherein the second non-light-emitting period t12 includes a bias adjustment period t3. During the bias adjustment period t3, the bias transistor T8 is turned on to adjust the bias state of the driving transistor T1. During the second light-emitting period t22, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on to transmit the driving current converted by the driving transistor T1 to the light-emitting element 16.

[0141] It should be noted that the above-described pixel circuit driving process is for illustrative purposes only. In other feasible driving methods, the bias transistor T8 can also be turned on during the first non-light-emitting period t11 of the write frame F1, and the bias transistor T8 can be turned on once, twice or more during the first non-light-emitting period t11 and / or the second non-light-emitting period t12.

[0142] Based on the above structure, as shown in Figure 17, which is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, the display panel further includes a silicon semiconductor layer ss and a fourth metal layer M1. The fourth metal layer M1 is located on the side of the silicon semiconductor layer ss away from the substrate 1, and the second metal layer Mc is located on the side of the fourth metal layer M1 away from the substrate 1.

[0143] The silicon semiconductor layer ss includes the active layer ac' of the second transistor T0', and the fourth metal layer M1 includes the gate g' of the second transistor T0'. The active layer ac' of the second transistor T0' can be electrically connected to other transistors or other signal lines via connecting leads 50, which are located on the third metal layer SD.

[0144] In addition, the display panel may also include a fifth metal layer M0, which is located between the silicon semiconductor layer ss and the substrate 1. The fifth metal layer M0 includes a shielding metal 60. In a direction perpendicular to the plane of the substrate 1, at least part of the shielding metal 60 overlaps with the channel of the active layer ac' of the second transistor T0', preventing external light from shining on the channel of the second transistor T0' and affecting the characteristics of the second transistor T0'.

[0145] Based on the above circuit structure, as shown in Figure 18, which is another structural schematic diagram of the display panel provided in the embodiment of the present invention, the first shift register 12 includes a first sub-shift register 12-1 electrically connected to the threshold compensation scan line S2N and a second sub-shift register 12-2 electrically connected to the reset scan line S1N.

[0146] The display panel also includes a second shift register 16 electrically connected to the write scan line Sp, a third shift register 17 electrically connected to the light emission control scan line Emit, and a fourth shift register 18 electrically connected to the bias scan line Sp*.

[0147] In one configuration, the display panel includes two second shift registers 16, which are located on opposite sides of the display area AA, to drive the write scan line Sp on both sides, thereby improving the driving capability of the write scan line.

[0148] The display panel includes a first sub-shift register 12-1, a second sub-shift register 12-2, a third shift register 17, and a fourth shift register 18. Two of these four shift registers are located on one side of the display area AA, and the other two are located on the other side of the display area AA. These four shift registers drive the connected scan lines on one side only.

[0149] In one feasible implementation, as shown in Figures 19 and 20, Figure 19 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention, and Figure 20 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. The display area AA includes a plurality of circuit rows 19 arranged along a first direction x, and the circuit rows 19 include a plurality of pixel circuits 4 arranged along a second direction y.

[0150] The display panel also includes a first shift register 12, which includes a plurality of cascaded first shift units 20. Each first shift unit 20 is electrically connected to a second sub-scan line 5-2 corresponding to m circuit rows 19, where m ≥ 2. Furthermore, the m trace portions 6 on the same side of the light-transmitting hole 2 in these m second sub-scan lines 5-2 are connected to the same first winding 9. That is, the first winding 9 included in these m second sub-scan lines 5-2 is the same first winding 9. This reduces the number of first windings 9 required in the second sub-scan lines 5-2, thereby reducing the wiring space occupied by the first windings 9.

[0151] In addition, the first shift register 12 also includes a plurality of cascaded second shift units 21, one of which is electrically connected to the first sub-scan line 5-1 corresponding to m circuit rows 19.

[0152] Furthermore, referring to Figure 20, among the m second sub-scan lines 5-2 electrically connected in the same first shift unit 20, each of the m second sub-scan lines 5-2 includes a first trace portion 10, so that the load of these m second sub-scan lines 5-2 tends to be consistent, thereby improving the load consistency of different second sub-scan lines 5-2.

[0153] Furthermore, referring to Figure 20, in the m second sub-scan lines 5-2 electrically connected to the same first shift unit 20, the first trace portions 10 of the m second sub-scan lines 5-2 overlap along the first direction x. That is, the first trace portions 10 of these m second sub-scan lines 5-2 are either all on the left side of the light-transmitting aperture 2 or all on the right side of the light-transmitting aperture 2. In this way, regardless of whether the first shift register 12 is located on the side of the first trace portion 10 away from the light-transmitting aperture 2 or on the side of the first trace portion 10 closer to the light-transmitting aperture 2, the signal flow direction in these m second sub-scan lines 5-2 is consistent, thereby weakening the signal voltage drop difference at different positions in these m second sub-scan lines 5-2.

[0154] In one feasible implementation, referring to Figures 21 to 27, the first wiring portion 10 is connected to the first via 22 and the second via 23, respectively.

[0155] On the first side fd of the first routing section 10, the first sub-routes 7 and 8 are connected through the first via 22; on the second side sd of the first routing section 10, one of the first sub-routes 7 and 8 is connected to the second via 23, and the other is not connected to the second via 23, thereby achieving the disconnection of the first sub-routes 7 and 8 on the second side sd. The signal in the first sub-routes 7 cannot be directly transmitted to the second sub-routes 8 on the second side through the second via 23, or the signal in the second sub-routes 8 cannot be directly transmitted to the first sub-routes 7 on the second side through the second via 23.

[0156] In one feasible implementation, as shown in Figures 21 to 24, Figure 21 is a schematic diagram of one structure of the second sub-scan line 5-2 provided in an embodiment of the present invention, Figure 22 is a cross-sectional view of Figure 21 along the B1-B2 direction, Figure 23 is another schematic diagram of the structure of the second sub-scan line 5-2 provided in an embodiment of the present invention, and Figure 24 is a cross-sectional view of Figure 23 along the C1-C2 direction. The first sub-trace 7 is located in the first metal layer MG, and the second sub-trace 8 is located in the second metal layer Mc. The first metal layer MG is located on the side of the second metal layer Mc away from the substrate 1. For example, the first metal layer MG is located on the side of the oxide semiconductor layer oxy away from the substrate 1, and the second metal layer Mc is located on the side of the oxide semiconductor layer oxy closer to the substrate 1.

[0157] The display panel includes a first connecting portion 24 and a second connecting portion 25, the first connecting portion 24 and the second connecting portion 25 are located in a third metal layer SD, the third metal layer SD is located on the side of the first metal layer MG away from the substrate 1.

[0158] There is at least one insulating layer 26 between the third metal layer SD and the first metal layer MG, and at least two insulating layers 26 between the third metal layer SD and the second metal layer Mc.

[0159] Both the first via 22 and the second via 23 include a first sub-via 27 and a second sub-via 28. The first sub-via 27 penetrates the insulating layer 26 between the third metal layer SD and the first metal layer MG, and the second sub-via 28 penetrates the insulating layer 26 between the third metal layer SD and the second metal layer Mc.

[0160] Referring to Figures 21 to 24, on the first side fd of the first routing portion 10, the first connecting portion 24 is electrically connected to the first sub-routing 7 through the first sub-via 27 in the first via 22, and the first connecting portion 24 is also electrically connected to the second sub-routing 8 through the second sub-via 28 in the first via 22.

[0161] That is, referring to Figures 22 and 24, on the first side fd of the first trace portion 10, in the direction perpendicular to the plane of the substrate 1, the first connection portion 24 overlaps with the first sub-via 27 and the second sub-via 28 in the first via 22. The first sub-trace 7 in the first trace portion 10 overlaps with the first sub-via 27 in the first via 22, and is connected to the first connection portion 24 through the first sub-via 27. The second sub-trace 8 in the first trace portion 10 overlaps with the second sub-via 28 in the first via 22, and is connected to the first connection portion 24 through the second sub-via 28.

[0162] Referring to Figures 21 and 22, on the second side sd of the first trace portion 10, the second connection portion 25 is electrically connected to the first sub-trace 7 through the first sub-via 27 in the second via 23. The second connection portion 25 is also connected to the second sub-via 28 in the second via 23. In a direction perpendicular to the plane of the substrate 1, there is a gap between the second sub-trace 8 and the second sub-via 28 in the second via 23.

[0163] That is, on the second side sd of the first trace portion 10, in the direction perpendicular to the plane of the substrate 1, the second connection portion 25 overlaps with the first sub-via 27 and the second sub-via 28 in the second via 23. The first sub-trace 7 in the first trace portion 10 overlaps with the first sub-via 27 in the second via 23, and is connected to the second connection portion 25 through the first sub-via 27. The second sub-trace 8 in the first trace portion 10 does not overlap with the second sub-via 28 in the second via 23. There is a gap between the projection of the second sub-trace 8 in the first trace portion 10 and the projection of the second sub-via 28 in the second via 23. The second sub-trace 8 is not connected to the second sub-via 28, and therefore the second sub-trace 8 is not connected to the second connection portion 25.

[0164] Alternatively, referring to Figures 23 and 24, on the second side sd of the first trace portion 10, the second connection portion 25 is electrically connected to the second sub-trace 8 through the second sub-via 28 in the second via 23. The second connection portion 25 is also connected to the first sub-via 27 in the second via 23. In a direction perpendicular to the plane of the substrate 1, there is a gap between the first sub-trace 7 and the first sub-via 27 in the second via 23.

[0165] That is, on the second side sd of the first trace portion 10, in the direction perpendicular to the plane of the substrate 1, the second connection portion 25 overlaps with the first sub-via 27 and the second sub-via 28 in the second via 23. The second sub-trace 8 in the first trace portion 10 overlaps with the second sub-via 28 in the second via 23, and is connected to the second connection portion 25 through the second sub-via 28. The first sub-trace 7 in the first trace portion 10 does not overlap with the first sub-via 27 in the second via 23. There is a gap between the projection of the first sub-trace 7 in the first trace portion 10 and the projection of the first sub-via 27 in the second via 23. The first sub-trace 7 is not connected to the first sub-via 27, and therefore the first sub-trace 7 is not connected to the second connection portion 25.

[0166] In the above structure, the first sub-line 7 and the second sub-line 8 are connected by a transition metal (first connecting part 24 and second connecting part 25).

[0167] When the second sub-scan line 5-2 adopts the design concept shown in Figure 1, on the first side fd of the first trace portion 10, the first connecting portion 24 is electrically connected to the first sub-trace 7 through the first sub-via 27 in the first via 22, and electrically connected to the second sub-trace 8 through the second sub-via 28 in the first via 22. On the second side sd of the first trace portion 10, the second connecting portion 25 is electrically connected to the first sub-trace 7 through the first sub-via 27 in the second via 23, and electrically connected to the second sub-trace 8 through the second sub-via 28 in the second via 23. Therefore, both the first side fd and the second side sd have mask patterns for the connecting portions and mask patterns for the sub-vias.

[0168] When the second sub-scan line 5-2 adopts the design concepts of Figures 21 and 23, although there is no connection between the first sub-line 7 and the second sub-line 8 on the second side SD of the first trace portion 10, the second connecting portion 25 and the second via 23 connected by the second connecting portion 25 are still retained on the second side SD. In this way, it is not necessary to readjust the mask pattern of the third metal layer SD, nor is it necessary to readjust the mask pattern of the second via 23, and there is no need to replace the mask, thus saving process costs. Moreover, retaining the second connecting portion 25 and the second via 23 on the second side SD can also make the overall distribution of the connecting portion and the via more uniform, resulting in a better layout design.

[0169] Alternatively, in another feasible implementation, as shown in Figures 25-28, Figure 25 is a schematic diagram of another structure of the second sub-scan line 5-2 provided in an embodiment of the present invention, Figure 26 is a cross-sectional view of Figure 25 along the D1-D2 direction, Figure 27 is another schematic diagram of the second sub-scan line 5-2 provided in an embodiment of the present invention, and Figure 28 is a cross-sectional view of Figure 27 along the F1-F2 direction. The first sub-line 7 is located in the first metal layer MG, and the second sub-line 8 is located in the second metal layer Mc. The first metal layer MG is located on the side of the second metal layer Mc away from the substrate 1. For example, the first metal layer MG is located on the side of the oxide semiconductor layer oxy away from the substrate 1, and the second metal layer Mc is located on the side of the oxide semiconductor layer oxy closer to the substrate 1. At least one insulating layer 26 is spaced between the first metal layer MG and the second metal layer Mc.

[0170] The first via 22 and the second via 23 both penetrate the insulating layer 26 between the first metal layer MG and the second metal layer Mc.

[0171] Referring to Figures 25 and 26, on the second side sd of the first trace portion 10, the first sub-trace 7 is connected to the second via 23, and there is a gap between the second sub-trace 8 and the second via 23 in a direction perpendicular to the plane of the substrate 1.

[0172] That is, on the second side sd of the first trace portion 10, in the direction perpendicular to the plane of the substrate 1, the first sub-trace 7 in the first trace portion 10 overlaps and connects with the second via 23, but the second sub-trace 8 in the first trace portion 10 does not overlap with the second via 23. There is a gap between the projection of the second sub-trace 8 in the first trace portion 10 and the projection of the second via 23. The second sub-trace 8 is not connected to the first sub-trace 7 by the second via 23.

[0173] Alternatively, referring to Figures 27 and 28, on the second side sd of the first trace portion 10, the second sub-trace 8 is connected to the second via 23, and there is a gap between the first sub-trace 7 and the second via 23 in a direction perpendicular to the plane of the substrate 1.

[0174] That is, on the second side sd of the first trace portion 10, in the direction perpendicular to the plane of the substrate 1, the second sub-trace 8 in the first trace portion 10 overlaps with the second via 23, but the first sub-trace 7 in the first trace portion 10 does not overlap with the second via 23. There is a gap between the projection of the first sub-trace 7 in the first trace portion 10 and the projection of the second via 23. The first sub-trace 7 is not connected to the second via 23 and the second sub-trace 8.

[0175] When the second sub-scan line 5-2 adopts the design concept shown in Figure 1, on the first side fd of the first routing section 10, the first sub-route 7 and the second sub-route 8 in the first routing section 10 are electrically connected through the first via 22. On the second side sd of the first routing section 10, the first sub-route 7 and the second sub-route 8 in the first routing section 10 are electrically connected through the second via 23. Therefore, via mask patterns exist on both the first side fd and the second side sd.

[0176] When the second sub-scan line 5-2 adopts the design schemes of Figures 25 and 27, although the first sub-line 7 and the second sub-line 8 are not connected on the second side SD of the first routing section 10, the second via 23 is still retained on the second side SD. In this way, the mask pattern of the via does not need to be readjusted, and the mask plate does not need to be replaced, saving process costs. Moreover, retaining the second via 23 on the second side SD can also make the overall distribution of vias more uniform and the layout design more optimized.

[0177] Further, as shown in Figures 29 to 32, Figure 29 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, Figure 30 is a cross-sectional view of Figure 29 along the F1-F2 direction, Figure 31 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, and Figure 32 is a cross-sectional view of Figure 31 along the G1-G2 direction. The display panel includes a first shift register 12, which is electrically connected to the second sub-scan line 5-2. The first shift register 12 is located on the side of the first trace portion 10 in the second sub-scan line 5-2 away from the light-transmitting hole 2.

[0178] The first shift register 12 is electrically connected to the first wiring section 10 via a first connection line 15, the first connection line 15 including a first sub-connection line 29.

[0179] Referring to Figures 29 and 30, on the second side sd of the first routing portion 10, the second via 23 is connected to the first sub-router 7, and the first sub-connector 29 is located in the second metal layer Mc, with the first sub-line connected to the second via 23. Alternatively, referring to Figures 31 and 32, on the second side sd of the first routing portion 10, the second via 23 is connected to the second sub-router 8, and the first sub-connector 29 is located in the first metal layer MG, with the first sub-line connected to the second via 23.

[0180] In this configuration, the second via 23 is reused as a connection via between the first shift register 12 and the second sub-scan line 5-2. This not only makes reasonable use of the second via 23, but also prevents metal from other traces from depositing in the second via 23 and causing a short circuit with the second sub-scan line 5-2.

[0181] Alternatively, referring to Figure 19, as shown in Figures 33 to 36, Figure 33 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, Figure 34 is a cross-sectional view of Figure 33 along the H1-H2 direction, Figure 35 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, and Figure 36 is a cross-sectional view of Figure 35 along the I1-I2 direction. The display area AA includes a plurality of circuit rows 19 arranged along the first direction x, and the circuit rows 19 include a plurality of pixel circuits 4 arranged along the second direction y.

[0182] The display panel also includes a first shift register 12, which includes a plurality of cascaded first shift units 20, wherein one first shift unit 20 is electrically connected to the second sub-scan lines 5-2 corresponding to m circuit rows 19, m≥2, and the m second sub-scan lines 5-2 are connected by a second connection line 30.

[0183] Referring to Figures 33 and 34, on the second side sd of the first routing portion 10, the second via 23 is connected to the second sub-route 8, and the second connecting line 30 is located in the first metal layer MG and connected to the second via 23. Alternatively, referring to Figures 35 and 36, on the second side sd of the first routing portion 10, the second via 23 is connected to the first sub-route 7, and the second connecting line 30 is located in the second metal layer Mc and connected to the second via 23.

[0184] When a first shift unit 20 is electrically connected to m second sub-scan lines 5-2, the m second sub-scan lines 5-2 are connected together through a second connecting line 30. The above configuration reuses the second via 23 as a connection via between the second sub-scan lines 5-2 and the second connecting line 30. This not only makes reasonable use of the second via 23, but also prevents metal from other traces from depositing in the second via 23 and causing a short circuit with the second sub-scan lines 5-2.

[0185] In one feasible implementation, referring again to Figures 3 and 4, in the second sub-scan line 5-2, the routing section 6 further includes a second routing section 31. In the second routing section 31, the first sub-routes 7 and 8 pass through the sub-region 3 along the second direction y, and the first sub-routes 7 and 8 are connected at both ends.

[0186] If all the traces 6 in the second sub-scan line 5-2 are designed as first traces 10, the overall load of the second sub-scan line 5-2 may be too large, which would exacerbate the load difference between the second sub-scan line 5-2 and the first sub-scan line 5-1. In this embodiment of the invention, by designing some traces 6 in the second sub-scan line 5-2 as first traces 10 and some traces 6 as second traces 31, the load of the second sub-scan line 5-2 can be increased within a reasonable range, thereby better mitigating the load difference between the second sub-scan line 5-2 and the first sub-scan line 5-1.

[0187] Furthermore, as shown in Figures 37 and 38, Figure 37 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention, and Figure 38 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. The display panel further includes a first shift register 12, which is electrically connected to the second sub-scan line 5-2.

[0188] The first shift register 12 is located on the side of the first trace 10 in the second sub-scan line 5-2 that is away from the second trace 31, and is connected to the first trace 10.

[0189] The first shift register 12 drives the second sub-scan line 5-2 on one side. Since the first sub-line 7 and the second sub-line 8 in the first routing section 10 are only connected on one side, their overall load will be larger. Connecting the first shift register 12 to the first routing section 10 can weaken the signal voltage drop difference on the routing sections 6 on both sides of the light-transmitting hole 2, thereby weakening the display difference of the sub-regions 3 on both sides of the light-transmitting hole 2.

[0190] Alternatively, as shown in Figures 39 and 40, where Figure 39 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention, and Figure 40 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention, the first shift register 12 can also be located on the side of the second routing section 31 in the second sub-scan line 5-2 away from the first routing section 10, and connected to the second routing section 31. In this case, the signal output by the first shift register 12 first flows through the second routing section 31, and then flows through the first routing section 10 via the first winding line 9.

[0191] In one feasible implementation, the first winding 9 is connected to either the first sub-trace 7 or the second sub-trace 8, and the first winding 9 is disposed on the same layer as the first sub-trace 7 or the second sub-trace 8 to which it is connected. For example, referring to FIG3, the first winding 9 is connected to the second sub-trace 8 and disposed on the same layer as the second sub-trace 8; or, referring to FIG4, the first winding 9 is connected to the first sub-trace 7 and disposed on the same layer as the first sub-trace 7.

[0192] The first winding 9 is on the same layer as the first sub-routing 7 or the second sub-routing 8 connected to it. There is no need to drill holes to connect the first winding 9 and the routing part 6, which makes the wiring simpler.

[0193] In one feasible implementation, as shown in FIG41, FIG41 is another structural schematic diagram of the second sub-scan line 5-2 provided in an embodiment of the present invention, wherein the first winding line 9 is disposed on a different layer from at least one of the first sub-trace 7 and the second sub-trace 8. Exemplarily, the first winding line 9 may be located in the third metal layer SD, or the first winding line may also be located in the fourth metal layer M1 or the fifth metal layer M0.

[0194] In the above structure, other metal layers can be selected to lay the first winding 9 according to the wiring situation in the area where the first winding 9 is located, making the wiring position of the first winding 9 more flexible.

[0195] Furthermore, it should be noted that the first winding 9 in the embodiments of the present invention can be arranged around the light-transmitting hole 2 in the second non-display area NAA2 as shown in FIG3, or, as shown in FIG42, FIG42 is another structural schematic diagram of the display panel provided in the embodiments of the present invention, at least a portion of the first winding 9 can also be arranged around the light-transmitting hole 2 in the first display area AA1.

[0196] Based on the same inventive concept, this embodiment of the invention also provides a display device, as shown in FIG43. FIG43 is a schematic diagram of a structure of the display device provided in this embodiment of the invention, which includes the aforementioned display panel 100. Of course, the display device shown in FIG43 is merely illustrative, and the display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, or television.

[0197] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Substrate; The display area includes a first display area and a second display area arranged along a first direction. The second display area includes a light-transmitting hole and a sub-area arranged along the second direction. The sub-area is located on the opposite side of the light-transmitting hole. The first direction intersects the second direction. The display area includes pixel circuitry. A first scan line is at least partially located in the display area and electrically connected to the pixel circuit. The first scan line includes at least one trace portion, and the trace portion includes a first sub-trace and a second sub-trace that are electrically connected. In a direction perpendicular to the plane of the substrate, the first sub-trace and the second sub-trace in the same trace portion at least partially overlap. The first scan line includes a first sub-scan line and a second sub-scan line, wherein the first sub-scan line is at least partially located in the first display area and the second sub-scan line is at least partially located in the second display area; The first sub-scan line includes a routing section, and the first sub-routes and the second sub-routes in the same routing section pass through the first display area along the second direction, and the first sub-routes and the second sub-routes are connected at both ends; The second sub-scan line includes at least two of the said trace portions, and the second sub-scan line also includes a first winding around the light-transmitting aperture. In the same second sub-scan line, one of the trace portions corresponds to one of the said sub-regions, and the two trace portions on both sides of the light-transmitting aperture are connected by the first winding. Furthermore, the trace portion in at least one second sub-scan line includes a first trace portion, and the first trace portion includes a first side and a second side opposite to each other in the second direction. The first sub-trace and the second sub-trace in the first trace portion are connected on the first side and not connected on the second side.

2. The display panel according to claim 1, characterized in that, The first side is the side of the first wiring section closest to the light-transmitting hole.

3. The display panel according to claim 1, characterized in that, The first side is the side of the first wiring section that is far away from the light-transmitting hole.

4. The display panel according to claim 1, characterized in that, The pixel circuit includes a first transistor, the active layer of the first transistor includes an oxide semiconductor material, and the gate of the first transistor is electrically connected to the first scan line. The gate of the first transistor includes a top gate and a bottom gate, the top gate being located in a first metal layer and the bottom gate being located in a second metal layer; the first metal layer is located on the side of the active layer away from the substrate, and the second metal layer is located on the side of the active layer close to the substrate; In the first scan line, the first sub-trace is located in the first metal layer and is partially multiplexed as the top gate, and the second sub-trace is located in the second metal layer and is partially multiplexed as the bottom gate.

5. The display panel according to claim 4, characterized in that, The first side is the side of the first wiring section closest to the light-transmitting hole; The display panel further includes a first shift register, which is electrically connected to the second sub-scan line. The first shift register is located on the side of the first sub-trace portion of the second sub-scan line to which it is connected, away from the light-transmitting hole. In the first trace portion, the second sub-trace is connected to the first shift register through the first sub-trace.

6. The display panel according to claim 4, characterized in that, The first side is the side of the first wiring section closest to the light-transmitting hole; The display panel further includes a first shift register, which is electrically connected to the second sub-scan line. The first shift register is located on the side of the first sub-trace portion of the second sub-scan line it is connected to that is away from the light-transmitting hole. In the first trace portion, the first sub-trace is connected to the first shift register through the second sub-trace.

7. The display panel according to claim 4, characterized in that, The width of the second sub-trace is greater than the width of the first sub-trace.

8. The display panel according to claim 4, characterized in that, The pixel circuit includes a driving transistor; The first transistor includes a threshold compensation transistor electrically connected between the second terminal of the driving transistor and the gate of the driving transistor, and the first scan line includes a threshold compensation scan line electrically connected to the threshold compensation transistor; And / or, the first transistor includes a gate reset transistor electrically connected between a first reset line and the gate of the driving transistor, and the first scan line includes a reset scan line electrically connected to the gate reset transistor.

9. The display panel according to claim 1, characterized in that, The display area includes a plurality of circuit rows arranged along the first direction, and the circuit rows include a plurality of pixel circuits arranged along the second direction; The display panel further includes a first shift register, which includes a plurality of cascaded first shift units, wherein one first shift unit is electrically connected to the second sub-scan lines corresponding to m of the circuit rows, m ≥ 2, and m of the traces located on the same side of the light-transmitting hole in the m second sub-scan lines are connected to the same first winding.

10. The display panel according to claim 9, characterized in that, Each of the m second sub-scan lines includes the first routing section.

11. The display panel according to claim 10, characterized in that, The first trace portion of the m second sub-scan lines overlaps along the first direction.

12. The display panel according to claim 1, characterized in that, The first trace portion is connected to the first via and the second via, respectively; On the first side of the first routing section, the first sub-routes and the second sub-routes are connected through the first via. On the second side of the first routing section, one of the first sub-routes and the second sub-routes is connected to the second via, and the other is not connected to the second via.

13. The display panel according to claim 12, characterized in that, The first sub-trace is located in the first metal layer, the second sub-trace is located in the second metal layer, and the first metal layer is located on the side of the second metal layer away from the substrate; The display panel includes a first connecting portion and a second connecting portion, the first connecting portion and the second connecting portion are located on a third metal layer, and the third metal layer is located on the side of the first metal layer away from the substrate; Wherein, both the first via and the second via include a first sub-via and a second sub-via, the first sub-via penetrating the insulating layer between the third metal layer and the first metal layer, and the second sub-via penetrating the insulating layer between the third metal layer and the second metal layer; On the first side of the first trace portion, the first connection portion is electrically connected to the first sub-trace through the first sub-via in the first via, and the first connection portion is also electrically connected to the second sub-trace through the second sub-via in the first via. On the second side of the first trace portion, the second connection portion is electrically connected to the first sub-trace through the first sub-via in the second via, and the second connection portion is also connected to the second sub-via in the second via. In a direction perpendicular to the plane of the substrate, there is a gap between the second sub-trace and the second sub-via in the second via. Alternatively, on the second side of the first trace portion, the second connection portion is electrically connected to the second sub-trace through the second sub-via in the second via, and the second connection portion is also connected to the first sub-via in the second via. In a direction perpendicular to the plane of the substrate, there is a gap between the first sub-trace and the first sub-via in the second via.

14. The display panel according to claim 12, characterized in that, The first sub-trace is located in the first metal layer, the second sub-trace is located in the second metal layer, and the first metal layer is located on the side of the second metal layer away from the substrate; Both the first via and the second via penetrate the insulating layer between the first metal layer and the second metal layer; On the second side of the first trace portion, the first sub-trace is connected to the second via, and there is a gap between the second sub-trace and the second via in a direction perpendicular to the plane of the substrate; Alternatively, on the second side of the first trace portion, the second sub-trace is connected to the second via, and there is a gap between the first sub-trace and the second via in a direction perpendicular to the plane of the substrate.

15. The display panel according to claim 14, characterized in that, The display panel includes a first shift register, which is electrically connected to the second sub-scan line. The first shift register is located on the side of the first trace portion of the second sub-scan line away from the light-transmitting hole. The first shift register is electrically connected to the first trace via a first connection line, the first connection line including a first sub-connection line; On the second side of the first trace portion, the second via is connected to the second sub-trace, the first sub-trace is located in the first metal layer, and the first sub-connection line is connected to the second via; Alternatively, on the second side of the first trace portion, the second via is connected to the first sub-trace, the first sub-connection line is located in the second metal layer, and the first sub-line is connected to the second via.

16. The display panel according to claim 14, characterized in that, The display area includes a plurality of circuit rows arranged along the first direction, and the circuit rows include a plurality of pixel circuits arranged along the second direction; The display panel further includes a first shift register, which includes a plurality of cascaded first shift units, wherein one first shift unit is electrically connected to the second sub-scan lines corresponding to m of the circuit rows, m≥2, and the m second sub-scan lines are connected by a second connection line; Wherein, on the second side of the first trace portion, the second via is connected to the second sub-trace, the second connecting line is located in the first metal layer, and the second connecting line is connected to the second via; Alternatively, on the second side of the first trace portion, the second via is connected to the first sub-trace, the second connecting line is located in the second metal layer, and the second connecting line is connected to the second via.

17. The display panel according to claim 1, characterized in that, In the second sub-scan line, the routing section further includes a second routing section; In the second routing section, the first sub-routing and the second sub-routing pass through the sub-region along the second direction, and the first sub-routing and the second sub-routing are connected at both ends.

18. The display panel according to claim 17, characterized in that, The display panel further includes a first shift register, which is electrically connected to the second sub-scan line. The first shift register is located on the side of the first trace portion of the second sub-scan line that is away from the second trace portion, and is connected to the first trace portion.

19. The display panel according to claim 17, characterized in that, The display panel further includes a first shift register, which is electrically connected to the second sub-scan line. The first shift register is located on the side of the second trace portion of the second sub-scan line away from the first trace portion and is connected to the second trace portion.

20. The display panel according to claim 1, characterized in that, The first winding is connected to the first sub-trace or the second sub-trace, and the first winding and the first sub-trace or the second sub-trace to which it is connected are disposed on the same layer.

21. The display panel according to claim 1, characterized in that, The first winding is disposed on a different layer from at least one of the first sub-routes and the second sub-routes.

22. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 21.

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