Display apparatus

Abstract

A display apparatus, comprising a plurality of cascaded gate driving sub-circuits (201) and at least one redundant hole. The redundant hole is provided in an adjacent region (202) next to the outer edge of a gate driving sub-circuit (201), and the ratio of the number of redundant holes in the adjacent region (202) to the number of contact holes in the gate driving sub-circuit (201) is in the range of 80% to 120%, thereby eliminating threshold voltage differences between transistors of a first-stage gate driving sub-circuit (201) and a last-stage gate driving sub-circuit (201) and transistors of gate driving sub-circuits (201) of other stages.

Description

Display device Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] In the field of display panel technology, CMOS (Complementary Metal-Oxide-Semiconductor) GOA (Gate-driver On Array) technology can achieve segmentation and frequency division, and output one Nscan gate drive signal and one or two Pscan gate drive signals. In this technology, the gate drive circuit includes an inverter formed by transistors using IGZO (Indium Gallium Zinc Oxide) and LTPS (Low Temperature Polycrystalline Silicon) as semiconductor materials.

[0003] However, in practical applications, the threshold voltages of IGZO transistors in different regions vary significantly. This difference in threshold voltage can alter the stable structure formed by the inverter, ultimately leading to abnormal output from the gate drive circuit. Particularly at the top and bottom of the gate drive circuit in the display panel, differences in the density of peripheral vias can cause the threshold voltages of transistors in the first or last stage of the gate drive sub-circuit to differ from those in other stages, resulting in a display unevenness (mura) phenomenon on the displayed image. Invention Overview

[0004] The purpose of this application is to provide a display device to solve the technical problem that the threshold voltage of the transistors in the first-stage gate driving sub-circuit or the last-stage gate driving sub-circuit in a conventional display panel differs from the threshold voltage of the transistors in other-stage gate driving sub-circuits.

[0005] An embodiment of this application provides a display device, including: a gate driving circuit, the gate driving circuit including a plurality of cascaded gate driving sub-circuits, the gate driving sub-circuit including at least one contact hole; and at least one redundant hole, the redundant hole being disposed in an adjacent region next to the outer edge of the gate driving sub-circuit, the ratio of the number of redundant holes located in the adjacent region to the number of contact holes located in the gate driving sub-circuit being in the range of 80% to 120%. Beneficial effects

[0006] The display device provided in the embodiments of this application provides a plurality of redundant holes in the adjacent area next to the outer edge of the gate driving sub-circuit. By setting the ratio of the number of redundant holes in the adjacent area to the number of contact holes in the gate driving sub-circuit to be in the range of 80% to 120%, the gate driving sub-circuit and its adjacent area have similar hole density distribution, avoiding transistor threshold voltage deviation caused by hole density differences. In particular, for the first-stage gate driving sub-circuit and the last-stage gate driving sub-circuit, by providing an appropriate number of redundant holes in the adjacent area next to their outer edges, the threshold voltage difference between the transistors in these areas and the transistors in other stages of the gate driving sub-circuit is effectively eliminated.

[0007] Furthermore, this application ensures that the adjustment effect of redundant vias on the transistor threshold voltage is essentially the same as that of actual contact holes by making the positions of redundant vias in the adjacent region correspond to the positions of contact holes in the gate driver sub-circuit, and by controlling the size difference between the redundant vias and contact holes within a specific range. In particular, for gate driver sub-circuits containing oxide semiconductor transistors and low-temperature polysilicon transistors, this application provides first and second redundant vias corresponding to the regions of the two different types of transistors, respectively. By setting the ratio of the number of these redundant vias to the corresponding contact holes and their size difference within a predetermined range, it effectively prevents large differences in the threshold voltage of oxide semiconductor transistors in the gate driver sub-circuit.

[0008] Furthermore, for the junction of the gate driving sub-circuit located in the arc edge region and the gate driving sub-circuit located in the straight edge region of the display panel, this application also sets corresponding redundant holes in these special locations, which solves the problem of uneven via density in local areas caused by the irregular shape of the display panel, and ensures that stable transistor threshold voltage characteristics can be maintained in irregular areas of the display panel (such as rounded corner areas).

[0009] Through the above technical solution, the display device provided by this application successfully solves the problem of threshold voltage difference of oxide semiconductor transistors caused by uneven via density in traditional display panels, significantly improves the output stability of the gate drive circuit, effectively avoids the phenomenon of uneven display in the display device, and thus improves the display quality of the display device. Attached Figure Description

[0010] Figure 1 is a schematic diagram of a display device provided in an embodiment of this application.

[0011] Figure 2 is a schematic diagram of the first embodiment of the display device provided in this application.

[0012] Figure 3 is a schematic diagram of a second embodiment of the display device provided in this application.

[0013] Figure 4 is a layout diagram of the gate driver sub-circuit and redundant vias in the display device shown in Figures 2 and 3.

[0014] Figure 5 is a circuit diagram of the gate driver sub-circuit in the display device shown in Figures 2 and 3. Embodiments of the present invention

[0015] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0016] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0017] The embodiments of this application can be combined with each other.

[0018] The display device provided in the embodiments of this application may be, for example, an OLED display device, a Mini-LED display device, or a Micro-LED display device. The embodiments of this application will be described using an OLED display device as an example.

[0019] As shown in Figures 1 to 3, the display device provided in the embodiments of this application includes a display panel, a timing controller, a source drive circuit, and a power management chip (the power management chip can be integrated with the timing controller into the same chip). The display panel is an organic light-emitting diode (OLED) display panel.

[0020] The display panel includes a display area AA and a non-display area. The display area AA has an array of m×n pixel units PX, where m and n are integers greater than 1. The non-display area is located around the display area AA and is used to arrange driving circuits and various signal lines. The display panel also includes multiple scan lines (SCAN), multiple data lines (DATA), and a gate driving circuit. The multiple scan lines (SCAN) extend along a first direction and are arranged along a second direction, and the multiple data lines (DATA) extend along the second direction and are arranged along the first direction, with the first direction perpendicular to the second direction. The gate driving circuit is located in the non-display area and is electrically connected to the multiple scan lines (SCAN). The source driving circuit is electrically connected to the multiple data lines (DATA) via a flexible circuit board. A timing controller is electrically connected to both the gate driving circuit and the source driving circuit.

[0021] The display panel includes an organic light-emitting diode (OLED) array substrate and an encapsulation layer. The OLED array substrate includes a substrate, a buffer layer disposed on the substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed within an opening area defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes scan lines (SCAN), a gate electrode, etc. The second metal layer includes data lines (DATA), a source electrode, a drain electrode, etc. The encapsulation layer is sealed to the OLED array substrate to prevent moisture and oxygen from penetrating the organic light-emitting layer.

[0022] Each pixel unit (PX) includes a pixel driving circuit and an organic light-emitting diode (OLED). The pixel driving circuit includes at least two thin-film transistors (TFTs) and a storage capacitor. One TFT acts as a switching transistor, with its gate electrically connected to the corresponding scan line and its source electrically connected to the corresponding data line. The other TFT acts as a driving transistor, with its gate electrically connected to the drain of the switching transistor, its source electrically connected to a first power supply voltage line, and its drain electrically connected to the anode of the OLED. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to either the source or drain of the driving transistor. The cathode of the OLED is electrically connected to a second power supply voltage line.

[0023] The gate driving circuit includes n cascaded gate driving units, each electrically connected to a scan line. Under the control of the timing controller, the gate driving units sequentially output scan signals, scanning each row of pixel units PX in the display area AA line by line. The source driving circuit, under the control of the timing controller, generates and outputs data signals based on the image data. The timing controller receives and processes externally input image data and timing signals, generates control signals, and transmits the image data to the source driving circuit. The power management chip provides operating voltages to various parts of the display device, including providing a second power supply voltage VSS to the cathode of the organic light-emitting diode, a first power supply voltage VDD to the first power supply voltage line, and gate driving voltages VGH / VGL to the gate driving circuit.

[0024] As shown in Figures 2 to 5, to address the issue of differences in threshold voltage between transistors in the first or last stage gate driving sub-circuit and other stage gate driving sub-circuits in the gate driving circuit, this application provides redundant vias at the top and bottom of the gate driving circuit GOA of the display panel 20, similar to the contact hole layout in the gate driving sub-circuit 201. For the small-sized display panel 20, since it is not a standard rectangle but has rounded corners, redundant vias are also provided at the intersection of the rounded corners and the straight edges of the display panel 20. Without these redundant vias, the difference in via density would cause differences in the threshold voltage of transistors in the first stage gate driving sub-circuit 201, the last stage gate driving sub-circuit 201, and the gate driving sub-circuit 201 at the intersection of the rounded corners and the straight edges of the display panel 20, compared to the threshold voltage of transistors in other stage gate driving sub-circuits 201, resulting in uneven display on the display panel 20.

[0025] Specifically, embodiments of this application provide a display device including a gate driving circuit and at least one redundant via.

[0026] The gate drive circuit uses CMOS GOA technology to implement the frequency division function. The gate drive circuit includes multiple cascaded gate drive sub-circuits 201, which refer to the first-stage gate drive sub-circuit 201 to the last-stage gate drive sub-circuit 201 as non-redundant gate drive sub-circuits (normal gate drive sub-circuits). Each gate drive sub-circuit 201 includes at least one contact hole.

[0027] The gate drive sub-circuit 201 includes an inverter formed by transistors using IGZO and LTPS as semiconductor materials, and outputs one Nscan gate drive signal and one Pscan gate drive signal or two Pscan gate drive signals.

[0028] This application uses the first-stage gate driver sub-circuit 201 as an example to illustrate the output of one Nscan gate drive signal and one Pscan gate drive signal, as shown in Figure 5. The nth-stage gate driver sub-circuit 201 includes 22 transistors T1-T22 and 3 capacitors C1-C3.

[0029] The gate of the first transistor T1 is electrically connected to node K, its source is electrically connected to the first low-level signal input terminal PVGL, and its drain is electrically connected to node P. The gate of the second transistor T2 is electrically connected to the first clock signal input terminal XCK, its source is electrically connected to node O, and its drain is electrically connected to node K. The gate of the third transistor T3 is electrically connected to node K, its source is electrically connected to the first high-level signal input terminal PVGH, and its drain is electrically connected to node P.

[0030] The gate of the fourth transistor T4 is electrically connected to the first clock signal input terminal XCK, and its drain is electrically connected to node K. The gate of the fifth transistor T5 is electrically connected to node P, its source is electrically connected to the first high-level signal input terminal PVGH, and its drain is electrically connected to the source of the fourth transistor T4.

[0031] The gate of the sixth transistor T6 is electrically connected to node Q, the source is electrically connected to the second clock signal input terminal CK, and the drain is electrically connected to the first scan signal output terminal Pout[n]. The gate of the seventh transistor T7 is electrically connected to node P, the source is electrically connected to the first high-level signal input terminal PVGH, and the drain is electrically connected to the first scan signal output terminal Pout[n].

[0032] The gate of the eighth transistor T8 is electrically connected to the dielectric P of the (n-2)th stage gate driver sub-circuit, the source is electrically connected to node M, and the drain is electrically connected to node Q.

[0033] The gate of the ninth transistor T9 is electrically connected to node W, the source is electrically connected to the second high-level signal input terminal NVGH, and the drain is electrically connected to the second scan signal output terminal Nout[n].

[0034] The gate of the tenth transistor T10 is electrically connected to node K, the source is electrically connected to the second low-level signal input terminal NVGL, and the drain is electrically connected to the second scan signal output terminal Nout[n].

[0035] The gate of the eleventh transistor T11 is electrically connected to the control signal input terminal Ctrl, the source is electrically connected to the first high-level signal input terminal PVGH, and the drain is electrically connected to node K.

[0036] The gate of the twelfth transistor T12 is electrically connected to the start signal input terminal STV, the source is electrically connected to the first high-level signal input terminal PVGH, and the drain is electrically connected to node O.

[0037] The gate of the thirteenth transistor T13 is electrically connected to the start signal input terminal STV, the source is electrically connected to the second low-level signal input terminal NVGL, and the drain is electrically connected to node O.

[0038] The gate of the fourteenth transistor T14 is electrically connected to node P, the source is electrically connected to the second low-level signal input terminal NVGL, and the drain is electrically connected to node K.

[0039] The source of the fifteenth transistor T15 is electrically connected to node K, and the drain is electrically connected to node W.

[0040] The gate of the sixteenth transistor T16 is electrically connected to node P, the source is electrically connected to the signal input terminal NLF, and the drain is electrically connected to the gate of the fifteenth transistor T15.

[0041] The gate of the seventeenth transistor T17 is electrically connected to the first clock signal input terminal XCK, and the drain is electrically connected to node W.

[0042] The gate of the eighteenth transistor T18 is electrically connected to node P, the source is electrically connected to the first high-level signal input terminal PVGH, and the drain is electrically connected to the source of the seventeenth transistor T17.

[0043] The source of the nineteenth transistor T19 is electrically connected to node K, and the drain is electrically connected to node M.

[0044] The gate of the twentieth transistor T20 is electrically connected to node P, the source is electrically connected to the signal input terminal PLF, and the drain is electrically connected to the gate of the nineteenth transistor T19.

[0045] The gate of the twenty-first transistor T21 is electrically connected to the first clock signal input terminal XCK, and the drain is electrically connected to node M.

[0046] The gate of the twenty-second transistor T22 is electrically connected to node P, the source is electrically connected to the first high-level signal input terminal PVGH, and the drain is electrically connected to the source of the twenty-first transistor T21.

[0047] The first plate of the first capacitor C1 is electrically connected to node Q, and the second plate is electrically connected to the first scan signal output terminal Pout[n].

[0048] The first plate of the second capacitor C2 is electrically connected to the gate of the fifteenth transistor T15, and the second plate is electrically connected to node W.

[0049] The first plate of the third capacitor C3 is electrically connected to the gate of the nineteenth transistor T19, and the second plate is electrically connected to node M.

[0050] Among them, the first transistor T1, the fourth transistor T4, the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, the seventeenth transistor T17, and the twenty-first transistor T21 are all dual-gate transistors, and the two gates of each of them are electrically connected.

[0051] As shown in Figures 2 to 4, the redundant via is disposed in the adjacent region 202 next to the outer edge of the gate driver sub-circuit 201.

[0052] The adjacent region 202 is located next to the outer edge of the first-stage gate driver sub-circuit 201 and / or the last-stage gate driver sub-circuit 201. The adjacent region 202 is a region located within a second predetermined distance H outside the outer edge of the gate driver sub-circuit 201. The second predetermined distance H is not greater than 60 micrometers, and in particular, the second predetermined distance H is 50 micrometers.

[0053] Furthermore, the gate driving circuit 201 includes a gate driving sub-circuit 201 located in the arc edge region of the display device and a gate driving sub-circuit 201 located in the straight edge region of the display device. The adjacent region 202 is also located next to the outer edge of the gate driving sub-circuit 201 in the straight edge region, close to the outer edge of the gate driving sub-circuit 201 in the arc edge region.

[0054] The ratio of the number of redundant vias in the adjacent region 202 of a gate drive sub-circuit 201 to the number of contact vias in the gate drive sub-circuit 201 is in the range of 80% to 120%.

[0055] The position of the redundant via in the adjacent region 202 of a gate driving sub-circuit 201 corresponds to the position of the contact via in the same gate driving sub-circuit 201. Positional correspondence means that, provided the positions of the redundant via in the adjacent region 202 and the contact via in the gate driving sub-circuit 201 are projected onto the same coordinate system, they are the same or have a deviation not exceeding a predetermined value. This predetermined value can be, for example, the radius of the smallest circumcircle of the redundant via or the contact via. Specifically, the relative position of the redundant via in the adjacent region 202 of the gate driving sub-circuit 201 is the same as the relative position of the contact via within the same gate driving sub-circuit 201 (position in the same coordinate system).

[0056] The absolute value of the difference between the size of the redundant hole and the contact hole corresponding to the location is less than or equal to 10% of the size of the contact hole, and the redundant hole and the contact hole have the same physical characteristics.

[0057] Specifically, the size of the redundant holes is the same as the size of the contact holes.

[0058] Within the gate drive sub-circuit 201 and its corresponding adjacent region 202, the distance between redundant vias and contact vias that correspond in position (e.g., located at the same relative position) is no greater than 60 micrometers. Preferably, this distance is 50 micrometers.

[0059] The absolute value of the difference between the area ratio of redundant vias in the adjacent region of a gate driver sub-circuit 201 and the area ratio of contact vias in the gate driver sub-circuit 201 is less than or equal to 10%.

[0060] The arrangement of redundant vias in the adjacent region 202 of a gate driving sub-circuit 201 follows the arrangement of contact vias in the same gate driving sub-circuit 201. The spacing between redundant vias and the distance between redundant vias and the outer edge are consistent with the corresponding parameters of the contact vias.

[0061] The shape, depth, and sidewall angle of the redundant via are basically the same as those of the contact via. Specifically, the ratio of the absolute value of the difference between the depth of the redundant via and the depth of the contact via to the depth of the contact via is less than or equal to 10%, and the ratio of the absolute value of the difference between the sidewall angle of the redundant via and the sidewall angle of the contact via to the sidewall angle of the contact via is less than or equal to 10%. The size deviation between the redundant via and the contact via is controlled within 10%. The redundant via and the contact via have similar etching and filling characteristics.

[0062] Although redundant vias do not participate in actual circuit connections, the material properties, thickness, and other parameters of the interlayer dielectric, metal layers, and semiconductor layers surrounding them are consistent with the parameters of the corresponding layers surrounding the contact vias. The region where the redundant via is located has the same dielectric and capacitive properties as the region where the contact via is located.

[0063] In a direction perpendicular to the plane where the display device is located, a redundant semiconductor layer is disposed below at least one redundant hole. The shape of the redundant semiconductor layer corresponds to the shape of the transistor semiconductor layer below the corresponding contact hole, and the ratio of the absolute value of the difference between the area of ​​the redundant semiconductor layer and the area of ​​the transistor semiconductor layer to the area of ​​the transistor semiconductor layer is less than or equal to 10%.

[0064] The outer edge is the outer edge of the gate driving sub-circuit 201 in the arrangement direction (second direction) of the plurality of gate driving sub-circuits 201. Specifically, the plurality of gate driving sub-circuits 201 are arranged sequentially along the edge of the display panel 20, and the outer edge of each gate driving sub-circuit 201 refers to the edge perpendicular to the arrangement direction of the gate driving sub-circuit 201, which is not connected to the adjacent gate driving sub-circuit 201.

[0065] The adjacent region 202 includes a first unit region, and the gate driving sub-circuit 201 includes a second unit region. The relative position of the first unit region in the adjacent region 202 is the same as the relative position of the second unit region in the gate driving sub-circuit 201, and the shape and area of ​​the first unit region are the same as the shape and area of ​​the second unit region.

[0066] The first unit region is located within the adjacent region 202, and the distance from its boundary to the outer edge of the gate driver sub-circuit 201 is equal to the distance from the second unit region to the inner reference edge of the gate driver sub-circuit 201. The relative coordinate positions of the first unit region and the second unit region within their respective regions are consistent, including the center point position, boundary position, etc.

[0067] Both the first and second unit regions are identical rectangles (though other shapes are also possible), with identical length, width, and other dimensional parameters. The relative positions of the four corner points, the orientation of the boundary lines, and the overall outline of the regions remain consistent between the two unit regions.

[0068] The absolute value of the difference between the area ratio of redundant holes in the first unit area and the area ratio of contact holes in the second unit area is less than or equal to 10%. Specifically, by setting the number of redundant holes and the area of ​​a single redundant hole, the difference between the ratio of the total area of ​​redundant holes in the first unit area to the area of ​​that unit area and the ratio of the total area of ​​contact holes in the second unit area to the area of ​​that unit area is controlled within 10%.

[0069] The area proportion of redundant holes in the first unit region is the same as the area proportion of contact holes in the second unit region. Same area proportion means that when the sum of the areas of all redundant holes in the first unit region is divided by the area of ​​the first unit region, the resulting value is equal to the sum of the areas of all contact holes in the second unit region divided by the area of ​​the second unit region. This ensures that the hole density is exactly the same in both unit regions.

[0070] Although the redundant vias in the first unit area do not perform actual circuit connection functions, their spatial distribution completely replicates the distribution characteristics of the contact vias in the second unit area, including the arrangement and spacing of the vias. This ensures that the two areas have the same parasitic capacitance distribution characteristics.

[0071] The gate driver circuit 201 includes at least one oxide semiconductor transistor and at least one low-temperature polysilicon transistor.

[0072] The plurality of contact holes include at least one first contact hole 2011 and at least one second contact hole 2012, wherein the first contact hole 2011 is located in the region where the low-temperature polysilicon transistor is located, and the second contact hole 2012 is located in the region where the oxide semiconductor transistor is located; the plurality of redundant holes include a plurality of first redundant holes 2021 and a plurality of second redundant holes 2022; the first redundant holes 2021 and the first contact holes 2011 are located in the same film layer, and the second redundant holes 2022 and the second contact holes 2012 are located in the same film layer.

[0073] The absolute value of the difference between the size of the first redundant hole 2021 and the size of the first contact hole 2011 is less than or equal to 10% of the size of the first contact hole 2011, and the absolute value of the difference between the size of the second redundant hole 2022 and the size of the second contact hole 2012 is less than or equal to 10% of the size of the second contact hole 2012.

[0074] Both the first redundant via 2021 and the second redundant via 2022 are disposed within an adjacent region 202 within approximately 50 micrometers of the outer edge of the gate driving sub-circuit 201. The distribution density of the first redundant via 2021 within the adjacent region 202 is the same as the distribution density of the first contact via 2011 within the gate driving sub-circuit 201, and the distribution density of the second redundant via 2022 within the adjacent region 202 is the same as the distribution density of the second contact via 2012 within the gate driving sub-circuit 201.

[0075] The dimensions of the first redundant via 2021 and the second redundant via 2022 are the same as the dimensions of the corresponding first contact via 2011 and the second contact via 2012 within the gate driver sub-circuit 201, respectively. Specifically, the geometric parameters such as the depth, width, and length of the first redundant via 2021 are consistent with the corresponding parameters of the first contact via 2011, and the geometric parameters such as the depth, width, and length of the second redundant via 2022 are consistent with the corresponding parameters of the second contact via 2012.

[0076] The first contact hole 2011 is the contact hole for the source and drain of the LTPS transistor in the gate driving sub-circuit 201, and the second contact hole 2012 is the contact hole for the source and drain of the IGZO transistor in the gate driving sub-circuit 201. That is, the first contact hole 2011 connects the source or drain of the LTPS transistor to the LTPS semiconductor layer, and the second contact hole 2012 connects the source or drain of the IGZO transistor to the IGZO semiconductor layer. Although the first redundant via 2021 and the second redundant via 2022 do not have actual electrical connection functions, the material properties of the interlayer dielectric, metal layer and semiconductor layer in the adjacent region 202 are consistent with the corresponding layers in the gate driving sub-circuit 201. The etching characteristics and filling characteristics of the first redundant via 2021 and the second redundant via 2022 are consistent with the corresponding characteristics of the first contact hole 2011 and the second contact hole 2012.

[0077] Within the adjacent region 202, the arrangement of the first redundant via 2021 and the second redundant via 2022 is the same as the arrangement of the first contact via 2011 and the second contact via 2012 within the gate drive sub-circuit 201.

[0078] The absolute value of the difference between the area ratio of the first redundant via 2021 in the adjacent region 202 of a gate driving sub-circuit 201 and the area ratio of the first contact via 2011 in the gate driving sub-circuit 201 is less than or equal to 10%; the absolute value of the difference between the area ratio of the second redundant via 2022 in the adjacent region 202 of a gate driving sub-circuit 201 and the area ratio of the second contact via 2012 in the gate driving sub-circuit 201 is less than or equal to 10%.

[0079] Specifically, the absolute value of the difference between the area ratio of the first redundant hole 2021 in the first unit area and the area ratio of the first contact hole 2011 in the second unit area is less than 10%; and / or the absolute value of the difference between the area ratio of the second redundant hole 2022 in the first unit area and the area ratio of the second contact hole 2012 in the second unit area is less than 10%.

[0080] For example, when the area percentage of the first contact hole 2011 in the second unit area is 2.98%, the area percentage of the first redundant hole 2021 in the first unit area is controlled within the range of 2.68% to 3.28%. When the area percentage of the second contact hole 2012 in the second unit area is 2.46%, the area percentage of the second redundant hole 2022 in the first unit area is controlled within the range of 2.21% to 2.71%. By controlling the area percentages of the first redundant hole 2021 and the second redundant hole 2022, the through-hole density distribution in the first unit area can be made substantially consistent with the through-hole density distribution in the second unit area.

[0081] The ratio of the number of first redundant vias 2021 in the adjacent region 202 to the number of first contact vias 2011 in the gate drive sub-circuit 201 is in the range of 80% to 120%, and the ratio of the number of second redundant vias 2022 in the adjacent region 202 to the number of second contact vias 2012 in the gate drive sub-circuit 201 is in the range of 80% to 120%.

[0082] The absolute value of the difference between the ratio of the number of first redundant vias 2021 to the number of second redundant vias 2022 in adjacent region 202 and the ratio of the number of first contact vias 2011 to the number of second contact vias 2012 in gate drive sub-circuit 201 is less than or equal to 10%.

[0083] Specifically, the ratio of the number of first redundant holes 2021 to second redundant holes 2022 in the first unit area is the same as the ratio of the number of first contact holes 2011 to second contact holes 2012 in the second unit area. For example, when the ratio of the number of first contact holes 2011 to second contact holes 2012 in the second unit area is 55:45, the ratio of the number of first redundant holes 2021 to second redundant holes 2022 in the first unit area is also 55:45. By controlling the ratio of the number of first redundant holes 2021 to second redundant holes 2022, the distribution of the number of through holes in the first unit area can be made to be basically consistent with the distribution of the number of through holes in the second unit area.

[0084] In a direction perpendicular to the plane where the display device is located, a redundant semiconductor layer is disposed below the first redundant hole 2021 and the second redundant hole 2022. The shape of the redundant semiconductor layer is the same as the shape of the transistor semiconductor layer located below the first contact hole 2011 and the second contact hole 2012 in the gate drive sub-circuit 201. The ratio of the absolute value of the difference between the area of ​​the redundant semiconductor layer and the area of ​​the transistor semiconductor layer to the area of ​​the transistor semiconductor layer is less than or equal to 10%.

[0085] Specifically, in a direction perpendicular to the plane where the display device is located, a first transistor semiconductor layer (e.g., an LTPS transistor semiconductor layer) is disposed below the first contact hole 2011, a second transistor semiconductor layer (e.g., an IGZO transistor semiconductor layer) is disposed below the second contact hole 2012, a first redundant semiconductor layer (e.g., an LTPS redundant semiconductor layer) is disposed below the first redundant hole 2021, and a second redundant semiconductor layer (e.g., an IGZO redundant semiconductor layer) is disposed below the second redundant hole 2022; the absolute value of the difference between the area of ​​the first redundant semiconductor layer and the area of ​​the first transistor semiconductor layer is less than or equal to 10% of the area of ​​the first transistor semiconductor layer; the absolute value of the difference between the area of ​​the second redundant semiconductor layer and the area of ​​the second transistor semiconductor layer is less than or equal to 10% of the area of ​​the second transistor semiconductor layer.

[0086] When the gate drive sub-circuit 201 is composed of both IGZO transistors and LTPS transistors, an IGZO redundant semiconductor layer is disposed below the second redundant via 2022 corresponding to the second contact via 2012 of the IGZO transistor. This IGZO redundant semiconductor layer has the same shape, size, and area as the IGZO transistor semiconductor layer of the IGZO transistor. For the first redundant via 2021 corresponding to the first contact via 2011 of the LTPS transistor, an LTPS redundant semiconductor layer may or may not be disposed below it. When an LTPS redundant semiconductor layer is disposed, it has the same shape, size, and area as the LTPS transistor semiconductor layer of the LTPS transistor.

[0087] When the gate drive sub-circuit 201 is composed only of IGZO transistors, an IGZO redundant semiconductor layer is disposed below all the second redundant vias 2022 corresponding to the second contact vias 2012 of the IGZO transistors. Each IGZO redundant semiconductor layer has the same shape, size and area as the IGZO transistor semiconductor layer of its corresponding IGZO transistor.

[0088] Specifically, to ensure that the redundant via region and the contact via region have the same hydrogen dehydrogenation effect, an IGZO redundant semiconductor layer is disposed below the second redundant via 2022 near the IGZO transistor. The IGZO redundant semiconductor layer uses the same semiconductor material as the IGZO transistor semiconductor layer in the gate driver sub-circuit 201, and the shape of the IGZO redundant semiconductor layer is the same as that of the IGZO transistor semiconductor layer. By controlling the difference between the area of ​​the IGZO redundant semiconductor layer and the area of ​​the IGZO transistor semiconductor layer, the semiconductor characteristics of the second redundant via 2022 region and the second contact via 2012 region can be made substantially consistent, thereby avoiding threshold voltage non-uniformity caused by differences in semiconductor material characteristics.

[0089] The ratio of the absolute value of the difference between the area of ​​the redundant semiconductor layer and the area of ​​the transistor semiconductor layer to the area of ​​the transistor semiconductor layer is less than or equal to 10%.

[0090] In the gate drive sub-circuit 202, at least one first contact hole 2011 and at least one second contact hole 2012 are provided within a first predetermined distance next to an oxide semiconductor transistor (which serves as a buffer transistor of the gate drive sub-circuit 202, and may be, for example, the tenth transistor T10 shown in FIG. 5) with a channel width greater than or equal to 250 micrometers (e.g., a channel width of 300 micrometers). In the adjacent region, at least one first redundant hole 2021 and at least one second redundant hole 2022 are provided within a first predetermined distance next to the sub-region corresponding to the oxide semiconductor transistor with a channel width greater than or equal to 250 micrometers. The absolute value of the difference between the number of 2021 and the number of first contact holes 2011 is less than or equal to 10% of the number of first contact holes 2011; the absolute value of the difference between the number of second redundant holes 2022 and the number of second contact holes 2012 is less than or equal to 10% of the number of second contact holes 2022; the absolute value of the difference between the size of the first redundant hole 2021 and the size of the first contact hole 2011 is less than or equal to 10% of the size of the first contact hole 2011; and the absolute value of the difference between the size of the second redundant hole 2022 and the size of the second contact hole 2012 is less than or equal to 10% of the size of the second contact hole 2012.

[0091] As shown in Figure 2, multiple first redundant vias 2021 and second redundant vias 2022 are disposed in adjacent regions 202 next to the outer edges of the first-stage gate driving sub-circuit 201 and / or the last-stage gate driving sub-circuit 201. This arrangement ensures that the transistor threshold voltages of the first-stage and last-stage gate driving sub-circuits 201 are substantially consistent with the transistor threshold voltages of the other-stage gate driving sub-circuits 201. Specifically, the outer edge of the first-stage gate driving sub-circuit 201 refers to the edge away from the second-stage gate driving sub-circuit 201, and the outer edge of the last-stage gate driving sub-circuit 201 refers to the edge away from the penultimate-stage gate driving sub-circuit 201.

[0092] As shown in Figure 3, the gate driving circuit includes a gate driving sub-circuit 201 located in the arc-shaped edge region and a gate driving sub-circuit 201 located in the straight edge region. A plurality of first redundant vias 2021 and second redundant vias 2022 are also disposed in an adjacent region 202 of the gate driving sub-circuit 201 located in the straight edge region, near the outer edge of the gate driving sub-circuit 201 located in the arc-shaped edge region. The arc-shaped edge region is located at the rounded corner of the display panel 20, and the straight edge region is located at the non-rounded corner edge of the display panel 20.

[0093] The gate driving sub-circuit 201 in the straight edge region and the gate driving sub-circuit 201 in the arc edge region form a corner region at their intersection. In this corner region, the distribution density of the first redundant via 2021 and the second redundant via 2022 is consistent with the distribution density of the first contact via 2011 and the second contact via 2012 in the gate driving sub-circuit 201 in the straight edge region and the arc edge region.

[0094] This configuration eliminates the difference in threshold voltage between the transistors in the gate drive sub-circuit 201 at the intersection of the rounded corner and the straight edge of the display panel 20 and the threshold voltages of transistors in other stages of the gate drive sub-circuit 201. By setting first redundant vias 2021 and second redundant vias 2022 in the corner region that match the density of the first contact vias 2011 and the second contact vias 2012, the via density distribution in this region is made uniform. This eliminates the difference in threshold voltage between the transistors in the gate drive sub-circuit 201 at the intersection of the rounded corner and the straight edge of the display panel 20 and the threshold voltages of transistors in other stages of the gate drive sub-circuit 201, thereby avoiding display non-uniformity caused by via density differences.

[0095] As an improvement, as shown in Figure 4, in the direction (first direction) perpendicular to the arrangement direction (second direction) of the multiple gate driving sub-circuits 201, the light-emitting control circuit is disposed between the edge of the gate driving sub-circuit 201 and the display panel 20. Multiple redundant holes are provided in the adjacent area 401 between the light-emitting control circuit and the gate driving sub-circuit 201. The size, shape, number, area, and relative position of these redundant holes are consistent with the size, shape, number, area, and relative position of the contact holes in the light-emitting control circuit. Specifically, the absolute value of the difference between the size of redundant holes in adjacent regions and the size of contact holes in the light-emitting control circuit is less than or equal to 10% of the size of contact holes in the light-emitting control circuit; the shape of redundant holes in adjacent regions corresponds to (is consistent with) the shape of contact holes in the light-emitting control circuit; the ratio of the number of redundant holes in adjacent regions to the number of contact holes in the light-emitting control circuit is in the range of 80% to 120%; the ratio of the area of ​​redundant holes in adjacent regions to the area of ​​contact holes in the light-emitting control circuit is in the range of 80% to 120%; and the relative positions of redundant holes in adjacent regions correspond to (are consistent with) the relative positions of contact holes in the light-emitting control circuit.

[0096] The display device provided in the embodiments of this application provides a plurality of redundant holes in the adjacent region next to the outer edge of the gate driving sub-circuit 201. By setting the ratio of the number of redundant holes in the adjacent region 202 to the number of contact holes in the gate driving sub-circuit 201 to be in the range of 80% to 120%, the gate driving sub-circuit 201 and its adjacent region 202 have similar hole density distribution, avoiding transistor threshold voltage deviation caused by hole density difference. In particular, for the first-stage gate driving sub-circuit 201 and the last-stage gate driving sub-circuit 201, by providing an appropriate number of redundant holes in the adjacent region 202 next to their outer edges, the threshold voltage difference between the transistors in these regions and the transistors in other stages of the gate driving sub-circuit 201 is effectively eliminated.

[0097] Furthermore, this application ensures that the adjustment effect of redundant vias on the transistor threshold voltage is essentially consistent with that of actual contact holes by making the positions of redundant vias in the adjacent region 202 correspond to the positions of contact holes in the gate driving sub-circuit 201, and controlling the size difference between the redundant vias and contact holes within a specific range. Specifically, for the gate driving sub-circuit 201 containing oxide semiconductor transistors and low-temperature polysilicon transistors, this application provides first and second redundant vias corresponding to the regions of the two different types of transistors, respectively. By setting the ratio of the number of these redundant vias to the corresponding contact holes and their size difference within a predetermined range, it effectively prevents large differences in the threshold voltage of oxide semiconductor transistors in the gate driving sub-circuit 201.

[0098] Furthermore, for the junction of the gate driving sub-circuit 201 located in the arc edge region and the gate driving sub-circuit 201 located in the straight edge region in the display panel 20, this application also provides corresponding redundant holes at these special locations, which solves the problem of uneven via density in local areas caused by the irregular shape of the display panel 20, and ensures that stable transistor threshold voltage characteristics can be maintained in irregular areas (such as rounded corner areas) of the display panel 20.

[0099] Through the above technical solution, the display device provided by this application successfully solves the problem of threshold voltage difference of oxide semiconductor transistors caused by uneven via density in traditional display panels, significantly improves the output stability of gate drive circuit 201, effectively avoids uneven display phenomenon in display device, and thus improves the display quality of display device.

[0100] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, comprising: A gate driving circuit, the gate driving circuit including a plurality of cascaded gate driving sub-circuits, the gate driving sub-circuit including at least one contact hole; as well as At least one redundant via is disposed in an adjacent region next to the outer edge of the gate drive sub-circuit, wherein the ratio of the number of redundant vias in the adjacent region to the number of contact vias in the gate drive sub-circuit is in the range of 80% to 120%.

2. The display device according to claim 1, wherein, The position of the redundant via in the adjacent region corresponds to the position of the contact via in the gate driver sub-circuit.

3. The display device according to claim 2, wherein, The ratio of the absolute value of the difference between the size of the redundant hole and the size of the contact hole corresponding to the location to the size of the contact hole is less than or equal to 10%.

4. The display device according to claim 1, wherein, The adjacent region is the area located within 60 micrometers outside the outer edge of the gate driver sub-circuit.

5. The display device according to claim 4, wherein, The absolute value of the difference between the area ratio of the redundant via in the adjacent region and the area ratio of the contact via in the gate driver sub-circuit is less than or equal to 10%.

6. The display device according to claim 1, wherein, In a direction perpendicular to the plane where the display device is located, a redundant semiconductor layer is disposed below at least one of the redundant holes. The shape of the redundant semiconductor layer corresponds to the shape of the transistor semiconductor layer below the corresponding contact hole, and the ratio of the absolute value of the difference between the area of ​​the redundant semiconductor layer and the area of ​​the transistor semiconductor layer to the area of ​​the transistor semiconductor layer is less than or equal to 10%.

7. The display device according to claim 1, wherein, The gate driver sub-circuit includes at least one oxide semiconductor transistor and at least one low-temperature polysilicon transistor; The plurality of contact holes include at least one first contact hole and at least one second contact hole, wherein the first contact hole is located in the region where the low-temperature polycrystalline silicon transistor is located, and the second contact hole is located in the region where the oxide semiconductor transistor is located; The plurality of redundant holes includes at least one first redundant hole and at least one second redundant hole; The first redundant hole and the first contact hole are located in the same film layer, and the second redundant hole and the second contact hole are located in the same film layer.

8. The display device according to claim 7, wherein, The ratio of the number of first redundant vias located in the adjacent region to the number of first contact vias located in the gate driving sub-circuit is in the range of 80% to 120%, and the ratio of the number of second redundant vias located in the adjacent region to the number of second contact vias located in the gate driving sub-circuit is in the range of 80% to 120%.

9. The display device according to claim 7, wherein, The absolute value of the difference between the ratio of the number of first redundant vias to the number of second redundant vias in the adjacent region and the ratio of the number of first contact vias to the number of second contact vias in the gate drive sub-circuit is less than or equal to 10%.

10. The display device according to claim 7, wherein, The absolute value of the difference between the size of the first redundant hole and the size of the first contact hole is less than or equal to 10% of the size of the first contact hole, and the absolute value of the difference between the size of the second redundant hole and the size of the second contact hole is less than or equal to 10% of the size of the second contact hole.

11. The display device according to claim 7, wherein, The absolute value of the difference between the area ratio of the first redundant via in the adjacent region and the area ratio of the first contact via in the gate driving sub-circuit is less than or equal to 10%; The absolute value of the difference between the area ratio of the second redundant via in the adjacent region and the area ratio of the second contact via in the gate driving sub-circuit is less than or equal to 10%.

12. The display device according to claim 7, wherein, In a direction perpendicular to the plane where the display device is located, a first transistor semiconductor layer is disposed below the first contact hole, a second transistor semiconductor layer is disposed below the second contact hole, a first redundant semiconductor layer is disposed below the first redundant hole, and a second redundant semiconductor layer is disposed below the second redundant hole. The ratio of the absolute value of the difference between the area of ​​the first redundant semiconductor layer and the area of ​​the first transistor semiconductor layer to the area of ​​the first transistor semiconductor layer is less than or equal to 10%. The ratio of the absolute value of the difference between the area of ​​the second redundant semiconductor layer and the area of ​​the second transistor semiconductor layer to the area of ​​the second transistor semiconductor layer is less than or equal to 10%.

13. The display device according to claim 7, wherein, In the gate driving sub-circuit, at least one first contact hole and at least one second contact hole are provided within a first predetermined distance next to an oxide semiconductor transistor with a channel width greater than or equal to 250 micrometers. In the adjacent region, at least one first redundant via and at least one second redundant via are provided within the first predetermined distance next to the sub-region corresponding to the oxide semiconductor transistor with a channel width greater than or equal to 250 micrometers. Wherein, the absolute value of the difference between the number of the first redundant holes and the number of the first contact holes is less than or equal to 10% of the number of the first contact holes; the absolute value of the difference between the number of the second redundant holes and the number of the second contact holes is less than or equal to 10% of the number of the second contact holes; the absolute value of the difference between the size of the first redundant hole and the size of the first contact hole is less than or equal to 10% of the size of the first contact hole; and the absolute value of the difference between the size of the second redundant hole and the size of the second contact hole is less than or equal to 10% of the size of the second contact hole.

14. The display device according to claim 7, wherein, The first contact hole is the source-drain contact hole of the low-temperature polysilicon transistor, and the second contact hole is the source-drain contact hole of the oxide semiconductor transistor.

15. The display device according to claim 1, wherein, The adjacent region is located next to the outer edge of the first-level gate driver sub-circuit and / or the last-level gate driver sub-circuit.

16. The display device according to claim 15, wherein, The gate driving circuit includes a gate driving sub-circuit located in the arc edge region of the display device and a gate driving sub-circuit located in the straight edge region of the display device. The adjacent region is also located next to the outer edge of the gate driving sub-circuit in the straight edge region near the gate driving sub-circuit in the arc edge region.

17. The display device according to claim 1, wherein, The ratio of the absolute value of the difference between the depth of the redundant hole and the depth of the contact hole corresponding to the location to the depth of the contact hole is less than or equal to 10%.

18. The display device according to claim 1, wherein, The absolute value of the difference between the sidewall inclination angle of the redundant hole corresponding to the position and the sidewall inclination angle of the contact hole is less than or equal to 10% of the sidewall inclination angle of the contact hole.

19. The display device according to claim 1, wherein, The display device also includes a light-emitting control circuit; In a direction perpendicular to the arrangement direction of the plurality of gate driving sub-circuits, the light emission control circuit is disposed between the gate driving sub-circuits and the edge of the display device, and at least one redundant hole is provided in the adjacent area between the light emission control circuit and the gate driving sub-circuits. The ratio of the number of redundant holes in the adjacent region to the number of contact holes in the light-emitting control circuit is in the range of 80% to 120%.

20. The display device according to claim 19, wherein, The absolute value of the difference between the size of the redundant hole in the adjacent region and the size of the contact hole in the light-emitting control circuit is less than or equal to 10% of the size of the contact hole in the light-emitting control circuit.

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