Bus arbiter, bus device, and system on chip

Abstract

The present disclosure relates to a bus arbiter, a bus device, and a system on chip. The bus arbiter comprises: an arbitration logic unit, configured to generate an arbitration signal on the basis of a plurality of request signals according to a preset arbitration rule; a register unit, configured to register the arbitration signal to generate a grant signal; a valid signal processing unit, configured to generate an arbitration valid signal on the basis of the plurality of request signals and the grant signal; and a ready signal processing unit, configured to generate an arbitration ready signal on the basis of the grant signal and a destination ready signal from a destination end.

Description

Bus arbitrators, bus devices, and systems-on-a-chip

[0001] Cross-reference of related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202510114521.8, filed on January 23, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to the field of electronic circuit technology, and more specifically, to a bus arbitrator, a bus device, and a system-on-a-chip. Background Technology

[0004] In System-on-Chips (SoCs), various bus devices are widely used for data and instruction transmission. When multiple source and destination terminals interact, a bus arbiter is often required to select the current participating source. However, within the bus arbiter or bus device, there may be long timing paths, which limits the highest synthesizable frequency of the circuit. Summary of the Invention

[0005] One of the purposes of this disclosure is to provide a bus arbitrator, bus device, and system-on-a-chip.

[0006] According to a first aspect of this disclosure, a bus arbitrator is provided, comprising:

[0007] An arbitration logic unit is configured to generate an arbitration signal based on a plurality of request signals according to a preset arbitration rule, wherein each request signal originates from a valid source signal of a corresponding source among a plurality of source ends, and the arbitration signal is configured to indicate a source end determined based on the preset arbitration rule.

[0008] A register unit, which is communicatively connected to the arbitration logic unit, and configured to register the arbitration signal to generate an authorization signal;

[0009] An effective signal processing unit, communicatively connected to the register unit, is configured to generate an arbitration effective signal based on the plurality of request signals and the authorization signal, wherein the arbitration effective signal is configured to provide a destination effective signal for the destination end; and

[0010] A ready signal processing unit is communicatively connected to the register unit and configured to generate an arbitration ready signal based on the authorization signal and a destination ready signal from the destination end, wherein the arbitration ready signal is configured to provide a source ready signal for each of the plurality of source ends.

[0011] In some embodiments, the bus arbiter further includes:

[0012] A signal aggregation unit is communicatively connected to at least one of the arbitration logic unit and the effective signal processing unit, and the signal aggregation unit is configured to generate a request vector signal having multiple bits based on the plurality of request signals, so that the request vector signal is transmitted to the at least one of the arbitration logic unit and the effective signal processing unit.

[0013] In some embodiments, the bit width of the request vector signal is equal to the number of the plurality of request signals; or

[0014] The i-th bit in the request vector signal is configured to indicate the i-th request signal among the plurality of request signals.

[0015] In some embodiments, the arbitration logic unit is configured to generate an arbitration signal for the current arbitration cycle based on the plurality of request signals and an arbitration signal or authorization signal generated in the previous arbitration cycle.

[0016] In some embodiments, the preset arbitration rules include at least one of the following: polling rules, QoS priority rules, first-in-first-out rules, and rules for dynamically adjusting priorities using an aging mechanism.

[0017] In some embodiments, the register unit includes a register, wherein the input of the register is configured to acquire the arbitration signal, the clock input of the register is configured to acquire a clock signal, and the output of the register is configured to output the authorization signal.

[0018] In some embodiments, the effective signal processing unit includes a multiplexer, wherein the input of the multiplexer is configured to acquire a plurality of request signals, the control of the multiplexer is configured to acquire the authorization signal, and the output of the multiplexer is configured to output the arbitration valid signal.

[0019] In some embodiments, the bit width of the authorization signal is equal to the number of the plurality of request signals; or

[0020] The i-th bit of the authorization signal is configured to be associated with the i-th request signal among the plurality of request signals; or

[0021] The authorization signal is one-hot encoded, wherein bits in the authorization signal that have a different level than the other bits are configured to indicate the source determined based on the preset arbitration rule.

[0022] In some embodiments, the arbitration valid signal is equal to the result of an OR operation on all bits of the arbitration vector signal, wherein the arbitration vector signal is equal to the result of a bitwise AND operation on the request vector signal and the authorization signal, the i-th bit in the request vector signal being high indicates that the source valid signal of the i-th source among the plurality of source ends is active, and the j-th bit in the authorization signal being high indicates that the j-th source among the plurality of source ends is the source end determined based on the preset arbitration rules.

[0023] In some embodiments, the bus arbiter further includes:

[0024] A signal splitting unit is communicatively connected to the ready signal processing unit, and the signal splitting unit is configured to generate multiple arbitration ready component signals based on an arbitration ready signal with multiple bits generated by the ready signal processing unit.

[0025] In some embodiments, the ready signal processing unit includes an AND gate, the two inputs of which are respectively configured to acquire the authorization signal and the destination ready signal, and the output of the AND gate is configured to output the arbitration ready signal.

[0026] In some embodiments, the arbitration ready signal is equal to the result of a logical AND operation between the authorization signal and the destination ready signal, and the i-th bit in the arbitration ready signal is configured to indicate the source ready signal of the i-th source among the plurality of source ends.

[0027] According to a second aspect of this disclosure, a bus device is provided, including the bus arbitrator as described above.

[0028] In some embodiments, the bus device further includes a register slicing circuit configured to communicatively connect between the bus arbiter and the destination.

[0029] In some embodiments, the bus device is configured to operate based on the AXI bus protocol.

[0030] According to a third aspect of this disclosure, an on-chip system is provided, comprising:

[0031] Multiple sources;

[0032] The destination; and

[0033] A bus arbiter as described above, communicatively connected between the plurality of source ends and the destination end, or a bus device as described above, communicatively connected between the plurality of source ends and the destination end.

[0034] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0035] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0036] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0037] Figure 1 shows a schematic diagram of a system-on-a-chip;

[0038] Figure 2 shows a schematic diagram of the time path in the on-chip system of Figure 1;

[0039] Figure 3 shows a schematic diagram of the structure of a system-on-a-chip according to an exemplary embodiment of the present disclosure;

[0040] Figure 4 shows a timing diagram of some signals in the on-chip system of Figure 3;

[0041] Figure 5 shows a schematic diagram of the time path in the on-chip system of Figure 3;

[0042] Figure 6 shows a schematic diagram of the structure of a system-on-a-chip according to another exemplary embodiment of the present disclosure.

[0043] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0044] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0045] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0046] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. That is, the various techniques, methods, and apparatuses described herein are shown in an exemplary manner to illustrate different embodiments of this disclosure and are not intended to be limiting. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement the invention, and not exhaustive ways.

[0047] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0048] In system-on-a-chip (SoC) design, data and instruction transmission can be implemented according to a specific bus protocol. For example, communication within the SoC can be implemented based on widely used bus protocols such as AMBA (Advanced Microcontroller Bus Architecture) or AXI (Advanced eXtensible Interface). In a bus device, each channel can control the data and instruction transmission rate between the master and slave devices (or source and destination) based on a handshake mechanism using valid (VALID) and ready (READY) signals. For example, the VALID signal generated by the source can indicate whether data or instructions are valid, while the READY signal generated by the destination can indicate whether the corresponding data or instructions can be received. In this document, unless otherwise stated, a high VALID signal indicates valid data or instructions, and a low VALID signal indicates invalid data or instructions; similarly, a high READY signal indicates that the corresponding data or instructions can be received, and a low READY signal indicates that the corresponding data or instructions cannot be received. Thus, data or instructions are transmitted between the source and destination only when both the VALID and READY signals are high. However, it is understood that other voltage levels can be used to indicate the validity of data or instructions or the ability to receive them, as needed. This is not a limitation, and those skilled in the art can adjust the relevant circuitry appropriately according to the changes in voltage level representation based on the description herein.

[0049] The bus arbiter is one of the key technologies for shared bus devices. In one bus arbitration scheme, as shown in Figure 1, multiple source valid (VALID) signals generated by multiple source terminals 200' can be directly connected to the corresponding request lines of the bus arbiter 100'. That is, the request signal request[i] in the bus arbiter 100' can be equal to the source valid signal VALID_s[i] from the i-th source terminal 200', where i is an integer, starting from 1 (1≤i≤N), and N is the total number of source terminals 200'. The bus arbiter 100' can complete the arbitration between multiple request signals request[i] within the current arbitration cycle (or the current clock cycle) and determine the index number n of the winner. The destination ready (READY) signal generated by a single destination terminal 300' can be directly connected to the grant acquisition enable line of the bus arbiter 100'. That is, the grant acquisition enable signal take_grant in the bus arbiter 100' can be equal to the destination READY signal READY_t from the destination terminal 300'. If READY_t is low (i.e., READY_t = 0), then all grant enable signals grant[i] are low (i.e., grant[i] = 0), and correspondingly, all source-end ready (READY) signals of source terminals 200' will be low, i.e., READY_s[i] = grant[i] = 0, where i is an integer, starting from 1 (1 ≤ i ≤ N), and N is the total number of source terminals 200'; while if READY_t is high (i.e., READY_t = 0), then all grant enable signals grant[i] are low (i.e., grant[i] = 0), and all source-end ready (READY) signals of source terminals 200' are low (i.e., READY_t = 0). If DY_t=1), then, combined with the index number n of the winner determined by the arbitration, the nth grant enable signal grant[n] will be in a high level state (i.e., grant[n]=1), while other grant enable signals will be in a low level state. Correspondingly, the source ready signal of the nth source end 200' as the winner will satisfy READY_s[n]=grant[n]=1, while the source ready signals of other source ends 200' will be in a low level state, so as to carry out data or instruction transmission between the nth source end and the destination end.

[0050] As shown by the dashed arrow in Figure 2, based on the bus arbiter 100' in Figure 1, a time path or timing loop will be formed from the source VALID to the source READY. If the distance between the source 200' and the bus arbiter 100' is large on the back-end layout of the system-on-a-chip or chip, the above-mentioned time path will cause a large timing delay, becoming a critical path that limits the highest synthesizable frequency of the bus device.

[0051] To improve latency in bus devices, some bus arbitrators employ a multi-cycle arbitration (MCP) strategy, where arbitration is performed only once every two or more clock cycles, rather than within each clock cycle. However, while the MCP strategy increases the synthesizable frequency, it does not bring a substantial improvement in bandwidth performance and may even lead to a decrease in bandwidth performance. Taking the following two schemes for the read data channel in an AXI bus device (assuming a bit width DW of DW = 64 bits) as examples, in Scheme 1, without the MCP strategy, the highest synthesizable frequency Fmax of the AXI bus device is Fmax = 600MHz. Therefore, the theoretical bandwidth Bmax of the read data channel in the AXI bus device will satisfy Bmax = Fmax * DW = 4.8GB / s. In Scheme 2, using the MCP strategy and arbitrating every two clock cycles, the highest synthesizable frequency Fmax of the AXI bus device is Fmax = 1000MHz. Therefore, the theoretical bandwidth Bmax of the read data channel in the AXI bus device will satisfy Bmax = Fmax * DW / 2 = 4.0GB / s. It is evident that although the MCP strategy increases the frequency of the AXI bus device, the theoretical bandwidth actually decreases.

[0052] To address the aforementioned problems, this disclosure proposes a bus arbitrator. In an exemplary embodiment of this disclosure, as shown in FIG3, the bus arbitrator 100 may include an arbitration logic unit 110, a register unit 120, an active signal processing unit 130, and a ready signal processing unit 140.

[0053] The arbitration logic unit 110 can be configured to generate arbitration signals based on multiple request signals according to preset arbitration rules. For example, the arbitration logic unit 110 may include combinational logic circuits corresponding to the preset arbitration rules to implement the desired preset arbitration logic. The register unit 120 can be communicatively connected to the arbitration logic unit 110, and the register unit 120 can be configured to register arbitration signals to generate authorization signals. Here, multiple request signals can be transmitted through multiple request lines in the bus arbitrator 100, where each request signal can originate from the source valid signal of a corresponding source 200 among multiple source 200s. For example, the i-th request signal request[i] can be equal to the source valid signal VALID_s[i] from the i-th source 200, where i is an integer, i can start from 1 (1≤i≤N), and N is the total number of source 200s. The arbitration signal, or the authorization signal generated based on the arbitration signal, can be configured to indicate the source 200 selected or determined based on preset arbitration rules, so that it can be determined which of the multiple source 200s will communicate with the destination 300 based on the arbitration signal or authorization signal. Due to the presence of the register unit 120, the arbitration logic unit 110 can be configured to generate the arbitration signal in the current clock cycle based on the arbitration signal or authorization signal generated in the previous clock cycle. In other words, since the authorization signal is output from the register unit 120 inside the bus arbitrator 100, the time path from source VALID to source READY as shown in FIG. 2 is interrupted or eliminated, thereby greatly increasing the highest synthesizable frequency of the bus device, where the highest synthesizable frequency refers to the upper limit of the main frequency at which a semiconductor module (IP) can operate stably for a long time.

[0054] In some embodiments, the arbitration logic unit 110 may be configured to generate an arbitration signal in the current arbitration cycle based on a plurality of request signals and an arbitration signal or authorization signal generated in the previous arbitration cycle. Here, each arbitration cycle may be the same as each clock cycle in the bus device; or, as needed, it may be combined with the MCP strategy described above, and each arbitration cycle may be formed by a plurality of clock cycles in the bus device, without limitation.

[0055] In some embodiments, the preset arbitration rule may include at least one of the following: a round-robin rule, a QoS (Quality of Service) priority rule, a first-in-first-out (FIFO) rule, and a rule that dynamically adjusts priority using an aging mechanism. For example, on the read address channel or write address channel of an AXI bus device, a preset arbitration rule combining a QoS priority rule and a round-robin rule can be used. For instance, when different source terminals 200 have different priorities, the transmission of data or instructions between the source terminal 200 and the destination terminal 300 with the higher priority can be prioritized based on the QoS priority rule; additionally, for multiple source terminals 200 with the same priority, the transmission of data or instructions between the corresponding source terminal 200 and the destination terminal 300 can be sequentially executed based on the round-robin rule. On the read data channel or write response channel of an AXI bus device, a simple round-robin rule can be used as the preset arbitration rule. In other embodiments, other preset arbitration rules, such as a first-in-first-out rule or a rule that dynamically adjusts priority using an aging mechanism, may also be used depending on the specific scenario, and are not limited here.

[0056] In some embodiments, register unit 120 may include a register. The input terminal of the register (e.g., the D terminal shown in FIG3) can be configured to acquire an arbitration signal, the clock terminal of the register (e.g., the CK terminal shown in FIG3) can be configured to acquire a clock signal aclk, and the output terminal of the register (e.g., the Q terminal shown in FIG3) can be configured to output an authorization signal. Thus, the generated authorization signal can have a certain delay relative to the arbitration signal, allowing the arbitration logic unit 110 to generate the arbitration signal in the current clock cycle based on the arbitration signal or authorization signal generated in the previous clock cycle, thereby transforming the time loop in the bus arbitrator 100 into a unidirectional controllable time path. It is understood that, in order to generate the desired delay, register unit 120 may also include more registers or other circuit components, which is not limited here.

[0057] In some embodiments, the arbitration logic unit 110 may be configured to directly receive multiple request signals from multiple request lines. Alternatively, in other embodiments, to simplify the processing of request signals, as shown in FIG3, the bus arbitrator 100 may further include a signal aggregation unit 150, which may be communicatively connected to the arbitration logic unit 110. Furthermore, the signal aggregation unit 150 may be communicatively connected to multiple request lines, and the signal aggregation unit 150 may be configured to generate a request vector signal bus_request with multiple bits based on multiple request signals (request[1] to request[N]), so that the request vector signal is transmitted to the arbitration logic unit 110. In a specific example, the bit width of the request vector signal may be equal to the number of multiple request signals. Furthermore, the i-th bit in the request vector signal may be configured to indicate the i-th request signal among the multiple request signals; for example, the i-th bit in the request vector signal may be equal to the i-th request signal.

[0058] In an exemplary embodiment of this disclosure, as shown in FIG3, the valid signal processing unit 130 may be communicatively connected to the register unit 120, and the valid signal processing unit 130 may be configured to generate an arbitration valid signal based on a plurality of request signals and grant signals. In some embodiments, the valid signal processing unit 130 may be configured to directly receive a plurality of request signals from a plurality of request lines. Alternatively, in other embodiments, as shown in FIG3, the signal summarization unit 150 may be communicatively connected to the valid signal processing unit 130 to transmit request vector signals to the valid signal processing unit 130. The arbitration valid signal grant_valid may be configured to indicate whether the source end 200, determined based on preset arbitration rules, has a valid data or instruction transmission request, and the arbitration valid signal grant_valid may be configured to provide a destination valid signal VALID_t for the destination end to control the transmission of data or instructions between the corresponding source end 200 and the destination end 300. In some embodiments, the valid signal processing unit 130 can be configured such that if the source valid signal of the source end 200 selected based on the preset arbitration rule is in a high-level state, the arbitration valid signal grant_valid is in a high-level state, thereby causing the destination valid signal VALID_t to be in a high-level state, at which time the corresponding data or instruction transmission between the source end 200 and the destination end 300 may be performed; however, if the source valid signal of the source end 200 selected based on the preset arbitration rule is in a low-level state, or the source end with a high-level source valid signal is different from the source end selected based on the preset arbitration rule, or the source valid signals of all sources are in a low-level state, the arbitration valid signal grant_valid is in a low-level state, thereby causing the destination valid signal VALID_t to be in a low-level state, at which time the transmission of data or instructions between the source end 200 and the destination end 300 cannot be performed.

[0059] As mentioned above, depending on specific needs, the effective signal processing unit 130 can have various circuit configurations to generate the desired arbitration valid signal, and no limitation is made here. In some embodiments, as shown in FIG3, the effective signal processing unit 130 may include a multiplexer (MUX), wherein the input terminal of the multiplexer can be configured to acquire multiple request signals (for example, the multiplexer may have multiple input terminals, each of which can acquire a corresponding request signal, or the input terminal of the multiplexer can acquire a request vector signal and split it into multiple corresponding request signals according to the request vector signal), the control terminal of the multiplexer can be configured to acquire an authorization signal from the register unit 120, and the output terminal of the multiplexer can be configured to output an arbitration valid signal.

[0060] In some embodiments, the bit width of the grant signal can be equal to the number of multiple request signals. Furthermore, the i-th bit in the grant signal can be configured to be associated with the i-th request signal among the multiple request signals. Further, in some embodiments, the grant signal can be one-hot encoded, wherein bits in the grant signal grant_onehot with a level different from the other bits can be configured to indicate the source determined based on a preset arbitration rule. For example, when the i-th bit in the grant signal grant_onehot is high (i.e., grant_onehot[i] = 1), it indicates that the corresponding i-th request signal is high (i.e., request[i] = 1), and the corresponding i-th source 200 can transmit data or instructions, while the other request signals are low, and the corresponding other source 200 cannot transmit data or instructions temporarily.

[0061] In a specific example, the arbitration valid signal `grant_valid` can be equal to the result of the bitwise OR operation of all bits in the arbitration vector signal. The arbitration vector signal can be equal to the bitwise AND operation of the request vector signal `bus_request` and the grant signal `grant_onehot`, i.e., `grant_valid = |(bus_request&grant_onehot)`. As mentioned above, the i-th bit in the request vector signal `bus_request` being high indicates that the source valid signal `VALID_s[i]` of the i-th source 200 among the multiple source 200s is high, meaning the i-th source 200 is currently requesting data or instruction transmission. The j-th bit in the grant signal `grant_onehot` being high indicates that the j-th source 200 among the multiple source 200s is the source 200 determined based on the preset arbitration rules. Thus, the arbitration valid signal `grant_valid` is high only when i = j, i.e., when the source 200 determined based on the preset arbitration rules is currently requesting data or instruction transmission, thus making data or instruction transmission possible.

[0062] In an exemplary embodiment of this disclosure, as shown in FIG3, the ready signal processing unit 140 can be communicatively connected to the register unit 120, and the ready signal processing unit 140 can be configured to generate an arbitration ready signal based on an grant signal and a destination ready signal from the destination end. In some embodiments, the destination ready signal READY_t from the destination end can be transmitted to the ready signal processing unit 140 in the form of a grant acquisition enable signal take_grant via the grant acquisition enable line of the bus arbitrator 100. The arbitration ready signal bus_ready can be configured to provide a source ready signal READY_s[i] for each of the plurality of source ends 200. In some embodiments, the ready signal processing unit 140 can be configured such that if the destination ready signal READY_t is in a low-level state (i.e., READY_t = 0), the source ready signals provided to all source ends 200 are in a low-level state (i.e., READY_s[i] = 0), where i is an integer, i can start from 1 (1 ≤ i ≤ N), and N is the total number of source ends 200; while if the destination ready signal READY_t is in a high-level state (i.e., READY_t = 1), the source ready signal READY_s[n] of the nth source end 200 selected based on the preset arbitration rule will be in a high-level state (i.e., READY_s[n] = 1), while the source ready signals of other source ends 200 will be in a low-level state, thus making it possible to transmit data or instructions between the nth source end 200 and the destination end 300.

[0063] As mentioned above, depending on specific needs, the ready signal processing unit 140 can have various circuit configurations to generate the desired arbitration ready signal, which are not limited here. In some embodiments, as shown in FIG3, the ready signal processing unit 140 may include an AND gate. The two input terminals of the AND gate can be configured to acquire the grant signal grant_onehot and the destination ready signal VALID_t (or the grant acquisition enable signal take_grant), respectively, and the output terminal of the AND gate can be configured to output the arbitration ready signal bus_ready. In other words, the arbitration ready signal bus_ready can be equal to the result of the logical AND operation of the grant signal grant_onehot and the destination ready signal VALID_t, that is, the i-th bit of the arbitration ready signal bus_ready is equal to the result of the AND operation of the i-th bit of the grant signal grant_onehot and the destination ready signal VALID_t. The i-th bit in the arbitration ready signal bus_ready can be configured to indicate the source ready signal READY_s[i] of the i-th source terminal 200 among the plurality of source terminals 200. However, it is understood that in some other embodiments, if a low-level state indicates readiness and a high-level state indicates not yet ready, then an OR gate can be used instead of an AND gate to form the ready signal processing unit 140. Alternatively, depending on actual needs, the ready signal processing unit 140 may also include other components, which are not limited here.

[0064] In some embodiments, as shown in FIG3, the bus arbiter 100 may further include a signal splitting unit 160, which is communicatively connected to the ready signal processing unit 140. The signal splitting unit 160 may be configured to generate multiple arbitration ready component signals based on the arbitration ready signal bus_request generated by the ready signal processing unit 140, which has multiple bits. These arbitration ready component signals may be provided to the corresponding source end 200 via corresponding signal lines, thereby serving as the source end ready signal of the corresponding source end 200. In a specific example, the i-th arbitration ready component signal may be equal to the i-th bit of the arbitration ready signal, and the i-th arbitration ready component signal may serve as the source end ready signal READY_s[i] of the i-th source end 200. Furthermore, in some embodiments, the signal splitting unit 160 and the signal summarizing unit 150 may have the same or similar circuit structures, as long as their input and output sides are set in the desired direction, signal summarization or splitting can be achieved.

[0065] Figure 4 shows a specific example of the timing diagram of some signals used by the bus arbitrator 100 shown in Figure 3 to perform data or instruction transmission based on a polling rule. Here, aclk represents the clock signal, bus_request[i] represents the i-th bit in the request vector signal bus_request, and bus_request[i] = request[i] = VALID_s[i], take_grant represents the grant enable signal, and take_grant = READY_t, grant_valid represents the arbitration valid signal, and grant_onehot[i] represents the i-th bit in the one-hot encoded grant signal grant_onehot, where grant_onehot[i] = 1 indicates that the arbitration logic unit 110 is currently responding to the i-th source, i.e., the i-th source is selected to transmit data or instructions, and grant_onehot[i] = 0 indicates that the i-th source is not selected. As described above, data or instruction transmission can only occur when the arbitration valid signal grant_valid and the grant enable signal take_grant are both high. Furthermore, based on the bus arbitrator 100 in Figure 3, the arbitration operation according to the preset arbitration rules is processed on the rising edge of the clock signal aclk.

[0066] As shown in Figure 4, during clock cycle T0, the source valid signals VALID_s[0] to VALID_s[3] of the four source terminals 200 are all in a high-level state, that is, each bit of the request vector signal is 1 (i.e., bus_request[0] = 1, bus_request[1] = 1, bus_request[2] = 1, bus_request[3] = 1). At this time, only the 0th bit of the grant signal grant_onehot is 1, that is, grant_onehot[0] = 1, that is, responding to the 0th source terminal. After completing the arbitration within clock cycle T0, according to the polling rule, in the next clock cycle T1, the 1st source terminal will be responded to first, that is, the 1st bit of the grant signal grant_onehot is 1 (i.e., grant_onehot[1] = 1). It is important to note that if, during clock cycle T0, only the source valid signals VALID_s[0], VALID_s[2], and VALID_s[3] of the three source terminals 200 are at a high level, while VALID_s[1] is at a low level, then according to the polling rule, during clock cycle T1, the request signal request[2] corresponding to the second source terminal will be responded to, but the request signal request[1] will not be responded to. Furthermore, during clock cycle T1, since the grant acquisition enable signal take_grant = 0, it indicates that the destination terminal 300 has not yet been able to receive data or instructions, and therefore cannot transmit data or instructions, and the state of the grant signal grant_onehot remains unchanged, that is, grant_onehot[1] = 1. During the next clock cycle T2, the grant acquisition enable signal take_grant = 1, indicating that the destination terminal 300 has been able to receive data or instructions, and the arbitration valid signal grant_valid is also at a high level, so during clock cycle T2, it can respond to the request signal request[1] to transmit data or instructions. Then, within clock cycle T3, the request signal request[2] is responded to, i.e., grant_onehot[2] = 1. However, since the grant acquisition enable signal take_grant = 0 within clock cycles T3 and T4, data or instructions cannot be transmitted yet, and the state of the grant signal grant_onehot remains unchanged, i.e., grant_onehot[2] = 1. Until clock cycle T5, the grant acquisition enable signal take_grant changes to a high level, and the arbitration valid signal grant_valid is also in a high level. Therefore, within clock cycle T5, data or instructions can be transmitted in response to the request signal request[2]. Then, within clock cycle T6, the request signal request[3] corresponding to the third source will be responded to, i.e., grant_onehot[3] = 1.However, since the grant enable signal take_grant = 0 during clock cycle T6, data or instructions cannot be transmitted. Until clock cycle T7, the grant enable signal take_grant = 1, and the arbitration valid signal grant_valid is also at a high level. Therefore, data or instructions can be transmitted in response to the request signal request[3] during clock cycle T7. In addition, during clock cycle T7, the request signals request[0], request[1], and request[2] are all at a low level, that is, there is no new data or instruction transmission request. Therefore, the current source end of the response is maintained during clock cycle T7. During clock cycles T8 and T9, the request signal request[3] continues to be responded to. However, during clock cycle T8, there is no need for data or instruction transmission, so no transmission is performed. During clock cycle T9, the state of the grant signal grant_onehot remains unchanged, that is, grant_onehot[3] = 1. Meanwhile, since the request signal request[0] is high during clock cycle T9, the grant signal will satisfy grant_onehot[0] = 1 during clock cycle T10. However, since there are no other request signals during clock cycle T10, grant_onehot[0] remains 1 during clock cycle T11.

[0067] Figure 5 shows a schematic diagram of the time paths in the on-chip system of Figure 3. As indicated by the dashed arrows in Figure 5, there are a total of five time paths: 1. A first time path from the source 200 through (signal aggregation unit 150 and) arbitration logic unit 110 to the register unit 120; 2. A second time path from the source 200 through (signal aggregation unit 150 and) valid signal processing unit 130 to the destination 300; 3. A third time path from the register unit 120 through the valid signal processing unit 130 to the destination 300; 4. A fourth time path from the register unit 120 through the ready signal processing unit 140 (and signal splitting unit 160) to the source 200; and 5. A fifth time path from the destination 300 through the ready signal processing unit 140 (and signal splitting unit 160) to the source 200. As can be seen, based on the improved bus arbiter, the time loop from source VALID to source READY shown in Figure 2 is interrupted or eliminated, and the above five time paths are all unidirectionally controllable and can also occur simultaneously, thereby helping to maximize the highest synthesizable frequency of the bus device. Moreover, such a bus arbiter 100 also meets the requirement that the generation of the VALID signal in, for example, the AXI bus interface protocol does not depend on the READY signal.

[0068] According to a second aspect of this disclosure, a bus device is also provided, which may include the bus arbitrator 100 as described above. Furthermore, the bus device may also include multiple channels, such as a read address channel, a read data channel, a write address channel, a write data channel, and a write response channel.

[0069] Furthermore, in some embodiments, if certain source terminals are far from the destination terminal in subsequent layouts of the system-on-chip, the time path between the source and destination terminals may also cause a decrease in the highest synthesizable frequency of the bus device, especially the second and fifth time paths (time paths between the source and destination terminals) shown in FIG. 5, which may cause a decrease in the synthesis frequency. In response, in another exemplary embodiment of this disclosure, as shown in FIG. 6, the bus device may further include a register slicing circuit 400, which may be configured to communicatively connect between the bus arbiter 100 and the destination terminal 300. The register slicing circuit 400 may include circuit components such as registers, which can block or eliminate the time path between the source terminal 200 and the destination terminal 300 in a manner similar to register unit 120, thereby helping to improve the highest synthesizable frequency of the bus device.

[0070] In some embodiments, the bus device can be configured to operate based on the AXI bus protocol, meaning the bus device can be an AXI bus device. The AXI bus protocol targets high-performance, high-frequency system designs, is suitable for high-bandwidth, low-latency system designs, can achieve high-frequency operation without the need for complex bus bridges, can meet the interface requirements of numerous components, and possesses a highly flexible interconnect structure. For example, in an AXI bus device, a bus arbiter is typically used in the following scenarios: 1. Multiple master devices simultaneously access the read address of a slave device; 2. Multiple master devices simultaneously access the write address of the same slave device; 3. Multiple write response signals are simultaneously returned from different slave devices; and 4. Multiple read data are simultaneously returned from different slave devices. Based on the bus device of this disclosure, the data or instruction transmission efficiency related to these processes can be effectively improved.

[0071] According to a third aspect of this disclosure, a system-on-a-chip is also provided, which may include a plurality of source terminals 200, a destination terminal 300, and a bus arbitrator as described above, or a bus device as described above, communicatively connected between the plurality of source terminals 200 and the destination terminal 300.

[0072] In the technical solution disclosed herein, by setting up a register unit in the bus arbitrator, the arbitration logic unit can determine the arbitration result in the current clock cycle based on the arbitration result in the previous clock cycle, thereby eliminating the time loop from source VALID to source READY, making the time path in the bus arbitrator unidirectionally controllable, which helps to increase the highest synthesizable frequency of the bus device, and thus helps to improve the computing efficiency of the on-chip system.

[0073] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0074] The terms “front,” “back,” “top,” “bottom,” “above,” “below,” etc., used in the specification and claims, if present, are for descriptive purposes and are not necessarily used to describe unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein can, for example, operate on orientations different from those shown or otherwise described herein.

[0075] As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and not as a "model" to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited to any theory expressed or implied in the foregoing description of the technical field, background, invention, or detailed description.

[0076] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0077] The above description may refer to elements, nodes, or features that are “connected” or “coupled” together. As used herein, unless otherwise expressly stated, “connected” means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature electrically, mechanically, logically, or otherwise. Similarly, unless otherwise expressly stated, “coupled” means that one element / node / feature can be directly or indirectly connected to another element / node / feature mechanically, electrically, logically, or otherwise to allow interaction, even if the two features may not be directly connected. That is, “coupled” is intended to include both direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0078] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0079] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0080] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A bus arbitrator, comprising: An arbitration logic unit is configured to generate an arbitration signal based on a plurality of request signals according to a preset arbitration rule, wherein each request signal originates from a valid source signal of a corresponding source among a plurality of source ends, and the arbitration signal is configured to indicate a source end determined based on the preset arbitration rule. A register unit, which is communicatively connected to the arbitration logic unit, and configured to register the arbitration signal to generate an authorization signal; An effective signal processing unit, communicatively connected to the register unit, is configured to generate an arbitration effective signal based on the plurality of request signals and the authorization signal, wherein the arbitration effective signal is configured to provide a destination effective signal for the destination end; and A ready signal processing unit is communicatively connected to the register unit and configured to generate an arbitration ready signal based on the authorization signal and a destination ready signal from the destination end, wherein the arbitration ready signal is configured to provide a source ready signal for each of the plurality of source ends.

2. The bus arbiter according to claim 1, further comprising: A signal aggregation unit is communicatively connected to at least one of the arbitration logic unit and the effective signal processing unit, and the signal aggregation unit is configured to generate a request vector signal having multiple bits based on the plurality of request signals, so that the request vector signal is transmitted to the at least one of the arbitration logic unit and the effective signal processing unit.

3. The bus arbitrator according to claim 2, wherein, The bit width of the request vector signal is equal to the number of the plurality of request signals; or The i-th bit in the request vector signal is configured to indicate the i-th request signal among the plurality of request signals.

4. The bus arbitrator according to claim 1, wherein, The arbitration logic unit is configured to generate an arbitration signal in the current arbitration cycle based on the plurality of request signals and an arbitration signal or authorization signal generated in the previous arbitration cycle.

5. The bus arbitrator according to claim 1, wherein, The preset arbitration rules include at least one of the following: polling rules, QoS priority rules, first-in-first-out rules, and rules that dynamically adjust priority using an aging mechanism.

6. The bus arbitrator according to claim 1, wherein, The register unit includes a register, wherein the input of the register is configured to acquire the arbitration signal, the clock input of the register is configured to acquire a clock signal, and the output of the register is configured to output the authorization signal.

7. The bus arbiter according to claim 1, wherein, The effective signal processing unit includes a multiplexer, wherein the input of the multiplexer is configured to acquire multiple request signals, the control of the multiplexer is configured to acquire the authorization signal, and the output of the multiplexer is configured to output the arbitration valid signal.

8. The bus arbitrator according to claim 7, wherein, The bit width of the authorization signal is equal to the number of the plurality of request signals; or The i-th bit in the authorization signal is configured to be associated with the i-th request signal among the plurality of request signals; or The authorization signal is one-hot encoded, wherein bits in the authorization signal that have a different level than the other bits are configured to indicate the source determined based on the preset arbitration rule.

9. The bus arbitrator according to claim 8, wherein, The arbitration valid signal is equal to the result of the OR operation of all bits in the arbitration vector signal, wherein the arbitration vector signal is equal to the result of the bitwise AND operation of the request vector signal and the authorization signal, the level of the i-th bit in the request vector signal being high indicates that the source valid signal of the i-th source among the plurality of source ends is effective, and the level of the j-th bit in the authorization signal being high indicates that the j-th source among the plurality of source ends is the source end determined based on the preset arbitration rule.

10. The bus arbiter according to claim 1, further comprising: A signal splitting unit is communicatively connected to the ready signal processing unit, and the signal splitting unit is configured to generate multiple arbitration ready component signals based on an arbitration ready signal with multiple bits generated by the ready signal processing unit.

11. The bus arbitrator according to claim 1, wherein, The ready signal processing unit includes an AND gate, the two inputs of which are respectively configured to acquire the authorization signal and the destination ready signal, and the output of which is configured to output the arbitration ready signal.

12. The bus arbiter according to claim 11, wherein, The arbitration ready signal is equal to the result of a logical AND operation between the authorization signal and the destination ready signal, and the i-th bit in the arbitration ready signal is configured to indicate the source ready signal of the i-th source among the plurality of source ends.

13. A bus device comprising a bus arbitrator according to any one of claims 1 to 12.

14. The bus device of claim 13, further comprising a register slicing circuit configured to communicatively connect between the bus arbiter and the destination.

15. The bus device according to claim 13, wherein, The bus device is configured to operate based on the AXI bus protocol.

16. A system-on-a-chip, comprising: Multiple sources; Destination end; as well as A bus arbiter according to any one of claims 1 to 12, communicatively connected between the plurality of source ends and the destination end, or a bus device according to any one of claims 13 to 15, communicatively connected between the plurality of source ends and the destination end.

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