Semiconductor device, electronic device, stacked transistor, and fabrication method therefor

Abstract

The present disclosure provides a semiconductor device, an electronic device, a stacked transistor, and a fabrication method therefor. The stacked transistor fabrication method comprises: removing a second dummy gate structure to expose a second active structure and a gate isolation layer; coating a photoresist on the second active structure and the gate isolation layer in a first semiconductor unit, and removing at least the gate isolation layer in a second semiconductor unit by means of an etching process; sequentially removing a first dummy gate structure and the photoresist to expose a first active structure, the gate isolation layer, and the second active structure in the first semiconductor unit, and a first active structure and the second active structure in the second semiconductor unit; forming a first gate structure and a second gate structure on the basis of the first active structure, the gate isolation layer, and the second active structure in the first semiconductor unit, and simultaneously forming a third gate structure and a fourth gate structure on the basis of the first active structure and the second active structure in the second semiconductor unit.

Description

Semiconductor devices, electronic devices, stacked transistors and their fabrication methods

[0001] Cross-references to related applications

[0002] This disclosure is based on and claims priority to Chinese Patent Application No. 202510124629.5, filed on January 26, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the semiconductor field, and more particularly to a semiconductor device, electronic device, stacked transistor, and a method for fabricating the same. Background Technology

[0004] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, by integrating two or more layers of transistors in a vertical space, further increase transistor integration density and have become one of the important technologies for continuing the miniaturization of integrated circuits.

[0005] In some methods for fabricating stacked transistors, the active regions of two homogeneous transistor layers are formed by etching, and the stacked transistors are fabricated on both sides of the wafer by flipping the wafer. This can also be called the "self-aligned flip-chip transistor" method. However, in the "self-aligned flip-chip transistor" method, the stacked transistors fabricated on the same wafer can only be uniformly classified as either a split-gate structure or a common-gate structure. This limits design flexibility and further miniaturization of circuit size. Summary of the Invention

[0006] This disclosure provides a semiconductor device, an electronic device, a stacked transistor, and a method for fabricating the same.

[0007] This disclosure provides a method for fabricating a stacked transistor, comprising: the stacked transistor including a first semiconductor unit and a second semiconductor unit, the first semiconductor unit and the second semiconductor unit being disposed adjacent to each other in a first direction; each of the first semiconductor unit and the second semiconductor unit includes: a first active structure and a second active structure stacked along a second direction, a first dummy gate structure corresponding to the first active structure, a first source / drain structure corresponding to the first active structure, a second dummy gate structure corresponding to the second active structure, and a second source / drain structure corresponding to the second active structure; wherein a gate isolation layer is formed between the first dummy gate structure and the second dummy gate structure; the method includes: removing the second dummy gate structure to expose the second active structure and the gate isolation layer; coating photoresist on the second active structure and the gate isolation layer in the first semiconductor unit, and removing at least the gate isolation layer in the second semiconductor unit by an etching process; sequentially removing the first dummy gate structure and the photoresist to expose the first active structure, the gate isolation layer, and the second dummy gate structure in the first semiconductor unit. The second active structure, and the first active structure and the second active structure in the second semiconductor unit; based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, a first gate structure and a second gate structure are formed, and simultaneously based on the first active structure and the second active structure in the second semiconductor unit, a third gate structure and a fourth gate structure are formed; wherein, the gate isolation structure in the first semiconductor structure is located between the first gate structure and the second gate structure, and the third gate structure and the fourth gate structure are connected; the first gate structure and the first source-drain structure in the first semiconductor structure form a first transistor, the second gate structure and the second source-drain structure in the first semiconductor structure form a second transistor, the third gate structure and the first source-drain structure in the second semiconductor structure form a third transistor, and the fourth gate structure and the second source-drain structure in the second semiconductor structure form a fourth transistor; the first transistor and the second transistor form a first stacked transistor, and the third transistor and the fourth transistor form a second stacked transistor.

[0008] A second aspect of this disclosure provides a stacked transistor. The stacked transistor includes: a first stacked transistor and a second stacked transistor disposed adjacent to each other in a first direction; wherein the first stacked transistor includes: a first transistor and a second transistor disposed opposite to each other along a second direction; a gate isolation layer is formed between a first gate structure of the first transistor and a second gate structure of the second transistor, the gate isolation layer being used for electrical isolation between the first gate structure and the second gate structure; the second stacked transistor includes: a third transistor and a fourth transistor disposed opposite to each other along the second direction; the third gate structure of the third transistor and the fourth gate structure of the fourth transistor are connected.

[0009] This disclosure provides a third aspect of a semiconductor device, comprising: stacked transistors as described in the second aspect embodiment above.

[0010] This disclosure provides a fourth aspect of an electronic device, including: a circuit board and a semiconductor device as described in the third aspect embodiment above, the semiconductor device being disposed on the circuit board.

[0011] Compared with the prior art, this disclosure has the following advantages:

[0012] In this embodiment, by retaining the gate isolation layer in the first semiconductor unit, the first gate structure and the second gate structure in the subsequently fabricated first stacked transistor can be separated by the gate isolation layer, thereby forming a split-gate structure. Conversely, by removing the gate isolation layer in the second semiconductor unit, the third gate structure and the fourth gate structure in the subsequently fabricated second stacked transistor are connected, thereby forming a common-gate structure. Furthermore, the first semiconductor unit and the second semiconductor unit are arranged adjacent to each other in the first direction, which meets the requirements of standard logic units in a circuit. Therefore, this embodiment simultaneously fabricates stacked transistors with split-gate structures and stacked transistors with common-gate structures, which not only increases the flexibility of circuit design but also allows for further miniaturization of the size of standard circuit units and the overall circuit size.

[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of embodiments of this disclosure.

[0015] Figure 1 is a schematic flowchart of a method for fabricating a stacked transistor according to an embodiment of the present disclosure.

[0016] Figure 2 is a top view schematic diagram of a stacked transistor according to an embodiment of the present disclosure.

[0017] Figures 3 to 38 are schematic diagrams of the structure of a stacked transistor during the fabrication process according to embodiments of the present disclosure.

[0018] Figures 39 and 40 are schematic diagrams of the structure of a stacked transistor during the fabrication process according to embodiments of the present disclosure.

[0019] Explanation of reference numerals in the attached figures: Stacked transistor 10; First stacked transistor 101; Second stacked transistor 102; First transistor 11; Second transistor 12; Third transistor 13; Fourth transistor; First source / drain structure 112; First interlayer dielectric layer 113; First gate structure 114; First source / drain metal 115; Front metal interconnect layer 116; Second source / drain structure 122; Second interlayer dielectric layer 123; Second gate structure 124; Second source / drain metal 125; Back metal interconnect layer 126; Third gate structure 134; Fourth gate structure 144; Semiconductor substrate 20; Initial stacked structure 21; Initial barrier layer 22; Stacked structure 23; Barrier layer 24; Shallow trench isolation structure 25; 26. First dummy gate structure; 27. Gate isolation layer; 28. Second dummy gate structure; 29. ​​First active structure; 30. First sacrificial layer; 31. Second active structure; 32. Second sacrificial layer; 33. Dummy gate sidewall; 34. Isolation structure; 35. Internal sidewall; 36. First deep trench; 37. Filling structure; 38. Source-drain isolation structure; 40. First carrier wafer; 41. First semiconductor unit; 42. Photoresist; 43. Gate dielectric layer; 44. Gate filling structure; 45. Back gate isolation structure; 47. Back dielectric layer; 48. Second insulating layer; 49. Second carrier wafer; 50. Front gate isolation structure; 51. Front dielectric layer; 52. Third insulating layer; 53. Detailed Implementation

[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure.

[0021] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments disclosed herein. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0022] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the important technologies for continuing the miniaturization of integrated circuits.

[0023] In one embodiment, there are two approaches to the fabrication process of stacked transistors: the first is a monolithic approach, and the second is a sequential approach.

[0024] The first approach involves fabricating N-channel field-effect transistors (NFETs) and P-channel field-effect transistors (PFETs) on the same substrate through repeated exposure, etching, and diffusion processes, vertically stacking the two transistors. However, the fabrication process of the first approach dictates that the transistors in the same layer of the stacked transistors must be of the same type, and they must be strictly in the same planar space, with no alignment deviation. The advantage of the first approach is its higher integration density. The disadvantages of the first approach include the following two points: (1) the process is complex, requiring extensive development and optimization of process technologies; (2) the polarity of the transistors in the same layer is fixed, requiring two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, resulting in poor design flexibility.

[0025] The second approach involves attaching a wafer to the top layer of the already fabricated bottom layer transistor to create a top layer transistor, thus vertically stacking the two transistors. However, this approach currently faces the following technical challenges: (1) fabrication of a high-quality active layer for the top layer transistor; (2) thinning and defect control of the bonding wafer for the top layer transistor; and (3) alignment errors exist between the top and bottom layer transistors, requiring extremely high photolithography precision.

[0026] The common technical challenges faced by the two schemes mentioned above include: (1) the thermal stability of the bottom device when fabricating the top device; (2) the performance of the top device under low thermal budget; and (3) the metal interconnection of transistors between the top and bottom layers.

[0027] To address the technical issues of the two aforementioned schemes, a flip-chip scheme for achieving self-aligned stacked transistors is proposed. This scheme forms the active regions of homogeneous transistors in the upper and lower layers through etching, and fabricates stacked transistors on both sides of the wafer through flipping, thus overcoming the shortcomings of the two schemes. This can also be called the "self-aligned flip-chip transistor" scheme.

[0028] However, in the "self-aligned flip-chip transistor" scheme, the stacked transistors fabricated on the same wafer can only be either a split-gate structure or a common-gate structure. This limits design flexibility and further miniaturization of circuit size. Therefore, there is room for optimization in the "self-aligned flip-chip transistor" scheme.

[0029] To address the aforementioned technical problems, this disclosure provides a semiconductor device, an electronic device, a stacked transistor, and a method for fabricating the same, to optimize the fabrication process of the gate structure in the "self-aligned flip-chip transistor" scheme, enabling the simultaneous fabrication of stacked transistors with split-gate structures and stacked transistors with common-gate structures, increasing the flexibility of circuit design, and allowing for further miniaturization of the size of standard circuit units and the overall circuit size.

[0030] In a first aspect, embodiments of this disclosure provide a method for fabricating stacked transistors.

[0031] In some embodiments, the stacked transistor includes a first semiconductor unit and a second semiconductor unit, which are disposed adjacent to each other in a first direction. Each of the first and second semiconductor units includes: a first active structure and a second active structure stacked along a second direction; a first dummy gate structure corresponding to the first active structure; a first source / drain structure corresponding to the first active structure; a second dummy gate structure corresponding to the second active structure; and a second source / drain structure corresponding to the second active structure. A gate isolation layer is formed between the first dummy gate structure and the second dummy gate structure.

[0032] Understandably, the first semiconductor unit and the second semiconductor unit are used to fabricate the first stacked transistor and the second stacked transistor, respectively. The first stacked transistor and the second stacked transistor are arranged adjacent to each other in a first direction. That is, the first direction can be the arrangement direction of adjacent stacked transistor units, and the second direction can be the stacking direction of the internal structure of each stacked transistor unit. For example, when each stacked transistor unit includes two transistors, the second direction can be the stacking direction of the two transistors. The second direction can be perpendicular to the first direction. In some embodiments, the first direction can be a direction perpendicular to the channel direction.

[0033] Understandably, the first and second active structures described above are stacked along the second direction, and can be used to form different transistors. Similarly, the first dummy gate structure and the first source-drain structure corresponding to the first active structure are used together to form the same transistor. The second dummy gate structure and the second source-drain structure corresponding to the second active structure are used together to form the same transistor.

[0034] It should be noted that the first pseudo-gate structure and the first source-drain structure corresponding to the first active structure refer to the structures adjacent to the first active structure in the first direction or a third direction upward. The second pseudo-gate structure and the second source-drain structure corresponding to the second active structure refer to the structures adjacent to the second active structure in the first direction or a third direction upward. The third direction can be perpendicular to the second direction or the first direction.

[0035] In some embodiments, the gate isolation layer between the first dummy gate structure and the second dummy gate structure corresponds to the junction of the first active structure and the second active structure. The gate isolation layer is used to isolate the gate structures of transistors located on both sides of the gate isolation layer in a second direction.

[0036] Figure 1 is a schematic flowchart illustrating a method for fabricating a stacked transistor according to an embodiment of the present disclosure. Referring to Figure 1, after obtaining the first semiconductor unit and the second semiconductor unit described above, the method for fabricating the stacked transistor may include:

[0037] Step S101: Remove the second dummy gate structure to expose the second active structure and the gate isolation layer;

[0038] Step S102: Coat photoresist over the second active structure and gate isolation layer in the first semiconductor unit, and remove at least the gate isolation layer in the second semiconductor unit by etching process;

[0039] Step S103: Sequentially remove the first dummy gate structure and photoresist to expose the first active structure, gate isolation layer and second active structure in the first semiconductor unit, as well as the first active structure and second active structure in the second semiconductor unit;

[0040] Step S104: Based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, a first gate structure and a second gate structure are formed, and simultaneously based on the first active structure and the second active structure in the second semiconductor unit, a third gate structure and a fourth gate structure are formed.

[0041] In this structure, the gate isolation structure in the first semiconductor structure is located between the first gate structure and the second gate structure, and the third gate structure and the fourth gate structure are connected; the first gate structure and the first source-drain structure in the first semiconductor structure form a first transistor, the second gate structure and the second source-drain structure in the first semiconductor structure form a second transistor, the third gate structure and the first source-drain structure in the second semiconductor structure form a third transistor, and the fourth gate structure and the second source-drain structure in the second semiconductor structure form a fourth transistor; the first transistor and the second transistor form a first stacked transistor, and the third transistor and the fourth transistor form a second stacked transistor.

[0042] It should be noted that the steps shown in Figure 1 are not exclusive, and other steps can be performed before, after, or between any of the steps shown in the operation; the order of the steps shown in Figure 1 can be adjusted according to actual needs.

[0043] It should be noted that, for ease of explanation, the source-drain structure mentioned in the embodiments of this disclosure is an abbreviation, referring to the source structure and / or drain structure. Furthermore, the term "source-drain" in structures such as source-drain metals and source-drain grooves is also an abbreviation for "source and / or drain".

[0044] It is understood that, through the above-described fabrication process, the gate isolation layer in the first semiconductor unit can be retained, allowing the first gate structure and the second gate structure in the subsequently fabricated first stacked transistor to be separated by the gate isolation layer, thereby forming a split-gate structure. Conversely, through the above-described fabrication process, the gate isolation layer in the second semiconductor unit can be removed, allowing the third and fourth gate structures in the subsequently fabricated second stacked transistor to be connected, thereby forming a common-gate structure. Furthermore, the first and second semiconductor units are arranged adjacent to each other in the first direction, which meets the requirements of standard circuit logic units. Therefore, the embodiments of this disclosure achieve the simultaneous fabrication of stacked transistors with split-gate structures and stacked transistors with common-gate structures, increasing the flexibility of circuit design and allowing for further miniaturization of the size of standard circuit units and the overall circuit size.

[0045] The steps described above will be explained in further detail below.

[0046] In some embodiments, during the fabrication of the stacked transistor, a first semiconductor unit and a second semiconductor unit may first be formed. Subsequently, based on obtaining the first semiconductor unit and the second semiconductor unit, steps S101 to S104 described above are performed.

[0047] Understandably, both the first and second semiconductor units include a first active structure, a second active structure, a first source-drain structure, a second source-drain structure, a first dummy gate structure, a second dummy gate structure, and a gate isolation layer. The first source-drain structure is formed based on the first active structure, and the first dummy gate structure encloses the first active structure; the second source-drain structure is formed based on the second active structure, and the second dummy gate structure encloses the second active structure. The gate isolation layer is located between the first and second dummy gate structures.

[0048] Understandably, both the first and second semiconductor units can be fabricated using standard stacked transistor fabrication processes. For example, the first and second semiconductor units can be fabricated using a "self-aligned flip-chip stacked transistor" process.

[0049] In some embodiments, forming a first semiconductor unit and a second semiconductor unit includes: forming a first active structure and a second active structure on a semiconductor substrate, wherein the second active structure is closer to the semiconductor substrate than the first active structure; sequentially forming a second dummy gate structure, a gate isolation layer, and a first dummy gate structure on the semiconductor substrate; sequentially forming a first source / drain structure and a first interlayer dielectric layer based on the first active structure; forming a first carrier wafer on the first dummy gate structure and the first interlayer dielectric layer; flipping and removing the semiconductor substrate; and sequentially forming a second source / drain structure and a second interlayer dielectric layer based on the second active structure.

[0050] Understandably, after forming the first and second active structures on the semiconductor substrate, a first and second dummy gate structure can be fabricated using a post-gate process. A gate isolation layer can also be formed between the first and second dummy gate structures. After fabricating the first and second dummy gate structures, a first source / drain structure and a first interlayer dielectric layer encapsulating the first source / drain structure can be formed based on the first active structure (the active structure away from the semiconductor substrate). A first carrier wafer is then connected to the first dummy gate structure and the first interlayer dielectric layer. The first carrier wafer is flipped so that the semiconductor substrate is positioned at the top in the fabrication direction (or the second direction) to facilitate subsequent fabrication processes. After the semiconductor substrate is positioned at the top, it can be removed to expose the second active structure, and the second source / drain structure and the second interlayer dielectric layer encapsulating the second source / drain structure can be formed based on the second active structure. Thus, the first semiconductor unit and the second semiconductor unit are obtained.

[0051] In some embodiments, forming a first active structure and a second active structure on a semiconductor substrate includes: forming a stacked structure on the semiconductor substrate and etching the stacked structure to form the first active structure and the second active structure in one step.

[0052] In one embodiment, the stacked structure can vary depending on the type of transistors in the stacked transistors. In one embodiment, when the transistors in the stacked transistors are fin field-effect transistors (FinFETs), the stacked structure can be formed by depositing a single semiconductor material; in another embodiment, when the transistors in the stacked transistors are gate-all-around field-effect transistors (GAAFETs), the stacked structure can be formed by alternating deposition of multiple semiconductor materials.

[0053] In one example, in a fully all-around gate field-effect transistor, the stacked structure can be formed by alternating deposition of silicon and silicon-germanium. Silicon is used to form the channel layer in the transistor, and silicon-germanium is used to form the support layer in the transistor.

[0054] In some embodiments, forming a first active structure and a second active structure on a semiconductor substrate includes: forming an initial barrier layer and a stacked structure on the semiconductor substrate, and sequentially etching the stacked structure and the initial barrier layer to form the first active structure, the second active structure, and the barrier layer in one step. The barrier layer is formed from the initial barrier layer and is located on the side of the second source / drain structure away from the first active structure.

[0055] In one embodiment, the initial barrier layer may be formed by depositing a material with a predetermined hardness. In one example, the first material layer may be silicon-germanium.

[0056] In some embodiments, forming a first active structure and a second active structure on a semiconductor substrate includes: forming a first stacked structure, an initial first sacrificial layer, a second stacked structure, and an initial second sacrificial layer on the semiconductor substrate, and sequentially etching the first stacked structure, the initial first sacrificial layer, the second stacked structure, and the initial second sacrificial layer to form the first active structure, the first sacrificial layer, the second active structure, and the second sacrificial layer in one step. Here, the first sacrificial layer is used to isolate the first active structure and the second active structure. The structures of the first stacked structure and the second stacked structure can be referred to the stacked structure described above, and will not be repeated here for the sake of brevity. The first stacked structure is used to form the first active structure, and the second stacked structure is used to form the second active structure.

[0057] In one embodiment, the first sacrificial layer can be removed in a subsequent fabrication step. An insulating material can be deposited at the site where the first sacrificial layer is removed to form an isolation structure, thereby achieving electrical isolation between the upper and lower transistor layers. In one example, the first sacrificial layer can be formed by silicon-germanium deposition. Here, the percentage of germanium atoms in the silicon-germanium forming the first sacrificial layer differs from the percentage of germanium atoms in the silicon-germanium forming the stacked structure.

[0058] In one embodiment, the second sacrificial layer can be removed in a subsequent fabrication step. A gate structure can then be deposited at the location where the second sacrificial layer is removed, thereby achieving a full-around gate structure. In one example, the first sacrificial layer can be formed by silicon-germanium deposition.

[0059] In some embodiments, when the first semiconductor cell and the second semiconductor cell have a barrier layer, after forming the first active structure and the second active structure, an oxide material can be deposited on the semiconductor substrate to form an initial shallow trench isolation (STI) structure, and the initial shallow trench isolation structure can be etched back to form a shallow trench isolation structure. Here, the shallow trench isolation structure encloses the barrier layer, and the second active structure and the first active structure are exposed outside the shallow trench isolation structure.

[0060] In one embodiment, the oxide material forming the shallow trench isolation structure can be: silicon-based oxide (SiO2). x (where x is the number of oxygen atoms), for example, silicon dioxide (SiO2).

[0061] In some embodiments, after forming the shallow trench isolation structure, dummy gate material and isolation material can be deposited in the gate regions of the stacked transistors (the gate regions corresponding to the first semiconductor unit and the second semiconductor unit) to form a first dummy gate structure, a gate isolation layer, and a second dummy gate structure. Here, the first dummy gate structure and the second dummy gate structure are formed of dummy gate material, and the gate isolation layer is formed of isolation material. In some embodiments, after forming the first dummy gate structure and the second dummy gate structure, sidewall material can also be deposited on the semiconductor substrate to form dummy gate sidewalls on the side surfaces of the dummy gate structure, the surfaces (top surface and side surface) of the first active structure, and the surfaces (side surface) of the second active structure.

[0062] In one embodiment, the dummy gate material can be polycrystalline silicon, amorphous silicon, or other similar materials. In another embodiment, the isolation material can be an insulating material. The sidewall material can also be an insulating material. In embodiments of this disclosure, the insulating material is, for example, silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or other similar materials.

[0063] In some embodiments, when a first sacrificial layer is formed between the first active structure and the second active structure, the dummy gate sidewall also covers the surface (side surface) of the first sacrificial layer when the dummy gate sidewall is formed. After forming the dummy gate sidewall, the dummy gate sidewall on the surfaces of the first active structure and the first sacrificial layer can be removed to expose the first active structure and the first sacrificial layer. In some embodiments, after exposing the first active structure and the first sacrificial layer, the first active structure in the source / drain region of the stacked transistor can be removed, and the first sacrificial layer in the source / drain region and the gate region can be removed. In some embodiments, after removing the first sacrificial layer, a gap is formed between the first active structure and the second active structure in the gate region. At this time, insulating material can be deposited in the gap to form an isolation structure.

[0064] It is understandable that when removing the first active structure in the source-drain region, the first pseudo-gate structure can be used as a hard mask to etch the first active structure.

[0065] In some embodiments, after forming the isolation structure, the support layer in the first active structure within the gate region (formed by the support layer in the stacked structure) can be laterally etched to form the internal sidewall (also understood as the first dummy gate sidewall) of the front transistor (composed of the first transistor and the third transistor) in the stacked transistor. In some embodiments, after forming the first dummy gate sidewall, the second active structure in the source / drain region can be removed to expose the semiconductor substrate. Subsequently, an insulating material is deposited in the source / drain region to form a filling structure. Here, the height of the filling structure is greater than the height of the second active structure but less than the height of the first active structure.

[0066] In one embodiment, laterally etching a support layer in a first active structure within a gate region to form an internal sidewall of a front-side transistor in a stacked transistor includes: laterally etching a support layer in a first active structure within a gate region to form a sidewall trench, and depositing sidewall material within the sidewall trench to form an internal sidewall of a front-side transistor in a stacked transistor.

[0067] In some embodiments, after forming the fill structure, an insulating material may be deposited on the fill structure to form a source-drain isolation structure. Here, the source-drain isolation structure is used to electrically isolate the source-drain structure in the front-side transistor and the source-drain structure in the back-side transistor. In some embodiments, after forming the source-drain isolation structure, a first source-drain structure may be epitaxially grown in the source-drain region based on the channel layer (formed by the channel layer in the stacked structure) in the first active structure in the gate region. In some embodiments, after forming the first source-drain structure, a dielectric material may be deposited on the first active structure to form a first interlayer dielectric layer encapsulating the first source-drain structure.

[0068] In one embodiment, the dielectric material forming the first interlayer dielectric layer may be a material such as silicon carbide (SiCN) or silicon nitride (Si3N4).

[0069] In some embodiments, after forming the first interlayer dielectric layer, an insulating material can be deposited on the first dummy gate structure and the first interlayer dielectric layer to form a first insulating layer, and the first insulating layer is bonded to a first carrier wafer. Subsequently, the first carrier wafer is flipped to change the fabrication positions of the first active structure and the second active structure. In some embodiments, after the first carrier wafer is flipped, the semiconductor substrate can be removed to expose the second active structure.

[0070] In some embodiments, when forming a shallow trench isolation structure having a barrier layer and encapsulating the barrier layer, removing the semiconductor substrate can expose the shallow trench isolation structure and the filling structure. The shallow trench isolation structure can then be removed, and a dummy gate material can be deposited at the location where the shallow trench isolation structure was removed, such that the height of the second dummy gate structure is equal to the height of the filling structure.

[0071] In some embodiments, after removing the semiconductor substrate, the filling structure in the source / drain region can be removed to expose the second active structure in the source / drain region. Subsequently, the support layer in the second active structure in the gate region can be laterally etched to form the internal sidewall of the back transistor in the stacked transistor (also understood as the second pseudo-gate sidewall). In some embodiments, the second source / drain structure can be epitaxially grown in the source / drain region based on the channel layer in the second active structure in the gate region on top of the source / drain isolation structure. In some embodiments, after forming the second source / drain structure, a dielectric material can be deposited on the second active structure to form a second interlayer dielectric layer encapsulating the second source / drain structure.

[0072] Thus, the first semiconductor unit and the second semiconductor unit are formed.

[0073] In step S101, the second pseudo-gate structure is removed to expose the second active structure and the gate isolation layer.

[0074] Understandably, after obtaining the first semiconductor unit and the second semiconductor unit, the first pseudo-gate structure is usually located on the lower layer and the second pseudo-gate structure is usually located on the upper layer. In order to facilitate the fabrication of stacked transistors, the second pseudo-gate structure can be removed to expose the second active structure corresponding to the second pseudo-gate structure, as well as the gate isolation layer located between the first pseudo-gate structure and the second pseudo-gate structure.

[0075] In some embodiments, when a barrier layer is formed in the first semiconductor unit and the second semiconductor unit, the second pseudo-gate structure can be removed by using the barrier layer as a hard mask and employing an etching process.

[0076] In step S102, photoresist is coated on the second active structure and gate isolation layer in the first semiconductor unit, and at least the gate isolation layer in the second semiconductor unit is removed by etching process.

[0077] Understandably, after exposing the second active structure and the gate isolation layer, photoresist can be coated over the second active structure and the gate isolation layer in the gate region of the first semiconductor unit. Simultaneously, to protect the structures in the source / drain regions (e.g., the second interlayer dielectric layer), photoresist can also be coated over the structures in the source / drain regions of both the first and second semiconductor units. Since the second active structure and the gate isolation layer in the gate region of the second semiconductor unit are exposed outside the photoresist, the gate isolation layer in the second semiconductor unit can be at least removed by a photolithography-etching process.

[0078] In some embodiments, when a barrier layer is formed in the second semiconductor unit, removing at least the gate isolation layer in the second semiconductor unit by photolithography-etching process includes: using the barrier layer as a mask, removing the gate isolation layer in the second semiconductor unit by anisotropic etching process; and removing a first portion of the first dummy gate structure in the second semiconductor unit by anisotropic etching process or isotropic etching process, wherein the first portion corresponds to the gate isolation layer in the second semiconductor unit.

[0079] Understandably, when a barrier layer is formed in the second semiconductor cell, the barrier layer can protect the second active structure in the second semiconductor cell from damage when the gate isolation layer is removed by the etching process.

[0080] Understandably, embodiments of this disclosure can use a barrier layer as a mask to sequentially etch the gate isolation layer in the second semiconductor unit and a first portion of the first dummy gate structure located below the gate isolation layer using an anisotropic etching process. Alternatively, embodiments of this disclosure can use a barrier layer as a mask to etch the gate isolation layer in the second semiconductor unit using anisotropic etching, and then remove the first portion of the first dummy gate structure located below the gate isolation layer using an isotropic etching process.

[0081] Step S103: Sequentially remove the first dummy gate structure and photoresist to expose the first active structure, gate isolation layer and second active structure in the first semiconductor unit, as well as the first active structure and second active structure in the second semiconductor unit.

[0082] Understandably, after photolithography removes the gate isolation layer in the second semiconductor unit, the first dummy gate structure and photoresist can be removed sequentially to open the gate regions of the first and second semiconductor units, exposing the active structures within the gate regions. Here, since the first semiconductor unit includes a gate isolation layer, removing the first dummy gate structure and photoresist exposes the first active structure, the gate isolation layer, and the second active structure in the first semiconductor unit; since the gate isolation layer in the second semiconductor unit is removed by photolithography in step S102, removing the first dummy gate structure and photoresist exposes the first active structure and the second active structure in the second semiconductor unit.

[0083] In some embodiments, the first dummy gate structure and photoresist are removed sequentially, including: removing the first dummy gate structure by an etching process, followed by removing the photoresist.

[0084] In some embodiments, the first dummy gate structure and photoresist are removed sequentially, including: removing a second portion of the first dummy gate structure in the second semiconductor unit and the first dummy gate structure in the first semiconductor unit by an isotropic etching process, wherein the second portion and the first portion constitute the first dummy gate structure in the second semiconductor unit; and removing the photoresist.

[0085] Understandably, in step S102, the first portion of the first dummy gate structure in the second semiconductor unit can be removed. Subsequently, an isotropic etching process can be used to remove the second portion of the first dummy gate structure in the second semiconductor unit and the first dummy gate structure in the first semiconductor unit, thereby completely removing the first dummy gate structure. Then, the photoresist is removed to complete the opening of the gate region.

[0086] Step S104: Based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, a first gate structure and a second gate structure are formed, and simultaneously based on the first active structure and the second active structure in the second semiconductor unit, a third gate structure and a fourth gate structure are formed.

[0087] Understandably, after the active structure of the gate region is exposed, the same fabrication process can be used to form the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure.

[0088] It is understood that, using standard semiconductor fabrication processes, a first gate structure can be fabricated based on a first active structure in a first semiconductor unit, a second gate structure can be fabricated based on a second active structure in a first semiconductor unit, a third gate structure can be fabricated based on a first active structure in a second semiconductor unit, and a fourth gate structure can be fabricated based on a second active structure in a second semiconductor unit. Here, the standard semiconductor fabrication process can be selected according to actual needs, and this disclosure does not limit it.

[0089] In one embodiment, the gate isolation structure in the first semiconductor structure is located between the first gate structure and the second gate structure, forming a split-gate structure; the third gate structure and the fourth gate structure are connected, forming a common-gate structure. The first gate structure and the first source-drain structure in the first semiconductor structure form a first transistor; the second gate structure and the second source-drain structure in the first semiconductor structure form a second transistor; the third gate structure and the first source-drain structure in the second semiconductor structure form a third transistor; and the fourth gate structure and the second source-drain structure in the second semiconductor structure form a fourth transistor. The first transistor and the second transistor form a first stacked transistor, and the third transistor and the fourth transistor form a second stacked transistor. Therefore, in this embodiment, a first stacked transistor with a split-gate structure and a second stacked transistor with a common-gate structure can be formed simultaneously.

[0090] In some embodiments, step S104 may include: depositing dielectric material on the first active structure, gate isolation layer and second active structure in the first semiconductor cell, and the first active structure and second active structure in the second semiconductor cell to form a gate dielectric layer; forming a second gate structure and a fourth gate structure based on the second active structure covered by the gate dielectric layer; and forming a first gate structure and a third gate structure based on the first active structure covered by the gate dielectric layer.

[0091] Understandably, in the process of fabricating the gate structures in the first and second stacked transistors, a dielectric material can first be deposited on the active structure within the gate region to form a gate dielectric layer. Subsequently, a second gate structure is formed based on the second active structure covered by the gate dielectric layer in the first semiconductor unit, and a fourth gate structure is formed based on the second active structure covered by the gate dielectric layer in the second semiconductor unit. Finally, a first gate structure is formed based on the first active structure covered by the gate dielectric layer in the first semiconductor unit, and a third gate structure is formed based on the first active structure covered by the gate dielectric layer in the second semiconductor unit.

[0092] In some embodiments, the dielectric material forming the gate dielectric layer can be set according to actual needs, and this disclosure does not limit this. For example, the gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. In one example, the first gate dielectric layer may include: a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0093] In one embodiment, the first active structure and the second active structure include channel layers and support layers alternately stacked along a second direction. Step S104 may include: removing the support layers in the first active structure and the second active structure to retain the first channel layer in the first active structure and the second channel layer in the second active structure. A dielectric material is deposited over the first channel layer, the gate isolation layer, and the second channel layer in the first semiconductor cell, and over the first channel layer and the second channel layer in the second semiconductor cell to form a gate dielectric layer. Subsequently, a second gate structure is formed based on the second channel layer covered by the gate dielectric layer in the first semiconductor cell, and a fourth gate structure is formed based on the second channel layer covered by the gate dielectric layer in the second semiconductor cell. Finally, a first gate structure is formed based on the first channel layer covered by the gate dielectric layer in the first semiconductor cell, and a third gate structure is formed based on the first channel layer covered by the gate dielectric layer in the second semiconductor cell.

[0094] It is understood that in the embodiments of this disclosure, forming the gate dielectric layer of all transistors in the stacked transistors through the same process can reduce the number of gate structure fabrication steps, simplify the fabrication process, and reduce the fabrication difficulty.

[0095] In some embodiments, forming a second gate structure and a fourth gate structure based on a second active structure covered by a gate dielectric layer includes: depositing semiconductor material on a first wafer to form a gate-filled structure. Here, the gate-filled structure encloses the first active structure in the first semiconductor cell, and the second active structure and gate isolation layer in the first semiconductor cell are exposed outside the gate-filled structure; the gate-filled structure encloses the first active structure in the second semiconductor cell, and the second active structure in the second semiconductor cell is exposed outside the gate-filled structure. A gate metal material is deposited on the gate isolation layer in the first semiconductor cell and the initial gate-filled structure in the second semiconductor cell to form the second gate structure and the fourth gate structure, respectively, wherein the second gate structure is connected to the gate isolation layer in the first semiconductor cell.

[0096] Understandably, the second and fourth gate structures are back-side gate structures. During the formation of the back-side gate structure, semiconductor material is first deposited on the first wafer to form an initial gate-filled structure, and then the initial gate-filled structure is etched back to form the final gate-filled structure. Here, the gate-filled structure at least covers the first active structure, exposing the second active structure. Subsequently, gate metal material is deposited on the gate-filled structure, simultaneously forming both the second and fourth gate structures.

[0097] In some embodiments, the gate metal material forming the gate structure can be set according to actual needs, and this disclosure does not limit this.

[0098] Understandably, since the gate isolation layer in the first semiconductor cell is retained, the positions of the gate filling structure in the first and second semiconductor cells can be different. For example, the gate filling structure can be located between the gate isolation layer and the first wafer in the first semiconductor cell. The upper surface of the gate filling structure can be located at the junction of the first and second active structures in the second semiconductor cell.

[0099] In one embodiment, an isolation structure is formed between the first active structure and the second active structure, and the upper surface of the gate filling structure may correspond to the isolation structure.

[0100] Understandably, the gate-fill structure can protect the first active structure during the formation of the second and fourth gate structures, thereby reducing device failure rate. In one example, the material forming the gate-fill structure can be amorphous silicon.

[0101] It should be noted that the first carrier wafer here is the carrier wafer connected to the first interlayer dielectric layer during the formation of the first semiconductor unit and the second semiconductor unit. Since the second active structure in the first semiconductor unit and the first active structure in the second semiconductor unit are on top and the first active structure is on the bottom, the first carrier wafer can be located at the bottom to support other structures, which facilitates the fabrication of stacked transistors.

[0102] In some embodiments, after forming a second gate structure and a fourth gate structure based on a second active structure covered with a gate dielectric layer, the method further includes: etching the second gate structure and the fourth gate structure using a single diffusion region cutting process to form a back isolation groove, wherein the front isolation groove is located at least between the second gate structure and the fourth gate structure; and depositing an insulating material in the back isolation groove to form a back gate isolation structure.

[0103] Understandably, after forming the second and fourth gate structures, an inter-cell isolation structure can also be formed. By employing a single-diffusion region cutting process to etch the second and fourth gate structures, a back-side isolation groove can be formed at least between the second and fourth gate structures. The back-side isolation groove is located at the junction of the second and fourth gate structures in the first direction, thereby forming a back-side gate isolation structure for electrically isolating the second and fourth gate structures after depositing insulating material in the back-side isolation groove. In one embodiment, by employing a single-diffusion region cutting process, the active region at the junction of adjacent cells in the first direction (the junction of the second and fourth transistors) can be etched to form the aforementioned back-side isolation groove at least between the second gate structure of the second transistor and the fourth gate structure of the fourth transistor.

[0104] In one embodiment, a single-diffusion region cutting process is used to etch the second gate structure and the fourth gate structure, forming back isolation grooves at both ends of the second gate structure and the fourth gate structure. Here, the two ends of the second gate structure refer to the two ends of the second gate structure in the first direction. The two ends of the fourth gate structure refer to the two ends of the fourth gate structure in the first direction. In one embodiment, by using a single-diffusion region cutting process, the active regions at the junctions of adjacent cells in the first direction (including the junctions of the second transistor and the fourth transistor, the junctions of the second transistor and other transistors, and the junctions of the fourth transistor and other transistors) can be etched to form the aforementioned back isolation grooves at both ends of the second transistor and the fourth transistor. Here, the two ends of the second transistor refer to the two ends of the second transistor in the first direction. The two ends of the fourth transistor refer to the two ends of the fourth transistor in the first direction.

[0105] In some embodiments, after forming a second gate structure and a fourth gate structure based on a second active structure covered with a gate dielectric layer, the method further includes: forming a back source / drain metal over the second source / drain structure; forming a back metal interconnect layer over the second gate structure, the fourth gate structure, and the back source / drain metal; bonding the back metal interconnect layer to a second carrier wafer; and flipping and removing the first carrier wafer to expose the gate fill structure.

[0106] Understandably, after forming the second and fourth gate structures, a second interlayer dielectric layer can be etched to form back-side source / drain metal vias, and metal material can be deposited within these vias to form the back-side source / drain metal. Subsequently, dielectric material is deposited on the second gate structure, the fourth gate structure, and the back-side source / drain metal to form a back-side dielectric layer. On top of this back-side dielectric layer, standard back-end semiconductor fabrication processes (such as inter-interconnect dielectric deposition, metal line formation, and lead-out pad formation) are used to fabricate a back-side metal interconnect layer. After forming the back-side metal interconnect layer, an insulating material can be deposited on it to form a second insulating layer, which is then bonded to a second carrier wafer. After bonding, the second carrier wafer is flipped so that the first carrier wafer is on top, and then the first carrier wafer is removed to expose the gate fill structure.

[0107] In this embodiment, after fabricating the second gate structure and the fourth gate structure, a back metal interconnect layer is fabricated. The back metal interconnect layer electrically connects the second source / drain structure, the second gate structure, and the fourth gate structure, thereby completing the fabrication of the back-side transistor.

[0108] In some embodiments, after forming a second gate structure and a fourth gate structure based on a second active structure covered by a gate dielectric layer, the method further includes: forming a second carrier wafer on the second gate structure, the fourth gate structure, and the second interlayer dielectric layer; and washing and removing the first carrier wafer to expose the gate filling structure.

[0109] Understandably, after forming the second gate structure, an insulating material can be deposited on the second gate structure, the fourth gate structure, and the second interlayer dielectric layer to form a second insulating layer, and then the second insulating layer is bonded to the second carrier wafer. After bonding, the second carrier wafer is flipped so that the first carrier wafer is on top, and then the first carrier wafer is removed to expose the gate fill structure.

[0110] In this embodiment, after the second gate structure and the fourth gate structure are formed, the back metal interconnect layer is not formed first, but the front transistor is formed first. This allows for the use of a higher fabrication temperature during the formation of the front transistor, thereby improving the thermal budget during the fabrication process.

[0111] In some embodiments, forming a first gate structure and a third gate structure based on a first active structure covered with a gate dielectric layer includes: removing a gate fill structure to expose a gate isolation layer and a fourth gate structure in a first semiconductor cell; depositing a gate metal material on the exposed gate isolation layer and fourth gate structure in the first semiconductor cell to form the first gate structure and the third gate structure, wherein the first gate structure is connected to the gate isolation layer in the first semiconductor cell.

[0112] Understandably, the first and third gate structures are front-side gate structures. During the formation of the front-side gate structure, the gate fill structure protecting the first active structure can first be removed to expose the gate isolation layer in the first semiconductor unit and the fourth gate structure in the second semiconductor unit, respectively. Subsequently, gate metal material is deposited on the exposed gate isolation layer in the first semiconductor unit and the fourth gate structure in the first semiconductor unit, thus simultaneously forming the first and third gate structures.

[0113] In some embodiments, a first gate structure and a second gate structure are stacked, with a gate isolation layer between the first gate structure and the second gate structure, thereby forming a split-gate structure. A third gate structure and a fourth gate structure are stacked, and the third gate structure and the fourth gate structure are connected, thereby forming a common-gate structure.

[0114] In some embodiments, after forming a first gate structure and a third gate structure based on a first active structure covered with a gate dielectric layer, the method further includes: etching the first gate structure and the third gate structure using a single diffusion region cut-off process to form a front isolation groove, wherein the front isolation groove is located at least between the first gate structure and the third gate structure; and depositing an insulating material in the front isolation groove to form a front gate isolation structure.

[0115] Understandably, after forming the first gate structure and the third gate structure, an inter-cell isolation structure can also be formed. By employing a single-diffusion region cutting process to etch the first gate structure and the third gate structure, a front isolation groove can be formed at least between the first gate structure and the third gate structure. The front isolation groove is located at the junction of the first gate structure and the third gate structure in the first direction, thereby forming a front gate isolation structure for electrically isolating the first gate structure and the third gate structure after depositing insulating material in the front isolation groove. In one embodiment, by employing a single-diffusion region cutting process, the active region at the junction of adjacent cells in the first direction (the junction of the first transistor and the third transistor) can be etched to form the aforementioned back isolation groove at least between the first gate structure of the first transistor and the third gate structure of the third transistor.

[0116] In one embodiment, a single-diffusion region cutting process is used to etch the first gate structure and the third gate structure, forming front isolation grooves at both ends of the first gate structure and at both ends of the third gate structure. Here, the two ends of the first gate structure refer to the two ends of the first gate structure in the first direction. The two ends of the third gate structure refer to the two ends of the third gate structure in the first direction. In one embodiment, by using a single-diffusion region cutting process, the active regions at the junctions of adjacent cells in the first direction (including the junctions of the first transistor and the third transistor, the junctions of the first transistor and other transistors, and the junctions of the third transistor and other transistors) can be etched to form the aforementioned back isolation grooves at both ends of the first transistor and the third transistor. Here, the two ends of the first transistor refer to the two ends of the first transistor in the first direction. The two ends of the fourth transistor refer to the two ends of the fourth transistor in the first direction.

[0117] In some embodiments, after forming a first gate structure and a third gate structure based on a first active structure covered with a gate dielectric layer, the method further includes: forming a front-side source / drain metal on the first source / drain structure; and forming a front-side metal interconnect layer on the first gate structure, the third gate structure, and the front-side source / drain metal.

[0118] Understandably, after forming the first gate structure and the third gate structure, the first interlayer dielectric layer can be etched to form front-side source / drain metal vias, and metal material can be deposited within the front-side source / drain metal vias to form front-side source / drain metal. Subsequently, dielectric material is deposited on the first gate structure, the third gate structure, and the front-side source / drain metal to form a front-side dielectric layer, and a front-side metal interconnect layer is formed on the front-side dielectric layer using standard back-end semiconductor fabrication processes.

[0119] In this embodiment, after fabricating the first gate structure and the third gate structure, a front-side metal interconnect layer is formed. The front-side metal interconnect layer electrically connects the first source / drain structure, the first gate structure, and the third gate structure, thereby completing the fabrication of the front-side transistor. Thus, with the back-side transistor and the front-side transistor fabricated, the fabrication of the first stacked transistor and the second stacked transistor is completed.

[0120] In some embodiments, when no back metal interconnect layer is formed, after forming the front metal interconnect layer, the method further includes: bonding the front metal interconnect layer and the third carrier wafer; flipping and removing the second carrier wafer to expose the second gate structure, the fourth gate structure and the second interlayer dielectric layer; forming a back source / drain metal over the second source / drain structure; and forming a back metal interconnect layer over the second gate structure, the fourth gate structure and the back source / drain metal.

[0121] Understandably, if the second and fourth gate structures are formed without forming a back metal interconnect layer, the back metal interconnect layer can be formed after the front metal interconnect layer. An insulating material is deposited on the front metal interconnect layer to form a third insulating layer, which is then bonded to a third carrier wafer. After bonding, the third carrier wafer is flipped so that the second carrier wafer is on top, and then the second carrier wafer is removed to expose the second gate structure, the fourth gate structure, and the second interlayer dielectric layer. The second interlayer dielectric layer is etched to form a back source / drain metal trench, and metal material is deposited within the back source / drain metal trench to form the back source / drain metal. Dielectric material is deposited on the second gate structure, the fourth gate structure, and the back source / drain metal to form a back dielectric layer. The back metal interconnect layer is then fabricated using standard back-end semiconductor fabrication processes on top of the back dielectric layer.

[0122] In this embodiment, after forming the first gate structure and the third gate structure, a front-side metal interconnect layer is formed, thereby completing the fabrication of the front-side transistor. After forming the front-side transistor, a back-side metal interconnect layer is formed, thereby completing the fabrication of the back-side transistor. Thus, with the back-side transistor and the front-side transistor fabricated, the fabrication of the first stacked transistor and the second stacked transistor is completed.

[0123] In this embodiment, by retaining the gate isolation layer in the first semiconductor unit, the first gate structure and the second gate structure in the subsequently fabricated first stacked transistor can be separated by the gate isolation layer, thereby forming a split-gate structure. Conversely, by removing the gate isolation layer in the second semiconductor unit, the third gate structure and the fourth gate structure in the subsequently fabricated second stacked transistor are connected, thereby forming a common-gate structure. Furthermore, the first semiconductor unit and the second semiconductor unit are arranged adjacent to each other in the first direction, which meets the requirements of standard circuit logic units. Therefore, this embodiment simultaneously fabricates stacked transistors with split-gate structures and stacked transistors with common-gate structures, which not only increases the flexibility of circuit design but also allows for further miniaturization of the size of standard circuit units and the overall circuit size.

[0124] Figure 2 is a top view of a stacked transistor according to an embodiment of the present disclosure. Referring to Figure 2, only the fin structure, gate structure, and source / drain structure of the stacked transistor 10 are shown. Figures 3 to 38 are structural schematic diagrams of a stacked transistor during its fabrication process according to an embodiment of the present disclosure. For ease of understanding, (a) of Figures 3 to 38 shows a cross-sectional view along the dashed line AA' in Figure 2; (b) of Figures 3 to 38 shows a cross-sectional view along the dashed line BB' in Figure 2; and (c) of Figures 3 to 38 shows a cross-sectional view along the dashed line CC' in Figure 2. The fabrication method of the stacked transistor in the present disclosure will now be described using the first embodiment in conjunction with the fabrication process of the stacked transistor shown in Figures 1 to 38.

[0125] In one example, the fabrication process of stacked transistors may include the following steps:

[0126] Step 1: Silicon germanium and silicon are epitaxially grown on semiconductor substrate 20 (formed from silicon) to form an initial stacked structure 21 and an initial barrier layer 22, resulting in the structure shown in Figure 3.

[0127] Understandably, the initial barrier layer 22 is located between the semiconductor substrate 20 and the initial stacked structure 21. Here, the initial stacked structure 21 is formed by alternating deposition of silicon-germanium and silicon. The initial barrier layer 22 is formed of silicon-germanium.

[0128] Step 2: Through photolithography, a stacked structure 23 and a barrier layer 24 are formed by etching in one step, resulting in the structure shown in Figure 4.

[0129] Understandably, in the cross-sectional view along the AA' direction and the cross-sectional view along the BB' direction, portions on both sides of the initial stacked structure 21 are etched to form a stacked structure 23 for fabricating a fully surrounding gate field-effect transistor.

[0130] In some embodiments, the percentage of germanium atoms in the silicon-germanium forming the barrier layer 24 differs from the percentage of germanium atoms in the silicon-germanium forming the stacked structure 23. The barrier layer 24 may have a certain degree of hardness, allowing it to function as an etching barrier layer after wafer fabrication.

[0131] In some embodiments, silicon-germanium forms a support layer in the stacked structure 23, and silicon forms a channel layer in the stacked structure 23. Referring to FIG4, the stacked structure 23 may include a first active structure 29, a first sacrificial layer 30, a second active structure 31, and a second sacrificial layer 32.

[0132] The third step is to deposit an oxide material on the semiconductor substrate 20 and etch the oxide material to a preset height to form a shallow trench isolation structure 25, thus obtaining the structure shown in Figure 5.

[0133] Here, the shallow trench isolation structure 25 encloses the barrier layer 24, and the stacked structure 23 is exposed outside the shallow trench isolation structure 25.

[0134] In the fourth step, polysilicon and isolation material are deposited in the gate region of the stacked transistor to form a first dummy gate structure 26, a gate isolation layer 27, and a second dummy gate structure 28. After the first dummy gate structure 26 and the second dummy gate structure 28 are formed, sidewall material is deposited to form dummy gate sidewalls 33, resulting in the structure shown in Figure 6.

[0135] Here, the first dummy gate structure 26 and the second dummy gate structure 28 are formed of polysilicon, and the gate isolation layer 27 is formed of an isolation material. In one embodiment, the first dummy gate structure 26 and the second dummy gate structure 28 are self-aligned.

[0136] The fifth step is to etch the pseudo-gate sidewall 33 to expose the first active structure 29 and the first sacrificial layer 30, thus obtaining the structure shown in Figure 7.

[0137] Understandably, anisotropic etching can be used to expose the first active structure 29 and the first sacrificial layer 30.

[0138] It should be noted that, as shown in Figure 7, after exposing the first active structure 29 and the first sacrificial layer 30, a portion of the pseudo-gate sidewall 33 is still retained on the sidewall of the first pseudo-gate structure 26 in the CC' direction cross-sectional view. This pseudo-gate sidewall 33 can be used as a hard mask in subsequent fabrication processes.

[0139] Step 6: Remove the first active structure 29 in the source / drain region to obtain the structure shown in Figure 8.

[0140] It is understandable that by using the first pseudo-gate structure 26 and the pseudo-gate sidewall 33 as hard masks, the first active structure 29 located in the source-drain region can be selectively etched.

[0141] The seventh step is to form an isolation structure 34 between the first active structure 29 and the second active structure 31 in the gate region, to obtain the structure shown in FIG9.

[0142] Understandably, the isolation structure 34 is middle dielectric isolation (MDI). In some embodiments, the isolation structure 34 may also be silicon-on-insulator (SOI) isolation.

[0143] In one embodiment, forming the isolation structure 34 may include: selectively removing the first sacrificial layer 30 to isolate the first active structure 29 and the second active structure 31; depositing an insulating material such as silicon nitride and planarizing the isolation structure 34 formed from the silicon nitride material using a chemical-mechanical planarization (CMP) process; and using an anisotropic etching process to remove excess isolation structure 34, retaining the isolation structure 34 between the first active structure 29 and the second active structure 31 within the gate region.

[0144] Step 8: Laterally etch the support layer in the first active structure 29 to a predetermined depth. Deposit insulating materials such as silicon nitride at the locations where the support layer is removed to form the internal sidewalls 35 of the front-side transistors (including the first transistor 11 and the third transistor 13), obtaining the structure shown in Figure 10.

[0145] It is understood that in this embodiment, the stacked transistor 10 is a gate-all-around field-effect transistor, therefore, an internal sidewall 35 needs to be formed. When the stacked transistor 10 is a fin field-effect transistor, a planar field-effect transistor, or a similar transistor, an internal sidewall 35 is not required.

[0146] In the ninth step, an anisotropic etching process is used to etch the second active structure 31 in the source / drain region and the second sacrificial layer 32 at the bottom of the second active structure 31 to form the first deep trench 36, thus obtaining the structure shown in Figure 11.

[0147] Step 10: Anisotropic etching is used to etch the barrier layer 24 and the shallow trench isolation structure 25 located in the source and drain regions to obtain the structure shown in Figure 12.

[0148] Understandably, after anisotropic etching of the barrier layer 24 located in the source / drain regions, the etched barrier layer 24 is formed. The etched barrier layer 24 is located in the gate region, and after wafer flipping, the position of the gate region can be obtained based on the etched barrier layer 24.

[0149] In the eleventh step, insulating material is deposited in the source and drain regions to form a filling structure 37, resulting in the structure shown in Figure 13.

[0150] In one embodiment, the height of the upper surface of the filling structure 37 is lower than the height of the upper surface of the isolation structure 34 but higher than the height of the lower surface of the isolation structure 34.

[0151] Step 12: Deposit insulating material on the filling structure 37 in the source / drain region and etch the insulating material back to the preset height to form the source / drain isolation structure 38, obtaining the structure shown in Figure 14.

[0152] Understandably, the source-drain isolation structure 38 is used for electrical isolation of the first source-drain structure 112 and the second source-drain structure 122.

[0153] In the thirteenth step, based on the first active structure 29 in the gate region, a first source-drain structure 112 is epitaxially formed in the source-drain region to obtain the structure shown in Figure 15.

[0154] Step 14: Deposit dielectric material in the source / drain region to form the first interlayer dielectric layer 113, obtaining the structure shown in Figure 16.

[0155] Step 15: An insulating material is deposited on the first pseudo-gate structure 26 and the first interlayer dielectric layer 113 to form a first insulating layer 39, and the first insulating layer 39 is bonded to the first carrier wafer 40 to obtain the structure shown in FIG17.

[0156] Step 16: Flip the first carrier wafer 40 and remove the semiconductor substrate 20 to obtain the structure shown in Figure 18.

[0157] Here, after removing the semiconductor substrate 20, the barrier layer 24, the shallow trench isolation structure 25, and the filling structure 37 can be exposed.

[0158] Step 17: Remove the shallow trench isolation structure 25 that encapsulates the barrier layer 24 to obtain the structure shown in Figure 19.

[0159] Step 18: Polysilicon is deposited at the location where the shallow trench isolation structure 25 is removed to complete the second pseudo-gate structure 28, resulting in the structure shown in Figure 20.

[0160] Step 19: Remove the filling structure in the source and drain regions to obtain the structure shown in Figure 21.

[0161] Step 20: Laterally etch the support layer in the second active structure 31 to a certain depth. Deposit insulating materials such as silicon nitride at the locations where the support layer is removed to form the internal sidewalls 35 of the back transistors (including the second transistor 12 and the fourth transistor 14), obtaining the structure shown in Figure 22.

[0162] In the twenty-first step, based on the second active structure 31 in the gate region, a second source / drain structure 122 is epitaxially formed in the source / drain region; a dielectric material is deposited in the source / drain region to form a second interlayer dielectric layer 123, thereby obtaining the structure shown in FIG23.

[0163] Understandably, by performing steps one through twenty-one, the first semiconductor unit 41 and the second semiconductor unit 42 in this embodiment of the present disclosure can be obtained, as shown in Figure 23.

[0164] Step 22: Remove the second pseudo-gate structure 28 to obtain the structure shown in Figure 24.

[0165] Step 23: Photoresist 43 is coated in the gate region and source / drain region of the first semiconductor unit 41, and photoresist 43 is coated in the source / drain region of the second semiconductor unit 42 to obtain the structure shown in FIG25.

[0166] In the twenty-fourth step, an anisotropic etching process is used to remove the gate isolation layer 27 in the second semiconductor unit 42 and the first dummy gate structure 26 located below the gate isolation layer 27 to obtain the structure shown in Figure 26.

[0167] Understandably, the first semiconductor unit 41 has a gate isolation layer 27, while the second semiconductor unit 42 does not. Photoresist 43 is used to protect the gate isolation layer 27 in the first semiconductor unit 41 from etching.

[0168] Step 25: Using an isotropic etching process, the first dummy gate structure 26 in the first semiconductor unit 41 and the first dummy gate structure 26 in the second semiconductor unit 42 are removed to obtain the structure shown in Figure 27.

[0169] Step 26: Remove the photoresist 43 coated in the gate region and source / drain region of the first semiconductor unit 41, and the photoresist 43 coated in the source / drain region of the second semiconductor unit 42, to obtain the structure shown in FIG28.

[0170] Understandably, after removing the photoresist, the first active structure 29 and the second active structure 31 in the gate region can be fully exposed.

[0171] Step 27: Deposit dielectric material on the first active structure 29 and the second active structure 31 to form a gate dielectric layer 44, obtaining the structure shown in Figure 29.

[0172] Understandably, the first semiconductor unit 41 has a gate isolation layer 27, and during the deposition of the dielectric material, a gate dielectric layer 44 can also be formed on the gate isolation layer 27.

[0173] Step 28: Deposit polysilicon material in the gate region to form gate filling structure 45, obtaining the structure shown in Figure 30.

[0174] Understandably, the gate filling structure 45 in the first semiconductor unit 41 is located between the gate isolation layer 27 and the first carrier wafer 40. The height of the gate filling structure 45 in the second semiconductor unit 42 is greater than the height of the gate filling structure 45 in the first semiconductor unit 41.

[0175] In some embodiments, an initial gate filling structure is formed by depositing polycrystalline silicon material, and then the initial gate filling structure is etched back to a preset height to form a gate filling structure 45.

[0176] Step 29: Deposit metal material in the gate region to form the second gate structure 124 and the fourth gate structure 144, to obtain the structure shown in Figure 31.

[0177] In the thirtieth step, a single diffusion region cutting process is used to etch the second gate structure 124 and the fourth gate structure 144 to form a back gate isolation groove, and an insulating material is deposited in the back gate isolation groove to form a back gate isolation structure 46, thus obtaining the structure shown in Figure 32.

[0178] Understandably, the back gate isolation structure 46 is used for electrical isolation of the second gate structure 124 and the fourth gate structure 144.

[0179] In the thirty-first step, the second interlayer dielectric layer 123 is etched to form a back-side source / drain metal via, and metal material is deposited within the back-side source / drain metal via to form a second source / drain metal 125; dielectric material is deposited on the second gate structure 124, the fourth gate structure 144, and the second source / drain metal 125 to form a back-side dielectric layer 47. A back-side metal interconnect layer 126 is formed on the back-side dielectric layer 47 to obtain the structure shown in FIG33.

[0180] It should be noted that since the back metal interconnect layer 126 is formed before the front gate structure, the back metal interconnect layer 126 can be made of high-temperature resistant materials in many cases.

[0181] Step 32: An insulating material is deposited on the back metal interconnect layer 126 to form a second insulating layer 48, and the second insulating layer 48 is bonded to the second carrier wafer 49. The second carrier wafer 49 is flipped over, and the first carrier wafer 40 and the first insulating layer 39 are removed to obtain the structure shown in FIG34.

[0182] Here, after removing the first carrier wafer 40 and the first insulating layer 39, the gate filling structure 45 can be exposed.

[0183] Step 33: Remove the gate filling structure 45 to obtain the structure shown in Figure 35.

[0184] Step 34: Deposit metal material in the gate region to form the first gate structure 114 and the third gate structure 134, obtaining the structure shown in Figure 36.

[0185] In some embodiments, when the first gate structure 114 and the third gate structure 134 are in use, the gate dielectric layer and the high-resistivity metal material layer can be etched as needed to reduce parasitic capacitance and resistance.

[0186] In the thirty-fifth step, a single diffusion region cutting process is used to etch the first gate structure 114 and the third gate structure 134 to form a front gate isolation groove, and an insulating material is deposited in the front gate isolation groove to form a front gate isolation structure 50, thus obtaining the structure shown in Figure 37.

[0187] Understandably, the front gate isolation structure 50 is used for electrical isolation between the first gate structure 114 and the third gate structure 134.

[0188] Step 36: The first interlayer dielectric layer 113 is etched to form a front-side source / drain metal via, and metal material is deposited within the front-side source / drain metal via to form a first source / drain metal 115; dielectric material is deposited on the first gate structure 114, the third gate structure 134, and the first source / drain metal 115 to form a front-side dielectric layer 51. A front-side metal interconnect layer 116 is formed on the front-side dielectric layer 51 to obtain the structure shown in FIG38.

[0189] Understandably, the first gate structure 114 and the first source / drain structure 112 and the first interlayer dielectric layer 113 corresponding to the first semiconductor unit 41 constitute the first transistor 11; the second gate structure 124 and the second source / drain structure 122 and the second interlayer dielectric layer 123 corresponding to the first semiconductor unit 41 constitute the first transistor 11; the third gate structure 134 and the first source / drain structure 112 and the first interlayer dielectric layer 113 corresponding to the second semiconductor unit 42 constitute the third transistor 13; and the fourth gate structure 144 and the second source / drain structure 122 and the second interlayer dielectric layer 123 corresponding to the second semiconductor unit 42 constitute the fourth transistor 14. The first transistor 11 and the second transistor 12 constitute the first stacked transistor 101, and the third transistor 13 and the fourth transistor 14 constitute the second stacked transistor 102. The first stacked transistor 101 has a split-gate structure, and the second stacked transistor 102 has a common-gate structure.

[0190] It should be noted that the types of gate structures, source-drain structures, isolation structures, etc., in the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14 are not limited.

[0191] This completes the fabrication of the stacked transistors in the embodiments of this disclosure.

[0192] In this embodiment, a two-wave-wash scheme is adopted, taking into account the fabrication sequence of the stacked transistor device structure and its subsequent interconnect structure, thereby improving the thermal budget of the overall device fabrication process. Based on the two-wave-wash scheme, photolithography patterning is used to simultaneously fabricate stacked transistors with separate gate structures and stacked transistors with common gate structures in two adjacent cells on the same wafer, bringing more flexible design methods and the possibility of further miniaturization of standard circuit cells. At the same time, the process complexity and device failure rate are reduced by integral molding of the gate dielectric layer and deposition of the gate filling structure.

[0193] Figures 39 to 40 are schematic diagrams of the structure of a stacked transistor during the fabrication process according to an embodiment of the present disclosure. For ease of understanding, Figure 39 to 40(a) shows a cross-sectional view along the direction of the dashed line AA' in Figure 2, Figure 39 to 40(b) shows a cross-sectional view along the direction of the dashed line BB' in Figure 2, and Figure 39 to 40(c) shows a cross-sectional view along the direction of the dashed line CC' in Figure 2. The fabrication method of the stacked transistor in the present disclosure will now be described with reference to the fabrication process of the stacked transistor shown in Figures 1 to 40, using a second embodiment.

[0194] The first step is the same as the first to thirtieth steps in the first embodiment above, as shown in Figures 3 to 32. For the sake of brevity, it will not be described again here.

[0195] The second step involves depositing insulating material on the second gate structure 124 and the fourth gate structure 144, based on the structure shown in Figure 32, to form a second insulating layer 48, and bonding the second insulating layer 48 to the second carrier wafer 49. The second carrier wafer 49 is then flipped, and the first carrier wafer 40 and the first insulating layer 39 are removed to expose the gate filling structure 45. After exposing the gate filling structure 45, steps 33 to 36 of the first embodiment are performed until the front-side metal interconnect layer 116 is obtained, resulting in the structure shown in Figure 39.

[0196] Thirdly, an insulating material is deposited on the front metal interconnect layer 116 to form a third insulating layer 52, and the third insulating layer 52 is bonded to the third carrier wafer 53. The third carrier wafer 53 is flipped, and the second carrier wafer 49 and the second insulating layer 48 are removed to expose the second gate structure 124 and the fourth gate structure 144. A dielectric material is deposited on the second gate structure 124, the fourth gate structure 144, and the second source / drain metal 125 to form a back dielectric layer 47. A back metal interconnect layer 126 is formed on the back dielectric layer 47 to obtain the structure shown in FIG40.

[0197] It should be noted that, compared with the two-time flipping scheme, since the metal interconnect layer is fabricated after the gate structure is completed, the front metal interconnect layer 116 and the back metal interconnect layer 126 do not need to be fabricated using high-temperature resistant materials, thus effectively reducing the fabrication cost.

[0198] This completes the fabrication of the stacked transistors in the embodiments of this disclosure.

[0199] In this embodiment, a three-wave-wash scheme is adopted, taking into account the fabrication sequence of the stacked transistor device structure and its subsequent interconnect structure, thereby improving the thermal budget of the overall device fabrication process. Based on the three-wave-wash scheme, photolithography patterning is used to simultaneously fabricate stacked transistors with separate gate structures and stacked transistors with common gate structures in two adjacent cells on the same wafer, bringing more flexible design methods and the possibility of further miniaturization of standard circuit cells. At the same time, the process complexity and device failure rate are reduced by integral molding of the gate dielectric layer and deposition of the gate filling structure.

[0200] Secondly, this disclosure provides a stacked transistor, which can be fabricated using the methods described in one or more embodiments corresponding to FIG1. ​​Referring to FIGS. 38 and 40, the stacked transistor 10 includes: a first stacked transistor 101 and a second stacked transistor 102 disposed adjacent to each other in a first direction. The first stacked transistor 101 includes: a first transistor 11 and a second transistor 12 disposed opposite to each other in a second direction; a gate isolation layer 27 is formed between the first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12, the gate isolation layer 27 being used for electrical isolation between the first gate structure 114 and the second gate structure 124; the second stacked transistor 102 includes: a third transistor 13 and a fourth transistor 14 disposed opposite to each other in the second direction; the third gate structure 134 of the third transistor 13 and the fourth gate structure 144 of the fourth transistor 14 are connected.

[0201] Understandably, the first stacked transistor 101 and the second stacked transistor 102 can be two adjacent transistors, or they can be understood as two adjacent rows of transistors. The gate structure of the upper and lower layers of transistors in the first stacked transistor 101 is a split-gate structure, while the gate structure of the upper and lower layers of transistors in the second stacked transistor 102 is a common-gate structure, thereby increasing the flexibility of circuit design and allowing the standard circuit unit and the overall circuit to be further miniaturized.

[0202] Furthermore, referring to Figure 38 or Figure 40, the first stacked transistor 101 has a gate isolation layer 27 in the middle of the front and back gate structures, while the second stacked transistor 102 does not have a gate isolation layer 27 in the middle of the front and back gate structures.

[0203] In some embodiments, each of the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14 is any one of a fin field-effect transistor, a gate-all-around field-effect transistor, a vertical field-effect transistor (VTFET), a complementary field-effect transistor, a forksheet transistor, and a planar field-effect transistor, and the embodiments of this disclosure are not limited thereto.

[0204] Understandably, the multi-wafer flipping scheme takes into account the fabrication sequence of the stacked transistor device structure and its subsequent interconnect structure, thus improving the overall thermal budget of the device fabrication process. Based on the multi-wafer flipping, photolithography patterning is used to simultaneously fabricate stacked transistors with separate gate structures and stacked transistors with common gate structures in two adjacent cells on the same wafer, bringing more flexible design methods and the possibility of further miniaturization of standard circuit cells. At the same time, the process complexity and device failure rate are reduced by integral molding of the gate dielectric layer and deposition of the gate filling structure.

[0205] Finally, the flip-chip method for realizing top and bottom transistors is compatible with existing mainstream device architectures. It can achieve front and back stacking of planar field-effect transistors, fin field-effect transistors, all-around gate field-effect transistors, fork-plate transistors, and even vertical field-effect transistors without requiring special process development for specific device architectures. This offers high flexibility and strong scalability from the perspective of semiconductor process node iteration. Flip-chip transistors are conceptually very advanced, have significant industrial value, and are highly practical with broad expansion prospects.

[0206] Thirdly, embodiments of this disclosure provide a semiconductor device, including: a stacked transistor as described in the above embodiments. The structure of the stacked transistor can be seen in Figures 38 and 40 above, and will not be described again here.

[0207] Fourthly, embodiments of this disclosure provide an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board. The semiconductor device includes the stacked transistors described above. The structure of the stacked transistors can be seen in Figures 38 and 40 above, and will not be repeated here.

[0208] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0209] The above description is merely a specific implementation of one embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a stacked transistor, the stacked transistor comprising a first semiconductor unit and a second semiconductor unit, the first semiconductor unit and the second semiconductor unit being disposed adjacent to each other in a first direction; Both the first semiconductor unit and the second semiconductor unit include: A first active structure and a second active structure, a first pseudo-gate structure corresponding to the first active structure, a first source-drain structure corresponding to the first active structure, a second pseudo-gate structure corresponding to the second active structure, and a second source-drain structure corresponding to the second active structure are stacked along a second direction; wherein a gate isolation layer is formed between the first pseudo-gate structure and the second pseudo-gate structure. The method includes: Remove the second pseudo-gate structure to expose the second active structure and the gate isolation layer; Photoresist is coated on the second active structure and gate isolation layer in the first semiconductor unit, and at least the gate isolation layer in the second semiconductor unit is removed by an etching process. The first dummy gate structure and the photoresist are removed sequentially to expose the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, as well as the first active structure and the second active structure in the second semiconductor unit. Based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, a first gate structure and a second gate structure are formed, and simultaneously based on the first active structure and the second active structure in the second semiconductor unit, a third gate structure and a fourth gate structure are formed. Wherein, the gate isolation structure in the first semiconductor structure is located between the first gate structure and the second gate structure, and the third gate structure and the fourth gate structure are connected; the first gate structure and the first source-drain structure in the first semiconductor structure form a first transistor, the second gate structure and the second source-drain structure in the first semiconductor structure form a second transistor, the third gate structure and the first source-drain structure in the second semiconductor structure form a third transistor, and the fourth gate structure and the second source-drain structure in the second semiconductor structure form a fourth transistor; the first transistor and the second transistor form a first stacked transistor, and the third transistor and the fourth transistor form a second stacked transistor.

2. The method according to claim 1, wherein, The process of forming a first gate structure and a second gate structure based on the first active structure, the gate isolation layer, and the second active structure in the first semiconductor unit, and simultaneously forming a third gate structure and a fourth gate structure based on the first active structure and the second active structure in the second semiconductor unit, includes: A dielectric material is deposited on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and on the first active structure and the second active structure in the second semiconductor unit to form a gate dielectric layer. Based on the second active structure covered by the gate dielectric layer, the second gate structure and the fourth gate structure are respectively formed; Based on the first active structure covered by the gate dielectric layer, the first gate structure and the third gate structure are respectively formed.

3. The method according to claim 2, wherein, The stacked transistor further includes: a first carrier wafer; both the first semiconductor unit and the second semiconductor unit further include: a first interlayer dielectric layer encapsulating the first source / drain structure; the first interlayer dielectric layer is connected to the first carrier wafer; The second active structure, based on the second active structure covered by the gate dielectric layer, forms the second gate structure and the fourth gate structure, respectively, including: Semiconductor material is deposited on the first carrier wafer to form a gate-filled structure, wherein the gate-filled structure encloses a first active structure in the first semiconductor unit, and a second active structure and a gate isolation layer in the first semiconductor unit are exposed outside the gate-filled structure; the gate-filled structure encloses a first active structure in the second semiconductor unit, and a second active structure in the second semiconductor unit is exposed outside the gate-filled structure. A gate metal material is deposited on the gate isolation layer in the first semiconductor unit and the initial gate filling structure in the second semiconductor unit to form the second gate structure and the fourth gate structure, respectively, wherein the second gate structure is connected to the gate isolation layer in the first semiconductor unit.

4. The method according to claim 3, wherein, After forming the second gate structure and the fourth gate structure based on the second active structure covered by the gate dielectric layer, the method further includes: A back-side source / drain metal is formed on top of the second source / drain structure; A back metal interconnect layer is formed on the second gate structure, the fourth gate structure, and the back source / drain metal; The back metal interconnect layer is bonded to the second carrier wafer; The first carrier wafer is flipped and removed to expose the gate fill structure.

5. The method according to claim 3, wherein, Both the first semiconductor unit and the second semiconductor unit further include: a second interlayer dielectric layer that encapsulates the second source / drain structure; Wherein, after forming the second gate structure and the fourth gate structure respectively based on the second active structure covered by the gate dielectric layer, the method includes: A second carrier wafer is formed on the second gate structure, the fourth gate structure, and the second interlayer dielectric layer; The first carrier wafer is flipped and removed to expose the gate fill structure.

6. The method according to claim 3, wherein, After forming the second gate structure and the fourth gate structure based on the second active structure covered by the gate dielectric layer, the method further includes: A single diffusion region cutting process is used to etch the second gate structure and the fourth gate structure to form a back isolation groove, wherein the back isolation groove is located at least between the second gate structure and the fourth gate structure; An insulating material is deposited within the back isolation groove to form a back gate isolation structure.

7. The method according to any one of claims 3 or 6, wherein, The first active structure, based on the gate dielectric layer, forms the first gate structure and the third gate structure, respectively, including: Remove the gate filling structure to expose the gate isolation layer and the fourth gate structure in the first semiconductor cell, respectively; A gate metal material is deposited on the exposed gate isolation layer and the fourth gate structure in the first semiconductor cell to form the first gate structure and the third gate structure, respectively, wherein the first gate structure is in contact with the gate isolation layer in the first semiconductor cell.

8. The method according to claim 7, wherein, After forming the first gate structure and the third gate structure based on the first active structure covered by the gate dielectric layer, the method further includes: A front-side source / drain metal is formed on top of the first source / drain structure; A front metal interconnect layer is formed on the first gate structure, the third gate structure, and the front source / drain metal.

9. The method according to claim 8, wherein, In the absence of a back metal interconnect layer, after forming the front metal interconnect layer, the method further includes: Bond the front metal interconnect layer to the third carrier wafer; The second carrier wafer is flipped and removed to expose the second gate structure, the fourth gate structure, and the second interlayer dielectric layer; A back-side source / drain metal is formed on top of the second source / drain structure; A back metal interconnect layer is formed on the second gate structure, the fourth gate structure, and the back source / drain metal.

10. The method according to claim 7, wherein, After forming the first gate structure and the third gate structure based on the first active structure covered by the gate dielectric layer, the method further includes: A single diffusion region cutting process is used to etch the first gate structure and the third gate structure to form a front isolation groove, wherein the front isolation groove is located at least between the first gate structure and the third gate structure; An insulating material is deposited within the front isolation groove to form a front gate isolation structure.

11. The method according to claim 1, wherein, Both the first semiconductor unit and the second semiconductor unit further include: a barrier layer, wherein the barrier layer is located on the side of the second source / drain structure away from the first active structure; The etching process, at least removing the gate isolation layer in the second semiconductor unit, includes: Using the barrier layer as a mask, the gate isolation layer in the second semiconductor unit is removed by anisotropic etching process; The first portion of the first dummy gate structure in the second semiconductor unit is removed by anisotropic etching or isotropic etching, wherein the first portion corresponds to the gate isolation layer in the second semiconductor unit. The sequential removal of the first dummy gate structure and the photoresist includes: The second part of the first dummy gate structure in the second semiconductor unit and the first dummy gate structure in the first semiconductor unit are removed by an isotropic etching process, wherein the second part and the first part constitute the first dummy gate structure in the second semiconductor unit. Remove the photoresist.

12. The method according to claim 1, wherein, Before removing the second dummy gate structure to expose the second source / drain structure and the gate isolation layer, the method further includes: The first semiconductor unit and the second semiconductor unit are formed.

13. The method according to claim 12, wherein, The formation of the first semiconductor unit and the second semiconductor unit includes: The first active structure and the second active structure are formed on a semiconductor substrate, wherein the second active structure is closer to the semiconductor substrate than the first active structure; The second dummy gate structure, the gate isolation layer, and the first dummy gate structure are sequentially formed on the semiconductor substrate. Based on the first active structure, the first source-drain structure and the first interlayer dielectric layer are formed sequentially. A first carrier wafer is formed on the first pseudo-gate structure and the first interlayer dielectric layer; The semiconductor substrate is then poured and removed. Based on the second active structure, the second source-drain structure and the second interlayer dielectric layer are formed sequentially.

14. The preparation method according to claim 1, wherein, Each of the first transistor, the second transistor, the third transistor, and the fourth transistor is: Any one of the following: fin field-effect transistor, all-around gate field-effect transistor, vertical field-effect transistor, complementary field-effect transistor, fork-plate transistor, and planar field-effect transistor.

15. A stacked transistor, fabricated using the fabrication method according to any one of claims 1 to 14, comprising: A first stacked transistor and a second stacked transistor are arranged adjacent to each other in a first direction; The first stacked transistor includes: a first transistor and a second transistor disposed opposite to each other along a second direction; a gate isolation layer is formed between the first gate structure of the first transistor and the second gate structure of the second transistor, the gate isolation layer being used to electrically isolate the first gate structure and the second gate structure; The second stacked transistor includes a third transistor and a fourth transistor disposed opposite to each other along a second direction; the third gate structure of the third transistor and the fourth gate structure of the fourth transistor are connected.

16. A semiconductor device, comprising: The stacked transistor as described in claim 15.

17. An electronic device comprising: The circuit board and the semiconductor device as claimed in claim 16, wherein the semiconductor device is disposed on the circuit board.

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