Photovoltaic cell, module, and system

Abstract

The present disclosure is applicable to the field of photovoltaics, and provides a photovoltaic cell, a module, and a system. A plurality of grid lines and a plurality of microarrays are arranged side by side in a first direction on a non‑illuminated surface of the photovoltaic cell; the grid lines extend in a second direction; each of the microarrays comprises a plurality of arranged microstructure units; and an included angle α between each microarray and a grid line in an edge region is greater than an included angle β between the microarray and the grid line in a region close to a center line.

Description

Photovoltaic cells, modules and systems

[0001] Priority information

[0002] This disclosure claims priority and benefits to patent application No. 202510089067.5, filed with the China National Intellectual Property Administration on January 21, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure pertains to the field of photovoltaic technology, and particularly relates to a solar cell, a battery module, and a photovoltaic system. Background Technology

[0004] Despite various methods to optimize light absorption and charge transport in existing solar cell technologies, several technical challenges remain to be addressed. Firstly, traditional planar backlight designs tend to allow direct light penetration and escape, reducing the light propagation path within the silicon substrate, lowering light absorption efficiency, and exacerbating interface recombination issues. This significantly affects the passivation effect of the back-side passivation film, leading to increased surface recombination losses and consequently reducing the open-circuit voltage.

[0005] Secondly, while designing microstructure units on the back surface in existing technologies can improve light absorption and optimize passivation to some extent, the existing microstructure unit design cannot effectively change the angle of light, causing some light to still escape when it reaches the light-facing surface, reducing the chance of light absorption and lowering the photoelectric conversion efficiency. Summary of the Invention

[0006] This disclosure provides a solar cell, a solar module, and a photovoltaic system, aiming to solve the problem of low light absorption efficiency in existing solar cells.

[0007] This disclosure is implemented as follows: a solar cell includes:

[0008] A silicon substrate has a backlight surface and a light-facing surface arranged opposite to each other. A plurality of gate lines and a plurality of microarrays are arranged side by side on the backlight surface along a first direction. The gate lines extend along a second direction. The microarrays include a plurality of arranged microstructure units. The microarrays and the gate lines have an angle between them. The first direction and the second direction intersect.

[0009] If the length of the silicon substrate along the second direction is L, then the area extending L / 9 from the two sides of the silicon substrate parallel to the first direction toward the center line is the edge region. The included angle of the edge region is α, and the included angle in the region close to the center line is β. The angle α is greater than the angle β.

[0010] Optionally, the difference between the angles of α and β is 1° to 15°.

[0011] Optionally, the difference between the angles of α and β is 2° to 13°.

[0012] Optionally, the difference between the angles of α and β is 4° to 13°.

[0013] Optionally, some microstructural units are arranged discontinuously.

[0014] Optionally, the second direction is perpendicular to the first direction.

[0015] Optionally, the grid lines are positioned on the backlight side.

[0016] Alternatively, the grid lines may have only one polarity.

[0017] Optionally, the gate lines include a first polarity gate line and a second polarity gate line with different polarities.

[0018] Optionally, along the first direction, a first doped region and a second doped region are alternately arranged on the backlight surface, a first polar gate line is disposed on the first doped region, and a second polar gate line is disposed on the second doped region.

[0019] Optionally, within the edge region, the microarrays in the adjacent first doped region and the microarrays in the adjacent second doped region are parallel.

[0020] Optionally, the distribution of microstructure units on at least one of the first doped region and the second doped region is non-uniform.

[0021] Optionally, the microstructural unit is a recessed structure.

[0022] Optionally, the projection of the bottom surface of the recessed structure onto the thickness direction of the solar cell is a polygon.

[0023] Optionally, the maximum size of the recessed structure in the first doped region is greater than or equal to the maximum size of the recessed structure in the second doped region.

[0024] Optionally, the number of sides of the polygon is at least one of 3 to 6.

[0025] Optionally, the size of the polygon in the first doped region is 20 μm to 35 μm, and the size of the polygon in the second doped region is 8 μm to 15 μm.

[0026] Optionally, the depth of the recessed structure along the thickness direction of the solar cell is 0.2 μm to 2 μm.

[0027] Optionally, the roughness of the first doped region is less than that of the second doped region.

[0028] Optionally, the microarray satisfies at least one of the following: at least partially stacked arrangement of two or more microstructural units; or adjacent but non-stacked arrangement of two or more microstructural units.

[0029] Optionally, at least one of the first doped region and the second doped region includes one or more of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon.

[0030] This disclosure also provides a battery assembly including the aforementioned solar cell.

[0031] This disclosure also provides a photovoltaic system including the aforementioned battery module.

[0032] The beneficial effects achieved by this disclosure are due to the microarray formed by multiple microstructural units. This microstructural unit design not only helps improve light absorption but also results in relatively low interface state recombination, thus not significantly affecting the passivation effect of the back passivation film. Simultaneously, the angle between the microarray and the gate lines allows the microstructural units at different angles to change the angle of light reflected from the back surface after it enters the silicon wafer from the light-facing side. Some light that would otherwise escape the silicon wafer is reflected back into the wafer upon reaching the front surface due to the angle change. This helps increase the light absorption path within the silicon wafer, thereby improving light absorption efficiency and ultimately increasing the current output and overall conversion efficiency of the battery. The angle α in the edge region and the angle β in the region near the center line further increase the propagation path of light within the silicon wafer, increasing the chance of light absorption and further enhancing the photoelectric conversion efficiency of the battery. Attached Figure Description

[0033] Figure 1 is a schematic diagram of the structure of the solar cell provided in this disclosure;

[0034] Figure 2 is an α-angle microscope view of the edge region of the solar cell provided in this disclosure;

[0035] Figure 3 is a β-angle microscope view of the solar cell near the center line provided in this disclosure;

[0036] Figure 4 shows the current trend when the α angle in the edge region and the β angle in the region near the center line have different angle differences.

[0037] Figure 5 is a schematic diagram showing the conversion efficiency trend when the α angle in the edge region and the β angle in the region near the center line have different angle differences.

[0038] Figure 6 is a schematic diagram of the printing defect rate when the α angle in the edge area and the β angle in the area near the center line have different angle differences.

[0039] Figure 7 is a schematic diagram showing the proportion of scratches when the α angle in the edge area and the β angle in the area near the center line have different angle differences.

[0040] Figure 8 shows the electrical performance data of each group of solar cells when the α angle in the edge region and the β angle in the region near the center line have different angle differences.

[0041] Figure 9 is a schematic diagram of the optical path in the microstructure unit;

[0042] Figure 10 is a partial schematic diagram of a microstructure unit under a microscope.

[0043] Explanation of reference numerals in the attached figures: 100, solar cell; 110, silicon substrate; 111, first side; 112, second side; 120, microarray; 121, microstructure unit; 130, grid line. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this disclosure and are not intended to limit this disclosure.

[0045] In the description of this disclosure, it should be understood that the terms “length”, “width”, “upper”, “lower”, “left”, “right”, “horizontal”, “top”, “bottom”, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0047] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0048] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0049] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0050] This disclosure utilizes a microarray composed of multiple microstructural units. This microstructural unit design not only enhances light absorption but also exhibits relatively low interface recombination, minimizing its impact on the passivation effect of the back-side passivation film. Furthermore, the microarray and the gate lines form an angle. When light enters the silicon wafer from the light-facing side, the different angles of the microstructural units allow the light to change its angle upon reflection from the back-facing side. Some light that would otherwise escape the silicon wafer is reflected back into the wafer due to this angle change, increasing the light absorption path within the wafer and thus improving light absorption efficiency. Ultimately, this enhances the battery's current output and overall conversion efficiency. The angle α in the edge region is larger than the angle β in the region closer to the center line, further increasing the light propagation path within the wafer and enhancing the chance of light absorption, thereby further improving the battery's photoelectric conversion efficiency.

[0051] Example 1

[0052] This embodiment provides a solar cell 100, including:

[0053] A silicon substrate 110 has a backlight surface and a light-facing surface arranged opposite to each other. A plurality of microarrays 120 and gate lines 130 are arranged side by side on the backlight surface along a first direction. The gate lines 130 extend along a second direction. The microarrays include a plurality of linearly arranged microstructure units. The linear direction of the microarrays 120 and the extension direction of the gate lines 130 have an angle. The first direction and the second direction intersect.

[0054] If the length of the silicon substrate 110 along the second direction is L, then the area extending L / 9 from the two sides of the silicon substrate 110 parallel to the first direction toward the center line is the edge region. The included angle of the edge region is α, and the included angle of the region near the center line is β. The angle α is greater than the angle β.

[0055] The silicon substrate 110 has two main surfaces: a light-facing surface and a back-lighting surface. The light-facing surface is the side that directly faces sunlight, while the back-lighting surface is the other side, and the two surfaces are arranged opposite each other. Typically, the back surface of the silicon substrate 110 includes alternating N-regions and P-regions. The N-regions contain N-type doped layers, and the P-regions contain P-type doped layers. The N-type and P-type doped layers form regions with different chemical properties, supporting the formation of PN junctions and the separation of charge carriers.

[0056] A plurality of gate lines and a plurality of microarrays are arranged along a first direction, and the gate lines extend along a second direction, which intersects the first direction. The gate lines can be arranged along the longitudinal direction of the silicon substrate and all extend in the transverse direction; that is, the first direction can be the longitudinal direction of the back contact cell, and the second direction can be the transverse direction of the back contact cell, with the two perpendicular to each other. Of course, in other embodiments, the first and second directions can also be other directions, for example, they can be the diagonal directions of the silicon substrate, and no specific limitation is made here. The plurality of gate lines and the plurality of microarrays can overlap each other.

[0057] As shown in Figure 1, the first direction is the longitudinal direction of the silicon substrate 110. Several microarrays 120 and gate lines 130 are arranged side-by-side along the first direction on the backlight surface. Typically, the gate lines 130 are straight lines extending along a second direction, which is perpendicular to the first direction and extends laterally along the silicon substrate 110. The microarray 120 is formed by arranging multiple microstructural units 121, where the microstructural units 121 have a small diameter. Multiple microstructural units 121 are densely overlapped and arranged to form the microarray 120. These microstructural units 121 can be of various shapes, such as pyramids, inverted pyramids, micropores, micropillars, etc., and are not limited here.

[0058] Understandably, the angle between the linear direction of the grid line 130 and the microarray 120 is the angle between the tangent at a certain position on the microarray 120 and the grid line 130. A specific position is selected on the microarray 120, and then the tangent at that position is drawn (if the microarray 120 is a straight line at that position, the tangent direction is consistent with the direction of the straight line; if the microarray 120 is a curve at that position, the tangent is the tangent of the curve). The grid line 130 itself is a series of parallel lines with a fixed direction, parallel to the two sides of the solar cell along the first direction. The grid line 130 itself has a certain width. When measuring the angle, the width of the grid line 130 is not considered; it is only approximated as a straight line parallel to the two sides of the solar cell along the first direction. In this application, only the tangent and the grid line 130 are considered as scalars, and directionality is not considered. The "angle" in this application refers to an angle greater than 0° and less than 90°.

[0059] As shown in Figures 2 and 3, the gate line 130 forms an angle with the microarray 120. Typically, the silicon substrate 110 is square, with the gate line 130 perpendicular to the first direction and parallel to the edge of the silicon substrate 110. The first side 111 consists of two opposing sides on the silicon substrate 110, parallel to the first direction. The second side 112 consists of two sides on the silicon substrate 110 connecting to the first side 111, perpendicular to the first side 111. An edge region extends 1 / 9 of its length from the first side 111 towards the center of the silicon substrate 110. There are two edge regions, opposite each other on both sides of the silicon substrate 110. The centerline is located at a distance L / 2 from the first side 111, positioned between the two edge regions. Within the edge region, the angle between the gate line 130 and the microarray 120 is α. Within the region closer to the centerline, the angle between the gate line 130 and the microarray 120 is β, where angle α is greater than angle β.

[0060] As shown in Figure 10, the microarray 120 is formed by arranging microstructure units 121. When light is incident on the microstructure unit 121, it undergoes multiple refractions and reflections between multiple surfaces, lengthening the propagation path of light within the silicon substrate 110 and increasing the opportunity for photons to interact with the silicon material. Depending on the angle at which the microstructure unit 121 is placed, light will exhibit different refraction and reflection effects on the microstructure unit 121. Different angles between the microarray 120 and the gate line 130 result in different positions for the microstructure unit 121, leading to different angles of refraction and reflection of light. This further complicates the propagation path of light within the silicon substrate 110, further lengthening the propagation path and increasing the opportunity for photons to interact with the silicon material, thereby improving the absorption rate.

[0061] Specifically, as shown in Figure 9, light enters the silicon wafer from the light-facing surface. The light propagates within the wafer, and some of it is absorbed by the silicon material and converted into electrical energy. Unabsorbed light reaches the back-light surface and is reflected by the microarray 120. The angle of the reflected light changes depending on the shape and arrangement of the microstructure units 121, and some light is reflected back into the silicon wafer, increasing the chance of light absorption. In different regions, the angle between the gate line 130 and the microarray 120 varies, creating a diffuse reflection effect. Diffuse reflection increases the propagation path of light within the silicon wafer, further improving the photoelectric conversion efficiency. After the light reflected back into the silicon wafer is absorbed, the resulting electron-hole pairs are collected by the gate line 130, forming a current output.

[0062] In addition, since the α angle in the edge region is different from the β angle in the region near the center line, the microstructure unit 121 at the corresponding position is placed at different angles. The microstructure unit 121 at different angles can better capture light at different incident angles, reduce light escape, improve the overall light capture efficiency, further reduce light reflection loss, and improve light transmission and absorption efficiency.

[0063] In this embodiment, by setting a microarray 120 formed by multiple microstructure units, the microstructure unit design not only helps to improve light absorption, but also has relatively low interface state recombination, which does not significantly affect the passivation effect of the back passivation film. Simultaneously, the microarray 120 and the gate line 130 have an angle. When light enters the silicon wafer from the light-facing surface, the microstructure units 121 at different angles can change the angle of the light when reflected from the back light-facing surface. Some of the light that would originally escape the silicon wafer is reflected back into the silicon wafer when it reaches the front surface again due to the angle change. This helps to increase the light absorption path in the silicon wafer, thereby improving the light absorption efficiency and ultimately improving the current output and overall conversion efficiency of the battery. The angle α in the edge region is larger than the angle β in the region near the center line, which can further increase the propagation path of light inside the silicon wafer, increase the chance of light absorption, and further enhance the photoelectric conversion efficiency of the battery.

[0064] In some embodiments, the difference between the angles α and β is between 1° and 15°.

[0065] When the difference between α and β is less than 1°, the difference between the α angle in the edge region and the β angle in the region near the center line is too small to achieve a good diffuse reflection effect or reduce light escape effectively, thus having little effect on improving photoelectric conversion efficiency. Conversely, when the difference between α and β is greater than 15°, the difference in light incident angle between the edge region and the region near the center line is too large, potentially leading to over-optimization of the light incident angle in one region and insufficient optimization in the other. For example, an excessively large angle in the edge region results in an excessively long light propagation path, increasing reflection loss; while an excessively small angle between the gate line and the microarray in the region near the center line may increase direct light transmission and reduce absorption. Furthermore, a large angle difference causes significant differences in light propagation paths between different regions, resulting in uneven light distribution within the silicon substrate 110. This reduces the overall photoelectric conversion efficiency because the photon absorption rate in some regions may be significantly higher than in others, causing an imbalance in efficiency.

[0066] Therefore, the angle difference between α and β is between 1° and 15°, which allows for optimization of the light incident angle between the edge region and the region near the center line. This ensures that light from different positions can effectively enter the silicon substrate 110, reducing reflection losses. Within this range, the propagation path length of light varies moderately in different regions, maintaining a uniform distribution of light within the silicon substrate 110 and improving the overall photoelectric conversion efficiency.

[0067] In some embodiments, the difference between the angle of α in the edge region and the angle of β in the region near the center line is 2° to 13°.

[0068] In the laboratory, when the angle α in the edge region and the angle β in the region near the center line have different angle differences, relevant electrical performance tests are conducted to obtain relevant laboratory data. The difference between the angle α in the edge region and the angle β in the region near the center line is x. The experimental data below are obtained by averaging the data from several tested battery cells. Random factors are unavoidable during the experiment, which may lead to errors in individual data points. By averaging the results of multiple experiments, these random errors can be effectively smoothed out, improving the stability of the data.

[0069] As shown in Figure 4, Jsc (Short Circuit Current Density) gradually increases with the increase of the x-angle. This is because the microarray 120 on the backlight surface changes the light transmission path and facilitates the absorption of light by the battery, generating more photogenerated carriers and increasing the current. However, the increase in Jsc gradually decreases with the increase of the x-angle. When the x-angle exceeds 13°, the increase in Jsc is only 0.01, which is negligible.

[0070] As shown in Figure 6, with the increase of the x-angle, the proportion of printing defects such as broken grid lines in the solar cells of each group increases. When the x-angle is less than 13°, the defect rate increases relatively slowly, but when the x-angle exceeds 13°, the defect rate increases sharply. Due to the increase in broken grid lines, the current collected by the grid lines 130 deteriorates, resulting in a smaller current gain due to the microstructure. Ultimately, this leads to a corresponding change in current; when the x-angle exceeds 13°, the current decreases significantly.

[0071] Understandably, due to the increased number of broken wires, the current collected by the gate line 130 deteriorates, resulting in a smaller current gain due to the microstructure.

[0072] Furthermore, as the x-angle increases, the series resistance Rs exhibits a pattern of first decreasing, then increasing, and then abruptly changing. Microstructure unit 121 increases the surface roughness of the silicon wafer, facilitating contact between the metal paste and the wafer surface and reducing the series resistance. When the x-angle is less than 13°, the number of defective cell prints is low, the series resistance decreases, and the fill factor (FF) increases accordingly. However, when the x-angle exceeds 13°, the proportion of defective cell prints increases sharply. The increase in series resistance caused by broken or thick lines exceeds the effect of microstructure unit 121, leading to an increase in series resistance and consequently a significant decrease in the fill factor (FF).

[0073] As shown in Figure 7, the proportion of scratches on the battery surface increases with the increase of the x-angle, especially when the x-angle exceeds 13°, the proportion of scratches increases sharply. These scratches are due to the increased arc angle formed by these microstructures, which increases the surface roughness. As a result, the silicon wafer surface is easily scratched when it comes into contact with the automation and equipment table during the battery manufacturing process, leading to poor surface passivation and consequently a decrease in Voc (Open-Circuit Voltage).

[0074] As shown in Figures 5 and 8, considering all electrical properties, when the x-angle is less than 2°, although the rates of printing defects and scratches are both low, the values ​​of Voc, Jsc, FF, and EFF (Efficiency) are also low. When the x-angle is greater than 13°, the rates of printing defects and scratches are too high, and the values ​​of Voc, FF, and EFF are also low. Although the value of Jsc increases, the increase is too small. When the x-angle is between 2° and 13°, the rates of printing defects and scratches remain at a low level, while Voc, Jsc, FF, and EFF all increase significantly.

[0075] Specifically, the angle x can be 2°, 2.2°, 3°, 3.3°, 4°, 4.5°, 5°, 5.4°, 6°, 6.5°, 7°, 8°, 9°, 10°, 11°, 12°, 13°, etc., or other values ​​within the range of 2° to 13°, to name just a few.

[0076] Angle differences less than 2° result in limited optimization, with minimal variation in light incident angle and light propagation path. While manufacturing is easy, significant performance improvements are difficult to achieve. Angle differences greater than 13° represent over-optimization, leading to uneven light propagation paths. Large angle differences may also affect the stability of microstructure unit 121, making the structure prone to deformation or damage during manufacturing and use, thus reducing the lifespan and reliability of the solar cell and causing an overall decrease in efficiency. Angle differences between 2° and 13° offer good optimization, with a moderate light incident angle, relatively uniform light propagation path, and good structural stability, making it a suitable choice for improving photoelectric conversion efficiency and overall performance.

[0077] Optionally, as shown in Figure 8, the values ​​of Voc, Jsc, FF, and EFF are most significantly improved when the x-angle is between 4° and 13°. That is, when the difference between the α-angle in the edge region and the β-angle in the region near the center line is between 4° and 13°, the performance of the solar cell 100 under different illumination conditions can achieve the optimal balance. This design significantly reduces reflection loss by optimizing the refraction and reflection of light on the microstructure unit 121 and the grid line 130, further improving the photon absorption rate and photoelectric conversion efficiency.

[0078] Example 2

[0079] As shown in Figure 10, in some embodiments, the microstructure units 121 are arranged discontinuously.

[0080] The arc-shaped microarray 120 formed by the overlapping of multiple microstructural units 121 is a non-continuous arrangement of microstructural units 121, meaning that there is a certain gap between some of the microstructural units 121, and they are not closely connected. Specifically, each microstructural unit 121 can have different shapes and sizes (usually at the micrometer level), and the spacing between some of the microstructural units 121 can also be different.

[0081] The discontinuous arrangement of microstructure units 121 makes the reflection path of light within the silicon wafer more complex. Multiple reflections between different microstructure units 121 increase the propagation path of light within the silicon wafer, thereby improving light absorption efficiency. Furthermore, due to the spacing between some microstructure units 121, light has more opportunities to be absorbed by the silicon wafer during reflection, reducing the amount of escaping light.

[0082] Example 3

[0083] In some embodiments, the grid lines are disposed on the back surface of the solar cell.

[0084] In back-contact solar cells (such as HBC cells), the grid lines are positioned on the back side of the cell. The front side is completely unobstructed by the grid lines, thus maximizing the effective area for absorbing sunlight and improving the cell's photoelectric conversion efficiency.

[0085] In some embodiments, the grid lines have only one polarity. In some batteries, all front-side current-collecting electrodes (such as the positive grid lines) are located on the back of the battery. This design means that there are no metal grid lines on the front of the battery, allowing all light to reach the photovoltaic material. This enables more sunlight to directly reach the photovoltaic material, thereby improving light absorption and the battery's photoelectric conversion efficiency.

[0086] In some embodiments, the grid lines include a first polarity grid line and a second polarity grid line of opposite polarity. The first polarity grid line and the second polarity grid line have opposite polarities; one is a positive grid line, and the other is a negative grid line. The positive grid line collects photogenerated electrons, and the negative grid line collects photogenerated holes. This can optimize the current path, reduce series resistance, and improve the overall performance of the battery.

[0087] In some embodiments, a first doped region and a second doped region are alternately disposed on the backlight surface along a first direction, a first polar gate line is disposed on the first doped region, and a second polar gate line is disposed on the second doped region.

[0088] Two distinct doped regions, a first doped region and a second doped region, are arranged alternately on the backlight surface of the silicon substrate 110. Specifically, a plurality of first doped regions and a plurality of second doped regions are arranged alternately along a first direction, and both the first and second doped regions extend along a second direction, which intersects the first direction. The arrangement direction of the first and second doped regions is consistent with the arrangement direction of the gate lines, and the extension direction of the first and second doped regions is consistent with the extension direction of the gate lines.

[0089] A first doped layer is disposed within a first doped region, and a second doped layer is disposed within a second doped region. The first and second doped layers have opposite polarities. Specifically, the first doped layer can be a P-type doped layer and the second doped layer can be an N-type doped layer, or vice versa. The first and second doped layers form doped regions with different electrical properties, supporting the formation of a PN junction and the separation of charge carriers.

[0090] A first polarity gate line is disposed on a first doped region, and the polarity of the first polarity gate line corresponds to that of the first doped region. A second polarity gate line is disposed on a second doped region, and the polarity of the second polarity gate line corresponds to that of the second doped region. That is, when the first doped region is a P-type doped layer and the second doped region is an N-type doped layer, the first polarity gate line is a positive gate line and the second polarity gate line is a negative gate line; when the first doped region is an N-type doped layer and the second doped region is a P-type doped layer, the first polarity gate line is a negative gate line and the second polarity gate line is a positive gate line.

[0091] In some embodiments, a spacer region is provided between the first doped region and the second doped region. This spacer region provides physical isolation between the first and second doped regions, facilitating clearer electric field separation between them. Optimization of the electric field can improve carrier separation efficiency, reduce direct recombination of carriers (electrons and holes) in these regions, reduce recombination losses, and increase open-circuit voltage.

[0092] In some embodiments, within the edge region, the microarray 120 in the adjacent first doped region and the microarray 120 in the second doped region are parallel.

[0093] Edge regions are typically high-risk areas for carrier recombination. Within these edge regions, the parallel alignment of the microarrays 120 within adjacent first and second doped regions ensures a more uniform light propagation path, reduces reflection losses, and increases light absorption, thereby improving photoelectric conversion efficiency. Simultaneously, the parallel microarrays 120 reduce recombination losses and the risk of carrier recombination in edge regions.

[0094] In some embodiments, the distribution of microstructure units on at least one of the first doped region and the second doped region is non-uniform.

[0095] The distribution density and arrangement of microstructural units can vary in different regions. Within the same doped region, the density or arrangement of microstructural units at different locations can differ. Specifically, the distribution of microstructural units in both the first and second doped regions can be uneven; the distribution of microstructural units in the first doped region can be uneven, but the distribution in the second doped region can be uniform; or the distribution of microstructural units in the first doped region can be uniform, but the distribution in the second doped region can be uneven.

[0096] By using non-uniformly distributed microstructural units, the propagation path of light in different regions can be optimized, reducing reflection loss at specific angles.

[0097] Example 4

[0098] In some embodiments, the microstructure units 121 are recessed structures.

[0099] The microstructure unit 121 is recessed from the backlight surface to the light-facing surface, that is, the distance from the top surface of the microstructure unit 121 to the light-facing surface is less than the distance from the backlight surface to the light-facing surface.

[0100] The recessed microstructure units 121 can form multiple reflective surfaces, increasing the multiple reflections of light within these microstructure units 121. This multiple reflection extends the light propagation path within the silicon substrate 110, improving light absorption efficiency. The recessed structure can also increase light scattering, making the light more uniformly distributed within the silicon substrate 110, thereby increasing the short-circuit current density (Jsc). Furthermore, the recessed microstructure units 121 can form optical waveguides, allowing light to propagate along a specific path, reducing direct light penetration and escape, and further improving the light capture rate.

[0101] In some embodiments, the depth of the recessed structure along the thickness direction of the battery cell is 0.2 μm to 2 μm.

[0102] That is, the distance from the bottom surface of the microstructure unit 121 to the backlight surface is 0.2μm to 2μm, specifically 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, 1.2μm, 1.5μm, 1.8μm, or 2μm, or other values ​​within the range of 0.2μm to 2μm, which are not limited here. This depth range is used to optimize the propagation and scattering characteristics of light, and improve the transmittance, reflectivity, and other properties of the optical material.

[0103] In some embodiments, the maximum size of the recessed structure in the first doped region is greater than or equal to the maximum size of the recessed structure in the second doped region.

[0104] The recessed structure can be formed by chemical etching, laser etching, mechanical etching, or plasma etching on the silicon substrate 110. The recessed structure typically forms a plane at the bottom. The dimensions of the recessed structure can be the length, width, diagonal length, or diameter of a circle, etc., and are not limited here. Measurements are taken from the largest recessed structure within the first and second doped regions. In some examples, the dimensions of the recessed structure can be measured directly using testing instruments (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.) to calibrate the film surface.

[0105] The size of the recessed structure in the first doped region is greater than or equal to the size of the recessed structure in the second doped region. This design can optimize the light reflection and electric field distribution on the back side, increase the light absorption path, promote charge separation and transport, and reduce surface recombination losses and current leakage.

[0106] Specifically, the first doped region can be an N-type doped region, and the second doped region can be a P-type doped region. For different doped regions, microstructure units 121 of different sizes are designed accordingly, which can more effectively improve the passivation quality of the corresponding regions and enhance the contact characteristics with the paste, so that the prepared solar cells can obtain higher cell conversion efficiency.

[0107] In some embodiments, the projection of the bottom surface of the recessed structure onto the thickness direction of the solar cell is a polygon. The bottom surface of the recessed structure can be a plane or it can be undulating. The number of sides of the polygon is at least 3 to 6. Specifically, the shape of the polygonal plane includes at least one of rhombus, square, trapezoid, approximately rhombus, approximately square, approximately trapezoid, pentagon, and hexagon. For example, the bottom surface can be entirely square, entirely rhombus, partially hexagonal, partially rhombus, partially trapezoidal, partially approximately square, and partially pentagonal, and so on. Other possible combinations are not excluded.

[0108] In some embodiments, the size of the polygon in the first doped region is 20 μm to 35 μm, and the size of the polygon in the second doped region is 8 μm to 15 μm.

[0109] The specific dimensions of the polygon within the first doped region can be 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, 25.5μm, 26μm, 27μm, 28μm, 29μm, 30μm, 31μm, 32μm, 33μm, 34μm, or 35μm, or other values ​​between 20μm and 35μm, without limitation here.

[0110] The dimensions of the bottom surface of the microstructure unit 121 in the second doped region can be 8μm, 9μm, 10μm, 10.5μm, 11μm, 12μm, 13μm, 13.6μm, 15μm, or other values ​​from 8μm to 15μm, which are not limited here.

[0111] Further limiting the bottom size of the microstructure unit 121 in different doping regions is beneficial to obtaining higher open-circuit voltage and fill factor, thereby achieving higher battery conversion efficiency.

[0112] Example 5

[0113] In some embodiments, the roughness of the first doped region is less than that of the second doped region.

[0114] The surface of the first doped region is smoother than that of the second doped region. This smoothness reduces light reflection and increases light absorption. Conversely, the rougher region increases light reflection and scattering within the material, lengthening the light path within the cell and thus increasing the probability of photon absorption. Simultaneously, the rougher region provides more surface area, facilitating more uniform deposition of the passivation layer, reducing surface recombination, and improving charge carrier lifetime. The combined use of these two roughness regions helps improve the photoelectric conversion efficiency and reliability of the battery.

[0115] Example 6

[0116] In some embodiments, in the microarray 120, at least some of two or more microstructure units 121 are stacked, and / or two or more microstructure units 121 are arranged adjacent to each other in a non-stacked arrangement.

[0117] Specifically, a microarray 120 may include two or more microstructure units 121 that are at least partially stacked, meaning at least two microstructure units 121 are partially stacked or completely overlapped. Alternatively, a microarray 120 may include two or more microstructure units 121 arranged adjacent to each other without stacking, meaning at least two microstructure units 121 are adjacent to each other but not stacked. Furthermore, a microarray 120 may include both two or more microstructure units 121 that are at least partially stacked and two or more microstructure units 121 that are adjacent to each other but not stacked.

[0118] It is understandable that when the microarray 120 includes two or more microstructure units 121 that are at least partially stacked and two or more adjacent but not stacked microstructure units 121, the roughness of the microarray 120 can be controlled within the required range. This is beneficial for enhancing the contact of the paste in the conductive area of ​​the solar cell in the screen printing process, improving the tension of the paste, improving the quality and yield of the solar cell, improving the open circuit voltage of the solar cell, improving the fill factor, and thus improving the photoelectric conversion efficiency.

[0119] Example 7

[0120] In some embodiments, at least one of the first doped region and the second doped region includes one or more of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon.

[0121] Polycrystalline silicon consists of many small grains, and the grain boundaries between these grains increase the probability of electron-hole recombination. The doping in polycrystalline silicon is relatively uniform because the dopant diffusion between grains is relatively consistent. Amorphous silicon lacks a long-range ordered lattice structure, and the material contains numerous dangling bonds and defects. Amorphous silicon exhibits higher doping inhomogeneity because defects and dangling bonds affect the distribution of dopant. Microcrystalline silicon has a structure intermediate between amorphous and polycrystalline silicon, possessing a certain grain structure but with smaller grain sizes. The defect density of microcrystalline silicon is lower than that of amorphous silicon but higher than that of polycrystalline silicon.

[0122] Depending on the type of cell, the doping type of the first and second doping regions is selected, and the performance of the solar cell is further optimized through composite design.

[0123] In some embodiments, the back side of the solar cell further includes a passivation contact structure, wherein the passivation contact structure includes an interface tunneling passivation film and a doped polycrystalline silicon film.

[0124] Interfacial tunneling passivation films are very thin films (typically between a few nanometers and tens of nanometers), and common materials include SiO2 and SiN. x Al2O3 and other substances are used to passivate silicon surfaces and reduce surface recombination.

[0125] Doped polycrystalline silicon films are relatively thick polycrystalline silicon films (typically between several hundred nanometers and several micrometers) that form good electrical contacts through doping (usually phosphorus or boron) while maintaining a high charge carrier lifetime.

[0126] The passivation contact structure can be a stacked configuration of an interface tunneling passivation film and a doped polycrystalline silicon film, or it can have other films placed between the tunneling passivation film and the doped polycrystalline silicon film. Passivation contact structures help improve the photoelectric conversion efficiency and stability of the battery.

[0127] In some embodiments, a back passivation film structure is also included, wherein the material of the back passivation film structure includes aluminum oxide.

[0128] The back-side passivation film structure is used to further reduce surface recombination on the back side. Aluminum oxide (Al₂O₃) is a very effective passivation material. Aluminum oxide has a high dielectric constant and good electrical insulation properties, which can form effective electrical isolation on the back side of the battery, reducing current loss. Furthermore, aluminum oxide has excellent chemical stability, resisting the effects of high temperature and humid environments, improving battery durability and reliability. At the same time, aluminum oxide can effectively reduce recombination on the silicon surface.

[0129] Example 8

[0130] This embodiment provides a battery assembly, including the solar cell 100 in the above embodiment.

[0131] The battery module may include multiple solar cells 100. The multiple solar cells 100 in the battery module can be connected in series to form a battery string. The battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between the individual solar cells can be achieved by welding the welding strips, or the connection between the individual battery strings can be achieved by using busbars.

[0132] The battery module may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulant film (not shown in the figures). The encapsulant film can be filled between the front and photovoltaic glass, the back and backsheet, and adjacent cells of the solar cell 100. As a filler, it can be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulant film can be EVA film or POE film. The specific choice can be made according to the actual situation and is not limited here.

[0133] Photovoltaic glass can be applied to the encapsulating film on the front side of the solar cell 100. The photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%. It can protect the solar cell 100 while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the solar cell 100 together, providing sealing, insulation, waterproofing, and moisture protection for the solar cell 100.

[0134] The backsheet can be attached to the adhesive film on the back of the solar cell 100. The backsheet provides protection and support for the solar cell 100, and has reliable insulation, water resistance, and aging resistance. Multiple options are available for the backsheet, typically tempered glass, acrylic glass, aluminum alloy TPT composite adhesive film, etc., and the specific choice depends on the specific circumstances and is not limited here. The backsheet, solar cell 100, adhesive film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module, providing stable support and installation. For example, the battery module can be installed at the desired location using the metal frame.

[0135] The beneficial effects of the battery module in this embodiment are equivalent to those of the solar cell 100 described above, and will not be repeated here.

[0136] Example 9

[0137] This embodiment provides a photovoltaic system, including the battery module described in the above embodiment.

[0138] Photovoltaic systems can be applied in photovoltaic power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios of photovoltaic systems are not limited to these; that is, photovoltaic systems can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation network as an example, a photovoltaic system can include photovoltaic arrays, combiner boxes, and inverters. A photovoltaic array can be a combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic arrays are connected to combiner boxes, which collect the current generated by the photovoltaic arrays. The collected current flows through an inverter and is converted into AC power required by the mains grid before being connected to the mains grid to achieve solar power supply.

[0139] The beneficial effects of the photovoltaic module in this embodiment are equivalent to those of the battery module described above, and will not be repeated here.

[0140] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A solar cell, wherein, include: A silicon substrate having a backlight surface and a light-facing surface arranged opposite to each other, a plurality of gate lines and a plurality of microarrays arranged side by side on the backlight surface along a first direction, the gate lines extending along a second direction, the microarrays comprising a plurality of arranged microstructure units, the microarrays having an angle with the gate lines, and the first direction intersecting the second direction; If the length of the silicon substrate along the second direction is L, then the area extending L / 9 from each of the two sides of the silicon substrate parallel to the first direction toward the center line is the edge region. The included angle in the edge region is α, and the included angle in the region close to the center line is β. The angle α is greater than the angle β.

2. The solar cell as described in claim 1, wherein, The difference between the angle of α and the angle of β is 1° to 15°.

3. The solar cell as described in claim 1, wherein, The difference between the angle of α and the angle of β is 2° to 13°.

4. The solar cell as claimed in claim 1, wherein, The difference between the angle of α and the angle of β is 4° to 13°.

5. The solar cell as claimed in claim 1, wherein, Some of the microstructural units are arranged discontinuously.

6. The solar cell as claimed in claim 1, wherein, The second direction is perpendicular to the first direction.

7. The solar cell as claimed in claim 1, wherein, The grid lines are disposed on the backlight surface.

8. The solar cell as claimed in claim 7, wherein, The grid lines have only one polarity.

9. The solar cell as claimed in claim 7, wherein, The gate lines include a first polarity gate line and a second polarity gate line with different polarities.

10. The solar cell as claimed in claim 9, wherein, Along the first direction, the backlight surface is alternately provided with a first doped region and a second doped region, the first polar gate line is disposed on the first doped region, and the second polar gate line is disposed on the second doped region.

11. The solar cell of claim 10, wherein, Within the edge region, the microarray in the first doped region and the microarray in the adjacent second doped region are parallel.

12. The solar cell of claim 10, wherein, The distribution of the microstructure units on at least one of the first doped region and the second doped region is not uniform.

13. The solar cell of claim 10, wherein, The microstructure unit is a recessed structure.

14. The solar cell of claim 13, wherein, The maximum size of the recessed structure in the first doped region is greater than or equal to the maximum size of the recessed structure in the second doped region.

15. The solar cell of claim 13, wherein, The projection of the bottom surface of the recessed structure onto the thickness direction of the battery cell is a polygon.

16. The solar cell of claim 15, wherein, The polygon has at least one of 3 to 6 sides.

17. The solar cell of claim 15, wherein, The polygon in the first doped region has a size of 20 μm to 35 μm, and the polygon in the second doped region has a size of 8 μm to 15 μm.

18. The solar cell of claim 13, wherein, The depth of the recessed structure along the thickness direction of the battery cell is 0.2 μm to 2 μm.

19. The solar cell of claim 10, wherein, The roughness of the first doped region is less than that of the second doped region.

20. The solar cell as claimed in claim 1, wherein, The microarray satisfies at least one of the following: Two or more of the microstructure units are at least partially stacked; Two or more of the microstructure units are arranged adjacent to each other and not stacked.

21. The solar cell of claim 10, wherein, At least one of the first doped region and the second doped region includes one or more of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon.

22. A battery assembly, wherein, Includes the solar cell described in any one of claims 1 to 21.

23. A photovoltaic system, wherein, Includes the battery assembly as described in claim 22.

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