Packaging structure and electronic device

Abstract

Provided in the present application are a packaging structure and an electronic device. The packaging structure comprises: a first chip, which comprises a first device layer, a first metal layer and a second metal layer which are stacked in sequence; and a second chip, which is located on one side of the first chip and comprises a second device layer, the number of functional units of the first device layer being less than the number of functional units in the second device layer. The second device layer comprises a first functional device and a second functional device, which belong to the same functional unit or different functional units and are both electrically connected to the first metal layer. In the present application, signal transmission between two functional devices of the second chip is achieved by means of the first metal layer of a first chip, which can mitigate the shortage of metal resources of upper metal layers of the second chip, and can improve the signal transmission efficiency between the two functional devices on the basis of sufficient metal resources of the first metal layer.

Description

Packaging structure and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510127429.5, filed on January 27, 2025, entitled "Packaging Structure and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a packaging structure and an electronic device. Background Technology

[0003] As the demand for chip computing power grows across various sectors, chip design and manufacturing are gradually shifting from 2D (D) to 2.5D and 3D. 2.5D and 3D chips can be stacked to increase integration density per unit area, thereby generating profits.

[0004] In the field of 2D chips, to improve chip performance and increase the efficiency of signal transmission between functional units within the chip, thicker metal layers (generally high-layer metal layers) can be used to transmit signals. However, in chip stacking scenarios, much of the metal resources in the high-layer metal layers are occupied by power networks, interconnect structures between stacked chips, etc., leading to a shortage of metal resources in the high-layer metal layers. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a packaging structure and electronic device that enables signal transmission between two functional devices of a second chip through the first metal layer of the first chip in a stacked two-chip configuration, thereby alleviating the shortage of metal resources in the higher metal layers of the second chip.

[0006] A first aspect of this application provides a packaging structure comprising: a first chip and a second chip. The first chip includes a first device layer, a first metal layer, and a second metal layer stacked sequentially, the first device layer including at least two functional units. The second chip is located on one side of the first chip, the second chip including a second device layer, the second device layer including at least two functional units, the number of functional units in the first device layer being less than the number of functional units in the second device layer. The second device layer includes a first functional device and a second functional device, the first functional device and the second functional device belonging to the same functional unit or different functional units, both the first functional device and the second functional device being electrically connected to the first metal layer.

[0007] In this design, the first and third metal layers can be referred to as lower metal layers, while the second and fourth metal layers can be referred to as higher metal layers. Typically, higher metal layers are used in power networks. Furthermore, the metal resources in higher metal layers are usually less than those in lower metal layers.

[0008] In this application, both the first functional device and the second functional device are electrically connected to the first metal layer of the first chip. Thus, signals transmitted between the first and second functional devices can be output from one functional device, pass through the first metal layer of the first chip, return to the second chip, and reach the other functional device. In other words, this application can utilize the first metal layer of the first chip to achieve signal transmission between the two functional devices of the second chip.

[0009] The direction of the signal transmitted between the first functional device and the second functional device can be from the first functional device to the second functional device, or it can be from the second functional device to the first functional device.

[0010] In scenarios where the second chip is stacked on top of the first chip, the fourth metal layer (higher metal layer) is primarily used for the power network. Signal transmission between the first and second functional devices is not achieved through the fourth metal layer; therefore, the solution in this application will not affect the power network of the second chip.

[0011] In scenarios where the first chip is stacked on top of the second chip, the second metal layer (higher metal layer) is primarily used for the power network. Signal transmission between the first and second functional devices occurs through the first metal layer, not the second metal layer. Therefore, the solution presented in this application will not affect the power network of the first chip.

[0012] In the scenario where the second metal layer of the first chip is used for interconnection with the second chip, since this application mainly uses the first metal layer (lower metal layer) of the first chip to realize signal transmission, rather than the second metal layer (higher metal layer), the interconnection between chips will not be affected.

[0013] Compared to using the chip's own high-level metal layer to achieve signal transmission between the chip's functional units, this application achieves signal transmission between two functional devices of the second chip through the first metal layer (low-level metal layer) of the first chip. This reduces the use of the second chip's high-level metal layer resources, thereby alleviating the shortage of the second chip's high-level metal layer resources.

[0014] Furthermore, in this application, the first chip may have fewer functional units than the second chip. The first chip only needs less metal resources in the first and / or second metal layers to satisfy the signal transmission of its own functional units, while the second chip needs to use more metal resources in the third and / or fourth metal layers to satisfy the signal transmission of its own functional units. Thus, the first metal layer is usually in a relatively idle state. However, this application mainly uses the first metal layer to realize the signal transmission between the first and second functional devices, thereby ensuring that there are sufficient metal resources to transmit the signal between the first and second functional devices. Moreover, based on the sufficient metal resources of the first metal layer, the signal transmission efficiency between the two functional devices can be improved by increasing the transmission linewidth, etc.

[0015] In one possible implementation, the packaging structure further includes a bonding layer located between the first chip and the second chip. The bonding layer includes a first conductive structure and a second conductive structure. A first functional device is electrically connected to the first conductive structure, and a second functional device is electrically connected to the second conductive structure. Both the first and second conductive structures are electrically connected to a first metal layer. Thus, the first and second functional devices can be electrically connected sequentially through the first conductive structure, the first metal layer, and the second conductive structure, thereby achieving signal transmission.

[0016] Furthermore, the bonding layer is located between the second metal layer of the first chip and the fourth metal layer of the second chip. In this way, the first chip and the second chip are directly connected by the bonding layer. Compared with the connection method using bumps, the interconnection path between the chips is shorter and the interconnection density is higher. This reduces the signal transmission distance between the two chips, helps to reduce the signal transmission delay between the chips, and improves the overall performance of the package structure.

[0017] In one possible implementation, the first metal layer includes a first metal line, and both a first conductive structure and a second conductive structure are electrically connected to the first metal line. In this way, signals between the first functional device and the second functional device can be transmitted through the first metal line.

[0018] In one possible implementation, the second chip further includes a third metal layer stacked on the second device layer, the third metal layer including a second metal line; the linewidth of the first metal line is greater than the linewidth of the second metal line. Thus, the wider linewidth of the first metal line results in lower resistance. Compared to achieving signal transmission between the first and second functional devices via the second metal line of the second chip, this application achieves signal transmission between the first and second functional devices via the first metal line, resulting in lower resistance along the signal transmission path, thereby reducing signal transmission delay caused by impedance on the metal line.

[0019] In one possible implementation, the third metal layer includes at least two second metal lines; the first metal layer also includes a third metal line closest to the first metal line; the spacing between the first and third metal lines is greater than the spacing between any two adjacent second metal lines. This larger spacing between the first and third metal lines reduces interference on the signal on the first metal line and also reduces the coupling capacitance on the first metal line. This results in a smaller coupling capacitance along the signal transmission path, less interference during signal transmission, reduced signal delay, and improved signal quality.

[0020] Furthermore, since the coupling capacitance on the signal transmission path between the first functional device and the second functional device in this application is small, the driving distance of a single driving device to the signal is longer. When the total length of the transmission path is not much different, the number of driving devices required on the signal transmission path in this application is reduced, which can reduce the signal transmission delay caused by the driving devices.

[0021] In one possible implementation, the second device layer further includes a third functional device and a fourth functional device, both of which are electrically connected to the third metal layer. In this way, signals between some functional units of the second chip can be transmitted through the first metal layer of the first chip, while signals between other functional units can be transmitted through the third metal layer of the second chip itself. This avoids signal interference caused by transmitting all signals between functional units of the second chip through the first metal layer when the second chip has many functional units, thus maintaining signal quality and transmission speed and improving signal transmission efficiency. Furthermore, by implementing the above method of transmitting signals between some functional units of the second chip through the first metal layer, the overall metal resources of the packaging structure can be used in a balanced and rational manner.

[0022] In one possible implementation, the second device layer further includes a first driving device, one end of which is electrically connected to the first functional device, and the other end of which is electrically connected to the first conductive structure. This allows the first driving device to drive signal transmission between the first and second functional devices, ensuring successful signal transmission. Throughout the signal transmission path, the first driving device is located close to the first functional device. When the first functional device is the transmitter of the signal, the first driving device enhances the initial driving capability of the signal, ensuring the quality of the signal received by the receiver. When the first functional device is the receiver of the signal, the first driving device can restore signal quality before the receiver receives the signal.

[0023] In one possible implementation, the first device layer includes a second driving device. One end of the second driving device is electrically connected to the first conductive structure at least through the first metal layer, and the other end of the second driving device is electrically connected to the second conductive structure at least through the first metal layer. When a signal is transmitted between the first functional device and the second functional device to the first chip, the signal transmission can be driven by the second driving device to restore signal quality and improve the signal quality received by the receiving functional device. Furthermore, since the first chip has fewer functional units than the second chip, the first device layer of the first chip has more space to place the driving device compared to the second chip, and the metal layer of the first chip has more metal resources to connect the driving devices. Therefore, the driving devices required for the signal transmission paths of the first and second functional devices can be placed within the first device layer of the first chip, thereby alleviating the space constraints of the device layer and the metal resources of the metal layer of the second chip.

[0024] In one possible implementation, the first device layer includes at least two second driving devices arranged sequentially along a first direction, whereby the first functional device points towards the second functional device. Any two adjacent second driving devices are electrically connected at least through a first metal layer. Thus, by using multiple second driving devices to drive the signal transmission between the first functional devices, signal degradation can be better reduced, and signal quality during subsequent transmission can be better enhanced.

[0025] In one possible implementation, one end of the second driving device closest to the first functional device is electrically connected to the second conductive structure at least through the first metal layer. For example, one end of the second driving device closest to the first functional device can be connected to the second conductive structure through a first metal line in the first metal layer, thereby enabling signal transmission through the first metal line.

[0026] In one possible implementation, the end of the second driving device closest to the second functional device is electrically connected to the adjacent second driving device at least through the first metal layer. For example, the end of the second driving device closest to the second functional device can be connected to the adjacent second driving device through a first metal line in the first metal layer, thereby enabling signal transmission through the first metal line.

[0027] In one possible implementation, the second device layer further includes a third driving device, one end of which is electrically connected to the second conductive structure, and the other end of which is electrically connected to the second functional device. The effect of the third driving device can be referred to the above description of the effect of the first driving device, and will not be repeated here.

[0028] A second aspect of this application provides an electronic device, characterized in that it includes a circuit board and a packaging structure according to any of the above embodiments, the packaging structure being disposed on the circuit board. The electronic device can achieve all the effects of the packaging structure. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 is a schematic diagram of the packaging structure in the related technology;

[0031] Figure 2 is a 3D schematic diagram of a packaging structure provided in an embodiment of this application;

[0032] Figure 3a is a schematic diagram of the encapsulation structure in the first embodiment of this application;

[0033] Figure 3b is a schematic diagram of the packaging structure in the second embodiment of this application;

[0034] Figure 3c is a schematic diagram of the packaging structure in the third embodiment of this application;

[0035] Figure 3d is a schematic diagram of the packaging structure in the fourth embodiment of this application;

[0036] Figure 4a is a schematic diagram of the packaging structure in the fifth embodiment of this application;

[0037] Figure 4b is a schematic diagram of the packaging structure in the sixth embodiment of this application;

[0038] Figure 4c is a schematic diagram of the packaging structure in the seventh embodiment of this application;

[0039] Figure 4d is a schematic diagram of the packaging structure in the eighth embodiment of this application;

[0040] Figure 5a is a schematic diagram of the encapsulation structure in the ninth embodiment of this application;

[0041] Figure 5b is a schematic diagram of the packaging structure in the tenth embodiment of this application;

[0042] Figure 6 is a schematic diagram of the encapsulation structure in the eleventh embodiment of this application;

[0043] Figure 7 is a schematic diagram of the encapsulation structure in the twelfth embodiment of this application;

[0044] Figure 8a is a schematic diagram of the encapsulation structure in the thirteenth embodiment of this application;

[0045] Figure 8b is a schematic diagram of the encapsulation structure in the fourteenth embodiment of this application;

[0046] Figure 8c is a schematic diagram of the packaging structure in the fifteenth embodiment of this application;

[0047] Figure 9a is a schematic diagram of the encapsulation structure in the sixteenth embodiment of this application;

[0048] Figure 9b is a schematic diagram of the encapsulation structure in the seventeenth embodiment of this application;

[0049] Figure 9c is a schematic diagram of the packaging structure in the eighteenth embodiment of this application;

[0050] Figure 10a is a schematic diagram of the encapsulation structure in the nineteenth embodiment of this application;

[0051] Figure 10b is a partial circuit topology diagram of the package structure shown in Figure 10a;

[0052] Figure 11 is a schematic diagram of the packaging structure in the twentieth embodiment of this application;

[0053] Figure 12a is a schematic diagram of the encapsulation structure in the twenty-first embodiment of this application;

[0054] Figure 12b is a partial circuit topology diagram of the package structure shown in Figure 12a;

[0055] Figure 13 is a schematic diagram of the packaging structure in the twenty-second embodiment of this application;

[0056] Figure 14a is a schematic diagram of the encapsulation structure in the twenty-third embodiment of this application;

[0057] Figure 14b is a partial circuit topology diagram of the package structure shown in Figure 14a;

[0058] Figure 15 is a schematic diagram of the packaging structure in the twenty-fourth embodiment of this application;

[0059] Figure 16 is a comparison diagram of the related technologies and a partial circuit topology diagram of the package structure shown in Figures 10a, 12a and 14a.

[0060] Icons: 1-Packaging structure; 10-First chip; 11-First device layer; 12-First metal layer; 13-Second metal layer; 111-Second driver device; 115-Fifth functional device; 116-Sixth functional device; 121-First metal line; 122-Third metal line; 20-Second chip; 21-Second device layer; 22-Third metal layer; 23-Fourth metal layer; 211-First functional device; 212-Second functional device; 213-First driver device; 214-Third driver device; 215-Third functional device; 216-Fourth functional device; 217-First functional unit; 218-Second functional unit; 221-Second metal line; 30-Bonding layer; 31-First conductive structure; 32-Second conductive structure; D1-Line spacing between first metal line 121 and third metal line 122; D2-Line spacing between any two adjacent second metal lines 221. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0062] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, while "more" refers to two or more. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0063] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0064] Terms such as “connected” and “linked” are used to express the interconnection or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Terms such as “upper,” “lower,” “left,” and “right” are used only relative to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and may vary accordingly depending on the orientation of the components in the drawings.

[0065] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0066] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0067] As the demand for chip computing power grows across various sectors, chip design and manufacturing are gradually shifting from 2D to 2.5D and 3D. 2.5D and 3D chips can increase integration density per unit area by stacking multiple chips, thereby generating profits.

[0068] In related technologies, to improve chip performance and increase the efficiency of signal transmission between functional units within a chip, a thicker metal layer (generally a high-level metal layer) can be used to transmit signals. Because the high-level metal layer is thicker and has low resistance, signals can be quickly transmitted to the vicinity of the next functional unit. Therefore, in the chip stacking application scenario shown in Figure 1, each chip can use its own high-level metal layer to achieve signal transmission between functional units. Specifically, as shown in Figure 1, the package structure 1 includes a first chip 10 and a second chip 20, with the second chip 20 stacked on one side of the first chip 10. The first chip 10 includes a first device layer 11, a first metal layer 12 (lower metal layer), and a second metal layer 13 (higher metal layer). The second chip 20 includes a second device layer 21, a third metal layer 22 (lower metal layer), and a fourth metal layer 23 (higher metal layer). The first device layer 11 includes a fifth functional device 115 and a sixth functional device 116, which are electrically connected through the second metal layer 13. The second device layer 21 includes a first functional device 211 and a second functional device 212, which are electrically connected through a fourth metal layer 23. Each of the above functional devices belongs to a functional unit.

[0069] However, the metal resources of the upper metal layers of a chip are already relatively scarce. In the case of chip stacking, many metal resources of the upper metal layers of a chip are occupied by power networks, interconnect structures between stacked chips, etc., which makes the metal resources of the upper metal layers even more scarce.

[0070] Specifically, referring to Figure 1, the first chip 10 and the second chip 20 are typically powered through a circuit board (not shown) connected below the first chip 10. Therefore, compared to a scenario without chip stacking (e.g., 2D), the power supply path of the stacked chip (e.g., the second chip 20) is longer, potentially leading to a larger voltage drop along the power supply path. To avoid excessive voltage drop, more metal resources in higher metal layers are needed to implement the power network. For example, wider metal lines in higher metal layers are required to implement the power supply path, minimizing resistance and voltage drop, thereby achieving a robust power network.

[0071] Meanwhile, the interconnection between stacked chips sometimes also utilizes high-layer metal resources. For example, the first chip 10 and the second chip 20 in the stack shown in Figure 1 can be interconnected by a hybrid bonding method, which requires the use of high-layer metal resources of the two stacked chips.

[0072] Therefore, as shown in Figure 1, using the high-level metal layer of the chip to realize data transmission between functional units may affect the power network of the second chip 20 stacked on top, causing power supply problems for the second chip 20, which in turn causes the second chip 20 to malfunction.

[0073] Based on this, in this application embodiment, a packaging structure is proposed, which can be packaging structure 1 as shown in Figure 2. Packaging structure 1 can be applied to electronic devices. In addition to packaging structure 1, the electronic device may also include a circuit board. Packaging structure 1 is disposed on the circuit board and electrically connected to the circuit board. Here, the electronic device can be, for example, a server, consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronic products, etc., and this application embodiment does not limit this. Illustrated, the aforementioned consumer electronics can be mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics can be smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. Automotive electronics can be car navigation systems, car displays, etc. Financial terminal products can include automated teller machines (ATMs) and electronic devices for self-service transactions. Communication electronic products can include servers, storage devices, radar, base stations, and other communication equipment.

[0074] As shown in Figure 2, the package structure 1 may include a first chip 10 and a second chip 20. The first chip 10 may be any of the following chips: system-on-chip (SOC), dummy chip, central processing unit (CPU), graphics processing unit (GPU), memory, input / output (I / O) chip, integrated passive device (IPD), high bandwidth memory (HBM), die-on-silicon interposer (DOI), fan-out RDL interposer (FOI), logic chip, etc. Specifically, the memory may be a static random access memory (SRAM) chip, etc. The second chip 20 may also be any of the chips listed above. Furthermore, the first chip 10 and the second chip 20 may be the same or different. This embodiment uses an SRAM chip as the first chip 10 and a logic chip as the second chip 20 for illustration.

[0075] As shown in Figure 3a, the first chip 10 may include a first device layer 11, a first metal layer 12, and a second metal layer 13 stacked sequentially. The second chip 20 may include a second device layer 21. Similar to the first chip 10, the second chip 20 may also include a third metal layer 22 and a fourth metal layer 23, and the second device layer 21, the third metal layer 22, and the fourth metal layer 23 are stacked sequentially.

[0076] Regarding the stacking method between the first chip 10 and the second chip 20, there are two cases: the second chip 20 is located above the first chip 10 and the second chip 20 is located below the first chip 10.

[0077] In the first case, in one example, as shown in FIG3a, the second chip 20 can be stacked on one side of the second metal layer 13 of the first chip 10, and the fourth metal layer 23 of the second chip 20 is close to the second metal layer 13, while the second device layer 21 of the second chip 20 is away from the second metal layer 13.

[0078] In another example, as shown in FIG3b, the second chip 20 may be stacked on one side of the second metal layer 13 of the first chip 10, and the second device layer 21 of the second chip 20 is close to the second metal layer 13, while the fourth metal layer 23 of the second chip 20 is away from the second metal layer 13.

[0079] In another example, as shown in FIG3c, the second chip 20 may be stacked on one side of the first device layer 11 of the first chip 10, and the second device layer 21 of the second chip 20 is close to the first device layer 11, while the fourth metal layer 23 of the second chip 20 is away from the first device layer 11.

[0080] In the fourth example, as shown in Figure 3d, the second chip 20 can be stacked on one side of the first device layer 11 of the first chip 10, and the fourth metal layer 23 of the second chip 20 is close to the first device layer 11, while the second device layer 21 of the second chip 20 is away from the first device layer 11.

[0081] In the second case, in one example, as shown in Figure 4a, the first chip 10 can be stacked on one side of the fourth metal layer 23 of the second chip 20, and the second metal layer 13 of the first chip 10 is close to the fourth metal layer 23, while the first device layer 11 of the first chip 10 is away from the fourth metal layer 23.

[0082] In another example, as shown in FIG4b, the first chip 10 may be stacked on one side of the fourth metal layer 23 of the second chip 20, and the first device layer 11 of the first chip 10 is close to the fourth metal layer 23, while the second metal layer 13 of the first chip 10 is away from the fourth metal layer 23.

[0083] In another example, as shown in FIG4c, the first chip 10 may be stacked on one side of the second device layer 21 of the second chip 20, and the first device layer 11 of the first chip 10 is close to the second device layer 21, while the second metal layer 13 of the first chip 10 is away from the second device layer 21.

[0084] In the fourth example, as shown in Figure 4d, the first chip 10 can be stacked on one side of the second device layer 21 of the second chip 20, and the second metal layer 13 of the first chip 10 is close to the second device layer 21, while the first device layer 11 of the first chip 10 is away from the second device layer 21.

[0085] Metal layers in a chip that are far from the device layer can be called high-level metal layers. For example, the second metal layer 13 and the fourth metal layer 23 can be called high-level metal layers of the first chip 10 and the second chip 20, respectively. Metal layers in a chip that are close to the device layer can be called low-level metal layers. For example, the first metal layer 12 and the third metal layer 22 can be called low-level metal layers of the first chip 10 and the second chip 20, respectively.

[0086] In one possible implementation, the first chip 10 and the second chip 20 may further include more metal layers, and this application embodiment does not impose specific limitations on this. For example, taking the first chip 10 as an example, the second chip 20 is similarly implemented. The first chip 10 may include three metal layers stacked sequentially, which, according to their order of proximity to the first device layer 11, may be referred to as the lower metal layer, the middle metal layer, and the higher metal layer, respectively.

[0087] Typically, higher metal layers are used in power networks. Furthermore, higher metal layers generally have fewer metal resources than lower and middle metal layers.

[0088] Both the first device layer 11 and the second device layer 21 may include multiple functional units, and each functional unit may include one or more functional devices. Different functional units can communicate with each other through the functional devices to work together.

[0089] A functional unit is an independent module within a chip, responsible for performing specific functions, such as arithmetic units, memory units, communication interfaces, control units, and security units. A functional device is the smallest physical entity that implements the specific function of a functional unit. Functional devices can include basic electronic components such as transistors, resistors, and capacitors, or more complex integrated circuit modules such as logic gates, complex logic networks, registers, flip-flops, latches, memory units, and communication interfaces.

[0090] As shown in Figure 3a, this embodiment uses the second device layer 21, which includes two functional devices (first functional device 211 and second functional device 212), as an example for illustration. For ease of understanding, these two functional devices can be considered to belong to two different functional units. Both the first functional device 211 and the second functional device 212 are electrically connected to the first metal layer 12. When the second chip 20 is a logic chip, the first functional device 211 and the second functional device 212 can be sequential logic devices, such as registers, flip-flops, latches, etc.

[0091] In this embodiment, the first chip 10 may have fewer functional units than the second chip 20. In this way, the first chip 10 can use less metal resources of the first metal layer 12 and / or the second metal layer 13 to meet the signal transmission of its own functional units, while the second chip 20 needs to use more metal resources of the third metal layer 22 and / or the fourth metal layer 23 to meet the signal transmission of its own functional units.

[0092] In this embodiment, both the first functional device 211 and the second functional device 212 are electrically connected to the first metal layer 12 of the first chip 10. Thus, the signal transmitted between the first functional device 211 and the second functional device 212 can be output from one functional device, pass through the first metal layer 12 of the first chip 10, and then return to the second chip 20 to reach the other functional device. That is, this embodiment utilizes the first metal layer 12 of the first chip 10 to achieve signal transmission between the two functional devices of the second chip 20.

[0093] The direction of the signal transmitted between the first functional device 211 and the second functional device 212 can be from the first functional device 211 to the second functional device 212, or from the second functional device 212 to the first functional device 211. This application does not specifically limit this direction.

[0094] In the scenario shown in Figures 3a to 3d, where the second chip 20 is stacked above the first chip 10, the fourth metal layer 23 (higher metal layer) is mainly used for the power network. Signal transmission between the first functional device 211 and the second functional device 212 is not achieved through the fourth metal layer 23. Therefore, the solution in this embodiment does not affect the power network of the second chip 20.

[0095] In the scenario shown in Figures 4a to 4d, where the first chip 10 is stacked on top of the second chip 20, the second metal layer 13 (higher metal layer) is mainly used for the power network. Signal transmission between the first functional device 211 and the second functional device 212 is conducted through the first metal layer 12, not the second metal layer 13. Therefore, the solution in this embodiment does not affect the power network of the first chip 10.

[0096] In the scenario shown in Figures 3a and 3b, and Figures 4c and 4d, where the second metal layer 13 of the first chip 10 is used for interconnection with the second chip 20, since the embodiments of this application mainly use the first metal layer 12 (lower metal layer) of the first chip 10 to realize signal transmission, rather than the second metal layer 13 (higher metal layer), the interconnection between chips will not be affected.

[0097] Compared to the related technologies shown in Figure 1, which use the chip's own high-level metal layer to achieve signal transmission between the functional units of the chip, the embodiments of this application use the first metal layer 12 (low-level metal layer) of the first chip 10 to achieve signal transmission between the two functional devices of the second chip 20, which can reduce the use of the high-level metal layer resources of the second chip 20 and thus alleviate the shortage of high-level metal layer resources of the second chip 20.

[0098] Furthermore, in any of the above embodiments, the first metal layer 12 is in a relatively idle state compared to the second metal layer 13. In this embodiment, the first metal layer 12 is mainly used to realize the signal transmission between the first functional device 211 and the second functional device 212, thereby ensuring that there are enough metal resources to transmit the signal between the first functional device 211 and the second functional device 212.

[0099] In one possible implementation, signals between all functional units of the second chip 20 can be transmitted through the first metal layer 12, thereby freeing up the metal resources of the higher metal layers of the second chip 20. For example, as shown in FIG5a, in addition to the first functional device 211 and the second functional device 212, the second device layer 21 also includes a third functional device 215 and a fourth functional device 216. The third functional device 215 and the fourth functional device 216 are both electrically connected to the first metal layer 12 of the first chip 10. Here, the third functional device 215 and the fourth functional device 216 belong to different functional units.

[0100] In this way, when the higher metal layer of the second chip 20 is used to transmit other signals (such as power signals), the signals between all functional units of the second chip 20 in this embodiment are transmitted through the first metal layer 12 of the first chip 10, which can avoid the interference of the other signals transmitted between these functional units by the higher metal layer of the second chip 20.

[0101] In another possible implementation, signals between some functional units of the second chip 20 can be transmitted through the first metal layer 12 of the first chip 10, while signals between other functional units can be transmitted through the third metal layer 22 of the second chip 20. For example, as shown in FIG5b, the third functional device 215 and the fourth functional device 216 are both electrically connected to the third metal layer 22 of the second chip 20.

[0102] In this way, when the second chip 20 has many functional units, it avoids the interference between signals caused by transmitting all signals between the functional units of the second chip 20 through the first metal layer 12. This maintains signal quality and transmission speed, and reduces signal transmission delay. Furthermore, by implementing signal transmission between a portion of the functional units of the second chip 20 through the first metal layer 12 in the above embodiment, the overall metal resources of the package structure 1 can be used in a balanced and rational manner.

[0103] The following detailed description uses the packaging structure 1 shown in Figure 3a as an example. The possible implementations of the packaging structure 1 shown in Figures 3b to 4d are similar in principle to the possible implementations of the packaging structure 1 shown in Figure 3a, and will not be described in detail again.

[0104] As shown in Figure 6, the package structure 1 may further include a bonding layer 30. The bonding layer 30 is located between the first chip 10 and the second chip 20. Specifically, the bonding layer 30 is located between the second metal layer 13 of the first chip 10 and the fourth metal layer 23 of the second chip 20. That is, the first chip 10 and the second chip 20 in the package structure 1 shown in Figure 6 can be connected through the bonding layer 30. In this way, by directly connecting the first chip 10 and the second chip 20 through the bonding layer 30, compared with methods such as using bumps for connection, the interconnection path between the chips is shortened and the interconnection density is increased, thereby reducing the signal transmission distance between the two chips, helping to reduce the signal transmission delay between chips, and improving the overall performance of the package structure 1.

[0105] The bonding layer 30 can be a hybrid bonding structure, a through-silicon via (TSV) bonding structure, etc., and this embodiment does not specifically limit it. This embodiment uses a hybrid bonding structure as an example for explanation. As shown in Figure 6, the hybrid bonding structure can include a thin and uniform dielectric material, such as silicon dioxide (SiO2) or silicon carbonitride (SiCN), deposited on the surface of the second metal layer 13 and the surface of the fourth metal layer 23. Corresponding micron- or even nanometer-sized columnar vias are formed on the dielectric material deposited on the two metal layers, and these columnar vias are filled with metal (usually copper) to form metal pillars. The metal pillars on the dielectric material deposited on the two metal layers are bonded one-to-one. These metal pillars can be called conductive structures, therefore the bonding layer 30 includes multiple conductive structures. As shown in Figure 6, the multiple conductive structures include a first conductive structure 31 and a second conductive structure 32. The first conductive structure 31 can be the metal pillar closest to the first functional device 211, and the second conductive structure 32 can be the metal pillar closest to the second functional device 212.

[0106] As shown in Figure 6, the first conductive structure 31 is electrically connected to the first functional device 211, and the second conductive structure 32 is electrically connected to the second functional device 212. For example, the electrical connection between the first conductive structure 31 and the first functional device 211, and the electrical connection between the second conductive structure 32 and the second functional device 212, can be achieved by wires passing through the third metal layer 22 and the fourth metal layer 23.

[0107] Since the first conductive structure 31 is the conductive structure closest to the first functional device 211, and the second conductive structure 32 is the conductive structure closest to the second functional device 212, the length of the signal transmission path between the first functional device 211 and the first conductive structure 31, as well as the length of the signal transmission path between the second functional device 212 and the second conductive structure 32, can be reduced. Since both of these signal transmission paths are part of the signal transmission path between the first functional device 211 and the second functional device 212, this example can reduce the length of the signal transmission path between the first functional device 211 and the second functional device 212, thereby reducing signal transmission delay.

[0108] As shown in Figure 6, both the first conductive structure 31 and the second conductive structure 32 are electrically connected to the first metal layer 12. In this way, the first functional device 211 and the second functional device 212 can be electrically connected sequentially through the first conductive structure 31, the first metal layer 12, and the second conductive structure 32, thereby realizing signal transmission.

[0109] In one possible implementation, as shown in FIG7, the first metal layer 12 may include a first metal line 121, and the first conductive structure 31 and the second conductive structure 32 may both be electrically connected to the first metal line 121. For example, the first conductive structure 31 may be electrically connected to one end of the first metal line 121 via a wire passing through the second metal layer 13 and through the first metal layer 12. In this way, signals between the first functional device 211 and the second functional device 212 can be transmitted through the first metal line 121.

[0110] In one possible implementation, as shown in FIG8a, the third metal layer 22 may include a second metal line 221, wherein the linewidth of the first metal line 121 is greater than the linewidth of the second metal line 221. This wider linewidth of the first metal line 121 results in lower resistance. Compared to using the second metal line 221 of the second chip 20 for signal transmission between the first functional device 211 and the second functional device 212, this embodiment uses the first metal line 121 for signal transmission, resulting in lower resistance along the signal transmission path and thus reducing signal transmission delay caused by impedance on the metal line.

[0111] Typically, the middle and lower metal layers of a chip have abundant metal resources, and the first chip 10 has fewer functional units. The first metal layer 12 occupies less metal resources for the functional units of the first chip 10 itself. Therefore, in this embodiment, a wider metal line on the first metal layer 12 can be used for signal transmission between the first functional device 211 and the second functional device 212.

[0112] Regarding the linewidths of the first metal line 121 and the second metal line 221, in another possible embodiment, as shown in FIG8b, the linewidth of the first metal line 121 is equal to the linewidth of the second metal line 221. In yet another possible embodiment, as shown in FIG8c, the linewidth of the first metal line 121 is smaller than the linewidth of the second metal line 221.

[0113] As shown in FIG9a, in one possible embodiment, the third metal layer 22 may include at least two second metal lines 221. The first metal layer 12 may also include a third metal line 122 that is closest to the first metal line 121. The line spacing D1 between the first metal line 121 and the third metal line 122 is greater than the line spacing D2 between any two adjacent second metal lines 221.

[0114] Thus, the larger spacing between the first metal line 121 and the third metal line 122 reduces interference on the signal on the first metal line 121 and also reduces the coupling capacitance on the first metal line 121. Compared to using the second metal line 221 of the third metal layer 22 of the second chip 20 itself to achieve signal transmission between the first functional device 211 and the second functional device 212, since the signal transmission between the first functional device 211 and the second functional device 212 is achieved through the first metal line 121 in this embodiment, the coupling capacitance on the signal transmission path is smaller, and the interference experienced during signal transmission is less, thereby reducing signal delay and improving signal quality.

[0115] Furthermore, since the coupling capacitance on the signal transmission path between the first functional device 211 and the second functional device 212 in this application is small, the driving distance of a single driving device to the signal is longer. When the total length of the transmission path is not much different, the number of driving devices required on the signal transmission path in this embodiment of the application is reduced, which can reduce the signal transmission delay caused by the driving devices.

[0116] Typically, the middle and lower metal layers of a chip have abundant metal resources, and the first chip 10 has relatively few functional units. The first metal layer 12 occupied by the functional units of the first chip 10 itself has relatively few metal resources. Therefore, a small number of metal lines can be set in the first metal layer 12 of the first chip 10. Thus, in this embodiment, the distance between the first metal line 121 on the first metal layer 12 and other surrounding metal lines can be relatively large, thereby achieving the aforementioned effects of reducing signal interference.

[0117] Regarding the spacing D1 between the first metal wire 121 and the third metal wire 122, as shown in FIG9b, in another possible embodiment, the spacing D1 between the first metal wire 121 and the third metal wire 122 is equal to the spacing D2 between any two adjacent second metal wires 221. As shown in FIG9c, in yet another possible embodiment, the spacing D1 between the first metal wire 121 and the third metal wire 122 is less than the spacing D2 between any two adjacent second metal wires 221.

[0118] In one possible implementation, as shown in FIG10a, the second device layer 21 may further include a first driving device 213. As shown in FIG10b, one end of the first driving device 213 is electrically connected to the first functional device 211, and the other end of the first driving device 213 is electrically connected to the first conductive structure 31.

[0119] For example, as shown in FIG10a, one end of the first driving device 213 is electrically connected to the first functional device 211 at least through the third metal layer 22. For example, one end of the first driving device 213 can be electrically connected to the first functional device 211 through an electrical connection structure located between the first driving device 213 and the first functional device 211, for example, through a metal wire in the third metal layer 22.

[0120] For example, when the signal transmission direction is from the first functional device 211 to the second functional device 212, the input terminal of the first driving device 213 can be electrically connected to the output terminal of the first functional device 211 through a metal wire of the third metal layer 22. In this way, the signal can be transmitted from the output terminal of the first functional device 211 to the input terminal of the first driving device 213, driven by the first driving device 213, and then transmitted from the output terminal of the first driving device 213 through the first conductive structure 31 to the first metal wire 121, then from the first metal layer 12 to the second conductive structure 32, and then from the second conductive structure 32 to the input terminal of the second functional device 212.

[0121] For example, the first driving device 213 can be a buffer or an inverter. In addition, the driving capability of the first driving device 213 may vary depending on the impedance of the metal wires in the signal transmission path, the distance of the transmission path, etc., and this application embodiment does not specifically limit this.

[0122] In this embodiment, the first driving device 213 can drive the signal transmission between the first functional device 211 and the second functional device 212, thereby ensuring successful signal transmission. Throughout the signal transmission path, the first driving device 213 is located close to the first functional device 211. When the first functional device 211 is the transmitter of the signal, the first driving device 213 can enhance the initial driving capability of the signal, ensuring the signal quality received by the receiver. When the first functional device 211 is the receiver of the signal, the first driving device 213 can restore signal quality before the receiver receives the signal.

[0123] In another possible implementation, as shown in FIG11, the second device layer 21 may include at least two first driving devices 213 arranged sequentially along a first direction. The first direction is the direction from the first functional device 211 to the second functional device 212, and any two adjacent first driving devices 213 are electrically connected at least through a third metal layer 22.

[0124] The number of first driving devices 213 may vary depending on the length of the signal transmission path between the first functional device 211 and the second functional device 212, as well as the impedance on the signal transmission path. Figure 11 only shows the case where the second device layer 21 includes two first driving devices 213. The case where the second device layer 21 includes more than two first driving devices 213 is similar and will not be shown.

[0125] Among them, the first driving device 213, which is closest to the first functional device 211, can be electrically connected to the first functional device 211 through at least the third metal layer 22, and the first driving device 213, which is closest to the second functional device 212, can be electrically connected to the first conductive structure 31 through at least the third metal layer 22.

[0126] For example, when the signal transmission direction is from the first functional device 211 to the second functional device 212, the input terminal of the first driver device 213 closest to the first functional device 211 is electrically connected to the output terminal of the first functional device 211 through a metal line in the third metal layer 22. In any two adjacent first driver devices 213, the output terminal of the first driver device 213 closest to the first functional device 211 is electrically connected to the input terminal of the first driver device 213 closest to the second functional device 212 through a metal line in the third metal layer 22. For example, the first conductive structure 31 can be the conductive structure closest to the first driver device 213 closest to the second functional device 212.

[0127] Thus, when the first functional device 211 is the signal transmitter, the multiple first driving devices 213 can more uniformly enhance the signal transmitted between the first functional device 211 and the second functional device 212, and can ensure that the signal maintains a high quality throughout the transmission path. When the first functional device 211 is the signal receiver, the multiple first driving devices 213 can significantly enhance the quality of the signal when it reaches the first functional device 211, so that the first functional device 211 receives a higher quality signal.

[0128] In one possible implementation, as shown in FIG12a, the first device layer 11 may include a second driving device 111. As shown in FIG12b, one end of the second driving device 111 is electrically connected to the first conductive structure 31 at least through the first metal layer 12, and the other end of the second driving device 111 is electrically connected to the second conductive structure 32 at least through the first metal layer 12.

[0129] For example, the input terminal of the second driving device 111 can be electrically connected to the first conductive structure 31 through a metal line (e.g., the first metal line 121) of the first metal layer 12, and the output terminal of the second driving device 111 can be electrically connected to the second conductive structure 32 through another metal line of the first metal layer 12. In this way, the signal output by the first functional device 211 can be transmitted to the second functional device 212 in sequence through the first conductive structure 31, the second driving device 111, and the second conductive structure 32.

[0130] Further descriptions of the second driving device 111 can be found in the above description of the first driving device 213, and will not be repeated here.

[0131] In this embodiment, when the signal between the first functional device 211 and the second functional device 212 is transmitted to the first chip 10, the signal transmission can be driven by the second driving device 111 to restore signal quality and improve the quality of the signal received by the receiving functional device. Furthermore, since the first chip 10 has fewer functional units than the second chip 20, its first device layer 11 has more space to accommodate driving devices compared to the second chip 20, and its metal layer has more metal resources to connect the driving devices. Therefore, the driving devices required for the signal transmission path of the first functional device 211 and the second functional device 212 can be placed within the first device layer 11 of the first chip 10, thereby alleviating the shortage of space resources in the device layer and metal resources in the metal layer of the second chip 20.

[0132] In another possible implementation, as shown in FIG13, the first device layer 11 may include at least two second driving devices 111 arranged sequentially along a first direction, and any two adjacent second driving devices 111 are electrically connected at least through the first metal layer 12.

[0133] The number of second driving devices 111 may vary depending on the length of the signal transmission path between the first functional device 211 and the second functional device 212, as well as the impedance on the signal transmission path. Figure 13 only shows the case where the first device layer 11 includes two second driving devices 111. The case where the first device layer 11 includes more than two second driving devices 111 is similar and will not be shown.

[0134] The input terminal of the first second driving device 111 along the first direction is electrically connected to the first conductive structure 31 via a metal line in the first metal layer 12. The output terminal of the last second driving device 111 along the first direction is electrically connected to the second conductive structure 32 via a metal line in the first metal layer 12. In any two adjacent second driving devices 111, the output terminal of the preceding second driving device 111 and the input terminal of the following second driving device 111 along the first direction are electrically connected via a metal line in the first metal layer 12.

[0135] In this way, by using multiple second driving devices 111 to drive the signal transmission between the first functional devices 211, signal degradation can be reduced and the signal quality can be enhanced in subsequent transmission processes.

[0136] In one possible implementation, as shown in FIG14a, the second device layer 21 may further include a third driving device 214. As shown in FIG14b, one end of the third driving device 214 is electrically connected to the second conductive structure 32, and the other end of the third driving device 214 is electrically connected to the second functional device 212.

[0137] For example, as shown in FIG14a, a segment of the third driving device 214 is electrically connected to the second functional device 212 at least through the third metal layer 22. For example, the output terminal of the third driving device 214 can be electrically connected to the input terminal of the second functional device 212 through a metal wire of the third metal layer 22. In this way, the signal output from the first functional device 211, after being transmitted to the second conductive structure 32, can be transmitted from the second conductive structure 32 to the input terminal of the third driving device 214, through the third driving device 214, and then from the output terminal of the third driving device 214 to the second functional device 212.

[0138] Further descriptions of the third driving device 214 can be found in the above description of the first driving device 213. The effects of the third driving device 214 can also be found in the above description of the effects of the first driving device 213, and will not be repeated here.

[0139] In another possible implementation, as shown in FIG15, the second device layer 21 may include at least two third driving devices 214 arranged sequentially along a first direction. The first direction is the direction from the first functional device 211 to the second functional device 212, and any two adjacent third driving devices 214 are electrically connected at least through a third metal layer 22.

[0140] The number of third driving devices 214 may vary depending on the length of the signal transmission path between the first functional device 211 and the second functional device 212, as well as the impedance along the signal transmission path. Figure 15 only shows the case where the second device layer 21 includes two third driving devices 214. The case where the second device layer 21 includes more than two third driving devices 214 is similar and will not be shown.

[0141] Among them, the third driving device 214 closest to the first functional device 211 can be electrically connected to the second conductive structure 32 at least through the third metal layer 22, and the third driving device 214 closest to the second functional device 212 can be electrically connected to the second functional device 212 at least through the third metal layer 22.

[0142] For example, as shown in FIG15, the input terminal of the third driving device 214 closest to the first functional device 211 can be electrically connected to the first functional device 211 through a metal line of the third metal layer 22. In any two adjacent third driving devices 214, the output terminal of the third driving device 214 closer to the first functional device 211 and the input terminal of the third driving device 214 closer to the second functional device 212 can be electrically connected through a metal line of the third metal layer 22. For example, the second conductive structure 32 can be the conductive structure closest to the third driving device 214 closest to the first functional device 211.

[0143] The effects of multiple third driving devices 214 can be referred to the above description of the effects of multiple first driving devices 213, and will not be repeated here.

[0144] To clearly illustrate the partial circuit topology of the chip based on the above embodiments, Figure 16 is used as an example to illustrate the following by comparing the partial circuit topology of the chip in the related art with the partial circuit topology of the chip in the above embodiments.

[0145] Please refer to Figure 16. The partial circuit topology of the first chip 10 and the second chip 20 in the related technology shown in Figure 16 is illustrated in the upper part of Figure 16. The first functional unit 217 in the second chip 20 includes a flip-flop 1 and a first functional device 211, where the first functional device 211 can be a logic gate device. Optionally, one or more logic gate devices can be connected between the flip-flop 1 and the first functional device 211. The second functional unit 218 in the second chip 20 includes a flip-flop 2 and a second functional device 212, where the second functional device 212 can be a logic gate device. Optionally, one or more logic gate devices can be connected between the second functional device 212 and the flip-flop 2. The flip-flop 1 and flip-flop 2 share the same clock signal (clock, CLK), and one or more driving devices (not shown in the figure) can optionally be present on the clock signal path. Signals between the first functional unit 217 and the second functional unit 218 are transmitted within the second chip 20.

[0146] Based on all the above embodiments, a partial circuit topology of the first chip 10 and the second chip 20 can be shown in the lower part of Figure 16. In the second chip 20, the first functional device 211 is electrically connected to the first conductive structure 31 via the first driver device 213. The first conductive structure 31 and the second conductive structure 32 are electrically connected via multiple second driver devices 111. The second conductive structure 32 is electrically connected to the second functional device 212 via the third driver device 214. Thus, signals from the first functional unit 217 to the second functional unit 218 can be transmitted from the first functional unit 217 sequentially through the first driver device 213, the first conductive structure 31, multiple second driver devices 111, the second conductive structure 32, and the third driver device 214 to the second functional unit 218.

[0147] For example, in the lower part of Figure 16, the metal line transmitting the signal between the first functional unit 217 and the second functional unit 218 has a wider line width and a larger line spacing with the nearest metal line (see Figures 8a and 9a above, not shown in Figure 16). Based on the effect analysis of the embodiment corresponding to Figure 9a, it can be seen that during signal transmission between the first functional unit 217 and the second functional unit 218, the delay caused by the impedance of the metal line on the signal transmission path is low, as is the delay caused by the driving device on the signal transmission path. This allows the signal transmission path, which might otherwise exhibit setup time violations, to meet the requirements. Specifically, for the signal transmission path between the first functional unit 217 and the second functional unit 218, for example, when a clock signal arrives, the flip-flop 1 in the first functional unit 217 outputs a first signal, and the direction of transmission of this first signal is from the first functional unit 217 to the second functional unit 218, then the setup time refers to the minimum time that the signal received by the flip-flop 2 in the second functional unit 218 must remain stable before the next clock signal arrives. If the first signal does not have enough time to stabilize before the next clock signal arrives, it may cause the flip-flop 2 in the second functional unit 218 to capture incorrect data, thus preventing the second functional unit 218 from outputting an accurate signal when the next clock signal arrives. However, when the delay of the first signal transmission is reduced, the first signal can reach the second functional unit 218 quickly, allowing more time to stabilize before the next clock signal arrives. Therefore, this application can ensure that the signal transmission path, which might otherwise cause setup time violations, meets the requirements.

[0148] Figure 16 above illustrates the following example: the first functional device 211 is the device in the first functional unit 217 that is closest to the second functional unit 218 along the first direction, and the second functional device 212 is the device in the second functional unit 218 that is closest to the first functional unit 217 along the opposite direction of the first direction. However, this does not constitute a limitation on this application. In some embodiments, the first functional device 211 may be a trigger 1 in the first functional unit 217, or it may be another device in the first functional unit 217. The second functional device 212 may be a trigger 2 in the second functional unit 218, or it may be another device in the second functional unit 218.

[0149] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A packaging structure, characterized in that, include: The first chip includes a first device layer, a first metal layer and a second metal layer stacked in sequence, and the first device layer includes at least two functional units. The second chip is located on one side of the first chip. The second chip includes a second device layer, which includes at least two functional units. The number of functional units in the first device layer is less than the number of functional units in the second device layer. The second device layer includes a first functional device and a second functional device. The first functional device and the second functional device belong to the same functional unit or different functional units. Both the first functional device and the second functional device are electrically connected to the first metal layer.

2. The packaging structure according to claim 1, characterized in that, The packaging structure further includes a bonding layer located between the first chip and the second chip, the bonding layer including a first conductive structure and a second conductive structure; The first functional device is electrically connected to the first conductive structure, the second functional device is electrically connected to the second conductive structure, and both the first conductive structure and the second conductive structure are electrically connected to the first metal layer.

3. The packaging structure according to claim 2, characterized in that, The first metal layer includes a first metal wire, and both the first conductive structure and the second conductive structure are electrically connected to the first metal wire.

4. The packaging structure according to claim 3, characterized in that, The second chip further includes a third metal layer stacked on the second device layer, the third metal layer including a second metal line; The linewidth of the first metal wire is greater than the linewidth of the second metal wire.

5. The packaging structure according to claim 4, characterized in that, The third metal layer includes at least two of the second metal wires; The first metal layer also includes a third metal line that is closest to the first metal line; The distance between the first metal wire and the third metal wire is greater than the distance between any two adjacent second metal wires.

6. The packaging structure according to claim 4 or 5, characterized in that, The second device layer also includes a third functional device and a fourth functional device, both of which are electrically connected to the third metal layer.

7. The packaging structure according to any one of claims 3-6, characterized in that, The second device layer further includes a first driver device, one end of which is electrically connected to the first functional device, and the other end of which is electrically connected to the first conductive structure.

8. The packaging structure according to any one of claims 3-6, characterized in that, The first device layer includes a second driving device, one end of which is electrically connected to the first conductive structure at least through the first metal layer, and the other end of which is electrically connected to the second conductive structure at least through the first metal layer.

9. The packaging structure according to claim 8, characterized in that, The first device layer includes at least two second driving devices arranged sequentially along a first direction, where the first direction is the direction from the first functional device to the second functional device, and any two adjacent second driving devices are electrically connected at least through the first metal layer.

10. The packaging structure according to claim 9, characterized in that, One end of the second driving device closest to the first functional device is electrically connected to the second conductive structure at least through the first metal layer.

11. The packaging structure according to claim 9 or 10, characterized in that, One end of the second driving device closest to the second functional device is electrically connected to the adjacent second driving device at least through the first metal layer.

12. The packaging structure according to any one of claims 3-6, characterized in that, The second device layer also includes a third driving device, one end of which is electrically connected to the second conductive structure, and the other end of which is electrically connected to the second functional device.

13. An electronic device, characterized in that, The invention includes a circuit board and a packaging structure as described in any one of claims 1 to 12, wherein the packaging structure is disposed on the circuit board.

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