Solar cell and solar cell manufacturing method

Abstract

A solar cell and a solar cell manufacturing method, belonging to the technical field of solar cells. The present application can ensure that a doped polysilicon layer in a second region and doped ions in an underlying substrate are completely removed, thereby greatly reducing parasitic absorption, further improving battery efficiency, and also effectively avoiding short circuits caused by contact between a first region and non-first regions. In addition, on the one hand, sidewall pyramid bases having a large size can be obtained, such that the insulativity of the front surface and the back surface of the substrate can be improved, and further, electric leakage caused by residual PN junctions on edges can be effectively reduced, and on the other hand, the second region can obtain pyramid bases having a large size, which can not only improve the passivation effect, but also enhance the light absorption capacity, thereby improving the photoelectric conversion efficiency; and pyramid bases having a small size in the first region improve ohmic contact, thus achieving better photoelectric conversion efficiency.

Description

A solar cell and a method for preparing a solar cell

[0001] This application claims priority to Chinese Patent Application No. 202510106465.3, filed on January 22, 2025, entitled "A Solar Cell and an RCA Cleaning Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of solar cell technology, and in particular to a solar cell and a method for preparing a solar cell. Background Technology

[0003] The core of TOPCon (Tunnel Oxide Passivating Contact) battery's back-side polyfin technology lies in the presence of a doped polysilicon layer in the first region and an undoped polysilicon layer in the second region. This design significantly reduces parasitic absorption and carrier recombination in the first region, thereby improving battery efficiency. Traditional polyfin battery fabrication methods mainly involve forming a locally doped polysilicon layer to create a height difference between the first and second regions. Furthermore, to further improve conversion efficiency, steps involving forming different tower morphologies in different regions are also included. For example, patent CN116779694A discloses a method for fabricating a Topcon battery with a linear poly structure on the back side, using etching and localized coating to create the height difference, and employing a wet chemical cleaning method to form towers of different sizes in the first and second regions. Additionally, to improve leakage current, towers also need to be formed on the side of the substrate. For example, patent CN117334592A discloses a method for detecting edge leakage in Topcon solar cells. This method uses a wet chemical cleaning process to form a tower base on the side of the substrate, and the larger the tower base size, the better the improvement effect. Existing solar cells struggle to simultaneously meet the requirements for height differences and different tower base morphologies. Summary of the Invention

[0004] The purpose of this application is to provide a solar cell and a method for fabricating a solar cell, which can simultaneously achieve a height difference between a substrate in a first region and a substrate in a second region on the back side, and different base morphologies in the second region, the side, and the first region of the substrate.

[0005] To achieve the above objectives, this application provides a solar cell, comprising: a substrate; the back side of the substrate includes a first region and a second region, wherein at least a portion of the surface of the first region is provided with grid lines, and the second region does not have grid lines;

[0006] The first region has a first dielectric layer, a first doped polysilicon layer, a second dielectric layer, and a second doped polysilicon layer sequentially disposed from the substrate to the back surface along the thickness direction of the substrate; the second region has no dielectric layer or doped polysilicon layer disposed thereon; the substrate height of the second region is lower than the substrate height of the first region, thus forming a height difference H;

[0007] Tower bases are formed in the first region, the second region, and the side of the substrate; the width of the tower base in the second region of the substrate is greater than the width of the tower base on the side of the substrate, and the width of the tower base on the side of the substrate is greater than the width of the tower base in the first region of the substrate.

[0008] Optionally, the difference between the width of the second region tower base of the substrate and the width of the side tower base of the substrate is 3μm-20μm.

[0009] Optionally, the difference between the width of the side base of the substrate and the width of the first region base of the substrate is 2μm-17μm.

[0010] Optionally, the width of the side base of the substrate is 12μm-25μm, including the values ​​at both ends.

[0011] Optionally, the width of the second region of the substrate is 15μm-30μm, including the values ​​at both ends;

[0012] And / or, the width of the first region of the substrate is 8μm-10μm, including the values ​​at both ends.

[0013] Optionally, the height difference H between the first region and the second region is 0.5μm-6μm, including the values ​​at both ends.

[0014] To achieve the above objectives, this application also provides a method for preparing a solar cell, used in any one of the above-described methods, comprising:

[0015] First pre-cleaning process of substrate;

[0016] The first alkaline cleaning is performed to create a height difference H between the substrate in the second region on the back side of the substrate and the substrate in the first region, and to form a tower-based structure in the first region, the second region and the side of the substrate; wherein, the first alkaline cleaning uses a first mixed solution, including 2%-4% NaOH and 1%-1.5% additives, the temperature of the first mixed solution is 65℃-70℃, and the cleaning time is 250s-500s;

[0017] A second alkaline cleaning is performed to make the width of the side column base of the substrate greater than the width of the first region column base of the substrate;

[0018] A third alkaline cleaning is performed to make the width of the second region base of the substrate greater than the width of the side base of the substrate;

[0019] Post-cleaning process; emitter fabrication process; gate line fabrication process.

[0020] Optionally, the second alkaline cleaning uses a second mixture comprising 1%-1.5% sodium hydroxide and 2%-4% hydrogen peroxide, and including the values ​​at both ends; the temperature of the second mixture is 60℃-65℃, and including the values ​​at both ends; the cleaning time of the second mixture is 90s-120s, and including the values ​​at both ends.

[0021] Optionally, the third alkaline cleaning uses a third mixture comprising 1%-1.5% sodium hydroxide and 2%-4% hydrogen peroxide, and including the values ​​at both ends; the temperature of the third mixture is 60℃-65℃, and including the values ​​at both ends; the cleaning time of the third mixture is 90s-120s, and including the values ​​at both ends.

[0022] Optionally, a second pre-cleaning process may be performed before the third alkaline cleaning.

[0023] Obviously, in the solar cell provided by this application, the substrate height of the second region is lower than that of the substrate height of the first region, creating a height difference. This ensures complete removal of doped ions from the polycrystalline silicon layer in the second region and the underlying substrate, thereby significantly reducing parasitic absorption and improving cell efficiency. It also effectively avoids short circuits caused by contact between the first and non-first regions. Furthermore, the width of the second region's base plate is greater than the width of the side base plates, which in turn is greater than the width of the first region's base plate. This results in larger side base plates, improving insulation on both the front and back sides of the substrate and effectively reducing leakage current caused by residual edge PN junctions. The larger base plate in the second region also improves passivation and light absorption, thus increasing photoelectric conversion efficiency. The smaller base plate in the first region improves ohmic contact, resulting in better photoelectric conversion efficiency. This application also provides a method for fabricating a solar cell with the aforementioned beneficial effects. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 is a schematic diagram of a solar cell provided in an embodiment of this application;

[0026] Figure 2 is a test diagram of the height difference between the first and second regions on the back side provided in an embodiment of this application;

[0027] Figure 3 is a schematic diagram of the structure of the boundary region between the first and second regions on the back side provided in an embodiment of this application;

[0028] Figure 4 is a schematic diagram of the height difference structure between the first and second regions on the back side provided in an embodiment of this application;

[0029] Figure 5 is a partially enlarged schematic diagram of the side tower base morphology provided in an embodiment of this application;

[0030] Figure 6 is a schematic diagram of the side profile of a tower base provided in an embodiment of this application;

[0031] Figure 7 is a schematic diagram of the morphology of the second region of the tower base on the back side provided in an embodiment of this application;

[0032] Figure 8 is a schematic diagram of the topography of the first region of the tower base on the back side provided in an embodiment of this application;

[0033] Figures 9 and 10 are schematic diagrams of the side tower base morphology of a traditional Polyfin battery.

[0034] The reference numerals in the attached figures are explained as follows: 11-Substrate; 12-Emitter; 13-Front-side passivation layer; 14-Antireflection layer; 15-Front-side gate line; 161-First dielectric layer; 171-First doped polysilicon layer; 162-Second dielectric layer; 171-Second doped polysilicon layer; 18-Back passivation layer; 19-Internal reflection layer; 20-Back gate line. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] Please refer to Figure 1, which is a schematic diagram of the structure of a solar cell provided in an embodiment of this application. The solar cell may include: a substrate 11; the back side of the substrate 11 includes a first region and a second region, the surface of the first region is at least partially provided with grid lines, and the second region does not have grid lines.

[0037] The first region has a first dielectric layer 161, a first doped polysilicon layer 171, a second dielectric layer 162, and a second doped polysilicon layer 172 sequentially disposed from the substrate 11 to the back surface along the thickness direction of the substrate 11; the second region has no dielectric layer or doped polysilicon layer disposed there; the height of the substrate 11 in the second region is lower than the height of the substrate 11 in the first region, so that a height difference H is formed.

[0038] Tower bases are formed in the first region, the second region, and the side of the substrate 11; the width of the tower base in the second region of the substrate 11 is greater than the width of the tower base on the side of the substrate 11; the width of the tower base on the side of the substrate 11 is greater than the width of the tower base in the first region of the substrate 11.

[0039] It should be noted that in this embodiment, the thickness direction of the substrate 11 refers to the direction perpendicular to the surface of the substrate 11, i.e., the X direction in Figure 1.

[0040] It should be noted that in this embodiment, the outline of the tower base is a quadrilateral-like structure, and there are several quadrilateral-like structures superimposed. After superposition, a polygon-like structure exists on the two-dimensional surface. Due to the different angles and numbers of the superimposed quadrilateral-like structures, the polygon-like structures formed on the two-dimensional surface are irregular polygon-like shapes. The length of the longest side of the quadrilateral-like and polygon-like structures is defined as the width of the tower base. In this embodiment, the width of the tower base is the average of the widths of several tower bases. For example, it can be the average of the average widths of the tower bases in several regions of fixed size.

[0041] In this embodiment, the height difference H between the first region and the second region can be 0.5μm-6μm, including the values ​​at both ends. Preferably, in this embodiment, the height difference H between the first region and the second region can be 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm…5.8μm, 5.9μm or 6μm.

[0042] In this embodiment, the difference between the width of the second region base of the substrate 11 and the width of the side base of the substrate 11 can be 3μm-20μm. Preferably, in this embodiment, the difference between the width of the second region base of the substrate 11 and the width of the side base of the substrate 11 can be 3μm, 4μm, 5μm, 6μm, 7μm...18μm, 19μm or 20μm.

[0043] In this embodiment, the difference between the width of the side base of the substrate 11 and the width of the first region base of the substrate 11 can be 2μm-17μm. Preferably, in this embodiment, the difference between the width of the side base of the substrate 11 and the width of the first region base of the substrate 11 can be 2μm, 3μm, 4μm, 5μm, 6μm, 7μm...18μm, 19μm or 20μm.

[0044] The width of the second region tower base of substrate 11 has a suitable difference from the width of the side tower base of substrate 11 and the width of the side tower base of substrate 11 has a suitable difference from the width of the first region tower base of substrate 11, so that the solar cell has a good passivation effect and a good light absorption capacity, thereby improving the photoelectric conversion efficiency and performance of the solar cell.

[0045] In this embodiment, the width of the side base of the substrate 11 can be 12μm-25μm, including the values ​​at both ends. Preferably, in this embodiment, the width of the side base of the substrate 11 can be 12μm, 13μm, 14μm, 15μm, 16μm, 17μm...23μm, 24μm or 25μm.

[0046] In this embodiment, the width of the second region base of the substrate 11 can be 15μm-30μm, including the values ​​at both ends. Preferably, the width of the second region base of the substrate 11 in this embodiment can be 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm…28μm, 29μm or 30μm.

[0047] In this embodiment, the width of the first region of the substrate 11 can be 8μm-10μm, including the values ​​at both ends. Preferably, in this embodiment, the width of the first region of the substrate 11 can be 8μm, 9μm, or 10μm.

[0048] The appropriate tower base dimensions of the first region, second region, and side of the substrate in this application effectively avoid lattice defects and stress in the solar cell, while giving the solar cell good light absorption capability, resulting in good photoelectric conversion efficiency and cell performance.

[0049] Preferably, in this embodiment, the height difference H between the first region and the second region can be 3 μm. In this embodiment, the width of the side base of the substrate 11 can be 20 μm. It should be noted that in this embodiment, when the height difference H between the first region and the second region is 3 μm, the width of the side base of the substrate 11 can reach 20 μm. At the same time, it can also ensure that the second region obtains a base with a width greater than 20 μm, and the first region obtains a base with a width less than 20 μm. This can ensure the complete removal of doped ions from the polysilicon layer in the second region and the underlying substrate 11, as well as better insulation of the front and back sides of the substrate 11, better passivation effect in the second region, and better ohmic contact in the first region.

[0050] This embodiment does not limit the specific type of substrate 11; substrate 11 can be, but is not limited to, an N-type substrate or a P-type substrate. This embodiment does not limit the specific type of substrate 11; substrate 11 can be, but is not limited to, a silicon substrate. This embodiment does not limit the specific thickness of substrate 11; for example, the thickness of substrate 11 can be 100μm-200μm, including the values ​​at both ends. Preferably, in this embodiment, the thickness of substrate 11 can be 100μm, 101μm, 102μm, 103μm, 104μm…198μm, 199μm, or 200μm.

[0051] This embodiment does not limit the specific types of the first dielectric layer 161 and the second dielectric layer 162. The first dielectric layer 161 and the second dielectric layer 162 can be any one of silicon oxide layer, silicon nitride layer, aluminum oxide layer and silicon oxynitride layer.

[0052] This embodiment does not limit the specific types of the first doped polysilicon layer 171 and the second doped polysilicon layer 172. The specific types of the first doped polysilicon layer 171 and the second doped polysilicon layer 172 can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the first doped polysilicon layer 171 and the second doped polysilicon layer 172 can be N-type doped polysilicon layers; when the substrate 11 is a P-type substrate, the first doped polysilicon layer 171 and the second doped polysilicon layer 172 can be P-type doped polysilicon layers. The N-type doped polysilicon layer contains N-type impurities, and the P-type doped polysilicon layer contains P-type impurities.

[0053] Furthermore, in this embodiment, both the surface of the second doped polysilicon layer 172 away from the second dielectric layer 162 and the second region can be provided with a back passivation layer 18 to improve the passivation effect; the surface of the back passivation layer 18 away from the substrate 11 can be provided with an inner reflection layer 19 to reduce light reflection; the surface of the inner reflection layer 19 away from the back passivation layer 18 can be provided with a back gate line 20, and the back gate line 20 sequentially penetrates the inner reflection layer 19, the back passivation layer 18, the second doped polysilicon layer 172 and the second dielectric layer 162 along the thickness direction, and contacts the first doped polysilicon layer 171.

[0054] This embodiment does not limit the specific type of the back passivation layer 18, which may include, but is not limited to, an aluminum oxide layer. This embodiment does not limit the specific type of the inner reflective layer 19, which may include, but is not limited to, a silicon nitride layer. This embodiment does not limit the specific type of the back gate line 20, which may be, but is not limited to, a metal gate line.

[0055] Furthermore, in this embodiment, the front side of the substrate 11 may include a first region and a second region. The surface of the first region is at least partially provided with gate lines, while the second region does not have gate lines. An emitter 12 may be provided on the front side of the substrate 11. The emitter 12 may include: the first region having a first dielectric layer, a first doped polysilicon layer, a second dielectric layer, and a second doped polysilicon layer sequentially disposed from the substrate 11 toward the front surface along the thickness direction of the substrate 11; and the second region not having a dielectric layer and a doped polysilicon layer disposed.

[0056] Furthermore, a front passivation layer 13 can be provided on the surface of the emitter 12 away from the substrate 11 to improve the passivation effect; an anti-reflection layer 14 can be provided on the surface of the front passivation layer 13 away from the emitter 12 to reduce light reflection; a front gate line 15 can be provided on the surface of the anti-reflection layer 14 away from the front passivation layer 13, and the front gate line 15 passes through the anti-reflection layer 14 and the front passivation layer 13 sequentially along the thickness direction and contacts the emitter 12.

[0057] This embodiment does not limit the specific type of emitter 12. The specific type of emitter 12 can be determined according to the specific type of substrate 11. For example, when substrate 11 is an N-type substrate, emitter 12 can be a P-type emitter; when substrate 11 is a P-type substrate, emitter 12 can be an N-type emitter. In this embodiment, the P-type emitter is doped with P-type impurities, and the N-type emitter is doped with N-type impurities.

[0058] This embodiment does not limit the specific type of the front passivation layer 13, which may include, but is not limited to, an aluminum oxide layer. This embodiment does not limit the specific type of the antireflection layer 14, which may include, but is not limited to, a silicon nitride layer. This embodiment does not limit the specific type of the front gate line 15, which may be, but is not limited to, a metal gate line.

[0059] Furthermore, in order to improve the light trapping effect of the front side of the substrate 11, the front side of the substrate 11 in this embodiment may have a pyramidal textured surface.

[0060] Based on the above embodiments, the substrate height of the second region in this application is lower than that of the substrate height of the first region, creating a height difference. This ensures complete removal of doped ions from the polysilicon layer and the underlying substrate in the second region, thereby significantly reducing parasitic absorption and improving battery efficiency. Simultaneously, it effectively avoids short circuits caused by contact between the first and non-first regions. Furthermore, the width of the second region's base plate is greater than the width of the side base plate, which in turn is greater than the width of the first region's base plate. This results in a larger side base plate, improving insulation on both the front and back sides of the substrate and effectively reducing leakage caused by residual edge PN junctions. The larger base plate in the second region also enhances passivation and light absorption, thus improving photoelectric conversion efficiency. The smaller base plate in the first region improves ohmic contact, resulting in better photoelectric conversion efficiency.

[0061] This application also provides a method for fabricating a solar cell, which can be used for the above-mentioned solar cell fabrication, including:

[0062] S11: First pre-cleaning process of substrate.

[0063] It should be noted that the purpose of step S11 in this embodiment is to prepare for subsequent polishing. This embodiment does not limit the specific process of the first pre-cleaning process, and may include, but is not limited to, placing the substrate to be cleaned in HF for the first acid wash to obtain a substrate 11 with the oxide layers on the front and side surfaces of the substrate to be cleaned removed.

[0064] S12: First alkaline cleaning to create a height difference H between the substrate in the second region on the back side of the substrate and the substrate in the first region, and to form a tower base structure in the first region, the second region and the side of the substrate; wherein, the first alkaline cleaning uses a first mixed solution, including 2%-4% NaOH and 1%-1.5% additives, the temperature of the first mixed solution is 65℃-70℃, and the cleaning time is 250s-500s.

[0065] S13: Second alkaline cleaning to make the width of the side column base of the substrate greater than the width of the first region column base of the substrate.

[0066] This embodiment does not limit the specific process conditions of the second alkaline cleaning. For example, the second alkaline cleaning can use a second mixture, which includes sodium hydroxide with a concentration of 1%-1.5% and hydrogen peroxide with a concentration of 2%-4%, and includes the values ​​at both ends; the temperature of the second mixture is 60℃-65℃, and includes the values ​​at both ends; the cleaning time of the second mixture is 90s-120s, and includes the values ​​at both ends.

[0067] S14: Third alkaline cleaning to make the width of the second region base of the substrate greater than the width of the side base of the substrate.

[0068] This embodiment does not limit the specific process conditions of the third alkaline cleaning. For example, the third alkaline cleaning can use a third mixture, which includes sodium hydroxide with a concentration of 1%-1.5% and hydrogen peroxide with a concentration of 2%-4%, and includes the values ​​at both ends; the temperature of the third mixture is 60℃-65℃, and includes the values ​​at both ends; the cleaning time of the third mixture is 90s-120s, and includes the values ​​at both ends.

[0069] Furthermore, in this embodiment, a second pre-cleaning process can be performed before the third alkaline cleaning. It should be noted that the purpose of the second pre-cleaning process in this embodiment is to remove the remaining oxide layer and neutralize the alkaline solution. This embodiment does not limit the specific process of the second pre-cleaning process, and it may include, but is not limited to, placing the substrate 11 in an acid bath for a second acid wash to remove the remaining oxide layer, neutralizing the alkaline solution, and then rinsing with deionized water.

[0070] S15: Post-cleaning process; emitter fabrication process; gate line fabrication process.

[0071] It should be noted that the purpose of the post-cleaning process in this embodiment is to remove impurities adhering to the surface. This embodiment does not limit the specific process of the post-cleaning process, and it may include, but is not limited to, the following:

[0072] The substrate 11 was placed in an acid bath for a third acid wash, and then rinsed with deionized water.

[0073] The substrate 11 is rinsed;

[0074] The substrate 11 is dried and ready for use.

[0075] This embodiment does not limit the specific process of the emitter preparation procedure, as long as the emitter 12 in the above embodiment can be formed.

[0076] This embodiment does not limit the specific process of the gate line fabrication step, as long as the gate lines in the above embodiment can be formed.

[0077] Based on the above embodiments, the process parameters used for cleaning the substrate in this application are a mixture of 2%-4% NaOH and 1%-1.5% additives, with a temperature of 65℃-70℃ and a cleaning time of 250s-500s. Simultaneously, the second backside region is etched while cleaning the decoupling. By controlling at least two process parameters, a height difference can be simultaneously achieved between the first and second regions, with the substrate height in the second region being lower than that in the first region. Furthermore, the width of the base in the second region can be increased, and a base can be formed on the side of the substrate. The width of the base in the second region is greater than the width of the base on the side of the substrate, and the width of the base on the side of the substrate is greater than the width of the base in the first region. The process is simplified and can achieve the following simultaneously: (1) Ensure complete removal of doped ions from the second region polysilicon layer and the bottom substrate, thereby greatly reducing parasitic absorption and improving battery efficiency, while effectively avoiding short circuits caused by contact between the first region and non-first region; (2) Obtain a larger side base, thereby improving the insulation of the front and back sides of the substrate, thereby effectively reducing leakage caused by residual edge PN junctions; The larger base in the second region not only improves the passivation effect but also improves the light absorption capacity, thereby improving the photoelectric conversion efficiency; The smaller base in the first region improves the ohmic contact, giving it better photoelectric conversion efficiency.

[0078] This application also provides another RCA cleaning method, which can be used in the above-mentioned solar cell fabrication, including:

[0079] S21: Place the substrate to be cleaned in HF and perform the first acid wash to obtain the first substrate with the oxide layers on the front and side surfaces of the substrate to be cleaned removed.

[0080] It should be noted that in this embodiment, step S21 is performed in an acid pickling tank, and the purpose of this step is to prepare for subsequent polishing.

[0081] In this embodiment, the substrate to be cleaned includes at least the following: a first dielectric layer 161, a first doped polysilicon layer 171, a second dielectric layer 162, a second doped polysilicon layer 172, and a first impurity oxide layer are sequentially disposed along the thickness direction on the front, back, and side surfaces of the substrate to be cleaned.

[0082] It should be noted that, in this embodiment, a substrate to be cleaned needs to be provided before step S1. This embodiment does not limit the specific method of providing the substrate to be cleaned; the specific method can be determined according to the specific structure of the solar cell required. For example, the following methods can be used:

[0083] An emitter 12 and a second impurity oxide layer are formed sequentially from the substrate 11 to the front surface along the thickness direction, and the second impurity layer is deposited around the side of the substrate 11.

[0084] After the front side of the substrate 11 is processed, a first dielectric layer 161, a first doped polysilicon layer 171, a second dielectric layer 162, a second doped polysilicon layer 172, and a first impurity oxide layer are formed on the back side of the substrate 11 in sequence along the thickness direction from the substrate 11 to the back surface. The first dielectric layer 161, the first doped polysilicon layer 171, the second dielectric layer 162, the second doped polysilicon layer 172, and the first impurity oxide layer are all deposited around the side and front side of the substrate 11 to obtain the substrate to be cleaned.

[0085] Accordingly, in this embodiment, the oxide layers on the front and side of the substrate to be cleaned removed in step 1 specifically include: a first impurity oxide layer plated around the front of the substrate to be cleaned, and a first impurity oxide layer and a second impurity oxide layer plated around the side of the substrate to be cleaned.

[0086] Accordingly, the remaining oxide layer removed in step 4 of this embodiment specifically includes: a first impurity oxide layer in the first region on the back side of the third substrate, and a second impurity oxide layer on the front side of the third substrate.

[0087] Furthermore, in order to improve the light trapping effect on the front side of the substrate 11, this embodiment forms an emitter 12 and a second impurity oxide layer arranged sequentially from the substrate 11 to the front surface along the thickness direction on the front side of the substrate 11, and the second impurity layer is deposited around the side of the substrate 11. It may also include forming a pyramid textured surface on the front side of the substrate 11.

[0088] It should be noted that in this embodiment, the emitter 12 is generally formed on the front side of the substrate 11 by impurity diffusion. During the impurity diffusion process, a second impurity oxide layer is formed on the surface of the emitter 12 away from the substrate 11. This embodiment does not limit the specific type of the second impurity oxide layer. The specific type of the second impurity oxide layer can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the second impurity oxide layer can be a P-type oxide layer; when the substrate 11 is a P-type substrate, the second impurity oxide layer can be an N-type oxide layer. The P-type oxide layer may include, but is not limited to, a BSG (Borosilicate Glass) layer; the N-type oxide layer may include, but is not limited to, a PSG (Phosphorosilicate Glass) layer.

[0089] It should be noted that in this embodiment, the first doped polysilicon layer 171 and the second doped polysilicon layer 172 are generally formed by impurity diffusion. During the impurity diffusion process, a first impurity oxide layer is formed on the surface of the second doped polysilicon layer 172 facing away from the second dielectric layer 162. This embodiment does not limit the specific type of the first impurity oxide layer. The specific type of the first impurity oxide layer can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the first impurity oxide layer can be an N-type oxide layer; when the substrate 11 is a P-type substrate, the first impurity oxide layer can be a P-type oxide layer.

[0090] It should be noted that in this embodiment, alkaline polishing is performed before step S21. This process forms a base in both the first and second regions of the substrate 11. Therefore, before RCA cleaning, the first and second regions of the substrate to be cleaned already have bases of the same or approximately the same width. When the substrate to be cleaned is subsequently subjected to RCA cleaning, the surface of the base in the first region is covered with films such as the first dielectric layer 161, the first doped polysilicon layer 171, the second dielectric layer 162, and the second doped polysilicon layer 172, so it is not affected by the corrosion of the RCA cleaning solution, and the width of the base remains unchanged. However, the base in the second region is more affected by the corrosion of the RCA cleaning solution, and the width of the base will increase. This change in the width of the base is formed by the corrosion of the second region of the substrate during the formation of the side base in the RCA cleaning process.

[0091] S22: The first substrate is placed in a first mixed solution for cleaning. The first mixed solution includes 2%-4% NaOH and 1%-1.5% additives. The temperature of the first mixed solution is 65℃-70℃ and the cleaning time is 250s-500s, so that a height difference H is formed between the substrate in the second region on the back side of the first substrate and the substrate in the first region, and a tower base is formed on the side of the first substrate to obtain the second substrate. Then, it is rinsed with deionized water.

[0092] It should be noted that, in this embodiment, before step S22, a laser is used to irradiate the second region on the back side of the first substrate to remove the first impurity oxide layer in the second region. Laser irradiation removes only the first impurity oxide layer in the second region, while retaining the first impurity oxide layer in the first region. During subsequent cleaning, this first impurity oxide layer in the first region can protect the surface of the second doped polysilicon layer 172 in the first region.

[0093] It should be noted that the purpose of cleaning in the first mixed solution in this embodiment is to remove the second doped polysilicon layer 172, the second dielectric layer 162, the first doped polysilicon layer 171, the first dielectric layer 161 and part of the substrate 11 in the second region, as well as the second doped polysilicon layer 172, the second dielectric layer 162, the first doped polysilicon layer 171 and the first dielectric layer 161 on the front and sides of the substrate 11. This can create a height difference H between the substrate 11 in the first region and the substrate 11 in the second region on the back side of the first substrate, and the height of the substrate 11 in the second region is lower than the height of the substrate 11 in the first region. At the same time, it can increase the width of the tower base in the second region and form a tower base on the side of the substrate 11. The width of the tower base in the second region of the substrate 11 is greater than the width of the tower base on the side of the substrate 11, and the width of the tower base on the side of the substrate 11 is greater than the width of the tower base in the first region of the substrate. This step can be performed in the polysilicon removal tank.

[0094] It should be noted that in this embodiment, the concentration of NaOH can be 2%-4%, including both values; the concentration of the additive can be 1%-1.5%, including both values; the temperature of the first mixture can be 65℃-70℃, including both values; and the cleaning time can be 250s-500s, including both values. This embodiment, by controlling at least two process parameters, can simultaneously achieve a suitable height difference between the substrate 11 in the first region and the substrate 11 in the second region, and control the tower base morphology of the second region and the sides of the substrate 11, ensuring that the tower base morphology of each region meets the requirements.

[0095] Preferably, in this embodiment, the concentration of NaOH can be 4.2%; the concentration of the additive can be 1.04%; the temperature of the first mixture can be 68°C; the cleaning time can be 400s; correspondingly, the height difference H between the first region and the second region can be 3μm; and the width of the side column base of the substrate 11 can be 20μm. It should be noted that the preferred process parameter formulation in this embodiment, compared to the traditional formulation, increases the concentration of NaOH, decreases the concentration of the additive, increases the temperature, and increases the cleaning time. Through this process parameter formulation, the optimal height difference H between the first region and the second region, as well as the optimal column base dimensions of the first region, the second region, and the side column base of the substrate 11, can be obtained simultaneously.

[0096] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the residual NaOH on the surface of the second substrate; this step is performed in a water rinsing tank.

[0097] S23: The second substrate is placed in a second mixture for cleaning, the second mixture including alkaline solution and hydrogen peroxide, to obtain a third substrate, which is then rinsed with deionized water.

[0098] It should be noted that the purpose of using the second mixture for cleaning in this embodiment is to remove residual dirt on the surface of the second substrate; this step is performed in the post-cleaning tank.

[0099] In this embodiment, the alkaline solution in the second mixture can be NaOH with a concentration of 1%-1.5%, including both values. Preferably, the concentration of NaOH in this embodiment can be 1%, 1.1%, 1.2%, 1.3%, 1.4%, or 1.5%. The concentration of hydrogen peroxide in the second mixture in this embodiment can be 2%-4%, including both values. Preferably, the concentration of hydrogen peroxide in this embodiment can be 2%, 3%, or 4%. The temperature of the second mixture in this embodiment can be 60℃-65℃, including both values. Preferably, the temperature of the second mixture in this embodiment can be 60℃, 61℃, 62℃, 63℃, 64℃, or 65℃. Preferably, the cleaning time of the second mixture in this embodiment can be 90s-120s, including both values.

[0100] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the second mixture remaining on the surface of the third substrate; this step is performed in a water washing tank.

[0101] S24: The third substrate is placed in an acid bath for a second acid wash to remove the remaining oxide layer, neutralize the alkaline solution to obtain the fourth substrate, and then rinse with deionized water.

[0102] In this embodiment, the second pickling can use HF, and the concentration of HF can be 10%-15%, including both values. Preferably, the concentration of HF in this embodiment can be 10%, 11%, 12%, 13%, 14%, or 15%. Preferably, the temperature of HF in this embodiment can be room temperature. Preferably, the cleaning time of HF in this embodiment can be 100s-130s, including both values.

[0103] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the acid solution remaining on the surface of the fourth substrate; this step is performed in a water rinsing tank.

[0104] S25: The fourth substrate is placed in the third mixture for cleaning. The third mixture includes alkaline solution and hydrogen peroxide to obtain the fifth substrate, which is then rinsed with deionized water.

[0105] It should be noted that the purpose of using the third mixed solution for cleaning in this embodiment is to rinse away residual dirt on the surface of the fourth substrate; this step is performed in the post-cleaning tank.

[0106] In this embodiment, the alkaline solution in the third mixture can be NaOH with a concentration of 1%-1.5%, including both ends of the concentration range. Preferably, the concentration of NaOH in this embodiment can be 1%, 1.1%, 1.2%, 1.3%, 1.4%, or 1.5%. The concentration of hydrogen peroxide in the third mixture in this embodiment can be 2%-4%, including both ends of the concentration range. Preferably, the concentration of hydrogen peroxide in this embodiment can be 2%, 3%, or 4%. The temperature of the third mixture in this embodiment can be 60℃-65℃, including both ends of the temperature range. Preferably, the temperature of the third mixture in this embodiment can be 60℃, 61℃, 62℃, 63℃, 64℃, or 65℃. Preferably, the cleaning time of the third mixture in this embodiment can be 90s-120s, including both ends of the temperature range.

[0107] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the third mixture remaining on the surface of the fifth substrate; this step is performed in a water washing tank.

[0108] S26: Place the fifth substrate in an acid bath for a third acid wash to obtain the sixth substrate, and then rinse with deionized water.

[0109] Furthermore, in this embodiment, after rinsing with deionized water to remove desorbed impurities and residual hydrogen peroxide on the surface of substrate 11, the process may further include:

[0110] It should be noted that the purpose of the third acid wash in this embodiment is to clean the impurities attached to the surface of the fifth substrate.

[0111] In this embodiment, the third pickling can use HF, and the concentration of HF can be 10%-15%, including both values. Preferably, the concentration of HF in this embodiment can be 10%, 11%, 12%, 13%, 14%, or 15%. Preferably, the temperature of HF in this embodiment can be room temperature. Preferably, the cleaning time of HF in this embodiment can be 100s-130s, including both values.

[0112] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the acid solution remaining on the surface of the sixth substrate; this step is performed in a water rinsing tank.

[0113] S27: Rinse the sixth substrate to obtain the seventh substrate.

[0114] It should be noted that the purpose of step S27 in this embodiment is to rinse away the impurities attached to the surface of the sixth substrate.

[0115] Preferably, in this embodiment, the sixth substrate can be rinsed using a slow-pull method; this step is performed in a slow-pull groove.

[0116] S28: Dry the seventh substrate and set it aside for later use.

[0117] It should be noted that in this embodiment, after completing step S28, the subsequent process of battery cell fabrication is carried out.

[0118] Preferably, in this embodiment, CDA (Compressed Dry Air) is used to dry the seventh substrate using high temperature and hot air in the drying tank; the high temperature can be 90℃-100℃, including both ends.

[0119] Furthermore, this embodiment may further include the following after step S28:

[0120] A back passivation layer 18 is formed on both the surface of the second doped polysilicon layer 172 away from the second dielectric layer 162 and in the second region to improve the passivation effect.

[0121] An inner reflective layer 19 is formed on the surface of the back passivation layer 18 that is away from the substrate 11 to reduce light reflection;

[0122] A back gate line 20 is formed on the surface of the inner reflective layer 19 away from the back passivation layer 18, and the back gate line 20 sequentially penetrates the inner reflective layer 19, the back passivation layer 18, the second doped polysilicon layer 172 and the second dielectric layer 162 along the thickness direction, and contacts the first doped polysilicon layer 171.

[0123] Furthermore, this embodiment may also include the following steps after step S28:

[0124] A passivation layer 13 is formed on the surface of the emitter 12 away from the substrate 11 to improve the passivation effect;

[0125] An anti-reflection layer 14 is formed on the surface of the passivation layer 13 facing away from the emitter 12 to reduce light reflection;

[0126] A front gate line 15 is formed on the surface of the antireflection layer 14 away from the front passivation layer 13, and the front gate line 15 passes through the antireflection layer 14 and the front passivation layer 13 sequentially along the thickness direction and contacts the emitter 12.

[0127] Based on the above embodiments, this application can simultaneously achieve the formation of a height difference between the first region and the second region, with the substrate height of the second region being lower than that of the first region, as well as increasing the width of the tower base in the second region and forming a tower base on the side of the substrate, with the width of the tower base in the second region of the substrate being greater than the width of the tower base on the side of the substrate, and the width of the tower base on the side of the substrate being greater than the width of the tower base in the first region of the substrate. This simplifies the process flow and can simultaneously achieve: (1) ensuring complete removal of doped polysilicon layers and doped ions in the bottom substrate of the second region, thereby greatly reducing parasitic absorption and improving battery efficiency, while effectively avoiding short circuits caused by contact between the first region and non-first region; (2) obtaining a larger side tower base, thereby improving the insulation of the front and back sides of the substrate, thereby effectively reducing leakage caused by residual edge PN junctions; obtaining a larger tower base in the second region can not only improve the passivation effect but also improve the light absorption capacity, thereby improving the photoelectric conversion efficiency; the smaller tower base in the first region improves the ohmic contact, giving it better photoelectric conversion efficiency.

[0128] In addition, the finished solar cells provided in this embodiment were compared and verified with different height differences. The electrical performance of the solar cells with different height differences was tested by a screen printing tester. The efficiency data of the solar cells are shown in Table 1. The electrical performance parameters of the cells include: conversion efficiency (represented by Eta), open circuit voltage (represented by Voc), short circuit current (represented by Isc), fill factor (represented by FF), series resistance (represented by Rs), parallel resistance (represented by Rsh), and reverse current at -10V (represented by Irev10). The height difference test diagram of the first and second regions on the back is shown in Figure 2. The structure of the boundary region between the first and second regions on the back is shown in Figure 3. The height difference structure of the first and second regions on the back is shown in Figure 4.

[0129] Table 1. Efficiency data of solar cells

[0130] The height difference H between the first and second regions in this application ranges from 0.5 μm to 6 μm. In this embodiment, a solar cell with a height difference H of 0.3 μm between the first and second regions is used as a control group. As can be seen from Table 1, the efficiency of this control group is relatively low; while when the height difference H range between the first and second regions provided in this application is used, the efficiency is higher, with the optimal efficiency achieved when the height difference H between the first and second regions is 3 μm.

[0131] Under the process parameters of forming a 3μm height difference: 4.2% NaOH concentration and 1.04% additive concentration, temperature of 68℃ and cleaning time of 400s (compared to the original formulation, the NaOH concentration was increased, the additive concentration was decreased, the temperature was increased, and the cleaning time was increased), the width of the side column base is 20μm. The morphology of the side column base is shown in Figures 5 and 6. It can be seen from Figures 5 and 6 that the edge etching is more complete, and the front and back sides of the substrate are more insulating. In addition, as shown in Figures 7 and 8, column bases are formed in both the second and first regions on the back side, and the size of the column base in the second region is larger than the size of the column base on the side of the substrate 11, which is larger than the size of the column base in the first region.

[0132] Figures 9 and 10 show the side column morphology of a conventional Polyfin battery under the original formulation (i.e., the formulation before changes to the concentration of NaOH, the concentration of additives, the temperature, and the cleaning time): 3.7% NaOH and 1.3% additives, a temperature of 65°C, and a cleaning time of 290s. The width of the column is about 10μm.

[0133] The base size of this embodiment is larger than that of a traditional Polyfin battery, which can further improve the insulation of the front and back sides and more effectively reduce leakage caused by residual edge PN junctions.

[0134] In addition, the dark current of the finished solar cell provided in this embodiment was verified. Both experimental groups were finished solar cells provided in this embodiment. The conditions for experimental group 1 were: 3.7% NaOH and 1.3% additive, 65°C and 440s cleaning time; the conditions for experimental group 2 were: 3.7% NaOH and 1.3% additive, 65°C and 350s cleaning time. The difference between the two experimental groups was the process time. The control group was a non-Polyfind cell, using a conventional formula: 3.7% NaOH and 1.3% additive, 65°C and 290s cleaning time. The efficiency data of the obtained solar cells are shown in Table 2.

[0135] Table 2. Efficiency data of solar cells

[0136] As can be seen from Table 2, the Irev10 of both experimental groups was reduced compared to the control group: from 0.1A-0.2A to 0.04A. Obviously, this embodiment has a better leakage current improvement effect than the traditional Polyfin battery.

[0137] This document uses specific examples to illustrate the principles and implementation methods of this application. The various embodiments are progressive, with each embodiment focusing on its differences from others. Similar or identical parts between embodiments can be referred to interchangeably. The descriptions of the embodiments above are merely illustrative of the method and core ideas of this application. For those skilled in the art, various improvements and modifications can be made to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

[0138] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A solar cell, characterized in that, include: Substrate; the back side of the substrate includes a first region and a second region, wherein at least a portion of the surface of the first region is provided with gate lines, and the second region does not have gate lines; The first region has a first dielectric layer, a first doped polysilicon layer, a second dielectric layer, and a second doped polysilicon layer sequentially disposed from the substrate to the back surface along the thickness direction of the substrate; the second region has no dielectric layer or doped polysilicon layer disposed thereon; the substrate height of the second region is lower than the substrate height of the first region, thus forming a height difference H; Tower bases are formed in the first region, the second region, and the side of the substrate; the width of the tower base in the second region of the substrate is greater than the width of the tower base on the side of the substrate, and the width of the tower base on the side of the substrate is greater than the width of the tower base in the first region of the substrate.

2. The solar cell according to claim 1, characterized in that, The difference between the width of the second region tower base of the substrate and the width of the side tower base of the substrate is 3μm-20μm.

3. The solar cell according to claim 1, characterized in that, The difference between the width of the side base of the substrate and the width of the first region base of the substrate is 2μm-17μm.

4. The solar cell according to claim 1, characterized in that, The width of the side base of the substrate is 12μm-25μm, including the values ​​at both ends.

5. The solar cell according to claim 1, characterized in that, The width of the second region of the substrate is 15μm-30μm, including the values ​​at both ends; And / or, the width of the first region of the substrate is 8μm-10μm, including the values ​​at both ends.

6. The solar cell according to claim 1, characterized in that, The height difference H between the first region and the second region is 0.5μm-6μm, including the values ​​at both ends.

7. A method for preparing a solar cell, characterized in that, For the fabrication of the solar cell according to any one of claims 1 to 6, comprising: First pre-cleaning process of substrate; The first alkaline cleaning is performed to create a height difference H between the substrate in the second region on the back side of the substrate and the substrate in the first region, and to form a tower-based structure in the first region, the second region and the side of the substrate; wherein, the first alkaline cleaning uses a first mixed solution, including 2%-4% NaOH and 1%-1.5% additives, the temperature of the first mixed solution is 65℃-70℃, and the cleaning time is 250s-500s; A second alkaline cleaning is performed to make the width of the side column base of the substrate greater than the width of the first region column base of the substrate; A third alkaline cleaning is performed to make the width of the second region base of the substrate greater than the width of the side base of the substrate; Post-cleaning process; emitter fabrication process; gate line fabrication process.

8. The method for preparing a solar cell according to claim 7, characterized in that, The second alkaline cleaning uses a second mixture comprising 1%-1.5% sodium hydroxide and 2%-4% hydrogen peroxide, and including the values ​​at both ends; the temperature of the second mixture is 60℃-65℃, and including the values ​​at both ends; the cleaning time of the second mixture is 90s-120s, and including the values ​​at both ends.

9. The method for preparing a solar cell according to claim 7, characterized in that, The third alkaline cleaning uses a third mixture, which includes sodium hydroxide at a concentration of 1%-1.5% and hydrogen peroxide at a concentration of 2%-4%, and includes the values ​​at both ends; the temperature of the third mixture is 60℃-65℃, and includes the values ​​at both ends; the cleaning time of the third mixture is 90s-120s, and includes the values ​​at both ends.

10. The method for preparing a solar cell according to claim 7, characterized in that, Before the third alkaline cleaning, a second pre-cleaning process is performed.

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