Ray tracing method and apparatus, image processor and electronic device

By using identification information to indicate any node in the accelerated structure as the starting node for intersection calculation during ray tracing, the problem of high computational load in ray tracing is solved, achieving more efficient ray tracing and reduced power consumption.

WO2026157168A1PCT designated stage Publication Date: 2026-07-30HUAWEI TECH CO LTD
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
HUAWEI TECH CO LTD
Filing Date
2025-07-30
Publication Date
2026-07-30

AI Technical Summary

Technical Problem

Existing technologies involve a large computational load for intersection calculations during ray tracing, resulting in low ray tracing efficiency and high power consumption.

Method used

By obtaining ray information and identification information from the shader, the identification information is used to indicate any node (such as the root node, intermediate node, or leaf node) in the accelerated structure as the starting node for traversal and intersection calculation, thereby reducing the computational load and improving efficiency.

Benefits of technology

It reduces the computational load and power consumption of ray tracing and improves the generation efficiency of ray tracing.

✦ Generated by Eureka AI based on patent content.

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Abstract

A ray tracing method and apparatus, an image processor and an electronic device, relating to the technical field of image processing, used for reducing calculation load when performing intersection calculation on ray information in an acceleration structure, improving the efficiency of ray tracing, and reducing the power consumption of ray tracing apparatuses. The ray tracing method is applied to the ray tracing apparatus, and comprises: acquiring image information from a shader, the image information comprising ray information and identification information, the identification information being used for indicating a starting node for performing intersection calculation on the ray information in an acceleration structure, the acceleration structure being created on the basis of a scenario where the ray information is located, and the starting node being any node in the acceleration structure; starting from the starting node indicated by the identification information, performing traversal intersection calculation on the ray information in the acceleration structure to obtain an intersection result; and sending the intersection result to the shader, the intersection result being used for generating a target image in the scenario.
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Description

A ray tracing method, apparatus, graphics processor, and electronic device

[0001] This application claims priority to Chinese Patent Application No. 202510121227.X, filed on January 24, 2025, entitled “A Ray Tracing Method, Apparatus, Graphics Processor and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of graphics processing technology, and in particular to a ray tracing method, apparatus, graphics processor, and electronic device. Background Technology

[0003] In image rendering, ray tracing generates rendered images by simulating the propagation and interaction of light rays in a scene (i.e., interaction with objects in the scene). Traditional rasterization rendering discretizes continuous geometry into pixels and then colors these pixels to generate the rendered image. Ray tracing has gained widespread attention and application in the field of image processing due to its high-quality rendered images. Compared to traditional rasterization rendering, ray tracing requires significantly more computation. Currently, ray tracing computation is accelerated using application-specific integrated circuits (ASICs), specifically by accelerating the intersection calculation of multiple ray information during the ray tracing process to improve efficiency and shorten ray tracing time. However, the intersection calculation starts from the root node in the accelerated structure corresponding to the scene containing multiple ray information and performs intersection calculations with each ray information and all nodes in the accelerated structure, resulting in a large computational load.

[0004] Existing technologies can only reduce the computational load when calculating the intersection of local ray information; the computational load throughout the entire ray tracing process remains significant. Summary of the Invention

[0005] This application provides a ray tracing method, apparatus, graphics processor, and electronic device to reduce the computational load when performing intersection calculations on ray information in an accelerated structure, improve the efficiency of ray tracing, and reduce the power consumption of the ray tracing device.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] Firstly, a ray tracing method is provided, which is applied to a ray tracing device. The method includes: obtaining image information from a shader, the image information including ray information and identification information, wherein the identification information is used to indicate the starting node for intersecting the ray information in an accelerated structure, the accelerated structure being created based on the scene where the ray information is located, and the starting node being any node in the accelerated structure, such as any one of the root node, intermediate node, and leaf node in the accelerated structure; starting from the starting node indicated by the identification information, performing traversal and intersection calculations on the ray information in the accelerated structure to obtain the intersection result; and sending the intersection result to the shader, wherein the intersection result is used to generate a target image in the scene.

[0008] In the above technical solution, the ray tracing device obtains image information from the shader. The image information includes ray information and identification information. The identification information is the identification information corresponding to the ray information. The identification information is used to indicate the starting node for the intersection calculation of the ray information in the acceleration structure. The starting node can be any node in the acceleration structure, such as any one of the root node, intermediate node, and leaf node in the acceleration structure. Starting from the starting node indicated by the identification information, the ray information is traversed and the intersection calculation is performed in the acceleration structure. Compared with traversing and calculating the intersection of each ray information starting from the root node in the acceleration structure, the computational load of the intersection calculation is reduced, the efficiency of ray tracing is improved, and the power consumption of ray tracing is reduced. Furthermore, the intersection result is sent to the shader. The intersection result is used to generate the target image in the scene, which improves the efficiency of generating the target image.

[0009] In any possible implementation of the first aspect, the identification information includes a hierarchy identifier, which indicates the target hierarchy of the starting node in the acceleration structure. The above possible implementations, based on the hierarchy identifier, can determine the hierarchy where the starting node is located, facilitating subsequent determination of the starting node.

[0010] In any possible implementation of the first aspect, the method further includes: determining the root node in the acceleration structure as the starting node based on the hierarchical identifier. The above possible implementations can determine the starting node as the root node based on the hierarchical identifier, thus improving the efficiency of determining the starting node.

[0011] In any possible implementation of the first aspect, the identification information further includes a node identifier, which indicates the node of the starting node in the target level. The above possible implementations, which determine the starting node in the target level based on the node identifier, offer greater flexibility compared to using a fixed root node for the starting node corresponding to ray information.

[0012] In any possible implementation of the first aspect, the node identifier includes multiple node identifiers, indicating multiple nodes located in different layers of the acceleration structure; the starting node is the node belonging to the target layer among the multiple nodes. The above possible implementations, by determining the starting node in the target layer based on the node identifier, improve flexibility compared to using a fixed root node for the starting node corresponding to ray information.

[0013] In any possible implementation of the first aspect, the method further includes: determining the target level of the starting node in the acceleration structure based on the level identifier; determining the starting node based on the node identifier belonging to the target level among multiple node identifiers, wherein the starting node is an intermediate node or a leaf node in the acceleration structure. The above possible implementations, by determining the starting node in the target level based on the node identifier, improve flexibility compared to using a fixed root node for the starting node corresponding to ray information.

[0014] In any possible implementation of the first aspect, the ray tracing device includes: a bounding box testing unit, a spatial transformation unit, and a triangle testing unit; starting from the starting node indicated by the identification information, it performs traversal and intersection calculations on the ray information within the acceleration structure, including: if the starting node is the root node in the acceleration structure, the bounding box testing unit performs traversal and intersection calculations on the ray information within the acceleration structure; or, if the starting node is an intermediate node in the acceleration structure, the bounding box testing unit or the spatial transformation unit performs traversal and intersection calculations on the ray information within the acceleration structure; or, if the starting node is a leaf node in the acceleration structure, the triangle testing unit performs intersection calculations on the ray information within the acceleration structure. The above possible implementations, by utilizing different units to perform traversal and intersection calculations on the ray information within the acceleration structure when the starting nodes are different, improve the efficiency of the intersection calculation.

[0015] In any possible implementation of the first aspect, the ray tracing device further includes: an accelerated structure traversal unit; the method further includes: if the starting node is the root node in the accelerated structure, the accelerated structure traversal unit sends the root node and ray information to the bounding box test unit; or, if the starting node is an intermediate node in the accelerated structure, the accelerated structure traversal unit sends the intermediate node and ray information to the bounding box test unit or the spatial transformation unit; or, if the starting node is a leaf node in the accelerated structure, the accelerated structure traversal unit sends the leaf node and ray information to the triangle test unit. In the above possible implementations, when the starting nodes are different, different starting nodes and ray information are sent to different units, and different units perform traversal and intersection calculations on the ray information in the accelerated structure, thereby improving the efficiency of the intersection calculation.

[0016] Secondly, a ray tracing device is provided, comprising: an acquisition unit for acquiring image information from a shader, the image information including ray information and identification information, the identification information indicating the starting node for performing intersection calculations on the ray information in an accelerated structure, the accelerated structure being created based on the scene where the ray information is located, and the starting node being any node in the accelerated structure; an intersection calculation unit for performing intersection calculations on the ray information in the accelerated structure starting from the starting node indicated by the identification information to obtain the intersection result; and a sending unit for sending the intersection result to the shader, the intersection result being used to generate a target image in the scene.

[0017] In any possible implementation of the second aspect, the identification information includes a hierarchy identifier, which is used to indicate the target hierarchy of the starting node in the acceleration structure.

[0018] In any possible implementation of the second aspect, the apparatus further includes: a determining unit, configured to determine the root node in the acceleration structure as the starting node based on the hierarchical identifier.

[0019] In any possible implementation of the second aspect, the identification information also includes a node identifier, which is used to indicate the node of the starting node in the target level.

[0020] In any possible implementation of the second aspect, the node identifier includes multiple node identifiers, which indicate multiple nodes located at different layers in the acceleration structure; the starting node is the node belonging to the target layer among the multiple nodes.

[0021] In any possible implementation of the second aspect, the determining unit is further configured to: determine the target level of the starting node in the acceleration structure based on the level identifier; determine the starting node based on the node identifier belonging to the target level among multiple node identifiers, wherein the starting node is an intermediate node or a leaf node in the acceleration structure.

[0022] In any possible implementation of the second aspect, the intersection calculation unit includes: a bounding box testing unit, a spatial transformation unit, and a triangle testing unit; the bounding box testing unit is used to perform traversal intersection calculation of the ray information in the acceleration structure when the starting node is the root node or an intermediate node in the acceleration structure; the spatial transformation unit is used to perform traversal intersection calculation of the ray information in the acceleration structure when the starting node is an intermediate node in the acceleration structure; and the triangle testing unit is used to perform intersection calculation of the ray information in the acceleration structure when the starting node is a leaf node in the acceleration structure.

[0023] In any possible implementation of the second aspect, the intersection calculation unit further includes: an accelerated structure traversal unit: the accelerated structure traversal unit is used to send root node and ray information to the bounding box test unit when the starting node is the root node or an intermediate node in the accelerated structure; the accelerated structure traversal unit is used to send intermediate node and ray information to the spatial transformation unit when the starting node is an intermediate node in the accelerated structure; the accelerated structure traversal unit is used to send leaf node and ray information to the triangle test unit when the starting node is a leaf node in the accelerated structure.

[0024] Thirdly, a graphics processor is provided, the graphics processor including a processing core and memory, the memory being used to store image data, and the processing core being used to execute a ray tracing method as provided in the first aspect or any possible implementation thereof.

[0025] Fourthly, an electronic device is provided, the electronic device including a processor, the processor including a graphics processor and a central processing unit, the central processing unit being used to schedule the graphics processor, the graphics processor being the graphics processor provided in the third aspect.

[0026] Fifthly, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a device, cause the device to perform the ray tracing method provided by the first aspect or any possible implementation thereof.

[0027] Sixthly, a computer program product is provided, comprising a computer program (also referred to as code or instructions) that, when executed on a device, causes the device to perform the ray tracing method provided by the first aspect or any possible implementation thereof.

[0028] Understandably, the beneficial effects that can be achieved by the second to sixth aspects mentioned above can be referred to in the same way as the beneficial effects provided by the first aspect or any possible implementation of the first aspect, which will not be repeated here. Attached Figure Description

[0029] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0030] Figure 2 is a flowchart of a ray tracing method provided in an embodiment of this application;

[0031] Figure 3 is a schematic diagram of an acceleration structure provided in an embodiment of this application;

[0032] Figure 4 is a schematic diagram of a tree-shaped acceleration structure provided in an embodiment of this application;

[0033] Figure 5 is a schematic diagram of the structure of a GPU provided in an embodiment of this application;

[0034] Figure 6 is a schematic diagram of a traversal intersection calculation provided in an embodiment of this application;

[0035] Figure 7 is a flowchart of another ray tracing method provided in an embodiment of this application;

[0036] Figure 8 is a schematic diagram of another GPU structure provided in an embodiment of this application. Detailed Implementation

[0037] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this application and technology, and do not limit the scope of this application.

[0038] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0039] Each circuit or other component may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to imply a structure by indicating that the circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable (e.g., not turned on), it can still be referred to as "for performing that task." Circuits / components used with the term "for" include hardware, such as circuits that perform operations.

[0040] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, a, b, and c; where a, b, and c can be single or multiple.

[0041] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate an electrical connection, including direct connection via wires or terminals or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.

[0042] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0043] Before introducing the embodiments of this application, we will first introduce and explain the relevant knowledge of image processing.

[0044] In image rendering, ray tracing generates rendered images by simulating the propagation and interaction of light rays in a scene (i.e., interaction with objects in the scene). Traditional rasterization rendering discretizes continuous geometry into pixels and then colors these pixels to generate the rendered image. Ray tracing has gained widespread attention and application in the field of image processing due to its high-quality rendered images. Compared to traditional rasterization rendering, ray tracing requires significantly more computation. Currently, ray tracing computation is accelerated using application-specific integrated circuits (ASICs), specifically by accelerating the intersection calculation of multiple ray information during the ray tracing process to improve efficiency and shorten ray tracing time. However, the intersection calculation starts from the root node in the accelerated structure corresponding to the scene containing multiple ray information and performs intersection calculations with each ray information and all nodes in the accelerated structure, resulting in a large computational load.

[0045] The acceleration structure can also be called the full-scene acceleration structure. The acceleration structure includes a root node, multiple intermediate nodes, and multiple leaf nodes. The intermediate nodes are the subordinate nodes of the root node, and the leaf nodes are the subordinate nodes of the intermediate nodes. The intermediate nodes can be one or more levels. The intermediate node one level above and / or two levels above the leaf nodes can be called the bottom-level intermediate node.

[0046] In one possible embodiment, computational load is reduced by using prediction nodes. Multiple ray information points correspond to multiple prediction tables, and multiple ray information points belonging to the same direction correspond to the same prediction table. This direction can be the propagation direction of the multiple rays corresponding to the multiple ray information points in the scene; for example, the scene can be considered as a plane, and a coordinate system can be established on this plane, with multiple rays belonging to the same quadrant considered as rays in the same direction. The following explanation uses the first ray information among these multiple ray information points, and the prediction table corresponding to the first ray information, as an example.

[0047] Specifically, for the first ray information among multiple ray information, the ray tracing device queries a first prediction table. If the first prediction table does not store the identifiers of nodes (including leaf nodes and / or bottom intermediate nodes), it performs a traversal and intersection calculation on the first ray information within the acceleration structure, starting from the root node. The identifiers of the bottom intermediate nodes and leaf nodes that intersect with the first ray information in the acceleration structure are recorded in the first prediction table. If the first prediction table stores node identifiers, it performs an intersection calculation on the first ray information with the nodes indicated by the node identifiers stored in the first prediction table. Based on the calculation results, it determines whether further traversal and intersection calculations starting from the root node are needed. For example, if the first ray information does not intersect with the nodes indicated by the node identifiers stored in the first prediction table, it performs a traversal and intersection calculation on the first ray information within the acceleration structure, starting from the root node, and records the identifiers of the intersecting bottom intermediate nodes and leaf nodes in the first prediction table. If the first ray information intersects with the nodes indicated by the node identifiers stored in the first prediction table, the identifiers of the intersecting nodes are stored in the first prediction table. This process continues until the intersection calculation of multiple light sources is completed.

[0048] In one possible embodiment, when the distance between the starting coordinates of multiple rays corresponding to multiple ray information and the axis aligned bounding box (AABB) for which intersection calculation is required is greater than a preset distance, and the size of the AABB is smaller than a preset size, only the triangle in the AABB closest to the starting coordinates of the multiple rays is used to perform intersection calculation with the multiple ray information, and other triangles in the AABB are not used to perform intersection calculation, thereby reducing the number of intersection calculations.

[0049] However, the two possible embodiments described above can only reduce the computational load when calculating the intersection of local ray information; the computational load throughout the entire ray tracing process remains significant.

[0050] Based on this, embodiments of this application provide a ray tracing method to address the problem of high computational load when performing traversal and intersection calculations on ray information within an accelerated structure. Specifically, this method reduces the computational load during traversal and intersection calculations on the accelerated structure, thereby improving ray tracing efficiency and reducing the power consumption of the ray tracing device. This method can be applied to an image processor, which can then be used in electronic devices.

[0051] Optionally, the electronic device may include, but is not limited to: mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), camera, wearable device (e.g., smartwatch, smart bracelet, pedometer, etc.), audio equipment, audio and video player, set-top box, game console, printer, mouse, keyboard, in-vehicle equipment (e.g., equipment on vehicles such as cars, airplanes, ships, trains and high-speed trains), virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, smart home device (e.g., refrigerator, television, air conditioner, electricity meter, etc.), smart robot, workshop equipment, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, or wireless terminal in smart home, flying equipment (e.g., smart robot, hot air balloon, drone, airplane), etc.

[0052] The following example uses a mobile phone as an example to illustrate the structure of the electronic device. As shown in Figure 1, the electronic device may include components such as a radio frequency (RF) circuit 110, a memory 120, an input unit 130, a display unit 140, a sensor 150, an audio circuit 160, a processor 170, and a power supply 180.

[0053] RF circuit 110 can be used to send and receive information, or to receive or send signals during a call. Specifically, it receives downlink information from the base station and processes it in processor 170; additionally, it sends uplink data to the base station. Typically, RF circuit 110 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, RF circuit 110 can also communicate wirelessly with networks and other devices.

[0054] The memory 120 can be used to store data, software programs, and modules; it mainly includes a program storage area and a data storage area. The program storage area can store the operating system and application programs required for at least one function, such as sound playback and image playback functions. The data storage area can store data created based on the use of the electronic device, such as audio data, image data, and a phone book. Furthermore, the electronic device may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0055] The input unit 130 can be used to receive input numerical or character information, and to generate key signal inputs related to user settings and function control of the electronic device. Specifically, the input unit 130 may include a touch screen 131 and other input devices 132. The touch screen 131 can collect touch operations performed by the user on or near it (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touch screen), and drive the corresponding connected devices according to a pre-set program. Optionally, other input devices 132 may include, but are not limited to, one or more of the following: a physical keyboard, function keys (such as volume control buttons, power switch buttons, etc.), a trackball, a mouse, a joystick, etc.

[0056] Display unit 140 can be used to display information input by the user or information provided to the user, as well as various menus of the electronic device. In one example, display unit 140 may include display screen 141, which may be configured as a liquid crystal display (LCD), organic light-emitting diode (OLED), or similar device. Furthermore, touchscreen 131 may cover display screen 141. When touchscreen 131 detects a touch operation on or near it, it transmits the information to processor 170 to determine the type of touch event. Subsequently, processor 170 provides corresponding visual output on display screen 141 based on the type of touch event. Although in the figures, touchscreen 131 and display screen 141 are shown as two separate components to implement the input and output functions of the electronic device, in some embodiments, touchscreen 131 and display screen 141 can be integrated to achieve the input and output functions of the electronic device.

[0057] Sensor 150 may include one or more sensors for providing status assessments of various aspects of the electronic device. Sensor 150 may include a light sensor, which can be used in imaging applications, i.e., as a component of a camera or video camera. Furthermore, sensor 150 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor. Sensor 150 can detect acceleration / deceleration, orientation, on / off state, relative positioning of components, or temperature changes of the electronic device.

[0058] Audio circuitry 160, a speaker, and a microphone provide an audio interface between the user and the electronic device. Audio circuitry 160 converts received audio data into electrical signals and transmits them to the speaker, where the speaker converts them into sound signals for output. On the other hand, the microphone converts collected sound signals into electrical signals, which are then received by audio circuitry 160, converted into audio data, and output to RF circuitry 110 for transmission to, for example, another mobile phone, or to memory 120 for further processing.

[0059] The processor 170 is the control center of the electronic device, connecting various parts of the device through various interfaces and lines. It executes software programs and / or modules stored in the memory 120, and calls data stored in the memory 120, to perform various functions and process data, thereby providing overall monitoring of the electronic device. Optionally, the processor 170 may include a graphics processing unit (GPU). The processor 170 may also include one or more processing units, which may include, but are not limited to: a central processing unit (CPU), a network processing unit (NPU), an image signal processor (ISP), a tensor processing unit (TPU), a data processing unit (DPU), a digital signal processor (DSP), a microcontroller, or a microprocessor. Furthermore, the processor 170 may also include other hardware circuits or accelerators, such as application-specific integrated circuits (ASICs), complex programmable logic devices (CPLDs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Optionally, the processor 170 may also be a combination of functions that implement computing, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc.

[0060] The electronic device may also include a power supply 180 (e.g., a battery) to power various components. The power supply 180 can be logically connected to the processor 170 via a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. Optionally, the power management system can simultaneously support fast charging and non-fast charging technologies. In practical applications, the power management system can charge the battery in the power supply 180 using either fast charging or non-fast charging technologies.

[0061] Although not shown, the electronic device may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which will not be described in detail in the embodiments of this application. Those skilled in the art will understand that the structure of the electronic device shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0062] Figure 2 is a schematic flowchart of a ray tracing method provided in an embodiment of this application. This method can be applied to a GPU, which can also be called a ray tracing device. The ray tracing method includes the following steps.

[0063] S201: The GPU obtains image information from the shader. The image information includes ray information and identification information. The identification information is used to indicate the starting node for intersection calculation of the ray information in the acceleration structure. The acceleration structure is created based on the scene where the ray information is located, and the starting node is any node in the acceleration structure.

[0064] A shader can be a program within the GPU used for image rendering. For example, the GPU obtains image information by calling a program. In practical applications, the GPU receives instructions from the CPU, which instruct the GPU to perform intersection calculations on multiple ray information, and the GPU obtains image information from the shader.

[0065] In practical applications, image information may include multiple ray information and multiple identifier information. Each ray information corresponds one-to-one with one identifier information; that is, each ray information corresponds to one identifier information. The identifier information corresponding to each ray information is used to indicate the starting node for intersection calculation in the acceleration structure. The ray information in step S201 refers to any one of these multiple ray information, and the identifier information is the identifier information corresponding to that arbitrary ray information. The following explanation uses this arbitrary ray information as an example.

[0066] Furthermore, the acceleration structure is created based on the scene where the ray information is located, specifically based on the scene containing multiple objects. In one possible embodiment, the scene is surrounded by a first bounding box, and multiple objects in the scene containing the ray information are surrounded by multiple second bounding boxes, each second bounding box being used to surround one object. For each of the multiple objects, the object is divided into multiple blocks; for example, if the object is a chair, the chair is divided into a backrest and a seat. Multiple third bounding boxes are used to surround multiple blocks, each third bounding box being used to surround one block. For each of the multiple blocks, the block is divided into multiple planar images, and multiple fourth bounding boxes are used to surround these multiple planar images, each fourth bounding box being used to surround a planar shape. This results in the acceleration structure. For example, the planar shape can be a triangle or a quadrilateral. The bounding boxes (including the aforementioned first bounding box, multiple second bounding boxes, multiple third bounding boxes, and multiple fourth bounding boxes) can be AABBs, for example, the AABB can be a cuboid or a cube.

[0067] Optionally, the first bounding box of the scene (hereinafter referred to as the first bounding box) is the root node in the acceleration structure, and the root node is at the first level in the acceleration structure; multiple second bounding boxes comprising multiple objects (hereinafter referred to as multiple second bounding boxes) are multiple first intermediate nodes in the acceleration structure, and the multiple first intermediate nodes are at the second level in the acceleration structure; multiple third bounding boxes comprising multiple blocks (hereinafter referred to as multiple third bounding boxes) are multiple second intermediate nodes in the acceleration structure, and the multiple second intermediate nodes are at the third level in the acceleration structure; multiple fourth bounding boxes comprising multiple triangles (hereinafter referred to as multiple fourth bounding boxes) are multiple leaf nodes in the acceleration structure. The multiple leaf nodes are at the fourth level in the acceleration structure. The multiple first intermediate nodes and the multiple second intermediate nodes can be collectively referred to as multiple intermediate nodes.

[0068] In practical applications, this acceleration structure can also include more levels, such as a fifth level, a sixth level, etc. When the acceleration structure includes more levels, the last level can refer to the level where the multiple leaf nodes are located. This application does not specifically limit the number of levels in the acceleration structure. In this application embodiment, an example is given where the acceleration structure includes four levels (including the first to fourth levels).

[0069] Furthermore, the level where these multiple leaf nodes are located is the last level in the acceleration structure, that is, the level where these multiple leaf nodes are located is the lowest level in the acceleration structure, and the level where the root node is located is the first level in the acceleration structure, that is, the level where these multiple leaf nodes are located is the highest level in the acceleration structure.

[0070] Optionally, in the Vulkan application programming interface (VAPI) protocol, the first bounding box can also be called the top-level acceleration structures (TLAS), the second bounding box can also be called the instance, the third bounding box can also be called the geometry, and the fourth bounding box can also be called the primitive. The first level can also be called the TLAS level, the second level can be called the instance level, the third level can be called the geometry level, and the fourth level can be called the primitive level. The geometry level and the primitive level can also be called the bottom-level acceleration structures (BLAS). For example, Figure 3 is a schematic diagram of an acceleration structure (AS) provided in an embodiment of this application. The AS includes a TLAS and multiple BLASs, which can be represented as BLAS1 to BLASm respectively. The TLAS includes multiple instances, which can be represented as I1 to In respectively, and each instance corresponds to one BLAS. Each BLAS includes i geometric figures, where the i geometric figures included in BLAS1 can be represented as G11 to G1i respectively, and the i geometric figures included in BLASm can be represented as Gm1 to Gmi respectively. Each geometric figure can include j original figures, where the j original figures included in G11 can be represented as P111 to P11j respectively. m, n, i, and j are all positive integers.

[0071] In one possible embodiment, the acceleration structure can be a tree structure. For example, as shown in Figure 4, the acceleration structure includes a root node, multiple first intermediate nodes, multiple second intermediate nodes, and multiple leaf nodes. The multiple first intermediate nodes are nodes one level below the root node, the multiple second intermediate nodes are nodes one level below the first intermediate nodes, and the multiple leaf nodes are nodes one level below the second intermediate nodes.

[0072] In one possible embodiment, the identification information includes a level identifier, which is used to indicate the target level of the starting node in the acceleration structure. The target level can be any one of the first to fourth levels of the acceleration structure. For example, different values ​​of the level identifier indicate different target levels among the first to fourth levels. Specifically, a level identifier of 1 indicates that the target level is the first level; a level identifier of 2 indicates that the target level is the second level; a level identifier of 3 indicates that the target level is the third level; and a level identifier of 4 indicates that the target level is the fourth level.

[0073] In one possible embodiment, the identification information further includes node identifiers, which indicate the starting node as a node in the target level. The node identifiers may include multiple node identifiers, indicating multiple nodes located in different layers of the acceleration structure, with the starting node being the node belonging to the target level among these nodes. For example, the node identifiers may include three node identifiers, indicating three nodes located in the second to fourth levels of the acceleration structure, with the starting node being the node among these three nodes located in the target level.

[0074] Secondly, each ray information in the multiple ray information sets can include ray coordinates, a marker bit, and a storage address of the storage acceleration structure. The ray coordinates refer to the starting point and direction of the ray corresponding to the ray information in a coordinate system. This coordinate system can be a three-dimensional coordinate system, meaning the ray coordinates can be a direction vector. The marker bit can be used to mark the traversal boundaries and maximum distance, etc. The storage address of the storage acceleration structure can be a storage address in the memory of the electronic device where the GPU resides.

[0075] The following section, with reference to Figure 5, details the specific process of determining the starting node when the identification information includes different identifiers.

[0076] In one possible embodiment, the GPU determines the target level of the starting node in the acceleration structure based on the level identifier in the identification information, and determines the node of the starting node in the target level based on the node identifier in the identification information.

[0077] For example, Figure 5 is a schematic diagram of the structure of a GPU provided in an embodiment of this application. The GPU includes a hierarchy determination unit 51, a node determination unit 52, and a ray tracing unit 53 connected in sequence. The ray tracing unit 53 includes an accelerated structure traversal unit 531, a bounding box testing unit 532, a spatial transformation unit 533, and a triangle testing unit 534. The output terminal of the node determination unit 52 is connected to the input terminal of the accelerated structure traversal unit 531. The output terminal of the accelerated structure traversal unit 531 is connected to the input terminals of the bounding box testing unit 532, the spatial transformation unit 533, and the triangle testing unit 534, respectively. Any two units among the bounding box testing unit 532, the spatial transformation unit 533, and the triangle testing unit 534 are interconnected, that is, the output terminal and input terminal of the first unit in any two units are connected to the input terminal and output terminal of the second unit, respectively. In practical applications, the ray tracing unit can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0078] The hierarchy determination unit 51 is used to obtain ray information and identification information from the shader and determine the target hierarchy based on the identification information. The node determination unit 52 is used to determine the starting node in the target hierarchy based on the identification information. The accelerated structure traversal unit 531 is used to send different starting nodes and ray information to different units in the bounding box test unit 532, spatial transformation unit 533, and triangle test unit 534. The bounding box test unit 532 can be used to perform intersection calculations on the ray information and the intermediate nodes among the multiple intermediate nodes of the accelerated structure that do not require spatial transformation, as well as the root node. The spatial transformation unit 533 can be used to perform intersection calculations on the ray information and the intermediate nodes among the multiple intermediate nodes of the accelerated structure that require spatial transformation. The triangle test unit 534 can be used to perform intersection calculations on the ray information and the multiple leaf nodes of the accelerated structure.

[0079] In one possible embodiment, the identification information includes a hierarchy identifier.

[0080] The method provided in this application embodiment further includes: a layer determination unit 51 determines the target layer of the starting node in the acceleration structure as the first layer based on a layer identifier (e.g., the layer identifier is 1), and sends the light information and the first layer to a node determination unit 52. Since the first layer only includes the root node, the node determination unit 52 determines the starting node as the root node based on the first layer.

[0081] In one possible embodiment, the identification information includes a hierarchy identifier and a node identifier, wherein the node identifier includes a first intermediate node identifier, a second intermediate node identifier, and a leaf node identifier.

[0082] The method provided in this application embodiment further includes: a level determination unit 51 determines the target level of the starting node in the acceleration structure as the fourth level based on a level identifier (e.g., the level identifier is 4), and sends the light information and the fourth level to a node determination unit 52. The node determination unit 52 determines the starting node as the leaf node indicated by the leaf node identifier based on the fourth level and the leaf node identifier.

[0083] Optionally, when the level identifier is 2 or 3, the level determination unit 51 determines the target level as the second level or the third level. The node determination unit 52 determines the starting node as the first intermediate node indicated by the first intermediate node identifier based on the second level and the first intermediate node identifier; or, the node determination unit 52 determines the starting node as the second intermediate node indicated by the second intermediate node identifier based on the third level and the second intermediate node identifier.

[0084] In the two embodiments described above, the GPU determines the starting node for performing intersection calculations on the ray information in the acceleration structure based on the identification information corresponding to the ray information. The starting node can be any node in the acceleration structure, such as the root node, multiple first intermediate nodes, multiple second intermediate nodes, or multiple leaf nodes. Compared with the fixed root node for each ray information, this improves flexibility.

[0085] S202: Starting from the starting node indicated by the identification information, the GPU performs intersection calculations on the ray information in the acceleration structure to obtain the intersection result.

[0086] Since the starting node can be any node in the acceleration structure, and different coordinate systems can coexist within the acceleration structure, spatial coordinate system transformations may be required between different levels. Therefore, starting nodes belonging to different levels can be used for intersection calculations through different cells. The following explanation will continue with the GPU-based scenario shown in Figure 5.

[0087] In one possible embodiment, the starting node is the root node in the acceleration structure.

[0088] The method provided in this application embodiment further includes: a node determination unit 52 sending the root node and ray information to an acceleration structure traversal unit 531. The acceleration structure traversal unit 531 sending the root node and ray information to a bounding box testing unit 532. The bounding box testing unit 532 performs traversal intersection calculations on the ray information within the acceleration structure. Specifically, the bounding box testing unit 532 performs intersection calculations on the ray information with the root node and intermediate nodes among the multiple intermediate nodes in the acceleration structure that do not require spatial transformation. The spatial transformation unit 533 performs intersection calculations on the ray information with intermediate nodes among the multiple intermediate nodes in the acceleration structure that require spatial transformation. The triangle testing unit 534 performs intersection calculations on the ray information with multiple leaf nodes in the acceleration structure, thereby obtaining the intersection result of the ray information and the acceleration structure.

[0089] In one possible embodiment, the starting node is the first intermediate node in the acceleration structure.

[0090] The method provided in this application embodiment further includes: a node determination unit 52 sending a first intermediate node and ray information to an acceleration structure traversal unit 531. If no spatial coordinate transformation is required between the first intermediate node and the second intermediate node, the acceleration structure traversal unit 531 sends the first intermediate node and the ray information to a bounding box testing unit 532. The bounding box testing unit 532 performs traversal intersection calculations on the ray information in the acceleration structure. Specifically, the bounding box testing unit 532 performs intersection calculations on the ray information with the first intermediate node and the second node associated with the first intermediate node in the acceleration structure. The triangle testing unit 534 performs intersection calculations on the ray information with at least one leaf node associated with the first intermediate node in the acceleration structure, thereby obtaining the intersection result of the ray information and the acceleration structure.

[0091] If spatial coordinate transformation is required between the first intermediate node and the second intermediate node, the method provided in this application embodiment further includes: the accelerated structure traversal unit 531 sends the first intermediate node and the ray information to the spatial transformation unit 533, the spatial transformation unit 533 performs intersection calculation between the ray information and the first intermediate node and the second intermediate node associated with the first intermediate node in the accelerated structure, and the triangle testing unit 534 performs intersection calculation between the ray information and at least one leaf node associated with the first intermediate node in the accelerated structure, thereby obtaining the intersection result between the ray information and the accelerated structure.

[0092] In practical applications, it can be determined from the information of the acceleration structure whether a coordinate transformation is required between the first intermediate node and the second intermediate node.

[0093] In one possible embodiment, the starting node is a leaf node in the acceleration structure.

[0094] The method provided in this application embodiment further includes: the node determination unit 52 sending the leaf node and ray information to the accelerated structure traversal unit 531. The accelerated structure traversal unit 531 sends the leaf node and the ray information to the triangle testing unit 534, and the triangle testing unit 534 performs intersection calculation between the ray information and the leaf node to obtain the intersection result between the ray information and the accelerated structure.

[0095] In the above embodiments, the GPU determines the starting node for performing intersection calculations on the ray information in the acceleration structure based on the identification information corresponding to the ray information. The starting node can be any node in the acceleration structure, such as the root node, multiple first intermediate nodes, multiple second intermediate nodes, or multiple leaf nodes. Thus, the GPU performs intersection calculations on each ray information at the starting node. Compared with performing intersection calculations on each ray information fixed at the root node in the acceleration structure, this reduces the computational load of intersection calculations, improves the efficiency of ray tracing, and reduces the power consumption of ray tracing.

[0096] For example, taking the tree-shaped acceleration structure shown in Figure 4 above as an example, Figure 6 is a schematic diagram of a traversal intersection calculation provided by an embodiment of this application. In Figure 6(a), the GPU performs a traversal intersection calculation on the ray information in the acceleration structure with the root node as the starting node. That is, the GPU performs an intersection calculation on the ray information with each node in the acceleration structure according to the direction of the arrow shown in Figure (a). In Figure 6(b), the GPU performs a traversal intersection calculation on the ray information in the acceleration structure with the first intermediate node as the starting node. That is, the GPU performs an intersection calculation on each node in the subtree formed by the ray information and the first intermediate node according to the direction of the dashed arrow shown in Figure (b). Therefore, when the starting node is the first intermediate node, the computational load of the intersection calculation is reduced, the efficiency of ray tracing is improved, and the power consumption of ray tracing is reduced.

[0097] S203: The GPU sends the intersection result to the shader, and the intersection result is used to generate the target image in the scene.

[0098] Similarly, based on the above process, the GPU performs intersection calculations on each of the multiple ray information pieces within the accelerated structure, determining the intersection result corresponding to each ray information piece, with multiple ray information pieces corresponding to multiple intersection results. The GPU sends the multiple intersection results corresponding to the multiple ray information pieces to the shader, and the shader generates the target image for the scene based on these multiple intersection results.

[0099] For ease of understanding, the ray tracing method provided in the embodiments of this application will be described below with reference to Figures 5 and 7 above.

[0100] As exemplarily shown in FIG7, the ray tracing method provided in this application embodiment includes the following steps.

[0101] S701: The hierarchy determination unit 51 obtains image information from the shader. The image information includes light information and identification information. The identification information includes hierarchy identification and node identification.

[0102] S702: The level determination unit 51 determines the target level based on the level identifier.

[0103] S703: Node determination unit 52 determines the starting node in the target level based on the node identifier.

[0104] S704: The ray tracing unit 53 starts from the starting node, performs traversal and intersection calculations on the ray information in the acceleration structure to obtain the intersection result, and outputs the calculation result to the shader.

[0105] In this embodiment, the GPU obtains image information from the shader. The image information includes multiple ray information and multiple identifier information. The multiple identifier information corresponds to multiple ray information, with each ray information corresponding to one identifier information. For each ray information, the GPU determines the starting node for intersection calculation in the acceleration structure based on the identifier information corresponding to that ray information. The starting node can be any node among the multiple nodes included in the acceleration structure. For example, the starting node can be any node among the root node, multiple first intermediate nodes, multiple second intermediate nodes, or multiple leaf nodes in the acceleration structure. Starting from the starting node indicated by the identifier information, the ray information is traversed and intersection calculations are performed in the acceleration structure. Compared with traversing and performing intersection calculations in the acceleration structure for each ray information starting from the root node, this reduces the computational load of intersection calculations, improves the efficiency of ray tracing, and reduces the power consumption of ray tracing. Furthermore, the intersection result is sent to the shader, and the intersection result is used to generate the target image in the scene, improving the efficiency of generating the target image.

[0106] The foregoing primarily describes the solutions provided in this application from the perspective of the GPU. It is understood that, to achieve the aforementioned functions, the GPU includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0107] This application embodiment can divide the GPU into functional modules according to the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the division of functional modules according to each function as an example.

[0108] Figure 8 shows a schematic diagram of the structure of a GPU involved in the above embodiments when using integrated units. The GPU may include: an acquisition unit 801, an intersection calculation unit 802, and a sending unit 803. The acquisition unit 801 can be used to support the device in executing S201 of the above method embodiments; the intersection calculation unit 802 can be used to support the device in executing S202 of the above method embodiments; and the sending unit 803 can be used to support the device in executing S203 of the above method embodiments. All relevant content of each step involved in the above method embodiments can be referred to the functional description of the corresponding functional module, and will not be repeated here.

[0109] The GPU may also include a determination unit 804. The determination unit 804 can be used to determine the target level and the node of the starting node in the target level based on the identification information.

[0110] Based on hardware implementation, the acquisition unit 801 and determination unit 804 in this embodiment can be the hierarchy determination unit 51 and node determination unit 52 shown in FIG5 above. The intersection calculation unit 802 and sending unit 803 can be the ray tracing unit 53 shown in FIG5 above.

[0111] In another embodiment of this application, a GPU is also provided, which includes a processing core and memory for storing image data. The GPU can be the GPU shown in FIG5 above, and is used to perform the steps in the method embodiments provided above.

[0112] In another embodiment of this application, an electronic device is also provided, which includes a processor; wherein the processor includes a GPU and a CPU, the CPU is used to schedule the GPU, which may be the GPU shown in FIG5 above, for executing the steps in the method embodiments provided above.

[0113] It is understood that all relevant content of each step involved in the above method embodiments can be referenced in the embodiments of the GPU and the embodiments of the electronic device, and will not be repeated here.

[0114] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed.

[0115] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. This readable storage medium may include various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory, random access memory, magnetic disk, or optical disk. Based on this understanding, the technical solution of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0117] In another embodiment of this application, a readable storage medium is also provided, which stores computer-executable instructions that are executed by a device (which may be a microcontroller, chip, etc.) or a processor when executing the steps in the above method embodiments.

[0118] In another embodiment of this application, a computer program product is also provided, the computer program product including computer instructions stored in a readable storage medium; at least one processor of the device can read the computer instructions from the readable storage medium, and the at least one processor executes the computer instructions to cause the device to perform the steps in the above method embodiments.

[0119] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A ray tracing method, characterized by, Applied to ray tracing devices, the method includes: Image information is obtained from the shader. The image information includes ray information and identification information. The identification information is used to indicate the starting node for intersection calculation of the ray information in the acceleration structure. The acceleration structure is created based on the scene where the ray information is located. The starting node is any node in the acceleration structure. Starting from the starting node indicated by the identification information, the light information is traversed and intersection calculated in the acceleration structure to obtain the intersection result; The intersection result is sent to the shader, and the intersection result is used to generate the target image in the scene.

2. The method of claim 1, wherein, The identification information includes a hierarchy identifier, which is used to indicate the target hierarchy of the starting node in the acceleration structure.

3. The method of claim 2, wherein, The method further includes: The root node in the acceleration structure is determined as the starting node based on the hierarchical identifier.

4. The method according to claim 2 or 3, characterized in that, The identification information also includes a node identifier, which is used to indicate the node of the starting node in the target level.

5. The method of claim 4, wherein, The node identifier includes multiple node identifiers, and the multiple node identifiers indicate multiple nodes located in different layers of the acceleration structure; The starting node is the node belonging to the target level among the plurality of nodes.

6. The method of claim 5, wherein, The method further includes: The target level of the starting node in the acceleration structure is determined based on the level identifier; The starting node is determined based on the node identifier belonging to the target level among the plurality of node identifiers, and the starting node is an intermediate node or a leaf node in the acceleration structure.

7. The method according to any one of claims 1 to 6, characterized in that, The ray tracing device includes: a bounding box testing unit, a spatial transformation unit, and a triangle testing unit; the step of performing traversal and intersection calculations on the ray information in the acceleration structure, starting from the starting node indicated by the identification information, includes: If the starting node is the root node in the acceleration structure, the bounding box testing unit performs a traversal and intersection calculation on the ray information within the acceleration structure; or... If the starting node is an intermediate node in the acceleration structure, the bounding box testing unit or the spatial transformation unit performs a traversal and intersection calculation on the ray information within the acceleration structure; or... If the starting node is a leaf node in the acceleration structure, the triangle testing unit performs intersection calculations on the light information in the acceleration structure.

8. The method of claim 7, wherein, The ray tracing device further includes: an accelerated structure traversal unit; the method further includes: If the starting node is the root node in the acceleration structure, the acceleration structure traversal unit sends the root node and the ray information to the bounding box testing unit; or... If the starting node is an intermediate node in the acceleration structure, the acceleration structure traversal unit sends the intermediate node and the ray information to the bounding box testing unit or the spatial transformation unit; or... If the starting node is a leaf node in the acceleration structure, the acceleration structure traversal unit sends the leaf node and the light information to the triangle test unit.

9. A ray tracing device, characterized by The ray tracing device includes: An acquisition unit is used to acquire image information from a shader. The image information includes ray information and identification information. The identification information is used to indicate the starting node for performing intersection calculation on the ray information in an acceleration structure. The acceleration structure is created based on the scene where the ray information is located. The starting node is any node in the acceleration structure. The intersection calculation unit is used to perform intersection calculations on the light information in the acceleration structure, starting from the starting node indicated by the identification information, to obtain the intersection result; A sending unit is used to send the intersection result to the shader, and the intersection result is used to generate the target image in the scene.

10. The apparatus of claim 9, wherein, The identification information includes a hierarchy identifier, which is used to indicate the target hierarchy of the starting node in the acceleration structure.

11. The apparatus of claim 10, wherein, The device further includes: A determining unit is used to determine the root node in the acceleration structure as the starting node based on the hierarchical identifier.

12. The apparatus of claim 10 or 11, wherein, The identification information also includes a node identifier, which is used to indicate the node of the starting node in the target level.

13. The apparatus of claim 12, wherein, The node identifier includes multiple node identifiers, and the multiple node identifiers indicate multiple nodes located in different layers of the acceleration structure; The starting node is the node belonging to the target level among the plurality of nodes.

14. The apparatus of claim 13, wherein, The determining unit is further configured to: The target level of the starting node in the acceleration structure is determined based on the level identifier; The starting node is determined based on the node identifier belonging to the target level among the plurality of node identifiers, and the starting node is an intermediate node or a leaf node in the acceleration structure.

15. The apparatus of any of claims 9-14, wherein, The intersection calculation unit includes: a bounding box testing unit, a spatial transformation unit, and a triangle testing unit; The bounding box testing unit is used to perform traversal and intersection calculations on the ray information in the acceleration structure when the starting node is the root node or an intermediate node in the acceleration structure. The spatial transformation unit is used to perform traversal and intersection calculations on the acceleration structure for the light information when the starting node is an intermediate node in the acceleration structure. The triangle test unit is used to perform intersection calculations on the light information in the acceleration structure when the starting node is a leaf node in the acceleration structure.

16. The apparatus of claim 15, wherein, The intersection calculation unit further includes: an accelerated structure traversal unit. The accelerated structure traversal unit is used to send the root node and the ray information to the bounding box test unit when the starting node is the root node or the intermediate node in the accelerated structure; The acceleration structure traversal unit is used to send the intermediate node and the light information to the spatial transformation unit when the starting node is the intermediate node in the acceleration structure; The accelerated structure traversal unit is used to send the leaf node and the light information to the triangle test unit when the starting node is the leaf node in the accelerated structure.

17. A graphics processor, comprising: The graphics processor includes a processing core and memory, the memory being used to store image data, and the processing core being used to execute the ray tracing method as described in any one of claims 1-8.

18. An electronic device, comprising: The electronic device includes a processor including a graphics processor and a central processor for scheduling the graphics processor, the graphics processor being as claimed in claim 17.

19. A computer-readable storage medium, characterized in that, The computer readable storage medium has stored therein instructions which, when executed on a device, cause the device to perform the ray tracing method as claimed in any one of claims 1-8.

20. A computer program product, characterised in that, The computer program product includes a computer program which, when executed on a device, cause the device to perform the ray tracing method as claimed in any one of claims 1-8.