Piecewise-linear nonlinearity calibration apparatus for analog-to-digital converter, driver chip, and electronic device

Abstract

The present disclosure relates to a piecewise-linear nonlinearity calibration apparatus for an analog-to-digital converter, a driver chip, and an electronic device. The apparatus comprises: a first adjustment unit configured to: select a target slope from a slope storage unit on the basis of high-order n bits of an analog-to-digital conversion result, and use the target slope to adjust a low-order quantization value corresponding to N-n bits of the analog-to-digital conversion result to obtain an adjusted low-order quantization value, wherein an output range of the analog-to-digital converter is divided into a plurality of continuous interval segments, and each interval segment corresponds to one slope; and a second adjustment unit configured to adjust, on the basis of the slopes of a plurality of interval segments preceding the interval segment corresponding to the target slope, a high-order quantization value corresponding to the high-order n bits of the analog-to-digital conversion result, to obtain an adjusted high-order quantization value, and use the sum of the adjusted high-order quantization value and the adjusted low-order quantization value to obtain a calibrated analog-to-digital conversion result. Embodiments of the present disclosure can greatly reduce computational complexity, save area overhead, improve energy efficiency, and achieve high analog-to-digital conversion efficiency.

Description

Piecewise nonlinear calibration device, driver chip and electronic equipment for analog-to-digital converter

[0001] Cross-references to related applications

[0002] This invention claims priority to Chinese patent application No. 202510096660.2, filed on January 21, 2025, entitled "Piecewise Positive Linear Nonlinear Calibration Device, Driver Chip and Electronic Device for Analog-to-Digital Converter", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of integrated circuit technology, and in particular to a piecewise nonlinear calibration device, driver chip, and electronic device for an analog-to-digital converter. Background Technology

[0004] An analog-to-digital converter (ADC) is a typical analog-to-mixed-signal integrated circuit that converts analog signals into digital signals through quantization, serving as a bridge between the real world and digital systems. With advancements in integrated circuit technology, transistor sizes are continuously shrinking, and power supply voltages are gradually decreasing. Lower transistor output impedance and more limited voltage swings present significant nonlinear challenges to ADC design.

[0005] During signal conversion, non-ideal characteristics in the circuit can introduce nonlinearity, thereby reducing the performance of the analog-to-digital converter.

[0006] Meanwhile, advancements in manufacturing processes have also led to smaller footprints and higher energy efficiency in digital computing. Consequently, calibrating the nonlinearities introduced into analog circuits in the digital domain has become a crucial method. It leverages the advantages of digital computing under advanced manufacturing processes to address the irrational characteristics of analog circuits, and thus has broad application prospects.

[0007] Polynomial-based nonlinear calibration algorithms are a commonly used method. Nonlinear effects in circuits can be modeled using polynomial functions, and nonlinear errors can be extracted and corrected based on this model. Polynomial functions can accurately describe the nonlinear characteristics of actual circuits and require only a few parameters to achieve error extraction, making them the mainstream nonlinear calibration algorithm. Many mature backend error extraction schemes are available on the market, enabling error extraction at a relatively low cost. However, polynomial calculations require exponential operations on the signal, introducing significant delay, power consumption, and area overhead. This poses a considerable challenge to the practical application of the algorithm.

[0008] Another approach is to model and extract nonlinear errors using a piecewise linear method. By approximating the nonlinear function with a linear function, nonlinear calibration can be achieved through linear multiplication and addition operations, thus avoiding complex power operations and significantly reducing the overall system complexity. However, compared to polynomial-based nonlinear calibration algorithms, the piecewise linear calibration method requires a larger number of parameters, and their extraction is more difficult. For a cubic polynomial y = a1x + a3x... 3 In this case, only two parameters, a1 and a3, are needed to achieve accurate error extraction. However, if modeling is done using four piecewise linear segments, each segment requires a slope k. i and intercept b i Two parameters are needed to determine the accuracy, resulting in a total of eight parameters. If higher calibration accuracy is required, an even greater number of parameters are needed. Extracting these parameters is a very challenging problem.

[0009] Figures 1a and 1b illustrate existing schemes for extracting piecewise linear coefficients. These schemes extract the piecewise linear parameters through a foreground testing method. The basic idea is to use a digital-to-analog converter (DAC) to generate a pre-set test voltage, which is then input into the DAC. The nonlinear characteristics are determined based on the DAC's output, thus enabling the extraction of the piecewise linear coefficients. However, this scheme requires significant hardware overhead (an additional DAC) and can only perform foreground extraction, necessitating an interruption of the DAC's normal conversion. These drawbacks severely limit its applicability.

[0010] It is evident that traditional polynomial nonlinear error calibration algorithms have high computational complexity, introducing significant speed and area costs. Furthermore, existing nonlinear calibration methods based on piecewise linear curves suffer from high hardware overhead and low calibration efficiency, resulting in numerous limitations in practical applications. Summary of the Invention

[0011] According to one aspect of this disclosure, a piecewise linear nonlinear calibration device for an analog-to-digital converter is provided. The analog-to-digital converter is used to perform analog-to-digital conversion on an input analog input signal and output the analog-to-digital conversion result. The device includes:

[0012] The first adjustment unit is connected to the output terminal of the analog-to-digital converter. The first adjustment unit is used to: select a target slope from the slope storage unit according to the high n bits of the analog-to-digital conversion result, and adjust the low-bit quantization value corresponding to the Nn bits of the analog-to-digital conversion result using the target slope to obtain the adjusted low-bit quantization value, where N > n and are all positive integers, N is the conversion accuracy of the analog-to-digital converter, and the output range of the analog-to-digital converter is divided into multiple continuous intervals, each interval corresponding to a slope;

[0013] The second adjustment unit is connected to the output terminal of the analog-to-digital converter and the output terminal of the first adjustment unit. The second adjustment unit is used to: adjust the high-n quantization value corresponding to the high bit of the analog-to-digital conversion result according to the slope of multiple intervals before the interval corresponding to the target slope, to obtain the adjusted high-bit quantization value, and use the sum of the adjusted high-bit quantization value and the adjusted low-bit quantization value to obtain the calibrated analog-to-digital conversion result.

[0014] In one possible implementation, the slope storage unit includes a plurality of slope registers, each slope register storing a corresponding slope, and the first adjustment unit includes a first multiplexer and a first multiplier, wherein...

[0015] The multiple inputs of the first multiplexer are respectively connected to the slope registers of the slope storage unit. The control terminal of the first multiplexer is used to receive the high n bits of the analog-to-digital conversion result. The output terminal of the first multiplexer is connected to the first input terminal of the first multiplier. The output terminal of the first multiplexer is used to output the target slope.

[0016] The second input of the first multiplier is used to receive the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result. The first multiplier is used to perform the multiplication operation between the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result and the target slope. The output of the first multiplier is used to output the adjusted low-order quantization value.

[0017] In one possible implementation, the second adjustment unit includes a second multiplexer, an accumulator, a second multiplier, and a first adder, wherein...

[0018] The second multiplexer is used to select the slope of multiple intervals before the interval corresponding to the target slope from the slope storage unit according to the high n bits of the analog-to-digital conversion result, and input them into the accumulator. The accumulator is used to output the slope accumulation result.

[0019] The second multiplier is used to perform a multiplication operation between the high-n bits of the analog-to-digital conversion result and the slope accumulation result to obtain the adjusted high-n bits of the quantization value.

[0020] The first adder is connected to the output of the accumulator and the output of the first adjustment unit, and is used to sum the adjusted high-order quantization value and the adjusted low-order quantization value to obtain the calibrated analog-to-digital conversion result.

[0021] In one possible implementation, the target slope is the ratio of the ideal slope of the analog-to-digital converter to the actual slope corresponding to the interval segment to which the quantization value of the high n bits of the analog-to-digital conversion result belongs.

[0022] In one possible implementation, 2 n The total number of intervals to be divided.

[0023] In the initial case, the endpoints of each interval segment include the origin 0 and i×b0, where b0 = A / 2 n , 1≤i≤2 n And i is an integer, A = 2 N This represents the maximum output value of the analog-to-digital converter.

[0024] After the device performs one calibration, the endpoints of each interval segment include 0 and b. i ,

[0025] in, k i Let j represent the slope corresponding to the i-th interval segment, where j is a positive integer.

[0026] In one possible implementation, the device further includes a parameter update module for updating the slope in the slope register and the endpoints of each interval segment using the calibrated analog-to-digital conversion result.

[0027] In one possible implementation, the parameter update module includes an endpoint update unit and multiple slope update units. The slope update units are used to perform slope update operations, and the endpoint update units are used to perform endpoint update operations based on the updated slopes.

[0028] Each slope update unit includes an absolute value judge, a third multiplier, and a least mean square filter. For any slope update unit:

[0029] The absolute value determiner is used to determine the magnitude of the absolute value of the input sample and the value of the corresponding endpoint, and outputs the determination result to the third multiplier. The input sample is the difference between the calibrated analog-to-digital conversion result and the digital code of the random signal added to the analog input signal. The input sample serves as the final analog-to-digital conversion result. The determination result is 1 if the absolute value of the input sample is greater than the value of the corresponding endpoint; and 0 if the absolute value of the input sample is less than or equal to the value of the corresponding endpoint.

[0030] The third multiplier is used to perform the multiplication operation between the judgment result and the sample, and input the operation result into the least mean square filter.

[0031] The minimum mean square filter is used to receive preset update parameters and the operation result, and output the updated slope.

[0032] The preset update parameters are related to the digital code.

[0033] In one possible implementation, the least mean square filter includes a fourth multiplier, a second adder, and a delay unit, wherein,

[0034] The fourth multiplier receives the operation result output by the third multiplier and the preset update parameters. The output of the fourth multiplier is connected to the first input of the second adder. The output of the fourth multiplier outputs the product of the operation result output by the third multiplier and the preset update parameters.

[0035] The second input of the second adder is connected to the output of the delay unit.

[0036] The input terminal of the delay unit is connected to the output terminal of the second adder, serving as the output terminal of the minimum mean square filter.

[0037] Wherein, the preset update parameter is μ·sign(D) d μ represents the preset value, sign() represents the sign function, and D d This refers to the numerical code.

[0038] According to one aspect of this disclosure, a driver chip is provided, the driver chip including the piecewise linear nonlinear calibration device for the analog-to-digital converter.

[0039] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned driver chip.

[0040] This embodiment of the present disclosure sets up a first adjustment unit to select a target slope from the slope storage unit based on the high n bits of the analog-to-digital conversion result, and adjusts the low-order quantization values ​​corresponding to the Nn bits of the analog-to-digital conversion result using the target slope to obtain adjusted low-order quantization values. A second adjustment unit sets up a second adjustment unit to adjust the high-order quantization values ​​corresponding to the high n bits of the analog-to-digital conversion result based on the slopes of multiple intervals preceding the interval corresponding to the target slope, obtaining adjusted high-order quantization values. The sum of the adjusted high-order quantization values ​​and the adjusted low-order quantization values ​​is used to obtain the calibrated analog-to-digital conversion result. Compared to traditional polynomial calibration, this embodiment can greatly reduce computational complexity, save area overhead, and improve energy efficiency. Compared to existing segmented calibration methods, this embodiment does not require an additional digital-to-analog converter, reducing hardware overhead and cost. Furthermore, the conversion process does not need to be interrupted during the conversion process, resulting in high analog-to-digital conversion efficiency.

[0041] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0043] Figure 1a shows a schematic diagram of the error curve of the existing segmented calibration, and Figure 1b shows a block diagram of the existing segmented calibration.

[0044] Figure 2 shows a schematic diagram of a piecewise linear nonlinear calibration device for an analog-to-digital converter according to an embodiment of the present disclosure.

[0045] Figure 3a shows a schematic diagram of a piecewise linear nonlinear calibration device for an analog-to-digital converter according to an embodiment of the present disclosure.

[0046] Figure 3b shows a schematic diagram of the segmentation under the initial condition, and Figure 3c shows a schematic diagram of the segmentation after calibration.

[0047] Figure 4 shows a schematic diagram of a piecewise linear nonlinear calibration device for an analog-to-digital converter according to an embodiment of the present disclosure. Detailed Implementation

[0048] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0049] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0051] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0052] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0053] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0054] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0055] Please refer to Figure 2, which shows a schematic diagram of a piecewise linear nonlinear calibration device for an analog-to-digital converter according to an embodiment of the present disclosure.

[0056] The analog-to-digital converter 10 is used to perform analog-to-digital conversion on the input analog input signal (Vi) and output the analog-to-digital conversion result. As shown in Figure 2, the device includes:

[0057] The first adjustment unit 20 is connected to the output terminal of the analog-to-digital converter 10. The first adjustment unit 20 is used to: select a target slope from the slope storage unit 40 according to the high n bits of the analog-to-digital conversion result, and adjust the low-bit quantization value corresponding to the Nn bits of the analog-to-digital conversion result using the target slope to obtain the adjusted low-bit quantization value, where N > n and are all positive integers, N is the conversion accuracy of the analog-to-digital converter 10, and the output range of the analog-to-digital converter 10 is divided into multiple continuous intervals, each interval corresponding to a slope;

[0058] The second adjustment unit 30 is connected to the output terminal of the analog-to-digital converter 10 and the output terminal of the first adjustment unit 20. The second adjustment unit 30 is used to: adjust the high-order quantization value corresponding to the high n bits of the analog-to-digital conversion result according to the slope of multiple intervals before the interval corresponding to the target slope, to obtain the adjusted high-order quantization value, and use the sum of the adjusted high-order quantization value and the adjusted low-order quantization value to obtain the calibrated analog-to-digital conversion result (Dout).

[0059] This embodiment of the present disclosure sets up a first adjustment unit 20 to select a target slope from the slope storage unit 40 based on the high n bits of the analog-to-digital conversion result, and adjusts the low-order quantization values ​​corresponding to the Nn bits of the analog-to-digital conversion result using the target slope to obtain adjusted low-order quantization values. A second adjustment unit 30 adjusts the high-order quantization values ​​corresponding to the high n bits of the analog-to-digital conversion result based on the slopes of multiple intervals preceding the interval corresponding to the target slope, obtaining adjusted high-order quantization values. The sum of the adjusted high-order quantization values ​​and the adjusted low-order quantization values ​​is used to obtain the calibrated analog-to-digital conversion result. Compared to traditional polynomial calibration, this embodiment can greatly reduce computational complexity, save area overhead, and improve energy efficiency. Compared to existing segmented calibration methods, this embodiment does not require an additional digital-to-analog converter, reducing hardware overhead and cost. Furthermore, the conversion process does not need to be interrupted during the conversion process, resulting in high analog-to-digital conversion efficiency.

[0060] The embodiments disclosed herein do not limit the specific implementation of the first adjustment unit 20 and the second adjustment unit 30. Those skilled in the art can adopt appropriate technical solutions according to actual conditions and needs, as long as the corresponding functions can be achieved.

[0061] In one possible implementation, the slope storage unit 40 may include multiple slope registers, each storing a corresponding slope. This disclosure does not limit the number or type of slope registers; those skilled in the art can set them according to actual conditions and needs. For example, corresponding slope registers can be set according to the number of segments, and the number of slope registers can be greater than or equal to the specific number of segments. In one possible implementation, 2 n If the total number of intervals is 2, then the number of slope registers can be greater than or equal to 2. n That is, each interval corresponds to a slope. For example, if n=2, it can be divided into 4 intervals. The slope storage unit 40 can include at least 4 slope registers, which are used to store the corresponding slopes of the 4 intervals. For example, the intervals can be arranged in ascending order, and the slopes corresponding to each interval can be numbered sequentially. In this example, the slopes of the first interval to the fourth interval correspond to k1 to k4, respectively.

[0062] This disclosure does not limit the specific magnitude of the slope of each interval segment. Those skilled in the art can set it according to actual conditions and needs. For example, multiple tests can be performed in advance to obtain the simulation curves of the input and output of the analog-to-digital converter 10, and the slope of each interval segment can be set according to the number of segments and the simulation curves, and stored in the corresponding slope register. Of course, this disclosure does not limit the specific implementation method of obtaining the initial slope, and those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs.

[0063] The following provides an exemplary description of possible implementations of the first adjustment unit 20 and the second adjustment unit 30.

[0064] Please refer to FIG3a, which shows a schematic diagram of a piecewise linear nonlinear calibration device for an analog-to-digital converter 10 according to an embodiment of the present disclosure.

[0065] In one possible implementation, as shown in FIG3a, the first adjustment unit 20 may include a first multiplexer MUX1 and a first multiplier MUL1, wherein...

[0066] The multiple inputs of the first multiplexer MUX1 are respectively connected to the slope registers of the slope storage unit 40. The control terminal of the first multiplexer is used to receive the high n bits (MSB) of the analog-to-digital conversion result. The output of the first multiplexer MUX1 is connected to the first input of the first multiplier MUL1. The output of the first multiplexer MUX1 is used to output the target slope.

[0067] The second input of the first multiplier MUL1 is used to receive the least significant quantized (LSB) value corresponding to the Nn bits of the analog-to-digital conversion result. The first multiplier MUL1 is used to perform a multiplication operation between the LSB value corresponding to the Nn bits of the analog-to-digital conversion result and the target slope. The output of the first multiplier MUL1 is used to output the adjusted LSB value. cal ).

[0068] In one possible implementation, as shown in FIG3a, the second adjustment unit 30 may include a second multiplexer MUX2, an accumulator AND0, a second multiplier MUL2, and a first adder AND1, wherein...

[0069] The second multiplexer MUX2 is used to select the slope of multiple intervals before the interval corresponding to the target slope from the slope storage unit 40 according to the high n bits of the analog-to-digital conversion result, and input it into the accumulator AND0. The accumulator AND0 is used to output the slope accumulation result.

[0070] The second multiplier MUL2 is used to perform a multiplication operation between the high n bits of the analog-to-digital conversion result and the slope accumulation result to obtain the adjusted high n bits of the quantized value.

[0071] The first adder AND1 is connected to the output of the accumulator AND0 and the output of the first adjustment unit 20, and is used to sum the adjusted high-order quantization value and the adjusted low-order quantization value to obtain the calibrated analog-to-digital conversion result.

[0072] For example, if the high n bits of the analog-to-digital conversion result are located in the third interval, the target slope is k3. The target slope corresponds to the slopes of multiple intervals before the interval, including the slope k1 of the first interval and the slope k2 of the second interval. The accumulator AND0 outputs the slope accumulation result (k1+k2), and the adjusted high-order quantization value MSB_cal = (k1+k2)×MSB.

[0073] Of course, the above description of the first adjustment unit 20 and the second adjustment unit 30 is exemplary and should not be regarded as a limitation of the embodiments of this disclosure. Those skilled in the art can adopt other methods to implement it according to actual conditions and needs. For example, the mapping relationship between each interval segment and the slope can be established in advance, and the controller can be used to query the target interval segment where the high n bits of the analog-to-digital conversion result are located. Then, the target slope can be obtained through the target interval segment and the mapping relationship established in advance.

[0074] In one possible implementation, the target slope is the ratio of the ideal slope of the analog-to-digital converter (ADC) to the actual slope of the interval segment corresponding to the quantized value of the high n bits of the ADC result. This embodiment of the present disclosure ensures that the slope of each segment of the output result after multiplication is equal to the ideal slope, thereby achieving nonlinear calibration. The ideal slope of the ADC can be obtained from the technical manual.

[0075] Please refer to Figures 3b and 3c. Figure 3b shows a schematic diagram of the segmentation under the initial condition, and Figure 3c shows a schematic diagram of the segmentation after calibration.

[0076] For simplicity, Figures 3b and 3c only show the case where the input signal is greater than 0. For inputs less than 0, the same correction operation can be performed after taking the absolute value. Of course, the reference value "0" here can also be other values ​​of the minimum input of the ADC. For example, for differential circuits, the reference value can be negative. In addition, the selection of the high 2 bits (n=2) shown in the figure (corresponding to the 4-segment piecewise linear approximation) is only a special case. The number of segments can be increased or decreased according to the calibration accuracy requirements.

[0077] In one possible implementation, as previously described, 2n To represent the total number of intervals, in this example, n = 2, so it can be divided into 4 intervals, as shown in Figure 3b. Initially, the endpoints of each interval include the origin 0 and i × b0, where b0 = A / 2. n , 1≤i≤2 n And i is an integer, A = 2 N The maximum output value of the analog-to-digital converter 10 is represented by the endpoints 0, b0, 2b0, 3b0, and 4b0 (not shown), which includes four intervals: 0 to b0, b0 to 2b0, 2b0 to 3b0, and 3b0 to 4b0. The slopes corresponding to the four intervals are k1, k2, k3, and k4, respectively.

[0078] For example, after the device performs a calibration, the endpoints of each interval segment include 0 and b. i ,

[0079] in, k i Let j represent the slope corresponding to the i-th interval segment, where j is a positive integer.

[0080] For example, analog input signals often introduce nonlinearity due to non-ideal characteristics in the circuit. For instance, as shown in Figure 3a, the input signal introduces nonlinearity after passing through a nonlinear unit (such as a nonlinear amplifier, nonlinear sampling circuit, or any circuit module that causes nonlinearity). The presence of this nonlinearity will reduce the performance of the analog-to-digital converter 10. In various embodiments of this disclosure, the analog input signal to the analog-to-digital converter 10 can be regarded as including nonlinearity. After the analog input signal is input to the analog-to-digital converter 10, it is quantized by the analog-to-digital converter 10 to obtain a quantized result of N-bit output.

[0081] For example, the quantization result is fed into a piecewise linear nonlinear calibration device. The correction behavior of the piecewise linear nonlinear calibration device is determined by a pre-set number of piecewise linear segments. As shown in Figure 3a, taking a 4-segment piecewise linear system as an example, assuming the full swing is 0 to A, it can be divided into four segments according to the quantization result: 0 to A / 4, A / 4 to A / 2, A / 2 to 3A / 4, and 3A / 4 to A. The width of each segment is defined as b0 (here, b0 = A / 4). The signal is quantized in steps of b0 to obtain the MSB (quantization result, high n bits) and LSB (quantization residual, Nn bits). In this embodiment, the MSB reflects which segment the signal is in. For a segment number of 2... n In the case of powers of n, the first n bits can be directly used as the MSB and the remaining (Nn) bits as the LSB (for example, the four broken lines in Figure 3a and Figure 3b correspond to n=2).

[0082] For example, the graphs shown in Figures 3b and 3c illustrate the distribution of MSB and LSB with the input when the number of broken lines is set to 4. After the above division, each LSB segment can be approximated as a straight line. To achieve non-linear calibration, it is only necessary to adjust the slope of all LSBs to be consistent and then splice them together.

[0083] Therefore, in this embodiment of the present disclosure, the slope of the LSB can be changed by selecting the corresponding correction coefficient (k1~k4) through the MSB, so that the slopes of each part of the curve are equal, as shown in Figure 3c. For example, as shown in Figure 3c, for the overall curve of the input and output of the analog-to-digital converter 10, after correction, the slope of each LSB curve segment changes from unequal (gray dashed line) to equal (gray solid line). This operation corresponds to the principle that the first adjustment unit 20 selects the target slope from the slope storage unit 40 according to the high n bits of the analog-to-digital conversion result, and uses the target slope to adjust the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result to obtain the adjusted low-order quantization value.

[0084] Meanwhile, during the splicing process, considering the changes in the slopes of each part, an appropriate offset needs to be selected to ensure continuity after splicing. For example, as shown in Figure 3b, the range of the first LSB before correction is 0 to b0. After multiplying by the correction factor k1, as shown in Figure 3c, its range becomes 0 to k1b0. Therefore, the starting point of the second LSB becomes k1b0, denoted as b1. At the same time, the width of the coverage area of ​​the second LSB also changes from b0 to k2b0. So, the coverage area after correction is k1b0 to (k1+k2)b0, denoted as b1 to b2.

[0085] This embodiment of the disclosure uses a second adjustment unit 30 to adjust the high-n bits of the analog-to-digital conversion result based on the slopes of multiple intervals preceding the target slope interval. This reselects the correct offset, enabling efficient and accurate nonlinear piecewise linear calibration. This operation corresponds to the second multiplexer MUX2, accumulator AND0, second multiplier MUL2, and first adder AND1 shown in Figure 3a. The MSB selects the slopes of multiple intervals preceding the target slope interval, and the accumulator AND0 performs accumulation to correct the high-n bits of the quantization value, which is then compared with the LSB obtained in the previous step. cal Summing yields the final output.

[0086] The above operation requires a slope (ki) and an offset (bi). The offset can be determined by the slope and a predefined step size (b0). Taking a 4-segment polyline as an example, the endpoints are:

[0087] 0;

[0088] b1 = k1b0;

[0089] b2 = (k1 + k2)b0;

[0090] b3 = (k1 + k2 + k3)b0.

[0091] In summary, for the general case of the M-segment broken line, the aforementioned general formula can be obtained:

[0092] Please refer to Figure 4, which shows a schematic diagram of a piecewise linear nonlinear calibration device for an analog-to-digital converter 10 according to an embodiment of the present disclosure.

[0093] In one possible implementation, as shown in FIG4, the device may further include a parameter update module 60 for updating the slope in the slope register and the endpoints of each interval segment using the calibrated analog-to-digital conversion result.

[0094] The present disclosure does not limit the specific implementation of the parameter update module 60. Those skilled in the art can use relevant technologies to implement it according to actual conditions and needs, as long as the corresponding parameter update function can be achieved. The preferred implementation methods are described below by example.

[0095] In one possible implementation, as shown in FIG4, the parameter update module 60 may include an endpoint update unit 620 and a plurality of slope update units 610. The slope update unit 610 is used to perform slope update operations, and the endpoint update unit 620 is used to perform endpoint update operations based on the updated slope.

[0096] Each slope update unit 610 may include an absolute value judge 6110, a third multiplier MUL3, and a minimum mean square filter. For any slope update unit 610:

[0097] The absolute value determiner 6110 is used to determine the magnitude of the absolute value of the input sample and the value of the corresponding endpoint, and outputs the determination result to the third multiplier MUL3, wherein the input sample is the difference (D) between the calibrated analog-to-digital conversion result and the digital code of the random signal added to the analog input signal. out,cal -D d The input sample serves as the final analog-to-digital conversion result (Dout). The judgment result is 1 if the absolute value of the input sample is greater than the value of the corresponding endpoint, and 0 if the absolute value of the input sample is less than or equal to the value of the corresponding endpoint.

[0098] The third multiplier MUL3 is used to perform the multiplication operation between the judgment result and the sample, and input the operation result into the least mean square filter.

[0099] The minimum mean square filter is used to receive preset update parameters and the operation result, and output the updated slope.

[0100] The preset update parameters are related to the digital code.

[0101] It is worth noting that although Figure 4 shows the difference between the calibrated analog-to-digital conversion result achieved by the third adder and the digital code of the random signal added to the analog input signal, this embodiment of the present disclosure does not limit this. For example, the digital code of the random signal of the analog input signal can also be input into the first adder AND1 in Figure 3a, and the input sample can be obtained by using the first adder AND1, thereby saving hardware overhead.

[0102] For example, as shown in Figure 4, an adder can be used in advance to add the random signal Vd to the input signal Vin. The input signal Vin after adding the random signal Vd passes through a nonlinear unit and is then input to the analog-to-digital converter 10 as an analog input signal.

[0103] This disclosure does not limit the specific implementation of the absolute value judge 6110. Those skilled in the art can implement it using relevant technologies according to actual conditions and needs. For example, the absolute value judge 6110 may include a first comparator, an inverter, and a second comparator. The first comparator is used to compare the input sample with 0. If the input sample is less than 0, the input sample is inverted through the inverter to obtain the absolute value of the input sample. If the input sample is greater than 0, there is no need to perform an inversion operation through the inverter. The second comparator can be used to compare the absolute value of the input sample with the value of the corresponding endpoint. When the absolute value of the input sample is greater than the value of the corresponding endpoint, the judgment result is 1 (the second comparator outputs a high-level signal); when the absolute value of the input sample is less than or equal to the value of the corresponding endpoint, the judgment result is 0 (the second comparator outputs a low-level signal).

[0104] Of course, other methods can also be used to determine the absolute value of the input sample, such as using built-in functions: many hardware platforms provide built-in functions for calculating absolute values. For example, in C, the `abs` function can be used to calculate the absolute value of an integer, and the `fabs` function can be used to calculate the absolute value of a floating-point number; binary two's complement arithmetic: for signed integers, the absolute value can be calculated using the properties of binary two's complement. In two's complement representation, the two's complement of a negative number is the inverted binary representation of its absolute value plus one. Through this operation, the absolute value of a negative number can be obtained directly.

[0105] This disclosure does not limit the specific implementation of the endpoint update unit 620. Those skilled in the art can implement it using relevant technologies according to actual conditions and needs. For example, it can be implemented using a processing component. Exemplary processing components include, but are not limited to, a single processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed using hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0106] For example, after receiving the updated slope, the endpoint update unit 620 can utilize the aforementioned endpoint formula. Update the endpoints.

[0107] This disclosure does not limit the specific implementation of the least mean square filter. Those skilled in the art can use relevant technologies to implement it according to actual conditions and needs, as long as the corresponding parameter update function can be achieved. The preferred implementation methods are described below by example.

[0108] In one possible implementation, as shown in Figure 4, the least mean square filter may include a fourth multiplier MUL4, a second adder AND2, and a delay unit Delay1, wherein...

[0109] The fourth multiplier MUL4 receives the operation result output by the third multiplier MUL3 and the preset update parameters. The output of the fourth multiplier MUL4 is connected to the first input of the second adder AND2. The output of the fourth multiplier MUL4 outputs the product of the operation result output by the third multiplier MUL3 and the preset update parameters.

[0110] The second input of the second adder AND2 is connected to the output of the delay unit Delay1.

[0111] The input of the delay unit Delay1 is connected to the output of the second adder AND2, serving as the output of the minimum mean square filter.

[0112] Wherein, the preset update parameter is μ·sign(D) d μ represents the preset value, sign() represents the sign function, and D d This refers to the numerical code.

[0113] The embodiments disclosed herein do not limit the specific parameter settings of the delay unit Delay1, and the delay size can be flexibly set according to the actual situation and needs.

[0114] For example, as shown in Figure 4, a voltage signal Vd modulated by a pseudo-random code is added to the input signal Vin. This random code is independent of the input signal. After passing through a nonlinear unit, the input signal Vin is used as an input analog signal and input to the analog-to-digital converter 10 for quantization. The quantization result is then input to the nonlinear piecewise linear nonlinear calibration device (first adjustment unit 20, second adjustment unit 30) mentioned in Figure 2. The codeword D corresponding to this random code is then... d Subtracted from the number field (D) out,cal -D d Assuming the piecewise linear nonlinear calibration device can completely correct all nonlinear errors, then subtracting the resulting output Dout and random code D... d They are completely uncorrelated. Conversely, if nonlinearity is not completely eliminated, Dout and D... d There is still a correlation between them. Utilizing this characteristic, embodiments of this disclosure update the slope (ki) using a least mean square filter, such that Dout and D... d There is a correlation between them.

[0115] Since different calibration coefficients involve different samples, this embodiment of the present disclosure creatively uses a gated least mean square filter with an adaptive threshold to update the calibration coefficients.

[0116] For example, in the calibration device (first adjustment unit 20, second adjustment unit 30) shown in Figure 2, coefficient k1 directly affects samples with absolute values ​​from 0 to b0, whose corrected absolute value range is 0 to b1. Simultaneously, k1 also affects samples with absolute values ​​> b0, whose corrected range is > b1. This is because the calculation of these samples involves b1, b2, and b3, and k1 participates in the calculation of b1, b2, and b3. In other words, k1 affects all samples, so all samples will be used to update k1. Conversely, k4 only affects samples with corrected absolute values ​​> b3, so only these samples will be used to update k4.

[0117] Based on this observation, in this embodiment of the present disclosure, an absolute value judge 6110 and a third multiplier MUL3 are inserted before each least mean square filter as range selectors to judge the range of the input sample. Only when the input sample is within the corresponding range will it be sent to the least mean square filter to update the corresponding correction coefficient.

[0118] For example, as shown in Figure 4, the threshold of this range selector is the offset (bi), and bi is not a fixed value, but is determined by ki (the specific calculation formula is given above). In other words, bi is used to select samples to update ki. After updating k1 to k4, the corresponding b1 to b3 are recalculated and used as new thresholds to select updated samples. This is the adaptive threshold-gated least mean square filter proposed in this embodiment. In short, "adaptive threshold" means that the threshold (bi) determines whether to update the coefficients (ki), and the threshold is adjusted after the coefficients are updated, hence the name "adaptive threshold" (as opposed to "fixed threshold").

[0119] Using the above method, the calibration coefficients of the segmented polyline can be extracted in the background.

[0120] The nonlinear calibration algorithm of this disclosure has the following advantages:

[0121] 1. Piecewise nonlinear calibration is adopted, which can greatly reduce computational complexity, save area overhead, and improve energy efficiency compared with traditional polynomial calibration.

[0122] 2. The proposed adaptive threshold-gated least mean square filter can achieve background extraction of piecewise linear coefficients with very low digital cost, thus greatly expanding the application scenarios of the algorithm.

[0123] This disclosure presents a piecewise piecewise linear nonlinear calibration technique based on jitter injection and an adaptive threshold-gated least mean square filter. This technique enables background extraction of piecewise linear coefficients with low hardware complexity, thereby significantly expanding the application scope of the piecewise piecewise linear nonlinear calibration technique. This invention can be applied to all application scenarios requiring nonlinear error calibration, such as high-speed, high-precision pipelined analog-to-digital converters 10 and high-linearity sample-and-hold front-ends.

[0124] According to one aspect of this disclosure, a driver chip is provided, the driver chip including the piecewise linear nonlinear calibration device of the analog-to-digital converter 10.

[0125] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned driver chip.

[0126] The terminal device can be a user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, and wireless terminal in vehicle networking, etc. For example, the server can be a local server or a cloud server.

[0127] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A piecewise linear nonlinear calibration device for an analog-to-digital converter, characterized in that, The analog-to-digital converter is used to perform analog-to-digital conversion on the input analog input signal and output the analog-to-digital conversion result, wherein the device includes: The first adjustment unit is connected to the output terminal of the analog-to-digital converter. The first adjustment unit is used to: select a target slope from the slope storage unit according to the high n bits of the analog-to-digital conversion result, and adjust the low-bit quantization value corresponding to the Nn bits of the analog-to-digital conversion result using the target slope to obtain the adjusted low-bit quantization value, where N > n and are all positive integers, N is the conversion accuracy of the analog-to-digital converter, and the output range of the analog-to-digital converter is divided into multiple continuous intervals, each interval corresponding to a slope; The second adjustment unit is connected to the output terminal of the analog-to-digital converter and the output terminal of the first adjustment unit. The second adjustment unit is used to: adjust the high-n quantization value corresponding to the high bit of the analog-to-digital conversion result according to the slope of multiple intervals before the interval corresponding to the target slope, to obtain the adjusted high-bit quantization value, and use the sum of the adjusted high-bit quantization value and the adjusted low-bit quantization value to obtain the calibrated analog-to-digital conversion result.

2. The apparatus according to claim 1, characterized in that, The slope storage unit includes multiple slope registers, each storing a corresponding slope. The first adjustment unit includes a first multiplexer and a first multiplier. The multiple inputs of the first multiplexer are respectively connected to the slope registers of the slope storage unit. The control terminal of the first multiplexer is used to receive the high n bits of the analog-to-digital conversion result. The output terminal of the first multiplexer is connected to the first input terminal of the first multiplier. The output terminal of the first multiplexer is used to output the target slope. The second input of the first multiplier is used to receive the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result. The first multiplier is used to perform the multiplication operation between the low-order quantization value corresponding to the Nn bits of the analog-to-digital conversion result and the target slope. The output of the first multiplier is used to output the adjusted low-order quantization value.

3. The apparatus according to claim 1 or 2, characterized in that, The second adjustment unit includes a second multiplexer, an accumulator, a second multiplier, and a first adder, wherein, The second multiplexer is used to select the slope of multiple intervals before the interval corresponding to the target slope from the slope storage unit according to the high n bits of the analog-to-digital conversion result, and input them into the accumulator. The accumulator is used to output the slope accumulation result. The second multiplier is used to perform a multiplication operation between the high-n bits of the analog-to-digital conversion result and the slope accumulation result to obtain the adjusted high-n bits of the quantization value. The first adder is connected to the output of the accumulator and the output of the first adjustment unit, and is used to sum the adjusted high-order quantization value and the adjusted low-order quantization value to obtain the calibrated analog-to-digital conversion result.

4. The apparatus according to claim 1, characterized in that, The target slope is the ratio of the ideal slope of the analog-to-digital converter to the actual slope of the interval segment to which the quantization value corresponding to the high n bits of the analog-to-digital conversion result belongs.

5. The apparatus according to claim 1, characterized in that, 2 n The total number of intervals to be divided. In the initial case, the endpoints of each interval segment include the origin 0 and i×b0, where b0 = A / 2 n , 1≤i≤2 n And i is an integer, A = 2 N This represents the maximum output value of the analog-to-digital converter. After the device performs one calibration, the endpoints of each interval segment include 0 and b. i , in, k i Let j represent the slope corresponding to the i-th interval segment, where j is a positive integer.

6. The apparatus according to claim 5, characterized in that, The device further includes a parameter update module, used to update the slope in the slope register and the endpoints of each interval segment using the calibrated analog-to-digital conversion result.

7. The apparatus according to claim 6, characterized in that, The parameter update module includes an endpoint update unit and multiple slope update units. The slope update unit is used to perform slope update operations, and the endpoint update unit is used to perform endpoint update operations based on the updated slope. Each slope update unit includes an absolute value judge, a third multiplier, and a least mean square filter. For any slope update unit: The absolute value determiner is used to determine the magnitude of the absolute value of the input sample and the value of the corresponding endpoint, and outputs the determination result to the third multiplier. The input sample is the difference between the calibrated analog-to-digital conversion result and the digital code of the random signal added to the analog input signal. The input sample serves as the final analog-to-digital conversion result. The determination result is 1 if the absolute value of the input sample is greater than the value of the corresponding endpoint; and 0 if the absolute value of the input sample is less than or equal to the value of the corresponding endpoint. The third multiplier is used to perform the multiplication operation between the judgment result and the sample, and input the operation result into the least mean square filter. The minimum mean square filter is used to receive preset update parameters and the operation result, and output the updated slope. The preset update parameters are related to the digital code.

8. The apparatus according to claim 7, characterized in that, The minimum mean square filter includes a fourth multiplier, a second adder, and a delay unit, wherein... The fourth multiplier receives the operation result output by the third multiplier and the preset update parameters. The output of the fourth multiplier is connected to the first input of the second adder. The output of the fourth multiplier outputs the product of the operation result output by the third multiplier and the preset update parameters. The second input of the second adder is connected to the output of the delay unit. The input terminal of the delay unit is connected to the output terminal of the second adder, serving as the output terminal of the minimum mean square filter. Wherein, the preset update parameter is μ·sign(D) d μ represents the preset value, sign() represents the sign function, and D d This refers to the numerical code.

9. A driver chip, characterized in that, The driver chip includes a piecewise nonlinear calibration device for an analog-to-digital converter as described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the driver chip as described in claim 9.

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