Method for improving thickness uniformity of ion-implantation protective layer
By forming a uniform fourth dielectric layer capping layer on the mesa structure of the power MOSFET, the problem of inconsistent gate dielectric layer thickness was solved, improving the uniformity of ion implantation and product performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2025-08-06
- Publication Date
- 2026-07-30
AI Technical Summary
In the prior art, the inconsistent thickness of the gate dielectric layer on the mesa structure of power MOSFETs leads to poor uniformity of ion implantation depth, which affects product performance.
By forming a fourth dielectric layer as a capping layer on the mesa structure, the dielectric layer thickness is made uniform everywhere. Deep trenches are formed using photolithography and etching techniques, and a uniform protective layer is formed through chemical mechanical planarization and thermal oxidation to ensure the uniformity of ion implantation.
This method achieves uniformity in the thickness of the protective layer before ion implantation, improves the convergence of product performance parameters, and avoids the negative impact of uneven implantation depth on product performance.
Smart Images
Figure CN2025113015_30072026_PF_FP_ABST
Abstract
Description
Methods to improve the uniformity of ion implantation protective layer thickness Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the thickness uniformity of ion implantation protective layers. Background Technology
[0002] Power MOSFETs, as one of the main types of power semiconductor devices, are widely used in communications, computers, automobiles and consumer electronics, and are an important component of discrete devices and smart power integrated circuits.
[0003] One type of power MOS trench gate product forms gate dielectric layers of two thicknesses in the cell region. The thinner gate dielectric layer region can quickly discharge charge to achieve higher frequency application environments.
[0004] Existing processes following the formation of two gate dielectric layers of different thicknesses include:
[0005] Step 1: Provide a substrate 101. Deep trenches are formed on the cell regions of the substrate 101. A first gate dielectric layer 102 and a source polysilicon layer 103 are formed at the bottom of the deep trenches. An isolation dielectric layer is formed on the first gate dielectric layer 102 and the source polysilicon layer 103. Second and third gate dielectric layers (105, 104) of different thicknesses are formed on different deep trenches and the mesa structures on both sides. The thinner gate dielectric layer region can quickly discharge charge to achieve higher frequency application environments, forming the structure shown in Figure 1.
[0006] Step 2: Form a gate polysilicon layer 106 to fill the remaining deep trench, forming the structure shown in Figure 2;
[0007] Step 3: Please refer to Figure 3. Ion implantation is used to form the body region and the source region. Due to the inconsistent thickness of the second and third gate dielectric layers on the mesa structure, it has a significant impact on the uniformity of the subsequent implantation depth.
[0008] To address the aforementioned issues, a novel method is needed to improve the uniformity of the ion implantation protective layer thickness. Summary of the Invention
[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the uniformity of the thickness of the ion implantation protective layer, in order to solve the problem that the inconsistent thickness of the gate dielectric layer on the mesa structure in the prior art has a significant impact on the uniformity of the subsequent implantation depth.
[0010] To achieve the above and other related objectives, the present invention provides a method for improving the thickness uniformity of an ion-implanted protective layer, comprising:
[0011] Step 1: Provide a substrate, and form deep trenches on the cell regions of the substrate. Form a first gate dielectric layer and a source polysilicon layer at the bottom of the deep trenches. Form an isolation dielectric layer on the first gate dielectric layer and the source polysilicon layer. Form second and third gate dielectric layers of different thicknesses on different deep trenches and the mesa structures on both sides of them.
[0012] Step 2: Form a gate polysilicon layer to fill the remaining deep trenches;
[0013] Step 3: Form a fourth dielectric layer covering the gate polysilicon layer, the second and third gate dielectric layers, and etch back the fourth dielectric layer so that the total thickness of the dielectric layer at each point on the mesa structure is the target value.
[0014] Step 4: Use ion implantation to form the body region and the source region, with the dielectric layer on the mesa structure serving as the ion implantation protective layer.
[0015] Preferably, the deep trench is formed in step one using photolithography and etching methods.
[0016] Preferably, the material of the first gate dielectric layer in step one is oxide or silicon nitride.
[0017] Preferably, the materials of the second and third gate dielectric layers and the isolation dielectric layer in step one are oxides.
[0018] Preferably, the method for forming the gate polysilicon layer in step two includes: depositing the gate polysilicon layer; grinding the gate polysilicon layer to a first preset height, wherein the height of the second gate dielectric layer is lower than the height of the third gate dielectric layer, and the first preset height is not lower than the height of the third gate dielectric layer; and etching the gate polysilicon layer to a third preset height, wherein the second preset height is not higher than the height of the second gate dielectric layer.
[0019] Preferably, the grinding method in step two is chemical mechanical planarization grinding.
[0020] Preferably, the material of the fourth dielectric layer in step three is an oxide.
[0021] Preferably, the fourth dielectric layer is formed in step three using a thermal oxidation method.
[0022] Preferably, the thickness of the fourth dielectric layer in step three is greater than 800 angstroms.
[0023] As described above, the method for improving the uniformity of ion implantation protective layer thickness of the present invention has the following beneficial effects:
[0024] This invention achieves uniformity in the thickness of the ion implantation protective layer before ion implantation, avoiding a significant impact on the uniformity of subsequent implantation depth and resulting in better convergence of various product performance parameters. Attached Figure Description
[0025] Figure 1 shows a schematic diagram of the formation of second and third gate dielectric layers of different thicknesses in the prior art;
[0026] Figure 2 shows a schematic diagram of the formation of a gate polysilicon layer in the prior art;
[0027] Figure 3 shows a schematic diagram of ion implantation in the prior art;
[0028] Figure 4 shows a schematic diagram of the process flow of the present invention;
[0029] Figure 5 shows a schematic diagram of the formation of second and third gate dielectric layers of different thicknesses according to the present invention;
[0030] Figure 6 shows a schematic diagram of the formation of the gate polysilicon layer according to the present invention;
[0031] Figure 7 shows a schematic diagram of the formation of the fourth dielectric layer according to the present invention;
[0032] Figure 8 shows a schematic diagram of the fourth dielectric layer etched back according to the present invention;
[0033] Figure 9 shows a schematic diagram of ion implantation according to the present invention. Detailed Implementation
[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0035] Please refer to Figure 4. This invention provides a method for improving the uniformity of ion implantation protective layer thickness, comprising:
[0036] Step 1: Provide a substrate 201. Deep trenches are formed on the cell regions of the substrate 201. A first gate dielectric layer 202 and a source polysilicon layer 203 are formed at the bottom of the deep trenches. An isolation dielectric layer is formed on the first gate dielectric layer 202 and the source polysilicon layer 203. Second and third gate dielectric layers of different thicknesses are formed on different deep trenches and the mesa structures on both sides. The thinner gate dielectric layer region can quickly discharge charge to achieve higher frequency application environments, forming the structure shown in Figure 5.
[0037] In some embodiments, the deep trench is formed in step one using photolithography and etching methods, and the etching method is dry etching.
[0038] In some embodiments, the materials of the second and third gate dielectric layers and the isolation dielectric layer in step one are oxides.
[0039] In some embodiments, the material of the first gate dielectric layer in step one is silicon nitride or silicon dioxide.
[0040] Step 2: Form a gate polysilicon layer 206 to fill the remaining deep trench, forming the structure shown in Figure 6;
[0041] In some embodiments, the method of forming the gate polysilicon layer 206 in step two includes: depositing the gate polysilicon layer 206; grinding the gate polysilicon layer 206 to a first preset height, wherein the height of the second gate dielectric layer 205 is lower than the height of the third gate dielectric layer 204, and the first preset height is not lower than the height of the third gate dielectric layer 204; etching the gate polysilicon layer 206 to a second preset height, wherein the etching method is dry etching or wet etching, and the second preset height is not higher than the height of the second gate dielectric layer 205.
[0042] In some embodiments, the grinding method in step two is chemical mechanical planarization grinding.
[0043] Step 3: Form a fourth dielectric layer 207 covering the gate polysilicon layer 206, the second and third gate dielectric layers, and form the structure shown in Figure 7. Etch back the fourth dielectric layer 207. The etching method is dry etching or wet etching, so that the total thickness of the dielectric layer at all points on the mesa structure is the target value, and form the structure shown in Figure 8.
[0044] In some embodiments, the material of the fourth dielectric layer 207 in step three is an oxide.
[0045] In some embodiments, the fourth dielectric layer 207 is formed in step three by thermal oxidation, so that the second and third gate dielectric layers, which originally had two different thicknesses, have the same thickness after thermal oxidation.
[0046] In some embodiments, the thickness of the fourth dielectric layer 207 in step three is greater than 800 angstroms.
[0047] Step 4: Please refer to Figure 9. By using the ion implantation to form the body region and source region, the dielectric layer on the mesa structure serves as the ion implantation protective layer. This achieves uniformity in the thickness of the ion implantation protective layer before implantation, avoiding a significant impact on the uniformity of subsequent implantation depth and resulting in better convergence of various performance parameters of the product.
[0048] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0049] In summary, this invention achieves uniformity in the thickness of the ion implantation protective layer before ion implantation, avoiding a significant impact on the uniformity of subsequent implantation depth and resulting in better convergence of various product performance parameters. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0050] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for improving thickness uniformity of an ion implantation protective layer, comprising: At least including: Step 1: Provide a substrate, and form deep trenches on the cell regions of the substrate. Form a first gate dielectric layer and a source polysilicon layer at the bottom of the deep trenches. Form an isolation dielectric layer on the first gate dielectric layer and the source polysilicon layer. Form second and third gate dielectric layers of different thicknesses on different deep trenches and the mesa structures on both sides of them. Step 2: Form a gate polysilicon layer to fill the remaining deep trenches; Step 3: Form a fourth dielectric layer covering the gate polysilicon layer, the second and third gate dielectric layers, and etch back the fourth dielectric layer so that the total thickness of the dielectric layer at each point on the mesa structure is the target value. Step 4: Use ion implantation to form the body region and the source region, with the dielectric layer on the mesa structure serving as the ion implantation protective layer.
2. The method of claim 1, wherein: In step one, the deep trench is formed using photolithography and etching methods.
3. The method of claim 1, wherein: The material of the first gate dielectric layer in step one is silicon nitride or silicon dioxide.
4. The method of claim 1, wherein: The materials of the second and third gate dielectric layers and the isolation dielectric layer in step one are oxides.
5. The method of claim 1, wherein: The material of the isolation dielectric layer in step one is silicon nitride or silicon dioxide.
6. The method of claim 1, wherein: The method for forming the gate polysilicon layer in step two includes: depositing the gate polysilicon layer; grinding the gate polysilicon layer to a first preset height, wherein the height of the second gate dielectric layer is lower than the height of the third gate dielectric layer, and the first preset height is not lower than the height of the third gate dielectric layer; and etching the gate polysilicon layer to a third preset height, wherein the second preset height is not higher than the height of the second gate dielectric layer.
7. The method of claim 6, wherein: The grinding method described in step two is chemical mechanical planarization grinding.
8. The method of claim 1, wherein: The material of the fourth dielectric layer in step three is an oxide.
9. The method of claim 8, wherein: In step three, the fourth dielectric layer is formed using a thermal oxidation method.
10. The method of claim 8, wherein: The thickness of the fourth dielectric layer in step three is greater than 800 angstroms.
11. The method of claim 1, wherein: The method is used for the manufacture of power MOSFETs.