GOA driving buffer circuit, display driving chip and display apparatus

Abstract

A GOA driving buffer circuit, a display driving chip and a display apparatus. The GOA driving buffer circuit comprises a first branch and a second branch which are constructed by using non-high-voltage transistors, and a signal output terminal (OUT); the first branch and the second branch are each provided with a switch transistor connected to the signal output terminal (OUT) and a substrate switching circuit for controlling the voltage differences among a gate, a source and a drain of the switch transistor to be within a medium-voltage operating range, so that when the level range of the signal output terminal (OUT) is within a high-voltage domain, the non-high-voltage transistors in the GOA driving buffer circuit can be protected. Thus, the GOA driving buffer circuit using non-high-voltage transistors can not only implement the signal driving function, but also reduce or eliminate the use of high-voltage transistors, thereby reducing or eliminating steps of manufacturing high-voltage devices in a manufacturing process for display driving chips, and further reducing the number of photomasks used and reducing chip manufacturing costs.

Description

GOA driver buffer circuit, display driver chip and display device

[0001] This application claims priority to Chinese Patent Application No. 202510098614.6, filed on January 22, 2025, entitled "GOA Driver Buffer Circuit, Display Driver Chip and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display driver chip technology, and in particular to a GOA driver buffer circuit, a display driver chip, and a display device. Background Technology

[0003] In the current design of display driver integrated circuit (DDIC) chips for mobile phones, since the thin film transistors (TFTs) on the panel are usually designed with high voltage transistors, the GOA driving signal (or gate active driving signal) sent to the panel needs to be driven by a high voltage buffer. Technical issues

[0004] In traditional DDIC design, the GOA drive buffer circuit designed with high-voltage devices (such as high-voltage transistors) occupies a large chip area and uses a large number of photomasks, which leads to an increase in chip manufacturing costs. Therefore, how to provide a GOA drive buffer circuit that can reduce chip manufacturing costs is a technical problem that urgently needs to be solved by those skilled in the art. Technical solutions

[0005] The purpose of this application is to provide a GOA driving buffer circuit, a display driver chip, and a display device, which can reduce or eliminate the step of manufacturing high-voltage devices in the display driver chip manufacturing process, thereby saving the number of photomasks used and reducing chip manufacturing costs.

[0006] To achieve the above objectives:

[0007] In a first aspect, embodiments of this application provide a GOA driving buffer circuit, comprising: a signal output terminal. A first branch includes a first signal driving unit and a first switching unit connected in sequence, wherein the first switching unit includes a first switching transistor and a first substrate switching circuit. The gate of the first switching transistor is grounded, the source of the first switching transistor is connected to the first signal driving unit to receive a positive high-level signal, and the drain of the first switching transistor is connected to the signal output terminal to transmit a positive high-level signal to the signal output terminal when the positive high-level signal is a positive high-level signal. The first substrate switching circuit is connected to the source and drain of the first switching transistor to control the voltage difference between the gate, source, and drain of the first switching transistor within the medium-voltage operating range. A second branch includes a second signal driving unit and a second switching unit connected in sequence, wherein the second switching unit includes a second switching transistor and a second substrate switching circuit. The gate of the second switching transistor is grounded, the source of the second switching transistor is connected to the second signal driving unit to receive a negative high-level signal, and the drain of the second switching transistor is connected to the signal output terminal to transmit a negative high-level signal to the signal output terminal when the negative high-level signal is a negative high-level signal. The second substrate switching circuit connects the source and drain of the second switching transistor to control the voltage difference between the gate, source, and drain of the second switching transistor within the medium-voltage operating range. Specifically, the transistors in the first signal driving unit and the first switching unit of the first branch are both non-high-voltage transistors. Similarly, the transistors in the second signal driving unit and the second switching unit of the second branch are also non-high-voltage transistors.

[0008] In one embodiment, the first substrate switching circuit includes a third switching transistor and a fourth switching transistor. The gate of the third switching transistor is connected to the drain of the first switching transistor, the source of the third switching transistor is connected to the substrate of the first switching transistor, and the drain of the third switching transistor is connected to the source of the first switching transistor. The gate of the fourth switching transistor is connected to the source of the first switching transistor, the source of the fourth switching transistor is connected to the substrate of the first switching transistor, and the drain of the fourth switching transistor is connected to the drain of the first switching transistor. And / or, the second substrate switching circuit includes a fifth switching transistor and a sixth switching transistor. The gate of the fifth switching transistor is connected to the drain of the second switching transistor, the source of the fifth switching transistor is connected to the substrate of the second switching transistor, and the drain of the sixth switching transistor is connected to the drain of the second switching transistor.

[0009] In one embodiment, the positive high-level signal alternates between a positive high-level signal and a ground level. The negative high-level signal alternates between a negative high-level signal and a ground level.

[0010] In one embodiment, when the positive high-level signal is at a positive high level, the negative high-level signal is at a ground level. The first switching transistor is turned on to transmit the positive high-level signal received at its source to the signal output terminal, while the second switching transistor is turned off, the fifth switching transistor is turned on, and the sixth switching transistor is turned off, thereby switching the substrate of the second switching transistor to a ground level. When the negative high-level signal is at a negative high level, the positive high-level signal is at a ground level. The second switching transistor is turned on to transmit the negative high-level signal received at its source to the signal output terminal, while the first switching transistor is turned off, the third switching transistor is turned on, and the fourth switching transistor is turned off, thereby switching the substrate of the first switching transistor to a ground level.

[0011] In one embodiment, the first switching transistor is a PMOS transistor. The second switching transistor is an NMOS transistor.

[0012] In one embodiment, the first signal driving unit includes a positive voltage level shifting circuit and a first inverter. The first inverter includes a seventh switching transistor and an eighth switching transistor. The gate of the seventh switching transistor is connected to the output terminal of the positive voltage level shifting circuit, the source of the seventh switching transistor receives a positive high voltage level, and the drain of the seventh switching transistor is connected to the source of the first switching transistor. The gate of the eighth switching transistor is connected to the output terminal of the positive voltage level shifting circuit, the source of the eighth switching transistor is grounded, and the drain of the eighth switching transistor is connected to the source of the first switching transistor. The positive voltage level shifting circuit converts the received first low voltage domain signal into a first medium voltage domain signal and outputs the first medium voltage domain signal through its output terminal to drive the seventh and eighth switching transistors to cooperate in outputting a positive high voltage level signal. And / or, the second signal driving unit includes a negative voltage level shifting circuit and a second inverter. The second inverter includes a ninth switching transistor and a tenth switching transistor. The gate of the ninth switching transistor is connected to the output terminal of the negative voltage level shifting circuit, the source of the ninth switching transistor is grounded, and the drain of the ninth switching transistor is connected to the source of the second switching transistor. The gate of the tenth switching transistor is connected to the output of the negative voltage level shifting circuit, the source of the tenth switching transistor receives a negative high voltage level, and the drain of the tenth switching transistor is connected to the source of the second switching transistor. The negative voltage level shifting circuit is used to convert the received second low voltage domain signal into a second medium voltage domain signal, and outputs the second medium voltage domain signal through the output of the negative voltage level shifting circuit to drive the ninth and tenth switching transistors to cooperate in outputting a negative high voltage level signal.

[0013] In one embodiment, the GOA drive buffer circuit further includes an ESD resistor. The drains of both the first and second switching transistors are connected to the signal output terminal via the ESD resistor.

[0014] In one embodiment, the signal output terminal of the GOA driving buffer circuit is connected to the GOA scanning circuit on the OLED panel.

[0015] Secondly, embodiments of this application provide a display driver chip, including the GOA driver buffer circuit as described in any of the preceding claims.

[0016] Thirdly, embodiments of this application provide a display device including a GOA driving buffer circuit as described in any of the preceding claims. Beneficial effects

[0017] The GOA driving buffer circuit, display driver chip, and display device provided in this application embodiment include: a GOA driving buffer circuit, comprising: a signal output terminal; a first branch, comprising a first signal driving unit and a first switching unit connected in sequence, wherein the first switching unit includes a first switching transistor and a first substrate switching circuit; the gate of the first switching transistor is grounded, the source of the first switching transistor is connected to the first signal driving unit to receive a positive high-level signal, and the drain of the first switching transistor is connected to the signal output terminal to transmit a positive high-level signal to the signal output terminal when the positive high-level signal is a positive high-level signal; the first substrate switching circuit is connected to the source and drain of the first switching transistor to control the voltage difference between the gate, source, and drain of the first switching transistor within the medium-voltage operating range; a second branch, comprising a first signal driving unit and a first switching unit connected in sequence. The system includes a second signal driving unit and a second switching unit. The second switching unit includes a second switching transistor and a second substrate switching circuit. The gate of the second switching transistor is grounded, the source of the second switching transistor is connected to the second signal driving unit to receive a negative high-level signal, and the drain of the second switching transistor is connected to the signal output terminal to transmit a negative high-level signal to the signal output terminal when the negative high-level signal is a negative high-level signal. The second substrate switching circuit is connected to the source and drain of the second switching transistor to control the voltage difference between the gate, source, and drain of the second switching transistor within the medium-voltage operating range. The transistors in the first signal driving unit and the first switching unit of the first branch are both non-high-voltage transistors. The transistors in the second signal driving unit and the second switching unit of the second branch are both non-high-voltage transistors. Thus, the GOA driving buffer circuit in this application includes a first branch, a second branch, and a signal output terminal built using non-high voltage transistors (e.g., medium voltage transistors). Switching transistors connected to the signal output terminal are respectively set in the first and second branches, along with a substrate switching circuit that controls the voltage difference between the gate, source, and drain of the switching transistors within the medium voltage operating range. This ensures that when the signal output terminal's level range is within the high voltage domain, the non-high voltage transistors in the GOA driving buffer circuit can be protected. Therefore, the GOA driving buffer circuit using non-high voltage transistors can not only achieve its signal driving function but also reduce or eliminate the use of high voltage transistors. This allows the display driver chip manufacturing process to reduce or eliminate the steps involved in manufacturing high voltage devices, thereby saving the number of photomasks used and reducing chip manufacturing costs. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a schematic diagram of the framework of the GOA driving buffer circuit provided in the embodiment of this application.

[0020] Figure 2 is a circuit diagram of a GOA driving buffer circuit as exemplified in an embodiment of this application.

[0021] Figure 3 is a simulation waveform diagram of the GOA drive buffer circuit exemplified in the embodiments of this application.

[0022] Explanation of reference numerals in the attached diagram:

[0023] First signal driving unit U1a, second signal driving unit U1b, first switching unit U2a, second switching unit U2b, first substrate switching circuit U21a, second substrate switching circuit U21b, signal output terminal OUT;

[0024] First switching transistor M1, third switching transistor M3, fourth switching transistor M4, seventh switching transistor M7, and eighth switching transistor M8;

[0025] Second switching transistor M2, fifth switching transistor M5, sixth switching transistor M6, ninth switching transistor M9, and tenth switching transistor M10;

[0026] Positive voltage level shifting circuit LVS1, negative voltage level shifting circuit LVS2;

[0027] First node A, second node B, third node C;

[0028] First low-voltage domain signal INP, second low-voltage domain signal INN;

[0029] Positive voltage high level VGH, negative voltage low level VGL, ground level GND.

[0030] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Embodiments of the present invention

[0031] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present invention. Based on the description of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0032] Unless otherwise explicitly specified and limited, the terms "setup," "installation," and "connection" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms based on the specific circumstances.

[0033] The terms “upper,” “lower,” “left,” “right,” “front,” “back,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are only for the convenience of description and simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0034] The terms “first,” “second,” “third,” etc., are used merely to distinguish elements with similar properties, not to indicate or imply relative importance or a specific order.

[0035] The terms “include,” “comprising,” or any other variation thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0036] The terms “or” and “and / or” are interpreted as inclusive, or mean any one or any combination thereof. Therefore, “A, B or C” or “A, B and / or C” means “any one of the following: A; B; C; A and B; A and C; B and C; A, B and C”.

[0037] In the following description, the use of suffixes such as "module," "part," or "unit" to denote components is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0038] The following is a brief explanation of the terms that may be used in this application:

[0039] 1. The Display Driver Integrated Circuit (DDIC) is one of the main control components of a display panel, often referred to as the "brain" of the panel. The main function of the DDIC is to send drive signals and data to the display panel in the form of electrical signals, thereby controlling the screen's brightness and color, enabling the display of text, images, and other graphic information on the screen.

[0040] 2. OLED panels, used in display panels, are manufactured based on the electroluminescent properties of organic materials. When current passes through the organic light-emitting layer, electrons and holes recombine in the layer, releasing photons and thus emitting light. Each pixel is an independent light-emitting unit, eliminating the need for a backlight. For some low-power OLED panels, due to their self-emissive nature, the required driving voltage is lower than that of traditional LCD panels. For the display driver chip of OLED panels, the GOA (Geometric Alignment) driver buffer circuit can operate within a lower voltage range, making the design of medium-voltage devices in the display driver chip possible.

[0041] 3. The GOA drive buffer circuit is used to drive the GOA (Gate On Array or Gate Driver On Array) drive signal (or gate active drive signal) to the GOA scanning circuit on the display panel.

[0042] 4. Cost issues arising from the use of high-voltage devices in traditional DDIC designs:

[0043] (1) Large chip area: High-voltage devices need to withstand higher voltages, so their device structures are relatively complex. For example, they require thicker oxide layers to increase voltage withstand capability, or special device structure designs to disperse the electric field strength, thereby avoiding breakdown. This results in a larger area for a single high-voltage device compared to low-voltage or medium-voltage devices, which in turn increases the area of ​​the entire DDIC chip. The increase in chip area directly leads to an increase in the cost per chip, because the number of chips that can be cut from the same wafer area is reduced;

[0044] (2) Larger number of photomasks: In the traditional DDIC manufacturing process, photomasks are used to guide how the photoresist on the wafer is cured, thereby forming the physical structure of the circuit. The complex structural design of high-voltage devices requires more photomasks to achieve pattern transfer at different levels. For example, in some high-voltage device processes, additional photomasks may be needed to form special structural layers of the high-voltage device. Increasing the number of photomasks not only increases the complexity of the manufacturing process, but also leads to an increase in photomask costs, as the manufacturing cost of each photomask is relatively high. In addition, increasing the number of photomasks will also prolong the manufacturing cycle, because each additional photomask requires additional photolithography, exposure, development and other steps.

[0045] Referring to Figures 1 and 2, an embodiment of this application provides a GOA driving buffer circuit, including: a first branch, a second branch, and a signal output terminal OUT.

[0046] The first branch includes a first signal driving unit U1a and a first switching unit U2a connected in sequence.

[0047] In one embodiment, the first branch is used to perform signal processing through the cooperation of the first signal driving unit U1a and the first switching unit U2a to output a positive voltage high level VGH to the signal output terminal OUT.

[0048] Among them, the transistors in the first signal driving unit U1a and the first switching unit U2a of the first branch are both non-high voltage transistors.

[0049] In one embodiment, the non-high-voltage transistor may include low-voltage transistors and medium-voltage transistors. Preferably, the non-high-voltage transistor in this embodiment may be a medium-voltage transistor.

[0050] In one embodiment, the low-voltage transistor has a smaller device size compared to the high-voltage or medium-voltage transistor. The manufacture of the low-voltage transistor can reduce or eliminate the need for a photomask compared to the manufacture of the high-voltage transistor.

[0051] In one embodiment, the operating voltage of the low-voltage transistor can be, but is not limited to, between 1.2V and 3.3V, for processing and transmitting low-voltage signals. Due to its low operating voltage, the low-voltage transistor has relatively low power consumption, making it suitable for high-integration and low-power display driver chips. The low-voltage transistor has a fast switching speed, which can meet the needs of high-speed data processing and transmission. The low-voltage transistor has a small device size, which is beneficial to improving the integration of the chip. Optionally, the low-voltage transistor can be used in: (1) digital logic circuits: for processing and transmitting digital signals, such as clock circuits, control circuits, data processing circuits, etc.; (2) interface circuits: for signal interaction with external control circuits (such as microcontrollers, system processors).

[0052] In one embodiment, the medium-voltage transistor has a smaller device size compared to the high-voltage transistor. The manufacture of the medium-voltage transistor can reduce or eliminate the need for a photomask compared to the manufacture of the high-voltage transistor.

[0053] In one embodiment, the operating voltage of the medium-voltage transistor may be, but is not limited to, between 6V and 12V (e.g., greater than 3.3V and less than 12V) for processing and transmitting medium-voltage signals.

[0054] The first switching unit U2a includes a first switching transistor M1 and a first substrate switching circuit U21a.

[0055] In this configuration, the gate of the first switching transistor M1 is grounded, the source of the first switching transistor M1 is connected to the first signal driving unit U1a to receive a positive high-level signal, and the drain of the first switching transistor M1 is connected to the signal output terminal OUT to transmit the positive high-level signal VGH to the signal output terminal OUT when the positive high-level signal is a positive high-level signal VGH, or to turn off when the positive high-level signal is a ground level GND.

[0056] In one embodiment, the first switching transistor M1 is a non-high-voltage transistor and is a PMOS transistor. The PMOS transistor turns on when the absolute value of the gate-source voltage difference VGS is greater than its threshold voltage VTH.

[0057] The first substrate switching circuit U21a is connected to the source and drain of the first switching transistor M1 to control the voltage difference between the gate, source and drain of the first switching transistor M1 within the medium voltage operating range.

[0058] In one embodiment, the first substrate switching circuit U21a can switch the voltage level of the substrate of the first switching transistor M1. By changing the substrate voltage, the threshold voltage, leakage current, and electric field distribution of the first switching transistor M1 can be controlled, thereby ensuring that the first switching transistor M1 and its preceding transistor meet the withstand voltage requirements and improving the stability and reliability of the circuit.

[0059] In one embodiment, referring to FIG2, the first substrate switching circuit U21a includes a third switching transistor M3 and a fourth switching transistor M4.

[0060] In one embodiment, the gate of the third switching transistor M3 is connected to the drain of the first switching transistor M1, the source of the third switching transistor M3 is connected to the substrate of the first switching transistor M1, and the drain of the third switching transistor M3 is connected to the source of the first switching transistor M1.

[0061] In one embodiment, the third switching transistor M3 is a non-high voltage transistor and is a PMOS transistor.

[0062] In one embodiment, the gate of the fourth switching transistor M4 is connected to the source of the first switching transistor M1, the source of the fourth switching transistor M4 is connected to the substrate of the first switching transistor M1, and the drain of the fourth switching transistor M4 is connected to the drain of the first switching transistor M1.

[0063] In one embodiment, the fourth switching transistor M4 is a non-high voltage transistor and is a PMOS transistor.

[0064] In one embodiment, the first signal driving unit U1a is used to process and output a positive high-level signal.

[0065] In one embodiment, referring to FIG2, the first signal driving unit U1a includes a positive voltage level shift circuit LVS1 and a first inverter.

[0066] In one embodiment, the first inverter includes a seventh switching transistor M7 and an eighth switching transistor M8.

[0067] In one embodiment, the gate of the seventh switching transistor M7 is connected to the output terminal of the positive voltage level shifting circuit LVS1, the source of the seventh switching transistor M7 receives the positive voltage high level VGH, and the drain of the seventh switching transistor M7 is connected to the source of the first switching transistor M1.

[0068] In one embodiment, the seventh switching transistor M7 is a non-high voltage transistor and is a PMOS transistor.

[0069] In one embodiment, the gate of the eighth switching transistor M8 is connected to the output terminal of the positive voltage level shifting circuit LVS1, the source of the eighth switching transistor M8 is grounded, and the drain of the eighth switching transistor M8 is connected to the source of the first switching transistor M1.

[0070] In one embodiment, the eighth switching transistor M8 is a non-high voltage transistor and is an NMOS transistor.

[0071] In one embodiment, the positive voltage level shifting circuit LVS1 is used to convert the received first low voltage domain signal INP into a first medium voltage domain signal, and output the first medium voltage domain signal through the output terminal of the positive voltage level shifting circuit LVS1 to drive the seventh switching transistor M7 and the eighth switching transistor M8 to cooperate in outputting a positive voltage high level signal.

[0072] In one embodiment, the positive voltage level shifting circuit LVS1 can also be constructed using non-high voltage transistors.

[0073] The second branch includes a second signal driving unit U1b and a second switching unit U2b connected in sequence.

[0074] In one embodiment, the second branch is used to perform signal processing through the cooperation of the second signal driving unit U1b and the second switching unit U2b to output a negative voltage high level VGL to the signal output terminal OUT.

[0075] Among them, the transistors in the second signal driving unit U1b and the second switching unit U2b of the second branch are both non-high voltage transistors.

[0076] The second switching unit U2b includes a second switching transistor M2 and a second substrate switching circuit U21b.

[0077] In this configuration, the gate of the second switching transistor M2 is grounded, the source of the second switching transistor M2 is connected to the second signal driving unit U1b to receive a negative high-level signal, and the drain of the second switching transistor M2 is connected to the signal output terminal OUT to transmit a negative high-level signal VGL to the signal output terminal OUT when the negative high-level signal is a negative high-level signal VGL, or to turn off when the negative high-level signal is a ground level GND.

[0078] In one embodiment, the second switching transistor M2 is a non-high-voltage transistor and is an NMOS transistor. The NMOS transistor turns on when the gate-source voltage difference VGS is greater than its threshold voltage VTH.

[0079] The second substrate switching circuit U21b is connected to the source and drain of the second switching transistor M2 to control the voltage difference between the gate, source and drain of the second switching transistor M2 within the medium voltage operating range.

[0080] In one embodiment, the second substrate switching circuit U21b can switch the voltage level of the substrate of the second switching transistor M2. By changing the substrate voltage, the threshold voltage, leakage current, and electric field distribution of the second switching transistor M2 can be controlled, thereby ensuring that the second switching transistor M2 and its preceding transistor meet the withstand voltage requirements and improving the stability and reliability of the circuit.

[0081] In one embodiment, referring to FIG2, the second substrate switching circuit U21b includes a fifth switching transistor M5 and a sixth switching transistor M6.

[0082] In one embodiment, the gate of the fifth switching transistor M5 is connected to the drain of the second switching transistor M2, the source of the fifth switching transistor M5 is connected to the substrate of the second switching transistor M2, and the drain of the fifth switching transistor M5 is connected to the source of the second switching transistor M2.

[0083] In one embodiment, the fifth switching transistor M5 is a non-high voltage transistor and is an NMOS transistor.

[0084] In one embodiment, the gate of the sixth switching transistor M6 is connected to the source of the second switching transistor M2, the source of the sixth switching transistor M6 is connected to the substrate of the second switching transistor M2, and the drain of the sixth switching transistor M6 is connected to the drain of the second switching transistor M2.

[0085] In one embodiment, the sixth switching transistor M6 is a non-high voltage transistor and is an NMOS transistor.

[0086] In one embodiment, the second signal driving unit U1b is used to process and output a negative voltage high-level signal.

[0087] In one embodiment, referring to FIG2, the second signal driving unit U1b includes a negative voltage level displacement circuit LVS2 and a second inverter.

[0088] In one embodiment, the second inverter includes a ninth switching transistor M9 and a tenth switching transistor M10.

[0089] In one embodiment, the gate of the ninth switching transistor M9 is connected to the output terminal of the negative voltage level shifting circuit LVS2, the source of the ninth switching transistor M9 is grounded, and the drain of the ninth switching transistor M9 is connected to the source of the second switching transistor M2.

[0090] In one embodiment, the ninth switching transistor M9 is a non-high voltage transistor and is a PMOS transistor.

[0091] In one embodiment, the gate of the tenth switching transistor M10 is connected to the output terminal of the negative voltage level shifting circuit LVS2, the source of the tenth switching transistor M10 receives the negative voltage high level VGL, and the drain of the tenth switching transistor M10 is connected to the source of the second switching transistor M2.

[0092] In one embodiment, the tenth switching transistor M10 is a non-high voltage transistor and is an NMOS transistor.

[0093] In one embodiment, the negative voltage level shifting circuit LVS2 is used to convert the received second low voltage domain signal INN into a second medium voltage domain signal, and output the second medium voltage domain signal through the output terminal of the negative voltage level shifting circuit LVS2 to drive the ninth switching transistor M9 and the tenth switching transistor M10 to output a negative voltage high level signal.

[0094] In one embodiment, the negative voltage level shifting circuit LVS2 can also be constructed using non-high voltage transistors.

[0095] In one embodiment, the positive high-level signal can alternate between a positive high-level voltage (VGH) and a ground level (GND). The negative high-level signal can alternate between a negative high-level voltage (VGL) and a ground level (GND).

[0096] In one embodiment, when the positive high-level signal is positive high-level VGH and the negative high-level signal is ground level GND, the first switching transistor M1 is turned on to transmit the positive high-level VGH received at the source of the first switching transistor M1 to the signal output terminal OUT, and the second switching transistor M2 is turned off, the fifth switching transistor M5 is turned on, and the sixth switching transistor M6 is turned off, so as to switch the substrate of the second switching transistor M2 to ground level GND, thereby controlling the voltage difference between the gate, source, and drain of the second switching transistor M2 within the medium-voltage operating range.

[0097] In one embodiment, when the negative high-level signal is negative high-level VGL, the positive high-level signal is ground level GND. The second switching transistor M2 is turned on to transmit the negative high-level VGL received by the source of the second switching transistor M2 to the signal output terminal OUT. Meanwhile, the first switching transistor M1 is turned off, the third switching transistor M3 is turned on, and the fourth switching transistor M4 is turned off, so as to switch the substrate of the first switching transistor M1 to ground level GND, thereby controlling the voltage difference between the gate, source, and drain of the first switching transistor M1 within the medium-voltage operating range.

[0098] In one embodiment, the signal output terminal OUT has a voltage range from positive high level VGH to negative high level VGL, which is a high voltage range.

[0099] In one embodiment, the signal output terminal OUT of the GOA drive buffer circuit is connected to the GOA scanning circuit on the OLED panel. Optionally, traditional LCD panels require a high gate drive voltage (GOA drive signal level), which limits the use of high-voltage devices in the DDIC chip circuit design. With the advancement of panel technology, OLED panels typically use LTPS or IGZO technology. These materials have higher electron mobility. In some mobile terminal (e.g., mobile phones, smartwatches, etc.) display applications, a lower gate drive voltage can drive OLED pixel units. Thus, the GOA drive buffer circuit provided by this embodiment can be applied to the display of mobile terminals, reducing the use of high-voltage devices in the display, thereby reducing the number of photomasks and the manufacturing cost of the DDIC in the display.

[0100] In one embodiment, the GOA drive buffer circuit further includes an ESD resistor (or electrostatic discharge resistor). The drains of the first switching transistor M1 and the second switching transistor M2 are both connected to the signal output terminal OUT via the ESD resistor. By setting the ESD resistor, the circuit can be protected from electrostatic damage and stable signal transmission can be ensured.

[0101] In summary, the GOA driving buffer circuit provided in the above embodiments includes: a signal output terminal OUT. A first branch includes a first signal driving unit U1a and a first switching unit U2a connected in sequence, wherein the first switching unit U2a includes a first switching transistor M1 and a first substrate switching circuit U21a. The gate of the first switching transistor M1 is grounded, the source of the first switching transistor M1 is connected to the first signal driving unit U1a to receive a positive high-level signal, and the drain of the first switching transistor M1 is connected to the signal output terminal OUT to transmit a positive high-level signal VGH to the signal output terminal OUT when the positive high-level signal is a positive high-level signal VGH. The first substrate switching circuit U21a is connected to the source and drain of the first switching transistor M1 to control the voltage difference between the gate, source, and drain of the first switching transistor M1 within the medium-voltage operating range. A second branch includes a second signal driving unit U1b and a second switching unit U2b connected in sequence, wherein the second switching unit U2b includes a second switching transistor M2 and a second substrate switching circuit U21b. The gate of the second switching transistor M2 is grounded, and its source is connected to the second signal driving unit U1b to receive a negative high-level signal. The drain of the second switching transistor M2 is connected to the signal output terminal OUT to transmit a negative high-level signal VGL to the signal output terminal OUT when the negative high-level signal is a negative high-level signal VGL. The second substrate switching circuit U21b is connected to the source and drain of the second switching transistor M2 to control the voltage difference between the gate, source, and drain of the second switching transistor M2 within the medium-voltage operating range. The transistors in the first signal driving unit U1a and the first switching unit U2a in the first branch are both non-high-voltage transistors. Similarly, the transistors in the second signal driving unit U1b and the second switching unit U2b in the second branch are also non-high-voltage transistors. Thus, in this embodiment, the GOA driving buffer circuit includes a first branch, a second branch, and a signal output terminal OUT constructed using non-high voltage transistors (e.g., medium voltage transistors). The first and second branches are respectively equipped with switching transistors connected to the signal output terminal OUT, and a substrate switching circuit that controls the voltage difference between the gate, source, and drain of the switching transistors within the medium voltage operating range. This ensures that when the signal output terminal OUT's level range is within the high voltage domain, the non-high voltage transistors in the GOA driving buffer circuit can be protected. Therefore, the GOA driving buffer circuit using non-high voltage transistors can not only achieve its signal driving function but also reduce or eliminate the use of high voltage transistors. This allows the display driver chip manufacturing process to reduce or eliminate the steps involved in manufacturing high voltage devices, thereby saving the number of photomasks used and reducing chip manufacturing costs.

[0102] Thus, the GOA drive buffer circuit provided in this embodiment is an improvement on the traditional GOA drive buffer circuit in DDIC. It achieves the goal of replacing high-voltage devices with medium-voltage or low-voltage devices while meeting the driving performance requirements of GOA drive signals. This eliminates the step of manufacturing high-voltage devices during chip production, saves the number of photomasks, and reduces chip costs.

[0103] Based on the same inventive concept as the foregoing embodiments, and referring to Figures 2 and 3, this embodiment illustrates a GOA drive buffer circuit without high-voltage components for reference:

[0104] Referring to Figure 2, the GOA drive buffer circuit without high-voltage components provided in this example includes: a first branch, a second branch, and a signal output terminal OUT.

[0105] The first branch includes the positive voltage level shift circuit LVS1, the first inverter, and the first switching unit U2a.

[0106] The positive voltage level shifting circuit LVS1 is used to convert the received first low voltage domain signal INP into a first medium voltage domain signal, and output the first medium voltage domain signal through the output terminal of the positive voltage level shifting circuit LVS1.

[0107] The first inverter includes a seventh switching transistor M7 and an eighth switching transistor M8.

[0108] In this circuit, the gate of the seventh switching transistor M7 is connected to the output of the positive voltage level shifting circuit LVS1 to receive the first voltage domain signal, the source of the seventh switching transistor M7 receives the positive high voltage level VGH, and the drain of the seventh switching transistor M7 is connected to the first node A; the gate of the eighth switching transistor M8 is connected to the output of the positive voltage level shifting circuit LVS1 to receive the first voltage domain signal, the source of the eighth switching transistor M8 is grounded, and the drain of the eighth switching transistor M8 is connected to the first node A.

[0109] Specifically, the output terminal of the positive voltage level shifting circuit LVS1 outputs a first voltage domain signal to drive the seventh switching transistor M7 and the eighth switching transistor M8 to output a positive voltage high-level signal to the first node A.

[0110] The first switching unit U2a includes a first switching transistor M1 and a first substrate switching circuit U21a constructed from a third switching transistor M3 and a fourth switching transistor M4.

[0111] In this configuration, the gate of the first switching transistor M1 is grounded, the source of the first switching transistor M1 is connected to the first node A, and the drain of the first switching transistor M1 is connected to the third node C. The first transistor is a PMOS transistor.

[0112] The gate of the third switching transistor M3 is connected to the drain of the first switching transistor M1, the source of the third switching transistor M3 is connected to the substrate of the first switching transistor M1, and the drain of the third switching transistor M3 is connected to the first node A.

[0113] The gate of the fourth switching transistor M4 is connected to the first node A, the source of the fourth switching transistor M4 is connected to the substrate of the first switching transistor M1, and the drain of the fourth switching transistor M4 is connected to the drain of the first switching transistor M1.

[0114] In other words, the gates of the third switching transistor M3 and the fourth switching transistor M4 are connected to the drain and source of the first switching transistor M1, respectively.

[0115] The second branch includes the negative voltage level displacement circuit LVS2, the second inverter, and the second switching unit U2b.

[0116] The negative voltage level shifting circuit LVS2 is used to convert the received second low voltage domain signal INN into a second middle voltage domain signal, and output the second middle voltage domain signal through the output terminal of the negative voltage level shifting circuit LVS2.

[0117] The second inverter includes a ninth switching transistor M9 and a tenth switching transistor M10.

[0118] In this circuit, the gate of the ninth switching transistor M9 is connected to the output terminal of the negative voltage level shifting circuit LVS2, the source of the ninth switching transistor M9 is grounded, and the drain of the ninth switching transistor M9 is connected to the second node B; the gate of the tenth switching transistor M10 is connected to the output terminal of the negative voltage level shifting circuit LVS2, the source of the tenth switching transistor M10 receives the negative voltage high level VGL, and the drain of the tenth switching transistor M10 is connected to the second node B.

[0119] Specifically, the output terminal of the negative voltage level shifting circuit LVS2 outputs a second voltage domain signal to drive the ninth switching transistor M9 and the tenth switching transistor M10 to output a negative voltage high-level signal to the second node B.

[0120] The second switching unit U2b includes a second switching transistor M2 and a second substrate switching circuit U21b constructed from a fifth switching transistor M5 and a sixth switching transistor M6.

[0121] In this configuration, the gate of the second switching transistor M2 is grounded, the source of the second switching transistor M2 is connected to the second node B, and the drain of the second switching transistor M2 is connected to the third node C. The second transistor is an NMOS transistor.

[0122] In this configuration, the gate of the fifth switching transistor M5 is connected to the drain of the second switching transistor M2, the source of the fifth switching transistor M5 is connected to the substrate of the second switching transistor M2, and the drain of the fifth switching transistor M5 is connected to the second node B.

[0123] In this configuration, the gate of the sixth switching transistor M6 is connected to the second node B, the source of the sixth switching transistor M6 is connected to the substrate of the second switching transistor M2, and the drain of the sixth switching transistor M6 is connected to the drain of the second switching transistor M2.

[0124] In other words, the gate of the fifth switching transistor M5 and the gate of the sixth switching transistor M6 are connected to the drain and source of the second switching transistor M2, respectively.

[0125] The signal output terminal OUT is connected to the third node C through an ESD resistor.

[0126] Among them, the first switching transistor M1 to the tenth switching transistor M10, the positive voltage level shifting circuit LVS1, and the negative voltage level shifting circuit LVS2 are all medium voltage devices.

[0127] Optionally, the first substrate switching circuit U21a is used to switch the substrate level of the substrate of the first switching transistor M1 so as to control the voltage difference between the gate, source and drain of the first switching transistor M1 within the medium voltage operating range, so that the first switching transistor M1 and its preceding devices meet the voltage withstand requirements of medium voltage devices.

[0128] Optionally, the second substrate switching circuit U21b is used to switch the substrate level of the substrate of the second switching transistor M2 so as to control the voltage difference between the gate, source and drain of the second switching transistor M2 within the medium voltage operating range, so that the second switching transistor M2 and its preceding devices meet the voltage withstand requirements of medium voltage devices.

[0129] Optionally, the signal output terminal OUT is used to output a positive high voltage level VGH and a negative high voltage level VGL according to the actual timing requirements.

[0130] Alternatively, the circuit works as follows:

[0131] (1) When the voltage level of the first node A is positive high voltage level VGH, since the first switching transistor M1 is a PMOS transistor and its gate is grounded, the first switching transistor M1 is turned on, and the positive high voltage level VGH is transmitted from the first node A to the third node C through the first switching transistor M1.

[0132] (2) When the level of the second node B is ground level GND, since the level of the third node C is positive high voltage level VGH, and the second switching transistor M2 is an NMOS transistor with its gate grounded, the substrate level of the substrate of the second switching transistor M2 needs to be switched to ground level GND to meet the withstand voltage requirements of the medium voltage device. Therefore, the fifth switching transistor M5 is turned on, the sixth switching transistor M6 is turned off, and the substrate of the second switching transistor M2 is switched to be connected to the second node B so that the substrate level of the substrate of the second switching transistor M2 is switched to ground level GND.

[0133] (3) When the level of the second node B is the negative high voltage level VGL, since the second switching transistor M2 is an NMOS transistor and its gate is grounded, the second switching transistor M2 is turned on at this time, and the negative high voltage level VGL is transmitted from the second node B to the third node C through the second switching transistor M2.

[0134] (4) When the level of the first node A is ground level GND, since the level of the third node C is negative high voltage level VGL, the first switching transistor M1 is a PMOS transistor and its gate is grounded. The substrate level of the substrate of the first switching transistor M1 needs to be switched to ground level GND to meet the withstand voltage requirements of the medium voltage device. At this time, the third switching transistor M3 is turned on, the fourth switching transistor M4 is turned off, and the substrate of the first switching transistor M1 is switched to be connected to the first node A so that the substrate level of the substrate of the first switching transistor M1 is switched to ground level GND.

[0135] Specifically, the positive high-level signal alternates between the positive high-level signal VGH and the ground level GND; the negative high-level signal alternates between the negative high-level signal VGL and the ground level GND. When the positive high-level signal is the positive high-level signal VGH, the negative high-level signal is the ground level GND; when the negative high-level signal is the negative high-level signal VGL, the positive high-level signal is the ground level GND.

[0136] Referring to Figure 3, the simulation waveform obtained based on the aforementioned circuit working principle is as follows:

[0137] When the voltage level of the first node A is positive high voltage level VGH, the voltage level of the second node B is ground level GND, and the voltage level of the third node C is positive high voltage level VGH, the substrate voltage level of the first switching transistor M1 is positive high voltage level VGH, and the substrate voltage level of the second switching transistor M2 switches to ground level GND, which meets the withstand voltage requirements of medium voltage devices.

[0138] When the voltage level of the first node A is ground level GND, the voltage level of the second node B is negative high voltage level VGL, and the voltage level of the third node C is negative high voltage level VGL, the substrate voltage level of the second switching transistor M2 is negative high voltage level VGL, and the substrate voltage level of the first switching transistor M1 switches to ground level GND, thus meeting the withstand voltage requirements of medium voltage devices.

[0139] Optionally, "high voltage / non-high voltage" may refer only to the description of transistors, where non-high voltage transistors are used in both the level shifting circuit and the substrate switching circuit. The substrate switching circuit serves a protective function by ensuring that the substrate level of the first switching transistor M1 and the substrate level of the second switching transistor M2, respectively, are within the medium-voltage operating range of their gate, source, and drain during the transmission of the high and low levels of the GOA drive signal. In this example, the GOA drive buffer circuit without high-voltage devices outputs the GOA drive signal to the GOA scanning circuit on the OLED panel, enabling the GOA scanning circuit to drive the pixel units on the OLED panel.

[0140] Since the voltage level of the third node C is VGH~VGL (which is in the high voltage range), this exceeds the operating voltage range of the medium voltage transistor. The first switching transistor M1 and the second switching transistor M2 can block this high voltage and protect the medium voltage transistors in the preceding stage corresponding to the first switching transistor M1 and the second switching transistor M2, respectively.

[0141] In summary, the GOA drive buffer circuit without high-voltage components provided in this example can be used in low-voltage, low-power applications of mobile terminals (such as mobile phones, wearable devices, etc.). The GOA drive buffer circuit in DDIC can replace high-voltage components with medium-voltage components, reduce the number of photomasks, and lower chip costs.

[0142] This example provides a GOA drive buffer circuit without high-voltage components. It utilizes the characteristic that PMOS transistors transmit high levels and NMOS transistors transmit low levels, and sets up a first switching transistor M1 and a second switching transistor M2 to achieve time-division multiplexing of the positive high-voltage level VGH and the negative high-voltage level VGL. Furthermore, the gates of the first switching transistor M1 and the second switching transistor M2 are connected to GND, eliminating the need for external bias voltage and simplifying the circuit.

[0143] The GOA drive buffer circuit provided in this example, which does not use high-voltage components, utilizes a substrate switching circuit to ensure that the medium-voltage components always meet the withstand voltage requirements during the switching between positive and negative high levels at the signal output terminal OUT.

[0144] Based on the same inventive concept as the foregoing embodiments, this application provides a display driver chip, including a GOA driving buffer circuit as described in any of the preceding claims. The GOA driving buffer circuit includes a first branch, a second branch, and a signal output terminal OUT, all constructed using non-high-voltage transistors (e.g., medium-voltage transistors). The first and second branches are respectively equipped with switching transistors connected to the signal output terminal OUT, and a substrate switching circuit that controls the voltage difference between the gate, source, and drain of the switching transistors within the medium-voltage operating range. This ensures that when the signal output terminal OUT is in the high-voltage range, the non-high-voltage transistors in the GOA driving buffer circuit are protected. Therefore, the GOA driving buffer circuit using non-high-voltage transistors not only achieves its signal driving function but also reduces or eliminates the need for high-voltage transistors. This allows the display driver chip manufacturing process to reduce or eliminate the steps involved in fabricating high-voltage devices, thereby saving on the number of photomasks used and reducing chip manufacturing costs.

[0145] Based on the same inventive concept as the foregoing embodiments, this application provides a display device including a GOA driving buffer circuit or a display driver chip as described in any of the preceding claims. The GOA driving buffer circuit includes a first branch, a second branch, and a signal output terminal OUT constructed using non-high-voltage transistors (e.g., medium-voltage transistors). Switching transistors connected to the signal output terminal OUT are respectively provided in the first and second branches, along with a substrate switching circuit that controls the voltage difference between the gate, source, and drain of the switching transistors to remain within the medium-voltage operating range. This ensures that when the level range of the signal output terminal OUT is within the high-voltage domain, the non-high-voltage transistors in the GOA driving buffer circuit are protected. Therefore, the GOA driving buffer circuit using non-high-voltage transistors not only achieves its signal driving function but also reduces or eliminates the need for high-voltage transistors. This allows for fewer or no steps in the display driver chip manufacturing process, reducing the number of photomasks used and lowering chip manufacturing costs. Thus, the technical solution of this embodiment provides a low-cost display device.

[0146] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0147] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0148] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A GOA driving buffer circuit, characterized in that, include: Signal output terminal; The first branch includes a first signal driving unit and a first switching unit connected in sequence. The first switching unit includes a first switching transistor and a first substrate switching circuit. The gate of the first switching transistor is grounded, the source of the first switching transistor is connected to the first signal driving unit to receive a positive high-level signal, and the drain of the first switching transistor is connected to the signal output terminal to transmit the positive high-level signal to the signal output terminal when the positive high-level signal is positive high-level. The first substrate switching circuit is connected to the source and drain of the first switching transistor to control the voltage difference between the gate, source, and drain of the first switching transistor within the medium-voltage operating range. The second branch includes a second signal driving unit and a second switching unit connected in sequence. The second switching unit includes a second switching transistor and a second substrate switching circuit. The gate of the second switching transistor is grounded, the source of the second switching transistor is connected to the second signal driving unit to receive a negative high-level signal, and the drain of the second switching transistor is connected to the signal output terminal to transmit the negative high-level signal to the signal output terminal when the negative high-level signal is a negative high-level signal. The second substrate switching circuit is connected to the source and drain of the second switching transistor to control the voltage difference between the gate, source, and drain of the second switching transistor within the medium-voltage operating range. In this circuit, the transistors in the first signal driving unit and the first switching unit of the first branch are both non-high voltage transistors; the transistors in the second signal driving unit and the second switching unit of the second branch are both non-high voltage transistors.

2. The GOA driving buffer circuit according to claim 1, characterized in that, The first substrate switching circuit includes a third switching transistor and a fourth switching transistor; wherein the gate of the third switching transistor is connected to the drain of the first switching transistor, the source of the third switching transistor is connected to the substrate of the first switching transistor, and the drain of the third switching transistor is connected to the source of the first switching transistor; the gate of the fourth switching transistor is connected to the source of the first switching transistor, the source of the fourth switching transistor is connected to the substrate of the first switching transistor, and the drain of the fourth switching transistor is connected to the drain of the first switching transistor; and / or, The second substrate switching circuit includes a fifth switching transistor and a sixth switching transistor; wherein, the gate of the fifth switching transistor is connected to the drain of the second switching transistor, the source of the fifth switching transistor is connected to the substrate of the second switching transistor, and the drain of the fifth switching transistor is connected to the source of the second switching transistor; the gate of the sixth switching transistor is connected to the source of the second switching transistor, the source of the sixth switching transistor is connected to the substrate of the second switching transistor, and the drain of the sixth switching transistor is connected to the drain of the second switching transistor.

3. The GOA driving buffer circuit according to claim 2, characterized in that, The positive high-level signal alternates between a positive high-level signal and a ground level; The negative voltage high-level signal alternates between negative voltage high level and ground level.

4. The GOA driving buffer circuit according to claim 3, characterized in that, When the positive high-level signal is positive high-level, the negative high-level signal is ground level. The first switching transistor is turned on to transmit the positive high-level signal received by the source of the first switching transistor to the signal output terminal. The second switching transistor is turned off, the fifth switching transistor is turned on, and the sixth switching transistor is turned off to switch the substrate of the second switching transistor to ground level. When the negative high-level signal is negative high-level, the positive high-level signal is ground level. The second switching transistor is turned on to transmit the negative high-level signal received by the source of the second switching transistor to the signal output terminal. The first switching transistor is turned off, the third switching transistor is turned on, and the fourth switching transistor is turned off to switch the substrate of the first switching transistor to ground level.

5. The GOA driving buffer circuit according to claim 1, characterized in that, The first switching transistor is a PMOS transistor; The second switching transistor is an NMOS transistor.

6. The GOA drive buffer circuit according to any one of claims 1 to 5, characterized in that, The first signal driving unit includes a positive voltage level shifting circuit and a first inverter; wherein, the first inverter includes a seventh switching transistor and an eighth switching transistor; the gate of the seventh switching transistor is connected to the output terminal of the positive voltage level shifting circuit, the source of the seventh switching transistor receives the positive high voltage level, and the drain of the seventh switching transistor is connected to the source of the first switching transistor; the gate of the eighth switching transistor is connected to the output terminal of the positive voltage level shifting circuit, the source of the eighth switching transistor is grounded, and the drain of the eighth switching transistor is connected to the source of the first switching transistor; the positive voltage level shifting circuit is used to convert the received first low voltage domain signal into a first medium voltage domain signal, and output the first medium voltage domain signal through the output terminal of the positive voltage level shifting circuit to drive the seventh switching transistor and the eighth switching transistor to cooperate in outputting the positive high voltage level signal; and / or, The second signal driving unit includes a negative voltage level shifting circuit and a second inverter; wherein, the second inverter includes a ninth switching transistor and a tenth switching transistor; the gate of the ninth switching transistor is connected to the output terminal of the negative voltage level shifting circuit, the source of the ninth switching transistor is grounded, and the drain of the ninth switching transistor is connected to the source of the second switching transistor; the gate of the tenth switching transistor is connected to the output terminal of the negative voltage level shifting circuit, the source of the tenth switching transistor receives the negative high voltage level, and the drain of the tenth switching transistor is connected to the source of the second switching transistor; the negative voltage level shifting circuit is used to convert the received second low voltage domain signal into a second medium voltage domain signal, and output the second medium voltage domain signal through the output terminal of the negative voltage level shifting circuit, so as to drive the ninth switching transistor and the tenth switching transistor to cooperate in outputting the negative high voltage level signal.

7. The GOA drive buffer circuit according to any one of claims 1 to 5, characterized in that, It also includes ESD resistors; The drains of the first switching transistor and the second switching transistor are both connected to the signal output terminal through the ESD resistor.

8. The GOA drive buffer circuit according to any one of claims 1 to 5, characterized in that, The signal output terminal is connected to the GOA scanning circuit on the OLED panel.

9. A display driver chip, characterized in that, Includes the GOA drive buffer circuit as described in any one of claims 1 to 8.

10. A display device, characterized in that, Includes the GOA drive buffer circuit as described in any one of claims 1 to 8.

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