Circuit device and backplane

Abstract

Provided are a circuit device and a backplane. The circuit device (31) is used to provide a drive signal to N elements, and comprises: an insulating substrate (100) and, arranged on the insulating substrate (100), a circuit layer and a connection pad layer. The circuit layer comprises N driving sub-circuits (11) and M cascaded first control circuits (12). The N driving sub-circuits are connected to the M cascaded first control circuits. Orthographic projections of the N driving sub-circuits on the insulating substrate are located on at least one side of orthographic projections of the M cascaded first control circuits on the insulating substrate. The connection pad layer is located on the side of the circuit layer away from the insulating substrate, and the surface of the connection pad layer away from the insulating substrate is at least partially exposed. The connection pad layer comprises P connection pads, and the P connection pads are respectively connected to the N driving sub-circuits and the M cascaded first control circuits, wherein P>N+N / M+2, M<N, and P, N and M are all positive integers greater than 1.

Description

Circuit device and backplane

[0001] This application claims the priority of an international application titled "Display panel and display device" with application number PCT / CN2025 / 073967 filed on January 22, 2025, and the priority of an international application titled "Circuit device and backplane" with application number PCT / CN2025 / 096466 filed on May 22, 2025. The content thereof should be incorporated into this application by reference. Technical field

[0002] This document relates to, but is not limited to, the field of display technology, particularly a circuit device and a backplane. Background art

[0003] Micro Light Emitting Diodes (Micro LEDs) and Mini Light Emitting Diodes (Mini LEDs) have the advantages of small size and high brightness. Display devices using the above light-emitting devices are mainly applied in fields such as Augmented Reality (AR), Virtual Reality (VR), television (TV), and outdoor displays. Summary of the invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of the claims.

[0005] This embodiment provides a circuit device and a backplane to reduce costs.

[0006] On the one hand, this embodiment provides a circuit device for providing drive signals to N components, including: an insulating substrate, a circuit layer disposed on the insulating substrate, and a connection cushion layer. The circuit layer includes: N drive sub-circuits, M cascaded first control circuits; the orthographic projection of the N drive sub-circuits on the insulating substrate is located on at least one side of the orthographic projection of the M cascaded first control circuits on the insulating substrate. The connection cushion layer is located on the side of the circuit layer away from the insulating substrate, and at least part of the surface of the connection cushion layer away from the insulating substrate is exposed. The connection cushion layer includes: P connection pads, and the P connection pads are respectively connected to the N drive sub-circuits and the M cascaded first control circuits; where P > N + N / M + 2, M < N, and P, N, and M are all positive integers greater than 1.

[0007] In some exemplary embodiments, the M cascaded first control circuits are arranged and cascaded sequentially along a first direction or a second direction, the first direction and the second direction being parallel to the plane where the insulating substrate is located, and the first direction and the second direction intersecting; the N driving sub-circuits are arranged in an A×B array, where N = A×B and A and B are both positive integers greater than 1.

[0008] In some exemplary embodiments, one of A and B is an even number, and the N driving sub-circuits are symmetrically arranged relative to the M cascaded first control circuits.

[0009] In some exemplary embodiments, the circuit layer further includes: R cascaded second control circuits, the R cascaded second control circuits being connected to the N drive sub-circuits; and P connection pads being respectively connected to the N drive sub-circuits, the M cascaded first control circuits, and the R cascaded second control circuits, wherein P>N+N / M+4, and R is a positive integer greater than 0.

[0010] In some exemplary embodiments, R = 1, and the second control circuit and the M cascaded first control circuits are arranged sequentially in the same direction.

[0011] In some exemplary embodiments, the M cascaded first control circuits include: two sets of first control circuits, with the second control circuit located between the two sets of first control circuits.

[0012] In some exemplary embodiments, the first control circuit is configured to provide a scan signal to at least one driving sub-circuit, the at least one driving sub-circuit being configured to write a data signal under the control of the scan signal, and the second control circuit is configured to provide a light emission control signal to at least one driving sub-circuit, the driving sub-circuit being configured to generate the driving signal under the control of the light emission control signal.

[0013] In some exemplary embodiments, the P connecting pads are arranged in a C×D array, where P = C×D, and the ratio of C to D is less than 2, or the ratio of D to C is less than 2; both C and D are positive integers greater than 0.

[0014] In some exemplary embodiments, the P connection pads include: V active connection pads and K auxiliary connection pads, P = V + K, where V is a positive integer greater than 1 and K is a non-negative integer; the V active connection pads are connected to the circuit layer, and at least one of the K auxiliary connection pads is configured to be connected to the active connection pads for transmitting DC signals, or has no electrical connection to the circuit layer.

[0015] On the other hand, this embodiment provides a backplane, including: a circuit board, multiple components disposed on the circuit board, and circuit devices as described above; the circuit board is provided with multiple traces, the multiple traces including: a first type of trace and a second type of trace; the circuit devices are connected to N components through N first type traces; circuit devices that have a cascade relationship are connected through the second type of trace.

[0016] In some exemplary embodiments, the relative positional relationship of the N elements is consistent with the relative positional relationship of the N driving sub-circuits in the circuit device.

[0017] In some exemplary embodiments, the relative positional relationship between the circuit device and the N components connected to it is consistent with the relative positional relationship between the M cascaded first control circuits and the N drive sub-circuits in the circuit device.

[0018] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0019] Overview of the attached figures

[0020] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0021] Figure 1 is a schematic diagram of the circuit layer arrangement of the circuit device in at least one embodiment of the present disclosure;

[0022] Figure 2 is an equivalent circuit diagram of the driving sub-circuit of at least one embodiment of the present disclosure;

[0023] Figure 3 is an equivalent circuit diagram of the first control circuit of at least one embodiment of the present disclosure;

[0024] Figure 4 is an equivalent circuit diagram of the second control circuit of at least one embodiment of the present disclosure;

[0025] Figure 5 is a plan view of the circuit layer and the connection pad layer of a circuit device according to at least one embodiment of the present disclosure;

[0026] Figure 6 is a plan view of the connection pad layer of a circuit device according to at least one embodiment of the present disclosure;

[0027] Figure 7 is another planar schematic diagram of the connection pad layer of the circuit device according to at least one embodiment of the present disclosure;

[0028] Figure 8 is a structural schematic diagram of the back plate according to at least one embodiment of the present disclosure;

[0029] Figures 9 and 10 are partial planar schematic diagrams of the circuit board of the backplane according to at least one embodiment of the present disclosure;

[0030] Figure 11 is a schematic diagram of another arrangement of circuit layers of the circuit device according to at least one embodiment of the present disclosure;

[0031] Figure 12 is a schematic diagram of another arrangement of circuit layers of the circuit device according to at least one embodiment of the present disclosure;

[0032] Figure 13 is a partial plan view of the back plate according to at least one embodiment of the present disclosure;

[0033] Figure 14 is another schematic diagram of the circuit layer arrangement of the circuit device according to at least one embodiment of the present disclosure;

[0034] Figure 15 is a partial plan view of the back plate of at least one embodiment of the present disclosure;

[0035] Figure 16 is another schematic diagram of the circuit layer arrangement of the circuit device according to at least one embodiment of the present disclosure.

[0036] Detailed Explanation

[0037] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0038] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0039] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0040] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0041] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Joining" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on "components having some electrical function," as long as they enable the transmission of electrical signals between the connected constituent elements. Examples of "components having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0042] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0043] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0044] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0045] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0046] In this specification, "approximately" and "about" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" includes values ​​differing by less than 10%, such as values ​​differing by less than 5%.

[0047] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0048] In this specification, "A and B are of the same layer structure" and "A and B are arranged in the same layer" mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "Same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B. The "shape of A" in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0049] Light-emitting diodes (LEDs) are widely used in various product fields requiring high brightness and often operating in harsh outdoor environments due to their advantages such as high brightness, high reliability, adjustable color temperature, environmental friendliness, long lifespan, and low power consumption. With technological advancements, the size of LEDs used in these fields is decreasing, reaching the micro-LED range below 50 micrometers (µm). As display technology develops, the precision requirements for the circuitry driving LEDs are also increasing, leading to higher costs for these components.

[0050] This embodiment provides a circuit device for providing drive signals to N components, including: an insulating substrate, a circuit layer disposed on the insulating substrate, and a connection cushion layer. The circuit layer includes: N drive sub-circuits and M cascaded first control circuits, and the N drive sub-circuits are connected to the M cascaded first control circuits; the orthographic projection of the N drive sub-circuits on the insulating substrate is located on at least one side of the orthographic projection of the M cascaded first control circuits on the insulating substrate. The connection cushion layer is located on a side of the circuit layer away from the insulating substrate, and at least a part of the surface of the connection cushion layer away from the insulating substrate is exposed; the connection cushion layer includes: P connection pads, and the P connection pads are respectively connected to the N drive sub-circuits and the M cascaded first control circuits; wherein, P > N + N / M + 2, M < N, and P, N, and M are all positive integers greater than 1.

[0051] In this embodiment, by integrating N drive sub-circuits and M cascaded first control circuits in the circuit device, it is beneficial to reduce the number of required connection pads, beneficial to reduce the size of the circuit device, and reduce costs.

[0052] In some examples, the insulating substrate can be made of glass. The circuit device using glass as the insulating substrate has advantages such as better stability and flatness, low dielectric constant, and good electrical property consistency, and the preparation cost is relatively low.

[0053] In some exemplary embodiments, the M cascaded first control circuits can be arranged and cascaded in sequence along a first direction or a second direction. The first direction and the second direction are parallel to the plane where the insulating substrate is located, and the first direction and the second direction intersect. The N drive sub-circuits are arranged in an A×B array, where N = A×B and A and B are both positive integers greater than 1. In some examples, one of A and B is an even number, and the N drive sub-circuits are symmetrically arranged with respect to the M cascaded first control circuits. The arrangement manner of the first control circuits and the drive sub-circuits in this example can improve the utilization rate of the insulating substrate and is beneficial to reducing the size of the circuit device.

[0054] In some exemplary embodiments, the circuit layer can further include: R cascaded second control circuits, and the R cascaded second control circuits are connected to the N drive sub-circuits; the P connection pads are respectively connected to the N drive sub-circuits, the M cascaded first control circuits, and the R cascaded second control circuits, where R is a positive integer greater than 0, and P > N + N / M + 4. For example, R < M. In this example, by integrating N drive sub-circuits, M cascaded first control circuits, and R cascaded second control circuits in the circuit device, it is beneficial to ensure the stable output of the drive signal, reduce the number of required connection pads, and reduce costs.

[0055] In some exemplary embodiments, R=1, and the second control circuit and M cascaded first control circuits can be arranged sequentially in the same direction. The arrangement of the second and first control circuits in this example can improve the utilization rate of the insulating substrate, which is beneficial for reducing the size of circuit components; moreover, it facilitates the design of the connection lines between the second control circuit and the N drive sub-circuits.

[0056] In some exemplary embodiments, P connector pads are arranged in a C×D array, where P = C×D, and the ratio of C to D is less than 2, or the ratio of D to C is less than 2; both C and D are positive integers greater than 0. In some examples, when the connector pad layer satisfies the following conditions: the orthographic projection of a single connector pad onto the insulating substrate can be approximately square, and the spacing between adjacent connector pads can be approximately the same; then the ratio of C to D being less than 2, or the ratio of D to C being less than 2, can ensure the effective contact area for bonding the circuit devices to the backplane, which is beneficial for improving the bonding effect of the circuit devices on the backplane.

[0057] In some exemplary embodiments, the P connection pads may include: V active connection pads and K auxiliary connection pads, where P = V + K, V is a positive integer greater than 1, and K is a non-negative integer. The V active connection pads are connected to the circuit layer, and at least one of the K auxiliary connection pads is configured to be connected to an active connection pad transmitting a DC signal, or has no electrical connection to the circuit layer. This example ensures that the P connection pads are arranged in an array by using auxiliary connection pads. In some embodiments, connecting the auxiliary connection pads to the active connection pads transmitting the DC signal can help reduce the IR drop of the DC signal. In some embodiments, the auxiliary connection pads may not be used to transmit any signal, i.e., they may not be connected to any electrical pattern.

[0058] The following examples illustrate the solution of this embodiment.

[0059] Figure 1 is a schematic diagram of the circuit layer arrangement of a circuit device according to at least one embodiment of the present disclosure. In this example, N can be 12, M can be 6, and R can be 1. This example illustrates the circuit device providing drive signals to 12 components. As shown in Figure 1, the circuit device may include: an insulating substrate 100, a circuit layer disposed on the insulating substrate 100, and a connection pad layer. The circuit layer may include: twelve drive sub-circuits 11, six cascaded first control circuits 12, and a second control circuit 13. The twelve drive sub-circuits 11 are electrically connected to the six cascaded first control circuits 12, and the second control circuit 13 is electrically connected to the twelve drive sub-circuits 11. The orthographic projection of the twelve drive sub-circuits 11 on the insulating substrate 100 may be located on at least one side of the orthographic projection of the six cascaded first control circuits 12 on the insulating substrate 100, and on at least one side of the orthographic projection of the second control circuit 13 on the insulating substrate 100. For example, the twelve drive sub-circuits 11 can be divided into two groups, and the two groups of drive sub-circuits can be located on both sides of the six first control circuits 12 along one direction (e.g., the second direction D2). The second control circuit 13 and the six cascaded first control circuits 12 can be arranged sequentially along the same direction (e.g., the first direction D1).

[0060] In some examples, the element can be a light-emitting element. For example, a circuit device can be configured to drive four pixel units to emit light, each pixel unit may include three light-emitting elements, such as a light-emitting element emitting a first color light (e.g., red light), a light-emitting element emitting a second color light (e.g., green light), and a light-emitting element emitting a third color light (e.g., blue light). Each driving sub-circuit 11 can be configured to provide a driving signal to one light-emitting element to drive the light-emitting element to emit light. In other examples, the element can be a sensing element, and the circuit device in this example can be configured to drive the sensing element to perform a sensing function. In still other examples, the element can be other functional elements, and the circuit device in this example can be configured to drive the corresponding element to perform a specific function.

[0061] In some examples, as shown in Figure 1, the twelve driving sub-circuits 11 can be arranged in an array along the first direction D1 and the second direction D2, for example, in a 4×3 array, or in other words, in a four-row, three-column array. In this example, A can be 4, and B can be 3. A row of driving sub-circuits can include three driving sub-circuits 11 arranged along the first direction D1; four rows of driving sub-circuits can be arranged along the second direction D2; a column of driving sub-circuits can include four driving sub-circuits 11 arranged along the second direction D2; and multiple columns of driving sub-circuits can be arranged along the first direction D1. The six cascaded first control circuits 12 can be located in the middle of the twelve driving sub-circuits 11. For example, the twelve driving sub-circuits 11 can be symmetrically arranged with respect to the six cascaded first control circuits 12. For example, the six cascaded first control circuits 12 can be arranged in a row along the first direction D1 and located in the middle of the four rows of drive sub-circuits; the six cascaded first control circuits 12 can be arranged in two rows of drive sub-circuits along one side of the second direction D1 and two rows of drive sub-circuits along the other side of the second direction D2.

[0062] In some examples, each driver sub-circuit 11 may extend along a first direction D1. Extending the driver sub-circuit 11 along the first direction D1 means that the maximum length of the driver sub-circuit 11 projected onto the insulating substrate 100 along the first direction D1 is greater than the maximum length along the second direction D2.

[0063] In some examples, the driver sub-circuit 11 may include multiple transistors and at least one capacitor. For example, the driver sub-circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, T in the above driver sub-circuit refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In other examples, the driver sub-circuit may include at least one of the following: a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit.

[0064] In some examples, as shown in Figure 1, six cascaded first control circuits 12 can be arranged sequentially along a first direction D1. The second control circuit 13 can be arranged sequentially with the six cascaded first control circuits 12 along the same direction, for example, along the first direction D1. For example, the second control circuit 13 can be located on the same side of the six cascaded first control circuits 12 along the first direction D1. The six first control circuits 12 and one second control circuit 13 can be aligned along the first direction D1.

[0065] In some examples, a single first control circuit 12 may extend along the second direction D2, that is, the maximum length of the orthographic projection of the single first control circuit 12 onto the insulating substrate 100 along the second direction D2 may be greater than the maximum length along the first direction D1. A second control circuit 13 may extend along the second direction D2, that is, the maximum length of the orthographic projection of the second control circuit 13 onto the insulating substrate 100 along the second direction D2 may be greater than the maximum length along the first direction D1.

[0066] In some examples, a single first control circuit 12 may be configured to provide a scan signal to at least one (e.g., two) driver sub-circuits 11, and the at least one driver sub-circuit 11 may be configured to write a data signal under the control of the scan signal. A second control circuit 13 may be configured to provide light emission control signals to a plurality of (e.g., twelve) driver sub-circuits 11, and the driver sub-circuits 11 may be configured to generate a drive signal under the control of the light emission control signals.

[0067] The circuit device in this example integrates the driver sub-circuit 11, the first control circuit 12, and the second control electrode 13, which can help reduce costs; moreover, the arrangement of the driver sub-circuit 11, the first control circuit 12, and the second control circuit 13 can help reduce the size of the circuit device and improve the utilization rate of the insulating substrate.

[0068] The following examples illustrate the structure of the circuit layer using the driver sub-circuit, the first control circuit, and the second control circuit.

[0069] Figure 2 is an equivalent circuit diagram of the driving sub-circuit of at least one embodiment of the present disclosure. As shown in Figure 2, the driving sub-circuit of this example can be a 7T1C structure. The driving sub-circuit may include first pixel transistors PT1 to seventh pixel transistors PT7, and a storage capacitor Cst. The third pixel transistor PT3 can be a driving transistor. The gate of the third pixel transistor PT3 can be electrically connected to the first pixel node P1, the first terminal of the third pixel transistor PT3 can be electrically connected to the second pixel node P2, and the second terminal of the third pixel transistor PT3 can be electrically connected to the third pixel node P3. The gate of the second pixel transistor PT2 can be electrically connected to the scan terminal GL, the first terminal of the second pixel transistor PT2 can be electrically connected to the third pixel node P3, and the second terminal of the second pixel transistor PT2 can be electrically connected to the first pixel node P1. The gate of the first pixel transistor PT1 can be electrically connected to the reset control terminal RST, the first terminal of the first pixel transistor PT1 can be electrically connected to the initial signal terminal INIT, and the second terminal of the first pixel transistor PT1 can be electrically connected to the first pixel node P1. The gate of the fourth pixel transistor PT4 can be electrically connected to the scan terminal GL, the first electrode of the fourth pixel transistor PT4 can be electrically connected to the data terminal DL, and the second electrode of the fourth pixel transistor PT4 can be electrically connected to the second pixel node P2. The gate of the fifth pixel transistor PT5 can be electrically connected to the light emission control terminal EM, the first electrode of the fifth pixel transistor PT5 can be electrically connected to the first power supply terminal VDD, and the second electrode of the fifth pixel transistor PT5 can be electrically connected to the second pixel node P2. The gate of the sixth pixel transistor PT6 can be electrically connected to the light emission control terminal EM, the first electrode of the sixth pixel transistor PT6 can be electrically connected to the third pixel node P3, and the second electrode of the sixth pixel transistor PT6 can be electrically connected to the fourth pixel node P4. The gate of the seventh pixel transistor PT7 can be electrically connected to the reset control terminal RST, the first electrode of the seventh pixel transistor PT7 can be electrically connected to the initial signal terminal INIT, and the second electrode of the seventh pixel transistor PT7 can be electrically connected to the fourth pixel node P4. The first electrode of the storage capacitor Cst is electrically connected to the first power supply terminal VDD, and the second electrode of the storage capacitor Cst is electrically connected to the first pixel node P1. The first electrode of the light-emitting element EL driven by the driving sub-circuit 11 can be connected to the fourth pixel node P4, and the second electrode of the light-emitting element EL can be connected to the second power supply terminal VSS.

[0070] In some examples, as shown in Figure 1, the scan terminal GL and reset control terminal RST of two driver sub-circuits 11 located on the same side of the six cascaded first control circuits 12 in each column of driver sub-circuits can be connected to different first control circuits 12. The light emission control terminal EM of all driver sub-circuits 11 within the circuit device can be connected to the second control circuit 13. The two rows of driver sub-circuits located away from the six cascaded first control circuits 12 within the circuit device can both be connected to the first data terminal D1, and the two rows of driver sub-circuits located close to the six cascaded first control circuits 12 can both be connected to the second data terminal D2. The twelve driver sub-circuits 11 within the circuit device can be connected to the same initial signal terminal INIT and the first power supply terminal VDD.

[0071] In some examples, as shown in Figure 1, the fourth pixel node of each driving sub-circuit 11 can be connected to an anode connection terminal. For example, the fourth pixel nodes of the three driving sub-circuits in the first row can be connected to anode connection terminals AN1, AN2, and AN3, respectively; the fourth pixel nodes of the three driving sub-circuits in the second row can be connected to anode connection terminals AN4, AN5, and AN6, respectively; the fourth pixel nodes of the three driving sub-circuits in the third row can be connected to anode connection terminals AN7, AN8, and AN9, respectively; and the fourth pixel nodes of the three driving sub-circuits in the fourth row can be connected to anode connection terminals AN10, AN11, and AN12, respectively.

[0072] Figure 3 is an equivalent circuit diagram of the first control circuit according to at least one embodiment of the present disclosure. As shown in Figure 3, the first control circuit can be an 8T2C structure, which may include a first control transistor GT1 to an eighth control transistor GT8, a first control capacitor GC1, and a second control capacitor GT2.

[0073] In some examples, as shown in Figure 3, the gate of the first control transistor GT1 is electrically connected to the first clock signal terminal GCK, the first terminal of the first control transistor GT1 is connected to the first cascade input terminal G(a-1), and the second terminal of the first control transistor GT1 is electrically connected to the first control node GN1. The gate of the second control transistor GT2 is electrically connected to the first control node N1, the first terminal of the second control transistor GT2 is electrically connected to the first clock signal terminal GCK, and the second terminal of the second control transistor GT2 is electrically connected to the second control node GN2. The gate of the third control transistor GT3 is electrically connected to the first clock signal terminal GCK, the first terminal of the third control transistor GT3 is electrically connected to the fourth power supply terminal VGL, and the second terminal of the third control transistor GT3 is electrically connected to the second control node GN2. The gate of the fourth control transistor GT4 is electrically connected to the second control node GN2, the first terminal of the fourth control transistor GT4 is electrically connected to the third power supply terminal VGH, and the second terminal of the fourth control transistor GT4 is electrically connected to the first cascade output terminal G(i). The gate of the fifth control transistor GT5 is electrically connected to the third control node GN3. The first electrode of the fifth control transistor GT5 is electrically connected to the second clock signal terminal GCB, and the second electrode of the fifth control transistor GT5 is electrically connected to the first cascaded output terminal G(i). The gate of the sixth control transistor GT6 is electrically connected to the second control node GN2. The first electrode of the sixth control transistor GT6 is electrically connected to the third power supply terminal VGH, and the second electrode of the sixth control transistor GT6 is electrically connected to the first electrode of the seventh control transistor GT7. The gate of the seventh control transistor GT7 is electrically connected to the second clock signal terminal GCB, and the second electrode of the seventh control transistor GT7 is electrically connected to the first control node GN1. The gate of the eighth control transistor GT8 is electrically connected to the fourth power supply terminal VGL. The first electrode of the eighth control transistor GT8 is electrically connected to the first control node GN1, and the second electrode of the eighth control transistor GT8 is electrically connected to the third control node GN3. The first electrode of the first control capacitor GC1 is electrically connected to the second control node GN2, and the second electrode of the first control capacitor GC1 is electrically connected to the third power supply terminal VGH. The first electrode of the second control capacitor GC2 is electrically connected to the third control node GN3, and the second electrode of the second control capacitor GC2 is electrically connected to the first cascaded output terminal G(a). Here, i can be a positive integer.

[0074] In some examples, as shown in Figure 1, six cascaded first control circuits 12 can be arranged sequentially from left to right along the first direction D1. For example, the first-stage first control circuit within a single circuit device can be located to the left of the second-stage first control circuit, the first-stage first control circuit can be located on the far left, and the sixth-stage first control circuit can be adjacent to the second control circuit 13. The first cascaded input terminal of the first-stage first control circuit can be connected to the first input terminal GIN, and the first cascaded output terminal of the first-stage first control circuit can be connected to the first cascaded input terminal of the second-stage second control circuit; in the second to sixth stages of the first control circuit, the first cascaded input terminal of each stage of the first control circuit can be connected to the first cascaded output terminal of the previous stage of the first control circuit; the first cascaded output terminal of the sixth-stage first control circuit can be connected to the first output terminal GOUT.

[0075] In some examples, two drive sub-circuits 11 located on the same side and in the same column of the six cascaded first control circuits 12 within the circuit device 31 can be connected to the same scan terminal GL and the same reset control terminal RST. The scan terminal GL and reset control terminal RST connected to the two drive sub-circuits 11 can be connected to different levels of the first control circuits 12. For example, the scan terminal GL connected to the two drive sub-circuits 11 is connected to the first cascaded output terminal of the first-level first control circuit 12, and the reset control terminal RST connected to the two drive sub-circuits 11 is connected to the first cascaded output terminal of the first-level first control circuit 12 preceding the first-level first control circuit 12. For example, the scanning terminals GL of the two drive sub-circuits 11 located on one side of the first control circuit 12 along the second direction D2 and in the first column of the six-stage cascaded first control circuit 12 can be connected to the first cascaded output terminal of the first stage first control circuit 12, and the reset control terminals RST of the two drive sub-circuits 11 can be connected to the first input terminal GIN; the scanning terminals GL of the two drive sub-circuits 11 located on the other side of the first control circuit 12 along the second direction D2 and in the first column of the six-stage cascaded first control circuit 12 can be connected to the first cascaded output terminal of the fourth stage first control circuit 12, and the reset control terminals RST of the two drive sub-circuits 11 can be connected to the first cascaded output terminal of the third stage first control circuit 12.

[0076] Figure 4 is an equivalent circuit diagram of the second control circuit according to at least one embodiment of the present disclosure. As shown in Figure 4, the second control circuit can be an 8T3C structure, such as including the first light-emitting control transistor ET1 to the seventh light-emitting control transistor ET7, and the first light-emitting control capacitor EC1 to the third light-emitting control capacitor EC3.

[0077] In some examples, as shown in Figure 4, the gate of the first LED control transistor ET1 is electrically connected to the third clock signal terminal ECK, the first terminal of the first LED control transistor ET1 is electrically connected to the second cascade input terminal E(j-1), and the second terminal of the first LED control transistor ET1 is electrically connected to the first LED control node EN1. The gate of the second LED control transistor ET2 is electrically connected to the fourth power supply terminal VGL, the first terminal of the second LED control transistor ET2 is electrically connected to the first LED control node EN1, and the second terminal of the second LED control transistor ET2 is electrically connected to the second LED control node EN2. The gate of the third LED control transistor ET3 is electrically connected to the second LED control node EN2, the first terminal of the third LED control transistor ET3 is electrically connected to the fourth power supply terminal VGL, and the second terminal of the third LED control transistor ET3 is electrically connected to the second cascade output terminal E(j). The gate of the fourth LED control transistor ET4 is electrically connected to the third LED control node EN3, the first terminal of the fourth LED control transistor ET4 is electrically connected to the third power supply terminal VGH, and the second terminal of the fourth LED control transistor ET4 is electrically connected to the second cascade output terminal E(j). The gates of the first fifth light-emitting control transistor ET5a and the second fifth light-emitting control transistor ET5b are both electrically connected to the fourth light-emitting control node EN4. The first electrode of the second fifth light-emitting control transistor ET5b is electrically connected to the third light-emitting control node EN3, and the second electrode of the second fifth light-emitting control transistor ET5b is electrically connected to the first electrode of the first fifth light-emitting control transistor ET5a. The second electrode of the first fifth light-emitting control transistor ET5a is electrically connected to the first electrode of the first light-emitting control capacitor EC1. The second electrode of the first light-emitting control capacitor EC1 is electrically connected to the fourth light-emitting control node EN4. The gate of the sixth light-emitting control transistor ET6 is electrically connected to the first light-emitting control node EN1. The first electrode of the sixth light-emitting control transistor ET6 is electrically connected to the third power supply terminal VGH, and the second electrode of the sixth light-emitting control transistor ET6 is electrically connected to the third light-emitting control node EN3. The gate of the seventh light-emitting control transistor ET7 is electrically connected to the second cascaded input terminal E(j-1). The first electrode of the seventh light-emitting control transistor ET7 is electrically connected to the third power supply terminal VGH, and the second electrode of the seventh light-emitting control transistor ET7 is electrically connected to the fourth light-emitting control node EN4. The first electrode of the second light-emitting control capacitor EC2 is electrically connected to the third power supply terminal VGH, and the second electrode of the second light-emitting control capacitor EC2 is electrically connected to the third light-emitting control node EN3. The first electrode of the third light-emitting control capacitor EC3 is electrically connected to the second light-emitting control node EN2, and the second electrode of the third light-emitting control capacitor EC3 is electrically connected to the second cascaded output terminal E(j). Here, j is a positive integer.

[0078] In some examples, as shown in Figure 1, the second cascaded input of the second control circuit 13 can be connected to the second input EIN, and the second cascaded output of the second control circuit 13 can be connected to the second output EOUT. The second output EOUT of the second control circuit 13 can be connected to the light-emitting control terminal EM of the twelve driver sub-circuits 11. The circuit device in this example, by integrating a single second control circuit 13 to control the simultaneous illumination of the twelve driver sub-circuits 11, minimizes the area of ​​the circuit device.

[0079] In this example, the first data signal terminal DL1 and the second data signal terminal DL2 can work with the first control circuit 12 to provide data signals to twelve driving sub-circuits 11. Each data signal terminal can provide data signals to six driving sub-circuits 11 in a time-division manner. The twelve driving sub-circuits 11 can write data signals sequentially and in a time-division manner under the control of six first control circuits 12. One first control circuit 12 can control two driving sub-circuits 11 to write data signals simultaneously. The product between the number of data signal terminals and the number of first control circuits 12 can be the same as the number of data signals required by the driving sub-circuits 11. The ratio between the number of driving sub-circuits 11 (e.g., N) and the number of first control circuits 12 (e.g., M) can be the required number of data signals (i.e., the value of N / M).

[0080] Figure 5 is a plan view of the circuit layer and the connection pad layer of a circuit device according to at least one embodiment of the present disclosure. Figure 6 is a plan view of the connection pad layer of a circuit device according to at least one embodiment of the present disclosure.

[0081] In some examples, as shown in Figures 5 and 6, the connection pad layer may be located on the side of the circuit layer away from the insulating substrate 100, and the surface of the connection pad layer away from the insulating substrate 100 may be at least partially exposed. The connection pad layer 21 may include P connection pads arranged in an array along a first direction D1 and a second direction D2. For example, the P connection pads may be arranged in a C×D array. P = C×D, where C and D are both positive integers greater than 1, and the ratio of C to D is less than 2, or the ratio of D to C is less than 2. In this example, the values ​​of C and D may both be 5, and the value of P may be 25.

[0082] In some examples, the P connection pads may include: twelve anode signal connection pads 23-1 to 23-12, two data signal connection pads 23-13 and 23-14, a first power signal connection pad 23-15, an initial signal connection pad 23-16, a third power signal connection pad 241, a fourth power signal connection pad 242, a first input signal connection pad 243, a first output signal connection pad 244, a first clock signal connection pad 245, a second clock signal connection pad 246, a third clock signal connection pad 249, a second input signal connection pad 247, and a second output signal connection pad 248. In this example, all P connection pads are active, i.e., P = V.

[0083] In some examples, the P connection pads may include a first type of connection pads connected to twelve driver sub-circuits 11, and a second type of connection pads connected to six first control circuits 12 and one second control circuit 13. The first type of connection pads may include: twelve anode signal connection pads 23-1 to 23-12, two data signal connection pads 23-13 and 23-14, a first power signal connection pad 23-15, and an initial signal connection pad 23-16; the second type of connection pads may include: a third power signal connection pad 241, a fourth power signal connection pad 242, a first input signal connection pad 243, a first output signal connection pad 244, a first clock signal connection pad 245, a second clock signal connection pad 246, a third clock signal connection pad 249, a second input signal connection pad 247, and a second output signal connection pad 248.

[0084] In some examples, the twelve anode signal connection pads 23-1 to 23-12 can be connected one-to-one with the twelve anode connection terminals of the twelve drive sub-circuits 11, configured to output the drive signal generated by the drive sub-circuit 11. The first power signal connection pad 23-15 can be connected to the first power terminal VDD, configured to provide a first power signal. The initial signal connection pad 23-16 can be connected to the initial signal terminal INIT, configured to provide an initial signal. The first power signal and the initial signal can be constant voltage DC signals, and the voltage value of the first power signal can be greater than the voltage value of the initial signal.

[0085] In some examples, the third power signal connection pad 241 can be connected to the third power signal terminal VGH and configured to provide a third power signal. The fourth power signal connection pad 242 can be connected to the fourth power signal terminal VGL and configured to provide a fourth power signal. Both the third and fourth power signals can be constant voltage DC signals, and the voltage value of the third power signal can be greater than the voltage value of the fourth power signal. In this example, the third power signal connection pad 241 can be configured to simultaneously provide a third power signal to both the first control circuit 12 and the second control circuit 13; the fourth power signal connection pad 242 can be configured to simultaneously provide a fourth power signal to both the first control circuit 12 and the second control circuit 13. In other examples, the third power signal of the first control circuit and the third power signal of the second control circuit can be provided by different connection pads, and the fourth power signal of the first control circuit and the fourth power signal of the second control circuit can be provided by different connection pads. This embodiment is not limited in this respect.

[0086] In some examples, the first input signal connection pad 243 can be connected to the reset control terminal of the drive sub-circuit 11 to which the first-stage first control circuit 12 is connected, and can also be connected to the first input signal terminal GIN. The first clock signal connection pad 245 can be connected to the first clock signal terminal GCK and configured to provide a first clock signal; the second clock signal connection pad 246 can be connected to the second clock signal terminal GCB and configured to provide a second clock signal. The first output signal connection pad 244 can be connected to the first output signal terminal GOUT and configured to provide the output signal of the sixth-stage first control circuit 12 of this circuit device to the first input signal terminal GIN of the next cascaded circuit device.

[0087] In some examples, the third clock signal connection pad 249 can be connected to the third clock signal terminal ECK and configured to provide a third clock signal. The second input signal connection pad 247 can be connected to the second input signal terminal EIN and configured to provide an input signal to the second control circuit 13. The second output signal connection pad 248 can be connected to the second output signal terminal EOUT and configured to provide the output signal of the second control circuit 13 to the second input signal terminal EIN of the next cascaded circuit device.

[0088] The way the connection pads are set up in this example maximizes area utilization and ensures the optimal routing path between the connection pads and the corresponding connected circuits.

[0089] The fabrication process of the circuit device is illustrated below. The "patterning process" described in this example includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This embodiment does not limit the methods used.

[0090] In some examples, the fabrication process of the circuit devices may include: providing an insulating substrate, such as glass; fabricating a master wafer including a circuit layer and a connection pad layer; and cutting the master wafer to obtain multiple circuit devices. The process of fabricating the master wafer may include: depositing a first conductive film on the insulating substrate, and patterning the first conductive film using a patterning process to form a first conductive layer, for example, the first conductive layer may include the bottom gate of multiple transistors; subsequently, depositing a first insulating film and a semiconductor film, and patterning the semiconductor film using a patterning process to form a semiconductor layer, for example, the semiconductor layer may include the active layer of multiple transistors; subsequently, depositing a second insulating film and a second conductive film, and patterning the second insulating film and the second conductive film sequentially using a patterning process to form a second conductive layer, for example, the second conductive layer may include the top gate of multiple transistors; subsequently, depositing a third insulating film, and patterning the first conductive film using a patterning process to form a second conductive layer, for example, the second conductive layer may include the top gate of multiple transistors; and finally, depositing a third insulating film, and patterning the first conductive film on the insulating substrate ... The patterning process involves patterning a third insulating film, a second insulating film, and a first insulating film to form a third insulating layer, a second insulating layer, and a first insulating layer. Subsequently, a third conductive film is deposited and patterned using a patterning process to form a third conductive layer. For example, the third conductive layer may include the source and drain electrodes of multiple transistors. Subsequently, a fourth insulating film is coated and patterned using a patterning process to form a fourth insulating layer. Subsequently, a fifth insulating film is deposited and patterned using a patterning process to form a fifth insulating layer. Subsequently, a fourth conductive film is deposited and patterned using a patterning process to form a connection pad layer.

[0091] In some examples, the first conductive film, the second conductive film, the third conductive film, and the fourth conductive film can be made of metallic materials, such as any one or more of silver (Ag), molybdenum (Mo), aluminum (Al), and titanium (Ti), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc.

[0092] In some examples, the semiconductor thin film can be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene. For example, the semiconductor layer can be made of amorphous silicon or metal oxide.

[0093] In some examples, the first, second, third, and fifth insulating films can be any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The fourth insulating film can be an organic insulating material.

[0094] In some examples, after forming the bonding pad layer, the master wafer can be cut. For example, the master wafer can be cut along a slit to obtain multiple 10cm × 10cm square wafers; then, the square wafers can be cut along the slit to obtain 4-inch circular wafers, each of which can include multiple circuit devices. For example, bonding leads can be fabricated on the exposed bonding pads on the surface of each circular wafer, and the bonding leads can be electrically connected to the aforementioned bonding pads. For example, multiple bonding pads correspond one-to-one with multiple bonding leads. The bonding leads can be made of metallic materials, such as any one or more of silver (Ag), gold (Au), copper (Cu), and tin (Sn), or alloys of the above metals, such as silver tin oxide (SnAg) or tin-lead alloy (SnPb), and can be a single-layer structure or a multi-layer structure. The orthographic projection of the bonding lead onto the glass substrate and the orthographic projection of the connected bonding pad onto the glass substrate can at least partially overlap. For example, the orthographic projection of the bonding lead onto the glass substrate can be located within the orthographic projection range of the connected bonding pad onto the glass substrate. For example, the orthographic projection of the bonding pins onto the glass substrate can coincide with the orthographic projection of the connected pads onto the glass substrate. The circuit devices can then be connected to the first pad group on the circuit board via multiple bonding pins. Subsequently, the glass substrate of each wafer is thinned, for example, from 0.5 mm to 0.1 mm. Then, the wafers are cut into multiple discrete circuit devices using a laser dicing process.

[0095] In some examples, because the circuit components are arranged on the backplane with a rotation angle of ≤5°, the dimensions of the circuit components need to meet a certain aspect ratio in order to ensure the contact area between the circuit components and the first pad on the backplane, as shown in the following formula:

[0096] Sin5°×(((w×m+(m-1)×c)×1 / 2)2+((h×n+(n-1)×c)×1 / 2)2)1 / 2<h;

[0097] Where w and h are the dimensions of the bonding pins in the plane parallel to the insulating substrate, w is the width of the bonding pin, and h is the length of the bonding pin. For example, the orthographic projection of the bonding pin onto the insulating substrate can be a square, i.e., w = h, to match the fabrication device capability. c is the spacing between two bonding pins. m is the number of bonding pins in the lateral direction (e.g., along the first direction D1), and n is the number of bonding pins in the longitudinal direction (e.g., along the second direction D2), where m and n are both positive integers greater than 0. Taking w = h = 40 micrometers and c = 50 micrometers as an example, we can obtain that m:n is less than 2:1, meaning the aspect ratio of the circuit device can be less than 2:1. Since multiple bonding pins and multiple connecting pads are connected one-to-one, when P connecting pads are arranged in a C×D array along the first direction D1 and the second direction D2, the ratio of C to D or D to C can be less than 2, and both C and D are positive integers greater than 0.

[0098] Figure 7 is another planar schematic diagram of the connection pad layer of a circuit device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 7, the P connection pads of the connection pad layer of the circuit device may include V active connection pads and K auxiliary connection pads 251. P = V + K, where V is a positive integer greater than 1 and K is a non-negative integer. The auxiliary connection pads 251 may be configured such that the P connection pads can meet the number requirements of the array arrangement. In some examples, at least one auxiliary connection pad 251 may not be connected to the circuit layer, and the auxiliary connection pad 251 is only used to meet the number requirements of the array arrangement. In some examples, the auxiliary connection pads 251 may be connected to at least one first-type connection pad or a second-type connection pad that transmits a constant voltage DC signal. For example, the first power signal connection pads 23-15 that transmit a first power signal may be electrically connected to at least one auxiliary connection pad 251; in other words, the first power signal may correspond to at least two connection pads, thereby reducing the voltage drop (IR Drop) of the first power signal. The auxiliary connection pads in this example can not only meet the number requirements of the array arrangement, but also reduce the transmission voltage drop of the DC signal.

[0099] Figure 8 is a structural schematic diagram of a backplane according to at least one embodiment of the present disclosure. Figures 9 and 10 are partial planar schematic diagrams of a circuit board according to at least one embodiment of the present disclosure. In some examples, as shown in Figures 8 to 10, the backplane may include: a circuit board 30, and a plurality of circuit devices 31 and a plurality of light-emitting devices 32 disposed on the circuit board 30. The circuit board 30 may include: a plurality of first pad groups 301 and a plurality of second pad groups 302. The circuit devices 31 may be connected to the first pad groups 301, and the light-emitting devices 32 may be connected to the second pad groups 302. The first pad groups 301 may include a plurality of first pads 3011 that correspond one-to-one with and are fixedly connected to a plurality of bonding pins of the circuit devices 31. The second pad groups 302 may include second pads that are respectively connected to the first electrode and the second electrode of the light-emitting device 32.

[0100] In some examples, as shown in Figure 8, circuit device 31 can be configured to drive light-emitting device 32 to emit light. The number of light-emitting devices 32 can be greater than the number of circuit devices 31. For example, the number of light-emitting devices 32 can be greater than or equal to twice the number of circuit devices 31. For example, one circuit device 31 can be configured to drive at least two light-emitting devices 32 to emit light. For example, one circuit device 31 can be configured to drive four light-emitting devices 32 to emit light. This example uses a smaller circuit device to drive the light-emitting devices, which can help improve the utilization rate of the circuit board, thereby reducing the manufacturing cost of the backplane. In some examples, a light-emitting device 32 can include three light-emitting elements that emit different colors of light, such as a first light-emitting element 321 emitting a first color of light, a second light-emitting element 322 emitting a second color of light, and a third light-emitting element 323 emitting a third color of light. The first color of light can be red light, the second color of light can be green light, and the third color of light can be blue light. For example, the light-emitting device 32 may include a blue LED, and red and green quantum dot materials located above a portion of the blue LED. The blue light emitted by the blue LED passes through the quantum dot film, and part of the blue light can be converted into red and green light. The unconverted blue light can be mixed with the red and green light emitted by the quantum dot film to form high-quality white light, thereby improving the color gamut and color performance of the back panel.

[0101] In some examples, as shown in Figure 8, the circuit board 30 may include multiple traces 303, multiple bridging electrodes 304, and multiple bonding electrodes 305. The multiple bridging electrodes 304 may be located on one side of the multiple light-emitting devices 32 along the fourth direction D4, and the multiple bonding electrodes 305 may be located on the other side of the multiple light-emitting devices 32 along the fourth direction D4. The multiple bridging electrodes 304 may connect multiple adjacent traces 303 along the fifth direction D5. The multiple bonding electrodes 305 may be configured to connect to an external circuit board. The fifth direction D5 intersects the fourth direction D4 and is parallel to the plane of the circuit board 30; for example, the fifth direction D5 may be perpendicular to the fourth direction D4. The third direction D3 may be perpendicular to the plane containing the fourth direction D4 and the fifth direction D5. For example, the first direction D1 may be parallel to the fifth direction D5, and the second direction D2 may be parallel to the fourth direction D4.

[0102] In some examples, as shown in Figure 8, taking one circuit device 31 driving four light-emitting devices 32 as an example, to maximize area utilization, the circuit device 31 can be placed in the middle of the four light-emitting devices 32. This example allows the first electrode of the light-emitting element to be connected to its corresponding first pad along the shortest path, thereby reducing anode resistance and anode crosstalk.

[0103] In some examples, as shown in Figure 10, the first pad group 301 may include 25 first pads 3011 arranged in a 5×5 array. These first pads 3011 can be connected one-to-one with multiple connection pads of the circuit device 31 and transmit corresponding signals. The twelve light-emitting elements connected to the circuit device 31 can be distributed around the circuit device 31. For example, the twelve light-emitting elements can be arranged in a six-row, two-column array, with one row including two light-emitting elements arranged along the fifth direction D5 and one column including six light-emitting elements arranged along the fourth direction D4.

[0104] In some examples, as shown in Figures 6, 8, and 10, the drive signal transmitted by anode signal pad 23-1 can be configured to drive the third light-emitting element 323 of the light-emitting device 32 at the upper left corner of the first pad group 301; anode signal pad 23-2 can be configured to drive the first light-emitting element 321 of the light-emitting device 32 at the upper left corner of the first pad group 301; and anode signal pad 23-5 can be configured to drive the second light-emitting element 322 of the light-emitting device 32 at the upper left corner of the first pad group 301. The drive signal transmitted by anode signal pad 23-3 can be configured to drive the first light-emitting element of the light-emitting device 32 at the upper right corner of the first pad group 301; the drive signal transmitted by anode signal pad 23-4 can be configured to drive the third light-emitting element of the light-emitting device 32 at the upper right corner of the first pad group 301; and the drive signal transmitted by anode signal pad 23-6 can be configured to drive the second light-emitting element of the light-emitting device 32 at the upper right corner of the first pad group 301. The driving signal transmitted by anode signal connection pad 23-9 can be configured to drive the third light-emitting element of the light-emitting device 32 at the lower left corner of the first pad group 301; the driving signal transmitted by anode signal connection pad 23-10 can be configured to drive the first light-emitting element of the light-emitting device 32 at the lower left corner of the first pad group 301; the driving signal transmitted by anode signal connection pad 23-7 can be configured to drive the second light-emitting element of the light-emitting device 32 at the lower left corner of the first pad group 301. The driving signal transmitted by anode signal connection pad 23-11 can be configured to drive the first light-emitting element of the light-emitting device 32 at the lower right corner of the first pad group 301; the driving signal transmitted by anode signal connection pad 23-12 can be configured to drive the third light-emitting element of the light-emitting device 32 at the lower right corner of the first pad group 301; the driving signal transmitted by anode signal connection pad 23-8 can be configured to drive the second light-emitting element of the light-emitting device 32 at the lower right corner of the first pad group 301.

[0105] In some examples, the relative positions of the twelve light-emitting elements connected to the circuit device can be consistent with the relative positions of the twelve driving sub-circuits within the circuit device. For example, the three light-emitting elements of a single light-emitting device can be arranged adjacently, and the three driving sub-circuits within the circuit device that provide driving signals to one light-emitting device can be arranged adjacently; the second light-emitting element of a single light-emitting device can be adjacent to both the first and third light-emitting elements, and the driving sub-circuit within the circuit device that provides driving signals to the second light-emitting element can be adjacent to both the driving sub-circuit that provides driving signals to the first light-emitting element and the driving sub-circuit that provides driving signals to the third light-emitting element.

[0106] In some examples, the relative positional relationship between the circuit device and the twelve light-emitting elements connected to it is consistent with the relative positional relationship between the six cascaded first control circuits and the twelve driving sub-circuits in the circuit device. For example, as shown in Figures 8 to 10, the twelve light-emitting elements connected to the circuit device 31 are located on both sides of the circuit device 31 along one direction; the twelve driving sub-circuits in the circuit device 31 are located on both sides of the six cascaded first control circuits along one direction.

[0107] In some examples, as shown in Figures 8 and 10, multiple traces 303 may include multiple first-type traces 3031, multiple second-type traces 3032, and multiple third-type traces 3033. First-type traces 3031 can connect circuit devices 31 and light-emitting elements. For example, one first-type trace 3031 can connect a first pad 3011 to a corresponding second pad. That is, circuit devices can be connected to twelve light-emitting elements via twelve first-type traces 3031.

[0108] In some examples, the second type trace 3032 can connect cascaded circuit devices. The third type trace 3033 can be configured to connect a first pad that transmits the same signal. In other words, the third type trace 3033 is used to connect the first pads of at least two circuit devices that receive the same signal.

[0109] In some examples, a circuit device 31 and its four connected light-emitting devices 32 constitute a repeating unit, and multiple repeating units can be arranged in an array along the fourth direction D4 and the fifth direction D5. Adjacent rows of circuit devices are cascaded. Specifically, the first pad corresponding to the first output terminal GOUT of any circuit device in a row arranged sequentially along the fifth direction D5 can be connected to the first pad corresponding to the first input terminal GIN of the adjacent circuit device in the next row via a second-type trace 3032; similarly, the first pad corresponding to the second output terminal EOUT of one circuit device in a row arranged sequentially along the fifth direction D5 can be connected to the first pad corresponding to the second input terminal EIN of the adjacent circuit device in the next row via a second-type trace 3032.

[0110] In some examples, the first pads corresponding to the first data signal terminals DL1 of circuit devices arranged sequentially along the fourth direction D4 are connected to the same Class 3 trace 3033, which is configured to transmit the first data signal. Similarly, the first pads corresponding to the second data signal terminals DL2 of circuit devices arranged sequentially along the fourth direction D4 are connected to the same Class 3 trace 3033, configured to transmit the second data signal. The first pads corresponding to the first input terminal GIN of circuit devices in the same row can be connected via Class 3 trace 3033, as can the first pads corresponding to the first output terminal GOUT of circuit devices in the same row, the first pads corresponding to the second input terminal EIN of circuit devices in the same row, and the first pads corresponding to the second output terminal EOUT of circuit devices in the same row. The first pads corresponding to the first power supply terminals VDD of multiple circuit devices can be connected via Class 3 traces 3033; the first pads corresponding to the initial signal terminals INIT of multiple circuit devices can be connected via Class 3 traces 3033; the first pads corresponding to the first clock signal terminals GCK of multiple circuit devices can be connected via Class 3 traces 3033; the first pads corresponding to the second clock signal terminals GCB of multiple circuit devices can be connected via Class 3 traces 3033; the first pads corresponding to the third clock signal terminals ECK of multiple circuit devices can be connected via Class 3 traces 3033; the first pads corresponding to the third power supply terminals VGH of multiple circuit devices can be connected via Class 3 traces 3033; and the first pads corresponding to the fourth power supply terminals VGL of multiple circuit devices can be connected via Class 3 traces 3033.

[0111] In this example, the backplane circuit board consists only of traces and pads, which can be implemented using fewer metal film layers, thus reducing manufacturing costs. By bonding the circuit devices integrating the driver sub-circuit, the first control circuit, and the second control circuit onto the circuit board, the small size of the circuit devices improves the utilization rate of the circuit board and reduces manufacturing costs. In some examples, the light-emitting device can be a miniature inorganic light-emitting diode chip. The miniature inorganic light-emitting diode chip and the circuit devices are respectively bonded onto the circuit board to form the light-emitting backplane, which reduces the manufacturing cost of the light-emitting backplane and improves its space utilization.

[0112] In other examples, where the circuitry does not include a second control circuit, the second control circuit shown in Figure 4 can be directly fabricated on the circuit board using semiconductor technology, or integrated into other circuitry and then fixedly connected to the circuit board via bonding. In still other examples, the second control circuit shown in Figure 4 can be omitted, and a row driver can be used directly to select the row to be updated. That is, the second input terminal EIN of each circuitry in the same row receives the same light-emitting control signal at the same time, and multiple rows of circuitry receive the light-emitting control signal sequentially and in a time-division manner.

[0113] Figure 11 is a schematic diagram of another arrangement of the circuit layer of the circuit device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 11, the circuit layer of the circuit device may include twelve driving sub-circuits 11, six cascaded first control circuits 12, and one second control circuit 13. The six cascaded first control circuits 12 may be divided into two groups, and the second control circuit 13 may be located between the first group of first control circuits 12a and the second group of first control circuits 12b. Each group of first control circuits may include three cascaded first control circuits 12. The twelve driving sub-circuits 11 may be symmetrically arranged about the six cascaded first control circuits 12. Two columns of driving sub-circuits may be located on both sides of the six cascaded first control circuits 12 along the first direction D1, and each column of driving sub-circuits may include six driving sub-circuits 11 arranged sequentially along the second direction D2. The circuit device of this example can be positioned on the circuit board as shown in the embodiments of Figures 8 to 10, and the circuit device may be located at the center of the four light-emitting devices. The remaining description of the circuit device and the corresponding backplane of this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0114] Figure 12 is a schematic diagram of another arrangement of the circuit layer of the circuit device according to at least one embodiment of the present disclosure. Figure 13 is a partial plan view of the backplane according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 12, the circuit layer of the circuit device may include twelve driving sub-circuits 11, six cascaded first control circuits 12, and a second control circuit 13. The twelve driving sub-circuits 11 may be located on the same side of the six cascaded first control circuits 12 along a first direction D1, and arranged in a two-column, six-row array. The second control circuit 13 may be located between the two sets of first control circuits 12a and 12b.

[0115] In some examples, as shown in Figures 12 and 13, the three light-emitting elements of a single light-emitting device are arranged adjacent to each other, and the three driving sub-circuits within the circuit device that provide driving signals to one light-emitting device can be arranged adjacent to each other. The second light-emitting element of a single light-emitting device can be adjacent to both the first and third light-emitting elements, and the driving sub-circuit within the circuit device that provides driving signals to the second light-emitting element can be adjacent to both the driving sub-circuit that provides driving signals to the first and third light-emitting elements. The six driving sub-circuits connected to two adjacent light-emitting devices are arranged adjacent to each other. In this example, the relative positional relationship of the twelve light-emitting elements connected to the circuit device can be consistent with the relative positional relationship of the twelve driving sub-circuits within the circuit device, which can help improve the space utilization of the backplane.

[0116] In some examples, as shown in Figure 13, the twelve light-emitting elements connected to circuit device 31 are located on the same side of circuit device 31 along one direction; the twelve driving sub-circuits within circuit device 31 are located on the same side of the six cascaded first control circuits along one direction. Circuit device 31 and the four light-emitting devices 32 connected to it can be a repeating unit, and multiple repeating units can be arranged in an array along the fourth direction D4 and the fifth direction D5. The first pads of adjacent circuit devices 31 along the fifth direction D5 that transmit the same signal can be connected through third-type traces, and the first pads of adjacent cascaded circuit devices 31 along the fourth direction D4 can be connected through second-type traces. In this example, the relative positional relationship between the circuit device and the twelve light-emitting elements connected to it, and the relative positional relationship between the six cascaded first control circuits and the twelve driving sub-circuits in the circuit device, are consistent, which can help improve the space utilization of the backplane.

[0117] The remaining description of the circuit components and corresponding backplane in this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0118] Figure 14 is a schematic diagram of another arrangement of the circuit layer of the circuit device according to at least one embodiment of the present disclosure. Figure 15 is a partial planar schematic diagram of the backplane according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 14, the circuit layer of the circuit device may include twelve driving sub-circuits 11, six cascaded first control circuits 12, and one second control circuit 13. The twelve driving sub-circuits 11 may be located on the same side (e.g., the upper side) of the six cascaded first control circuits 12 along the second direction D2, and arranged in a three-column, four-row array. The second control circuit 13 may be located on the same side of the six cascaded first control circuits 12 along the first direction D1.

[0119] In some examples, as shown in Figures 14 and 15, the three light-emitting elements of a single light-emitting device are arranged adjacent to each other, and the three driving sub-circuits within the circuit device that provide driving signals to one light-emitting device can be arranged adjacent to each other. The second light-emitting element of a single light-emitting device can be adjacent to both the first and third light-emitting elements, and the driving sub-circuit within the circuit device that provides driving signals to the second light-emitting element can be adjacent to both the driving sub-circuit that provides driving signals to the first and third light-emitting elements. The six driving sub-circuits connected to two adjacent light-emitting devices are arranged adjacent to each other. In this example, the relative positional relationship of the twelve light-emitting elements connected to the circuit device can be consistent with the relative positional relationship of the twelve driving sub-circuits within the circuit device, which can help improve the space utilization of the backplane.

[0120] In some examples, as shown in Figure 15, the twelve light-emitting elements connected to circuit device 31 are located on the same side of circuit device 31 along one direction (e.g., the fourth direction D4); the twelve driving sub-circuits within circuit device 31 are located on the same side of the six cascaded first control circuits along one direction (e.g., the second direction D2). Circuit device 31 and the four light-emitting elements 32 located on one side of it along the fourth direction D4 can be a repeating unit, and multiple repeating units can be arranged in an array along the fourth direction D4 and the fifth direction D5. The first pads of adjacent circuit devices 31 along the fifth direction D5 that transmit the same signal can be connected through third-type traces, and the first pads of adjacent cascaded circuit devices 31 along the fourth direction D4 can be connected through second-type traces. In this example, the relative positional relationship between the circuit device and the twelve light-emitting elements connected to it, and the relative positional relationship between the six cascaded first control circuits and the twelve driving sub-circuits in the circuit device, are consistent, which can help improve the space utilization of the backplane.

[0121] The remaining description of the circuit components and corresponding backplane in this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0122] Figure 16 is another schematic diagram of the circuit layer of a circuit device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 16, the circuit layer of the circuit device may include twelve driving sub-circuits 11, six cascaded first control circuits 12, and one second control circuit 13. The twelve driving sub-circuits 11 may be located on the same side (e.g., the lower side) of the six cascaded first control circuits 12 along the second direction D2, and arranged in a three-column, four-row array. The second control circuit 13 may be located on the same side of the six cascaded first control circuits 12 along the first direction D1. Further description of the circuit device and corresponding backplane of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0123] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0124] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A circuit device for providing drive signals to N components, comprising: An insulating substrate; A circuit layer disposed on the insulating substrate, the circuit layer comprising: N drive sub - circuits and M cascaded first control circuits; the N drive sub - circuits are connected to the M cascaded first control circuits; the orthographic projection of the N drive sub - circuits on the insulating substrate is located on at least one side of the orthographic projection of the M cascaded first control circuits on the insulating substrate; A connection cushion layer located on a side of the circuit layer away from the insulating substrate, and at least part of a surface of the connection cushion layer away from the insulating substrate is exposed; the connection cushion layer comprises: P connection pads, the P connection pads are respectively connected to the N drive sub - circuits and the M cascaded first control circuits; wherein, P > N + N / M + 2, M < N, and P, N, and M are all positive integers greater than 1.

2. The circuit device according to claim 1, wherein, The M cascaded first control circuits are arranged and cascaded in sequence along a first direction or a second direction, the first direction and the second direction are parallel to a plane where the insulating substrate is located, and the first direction intersects with the second direction; The N drive sub - circuits are arranged in an A×B array, where N = A×B and A and B are both positive integers greater than 1.

3. The circuit device according to claim 2, wherein, One of A and B is an even number, and the N drive sub - circuits are symmetrically arranged with respect to the M cascaded first control circuits.

4. The circuit device according to any one of claims 1 to 3, wherein, The circuit layer further comprises: R cascaded second control circuits, the R cascaded second control circuits are connected to the N drive sub - circuits; the P connection pads are respectively connected to the N drive sub - circuits, the M cascaded first control circuits, and the R cascaded second control circuits, where P > N + N / M + 4, and R is a positive integer greater than 0.

5. The circuit device according to claim 4, wherein, R = 1, and the second control circuit and the M cascaded first control circuits are arranged in sequence along the same direction.

6. The circuit device according to claim 5, wherein, The M cascaded first control circuits comprise: two groups of first control circuits, and the second control circuit is located between the two groups of first control circuits.

7. The circuit device according to any one of claims 4 to 6, wherein, The first control circuit is configured to provide a scan signal to at least one drive sub - circuit, the at least one drive sub - circuit is configured to write a data signal under the control of the scan signal, the second control circuit is configured to provide a light - emitting control signal to at least one drive sub - circuit, and the drive sub - circuit is configured to generate the drive signal under the control of the light - emitting control signal.

8. The circuit device according to any one of claims 1 to 7, wherein, The P connection pads are arranged in a C×D array, P = C×D, and the ratio of C to D is less than 2, or the ratio of D to C is less than 2; C and D are both positive integers greater than 0.

9. The circuit device according to any one of claims 1 to 8, wherein, The P connection pads comprise: V effective connection pads and K auxiliary connection pads, P = V + K, V is a positive integer greater than 1, and K is a non - negative integer; The V effective connection pads are connected to the circuit layer, and at least one of the K auxiliary connection pads is configured to be connected to an effective connection pad for transmitting a DC signal, or is not electrically connected to the circuit layer.

10. A backplane, comprising: A circuit board, wherein the circuit board is provided with multiple traces, the multiple traces including: a first type of trace and a second type of trace; Multiple components are disposed on the circuit board; and The circuit device as described in any one of claims 1 to 9 is disposed on the circuit board; The circuit device is connected to the N components via N traces of the first type; Circuit devices that are cascaded are connected through the second type of trace.

11. The backplate according to claim 10, wherein, The relative positions of the N components are consistent with the relative positions of the N driving sub-circuits in the circuit device.

12. The backplate according to claim 10 or 11, wherein, The relative positional relationship between the circuit device and the N components connected to it is consistent with the relative positional relationship between the M cascaded first control circuits and the N drive sub-circuits in the circuit device.

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