First circuit device, second circuit device and apparatus

Abstract

Provided are a first circuit device, a second circuit device and an apparatus. The first circuit device (31) is configured to provide a drive signal to N elements. The first circuit device (31) comprises: a first insulating substrate, a first circuit layer provided on the first insulating substrate and a first connection pad layer. The first circuit layer comprises N driving sub-circuits (11) arranged in a B×A array, N=A×B, and each of A and B being a positive integer greater than 0. The first connection pad layer is located on the side of the first circuit layer away from the first insulating substrate, and the surface of the first connection pad layer away from the first insulating substrate is at least partially exposed. The first connection pad layer comprises P connection pads, and the P connection pads are connected to the N driving sub-circuits (11), each of N and P being a positive integer greater than 0.

Description

First circuit device, second circuit device and apparatus

[0001] This application claims priority to international application filed on January 22, 2025, with application number PCT / CN2025 / 073967, entitled "Display Panel and Display Device", and international application filed on May 22, 2025, with application number PCT / CN2025 / 096466, entitled "Circuit Device and Backplane", the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a first circuit device, a second circuit device, and an apparatus. Background Technology

[0003] Micro LEDs and mini LEDs have advantages such as small size and high brightness. Display devices using these light-emitting devices are mainly used in augmented reality (AR), virtual reality (VR), television (TV), and outdoor displays. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This embodiment provides a first circuit device, a second circuit device, and an apparatus.

[0006] On one hand, this embodiment provides a first circuit device for providing drive signals to N components, comprising: a first insulating substrate, a first circuit layer disposed on the first insulating substrate, and a first connection pad layer. The first circuit layer includes N drive sub-circuits arranged in a B×A array, where N = A×B, and A and B are both positive integers greater than 0. The first connection pad layer is located on the side of the first circuit layer away from the first insulating substrate, and at least part of the surface of the first connection pad layer away from the first insulating substrate is exposed. The first connection pad layer includes P connection pads connected to the N drive sub-circuits, where N and P are both positive integers greater than 0.

[0007] In some exemplary implementations, P>N+A+B.

[0008] In some exemplary embodiments, the P connection pads include: E first input signal connection pads and F first output signal connection pads, where F = A × B; E and F are both positive integers greater than 1.

[0009] In some exemplary embodiments, the E first input signal connection pads include: b scan signal connection pads and a data signal connection pads. The b scan signal connection pads are configured to provide b scan signals, and the a data signal connection pads are configured to provide a data signal. Each scan signal is configured to control at least one driver sub-circuit to write a data signal. Wherein, a × b is less than or equal to N, and a and b are both positive integers greater than 0.

[0010] In some exemplary implementations, a = A, b = B; or, a = B, b = A.

[0011] In some exemplary embodiments, the first circuit layer further includes: a multiplexing circuits, each multiplexing circuit configured to convert one data signal into A / a data signals; the P connection pads are respectively connected to the N driver sub-circuits and the a multiplexing circuits.

[0012] In some exemplary implementations, P>N+a+b+A / a, a=b.

[0013] In some exemplary embodiments, the E first input signal connection pads further include at least one constant voltage signal connection pad configured to provide a constant voltage DC signal to the N drive sub-circuits.

[0014] On the other hand, this embodiment provides a second circuit device, including: a second insulating substrate, a second circuit layer disposed on the second insulating substrate, and a second connection pad layer. The second circuit layer includes: M cascaded first control circuits. The second connection pad layer is located on the side of the second circuit layer away from the second insulating substrate, and the surface of the second connection pad layer away from the second insulating substrate is at least partially exposed. The second connection pad layer includes: Q connection pads, the Q connection pads being connected to the M cascaded first control circuits, wherein Q>M+1, and Q and M are both positive integers greater than 0.

[0015] In some exemplary embodiments, the second circuit layer further includes: R cascaded second control circuits; R is a positive integer greater than 0; the Q connection pads are respectively connected to the M cascaded first control circuits and the R cascaded second control circuits, Q>M+R+2.

[0016] In some exemplary embodiments, the Q connection pads include: S second input signal connection pads and T second output signal connection pads, Q = S + T, T = M + R, S > 2, and S and T are both positive integers greater than 1.

[0017] On the other hand, this embodiment provides an apparatus, including: a circuit board, a plurality of components disposed on the circuit board, and at least one of the following: a plurality of first circuit devices as described above, and a plurality of second circuit devices as described above. The circuit board is provided with a plurality of traces, including: first type traces and second type traces. One first circuit device is connected to N of the components through N first type traces; at least one second circuit device is connected to the first circuit device through a second type trace.

[0018] In some exemplary embodiments, the multiple traces of the circuit board further include: a third type of trace, which is configured to connect two second circuit devices that are cascaded.

[0019] In some exemplary embodiments, the device includes: at least one first region, wherein a plurality of elements and a plurality of first circuit devices are disposed within a single first region. A group of second circuit devices is disposed along at least one side of the first region along a first direction, each group of second circuit devices including a plurality of cascaded second circuit devices; one second circuit device within each group of second circuit devices is connected to at least one first circuit device via a second type of trace.

[0020] In some exemplary embodiments, a first group of second circuit devices and a second group of second circuit devices are respectively arranged on both sides of the first region along the first direction, and the at least one first circuit device in the first region is connected to the same level of second circuit devices in the first group of second circuit devices and the second group of second circuit devices.

[0021] In some exemplary embodiments, the device includes: at least one first region, a plurality of elements and a plurality of first circuit devices disposed within a single first region, and a group of second circuit devices disposed on at least one side of the first region along a first direction. The at least one group of second circuit devices includes: a plurality of cascaded subgroups of second circuit devices, at least one subgroup of second circuit devices including: a first type of second circuit device and a second type of second circuit device; the first type of second circuit devices and the second type of second circuit devices within a first-level second circuit device subgroup are connected to the second type of second circuit devices within a previous-level second circuit device subgroup via the third type of trace; the first type of second circuit devices within a first-level second circuit device subgroup are connected to at least one group of first circuit devices within the first region via the second type of trace; the second type of second circuit devices within a first-level second circuit device subgroup are configured to provide a start signal to the next-level second circuit device subgroup.

[0022] In some exemplary embodiments, the plurality of elements includes a plurality of light-emitting devices, each light-emitting device including three light-emitting elements emitting light of different colors; the first circuit device includes twelve driving sub-circuits and a multiplexing circuit; the anode connection terminals of the twelve driving sub-circuits are connected to the twelve light-emitting elements one-to-one; the multiplexing circuit is configured to convert two data signals into six data signals; among the twelve light-emitting elements, the driving sub-circuit connected to every two light-emitting elements emitting the same color light is configured to receive the same data signal; and the driving sub-circuit connected to every two light-emitting elements is configured to receive the same scan signal.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood.

[0024] Overview of the attached figures

[0025] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0026] Figure 1 is a schematic diagram of the architecture of a first circuit device according to at least one embodiment of the present disclosure;

[0027] Figure 2 is an equivalent circuit diagram of the driving sub-circuit of at least one embodiment of the present disclosure;

[0028] Figure 3 is a schematic diagram of the structure of the first circuit layer of the first circuit device according to at least one embodiment of the present disclosure;

[0029] Figure 4 is a schematic diagram of another architecture of the first circuit device according to at least one embodiment of the present disclosure;

[0030] Figure 5 is another schematic diagram of the structure of the first circuit layer of the first circuit device according to at least one embodiment of the present disclosure;

[0031] Figure 6 is a trend chart showing the number of connection pads of the first circuit device in at least one embodiment of the present disclosure.

[0032] Figure 7 is a schematic diagram of the architecture of a second circuit device according to at least one embodiment of the present disclosure;

[0033] Figure 8 is an equivalent circuit diagram of the first control circuit of at least one embodiment of the present disclosure;

[0034] Figure 9 is an equivalent circuit diagram of the second control circuit of at least one embodiment of the present disclosure;

[0035] Figure 10 is a schematic diagram of the architecture of the second circuit layer of the second circuit device according to at least one embodiment of the present disclosure;

[0036] Figure 11 is a schematic diagram of an apparatus according to at least one embodiment of the present disclosure;

[0037] Figure 12 is a schematic diagram of the structure of the first region according to at least one embodiment of the present disclosure;

[0038] Figure 13 is another schematic diagram of an apparatus according to at least one embodiment of the present disclosure;

[0039] Figure 14 is another schematic diagram of an apparatus according to at least one embodiment of the present disclosure;

[0040] Figure 15 is a schematic diagram of the arrangement of light-emitting elements driven by the first circuit device in Example 1;

[0041] Figure 16 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 1;

[0042] Figure 17 is a schematic diagram of the operating timing of the first circuit device in Example 1;

[0043] Figure 18 is a schematic diagram of the arrangement of light-emitting elements driven by the first circuit device in Example 2;

[0044] Figure 19 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 2;

[0045] Figure 20 is a schematic diagram of the operating timing of the first circuit device in Example 2;

[0046] Figure 21 is a schematic diagram of the arrangement of light-emitting elements driven by the first circuit device in Example 3;

[0047] Figure 22 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 3;

[0048] Figure 23 is a schematic diagram of the operating timing of the first circuit device in Example 3;

[0049] Figure 24 is a schematic diagram of the arrangement of light-emitting elements driven by the first circuit device in Example 4;

[0050] Figure 25 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 4;

[0051] Figure 26 is a schematic diagram of the operating timing of the first circuit device in Example 4;

[0052] Figure 27 is a schematic diagram of the arrangement of light-emitting elements driven by the first circuit device in Example 5;

[0053] Figure 28 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 5;

[0054] Figure 29 is a schematic diagram of the operating timing of the first circuit device in Example 5.

[0055] Detailed Explanation

[0056] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0057] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0058] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0059] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0060] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Joining" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on "components having some electrical function," as long as they enable the transmission of electrical signals between the connected constituent elements. Examples of "components having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0061] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0062] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0063] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0064] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0065] In this specification, "approximately" and "about" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" includes values ​​differing by less than 10%, such as values ​​differing by less than 5%.

[0066] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0067] In this specification, "A and B are of the same layer structure" and "A and B are arranged in the same layer" mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "Same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view. The "shape of A" in this disclosure refers to the shape of A as projected onto the substrate.

[0068] Multiple circuits with different functions (such as a driver sub-circuit that provides electrical signals to electronic components and a control circuit that provides electrical signals to the driver sub-circuit) can be integrated into a circuit device with a smaller size. The electronic components and the circuit device are then placed on the passive matrix driver (PM) backplane, and the circuit device provides signals to the electronic components to realize the specific functions of the electronic components.

[0069] In some implementations, the electronic components can be electroluminescent diodes, such as those with dimensions on the order of hundreds of micrometers or even smaller. The circuitry can include a driving sub-circuit for directly supplying electrical signals to the LEDs, and / or a control circuit for supplying electrical signals to the driving sub-circuit. In scenarios where multiple LEDs are arranged according to a specific pattern to serve as display pixels, to achieve higher resolution and refresh rates, multiple driving sub-circuits and / or multiple control circuits matching the number of LEDs will be required.

[0070] This embodiment provides a first circuit device, a second circuit device, and an apparatus, which can help improve the reliability of the circuit device and reduce costs.

[0071] This embodiment provides a first circuit device for providing drive signals to N components, comprising: a first insulating substrate, a first circuit layer disposed on the first insulating substrate, and a first connection pad layer. The first circuit layer includes N drive sub-circuits arranged in a B×A array, where N = A×B, and A and B are positive integers greater than 0. The first connection pad layer is located on the side of the first circuit layer away from the first insulating substrate, and at least part of the surface of the first connection pad layer away from the first insulating substrate is exposed. The first connection pad layer includes P connection pads, which are connected to the N drive sub-circuits. N and P are both positive integers greater than 0. In some examples, P > N + A + B.

[0072] Compared to the implementation method of integrating the driving sub-circuit and control circuit into a single circuit device, the first circuit device provided in this embodiment integrates N driving sub-circuits separately, which can help reduce the size of the first circuit device and reduce costs. Devices using the first circuit device of this example can reduce the number of cascaded circuit devices, thereby avoiding display defects caused by cascading anomalies.

[0073] In some exemplary embodiments, the P connection pads may include: E first input signal connection pads and F first output signal connection pads, where F = A × B; E and F are both positive integers greater than 1. For example, E can be greater than A + B. In some examples, the E first input signal connection pads may include: b scan signal connection pads and a data signal connection pads, where the b scan signal connection pads are configured to provide b scan signals to N driver sub-circuits, and the a data signal connection pads are configured to provide a data signal. One scan signal is configured to control at least one driver sub-circuit to write one data signal; wherein a × b is less than or equal to N, and a and b are both positive integers greater than 0. For example, a = A, b = B; or a = B, b = A. The connection pad configuration in this example can meet the signal transmission requirements of the first circuit device.

[0074] In some exemplary embodiments, the first circuit layer may further include: *a* multiplexing circuits, each configured to convert one data signal into A / a data signals; the *P* connection pads are respectively connected to the *N* driver sub-circuits and the *a* multiplexing circuits. In some examples, *P* > *N* + *a* + *b* + *A* / a*, and *a* = *b*. This example, by setting multiplexing circuits, can help reduce the number of connection pads in the first connection pad layer, thereby helping to reduce costs.

[0075] In some exemplary embodiments, the E first input signal connection pads may further include: at least one constant voltage signal connection pad, the at least one constant voltage signal connection pad being configured to provide a constant voltage DC signal to the N drive sub-circuits.

[0076] The following examples illustrate the solution of this embodiment. In these examples, taking a light-emitting element as an example, the driving sub-circuit can be configured to provide a driving signal to drive the light-emitting element to emit light. In other examples, the element can be a sensing element, and the circuit device in this example can be configured to drive the sensing element to perform a sensing function. In still other examples, the element can be other functional elements, and the circuit device in this example can be configured to drive the corresponding element to perform a specific function.

[0077] Figure 1 is a schematic diagram of the architecture of a first circuit device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the first circuit device 31 may include at least one driving sub-circuit 11. The driving sub-circuit 11 may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the driving sub-circuit 11, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In other examples, the driving sub-circuit may include at least one of the following: a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit.

[0078] Figure 2 is an equivalent circuit diagram of the driving sub-circuit of at least one embodiment of the present disclosure. As shown in Figure 2, the driving sub-circuit of this example can be a 7T1C structure. The driving sub-circuit may include first pixel transistors PT1 to seventh pixel transistors PT7, and a storage capacitor Cst. The third pixel transistor PT3 can be a driving transistor. The gate of the third pixel transistor PT3 can be electrically connected to the first pixel node P1, the first terminal of the third pixel transistor PT3 can be electrically connected to the second pixel node P2, and the second terminal of the third pixel transistor PT3 can be electrically connected to the third pixel node P3. The gate of the second pixel transistor PT2 can be electrically connected to the scan terminal GL, the first terminal of the second pixel transistor PT2 can be electrically connected to the third pixel node P3, and the second terminal of the second pixel transistor PT2 can be electrically connected to the first pixel node P1. The gate of the first pixel transistor PT1 can be electrically connected to the reset control terminal RST, the first terminal of the first pixel transistor PT1 can be electrically connected to the initial signal terminal INIT, and the second terminal of the first pixel transistor PT1 can be electrically connected to the first pixel node P1. The gate of the fourth pixel transistor PT4 can be electrically connected to the scan terminal GL, the first electrode of the fourth pixel transistor PT4 can be electrically connected to the data terminal DL, and the second electrode of the fourth pixel transistor PT4 can be electrically connected to the second pixel node P2. The gate of the fifth pixel transistor PT5 can be electrically connected to the light emission control terminal EM, the first electrode of the fifth pixel transistor PT5 can be electrically connected to the first power supply terminal VDD, and the second electrode of the fifth pixel transistor PT5 can be electrically connected to the second pixel node P2. The gate of the sixth pixel transistor PT6 can be electrically connected to the light emission control terminal EM, the first electrode of the sixth pixel transistor PT6 can be electrically connected to the third pixel node P3, and the second electrode of the sixth pixel transistor PT6 can be electrically connected to the fourth pixel node P4. The gate of the seventh pixel transistor PT7 can be electrically connected to the reset control terminal RST, the first electrode of the seventh pixel transistor PT7 can be electrically connected to the initial signal terminal INIT, and the second electrode of the seventh pixel transistor PT7 can be electrically connected to the fourth pixel node P4. The first electrode of the storage capacitor Cst is electrically connected to the first power supply terminal VDD, and the second electrode of the storage capacitor Cst is electrically connected to the first pixel node P1. The first electrode of the light-emitting element EL driven by the driving sub-circuit 11 can be connected to the fourth pixel node P4, and the second electrode of the light-emitting element EL can be connected to the second power supply terminal VSS.

[0079] In some examples, the scanning terminal GL can be configured to transmit a scanning signal, the light emission control terminal EM can be configured to transmit a light emission control signal, the reset control terminal RST can be configured to transmit a reset control signal, and the data terminal DL can be configured to transmit a data signal. The initial signal terminal INTI can be configured to transmit an initial signal, the first power supply terminal VDD can be configured to transmit a first power supply signal, and the second power supply terminal VSS can be configured to transmit a second power supply signal. The first power supply signal, the second power supply signal, and the initial signal can all be constant voltage DC signals. The voltage value of the first power supply signal can be greater than the voltage value of the second power supply signal, and the voltage value of the initial signal can be between the voltage values ​​of the first power supply signal and the second power supply signal.

[0080] In some examples, as shown in Figures 1 and 2, a single driving sub-circuit 11 can be connected to seven signal terminals, including a first power supply terminal VDD, an initial signal terminal INIT, a data terminal DL, an anode connection terminal AN, a reset control terminal RST, a scan terminal GL, and a light emission control terminal EM. The anode connection terminal AN is connected to the fourth pixel node P4 of the driving sub-circuit 11. The seven signal terminals may include: six input signal terminals (i.e., including the first power supply terminal VDD, the initial signal terminal INIT, the data terminal DL, the reset control terminal RST, the scan terminal GL, and the light emission control terminal EM) and one output signal terminal (i.e., the anode connection terminal AN).

[0081] In some examples, as shown in Figure 1, the first circuit device 31 can integrate a driver sub-circuit 11. The first connection pad layer of the first circuit device 31 can include seven connection pads, i.e., P = 7. These seven connection pads can be connected one-to-one with the aforementioned seven signal terminals. The seven connection pads can include six first input signal connection pads and one first output signal connection pad. The six first input signal connection pads are connected one-to-one with the aforementioned six input signal terminals, and the first output signal connection pad is connected to the aforementioned output signal terminal (i.e., the anode connection terminal AN).

[0082] In some examples, as shown in Figure 1, the first circuit device 31 can integrate A driving sub-circuits 11, and the A driving sub-circuits 11 are arranged sequentially along the row direction X1, that is, arranged in a row and the row of driving sub-circuits includes A driving sub-circuits 11. In other words, the A driving sub-circuits 11 are arranged in a 1×A array manner. Each driving sub-circuit 11 in this row of driving sub-circuits can be connected to a data terminal DL and an anode connection terminal AN, that is, the row of driving sub-circuits is connected to A data terminals DL and A anode connection terminals AN; the row of driving sub-circuits can be connected to a reset control terminal RST, a scan terminal GL, an emission control terminal EM, a first power supply terminal VDD, and an initial signal terminal INIT. Therefore, the number of connection pads in the first connection pad layer of the first circuit device 31 integrating the row of driving sub-circuits is P = 2×A+5. The P connection pads may include A first output signal connection pads and A+5 first input signal connection pads; the A first output signal connection pads may be connected one-to-one with the A anode connection terminals AN, and the A+5 first input signal connection pads may be connected one-to-one with the A data terminals DL, a first power supply terminal VDD, an initial signal terminal INIT, a reset control terminal RST, a scan terminal GL, and a light emission control terminal EM.

[0083] In some examples, as shown in Figure 1, the first circuit device 31 can integrate B driving sub-circuits 11, and the B driving sub-circuits 11 are arranged sequentially along the column direction Y1, that is, arranged in a column and the column driving sub-circuit includes B driving sub-circuits 11. In other words, the B driving sub-circuits 11 are arranged in a B×1 array. Each driving sub-circuit 11 in this column is connected to a scan terminal GL and an anode connection terminal AN, that is, the column driving sub-circuit is connected to B scan terminals GL and B anode connection terminals AN; the column driving sub-circuit can be connected to a data terminal DL, a light emission control terminal EM, a first power supply terminal VDD and an initial signal terminal INIT. The first driving sub-circuit 11 in this column can be connected to the reset control terminal RST, and the remaining driving sub-circuits 11 are all connected to the scan terminal GL connected to the previous driving sub-circuit, so as to use the scan signal received by the previous driving sub-circuit as its own reset control signal. Therefore, the number of connection pads in the first connection pad layer of the first circuit device 31 integrating this column of driving sub-circuits is P = 2×B+5. The P connection pads may include B first output signal connection pads and B+5 first input signal connection pads; the B first output signal connection pads may be connected one-to-one with the B anode connection terminals AN, and the B+5 first input signal connection pads may be connected one-to-one with the B scan terminals GL, a first power supply terminal VDD, an initial signal terminal INIT, a reset control terminal RST, a data terminal DL, and a light emission control terminal EM.

[0084] In some examples, as shown in Figure 1, the first circuit device 31 can integrate N driving sub-circuits 11 arranged in a B×A array, i.e., the N driving sub-circuits are arranged in B rows and A columns, and the total number of driving sub-circuits N = A×B, where A and B are both positive integers greater than 0. Each row of driving sub-circuits in the B rows can be connected to the same scan terminal GL and the same reset control terminal RST; wherein, each row of driving sub-circuits in the B rows can be connected to one scan terminal GL, the first row of driving sub-circuits can be connected to the reset control terminal RST, and the next row of driving sub-circuits is connected to the scan terminal GL connected to the previous row of driving sub-circuits, so that the scan signal of the previous row of driving sub-circuits is used as the reset control signal of the current row. Each column of driving sub-circuits in the A columns can be connected to one data terminal DL. The N driving sub-circuits 11 can be connected to the same light emission control terminal EM, the same first power supply terminal VDD, and the same initial signal terminal INIT. Each driving sub-circuit 11 can be connected to an anode connection terminal AN. Therefore, the number of connection pads in the first connection pad layer of the first circuit device 31 integrating N driving sub-circuits is P = 4 + A + B + A × B. The P connection pads may include A × B first output signal connection pads and 4 + A + B first input signal connection pads; the A × B first output signal connection pads can be connected one-to-one with A × B anode connection terminals AN, and the 4 + A + B first input signal connection pads can be connected one-to-one with A data terminals DL, B scan terminals GL, a reset control terminal RST, a light emission control terminal EM, an initial signal terminal INIT, and a first power supply terminal VDD.

[0085] In this example, among the N driving sub-circuits 11 integrated in the first circuit device 31, the first row of driving sub-circuits can be reset using the reset control signal provided by the reset control terminal RST. Each row of driving sub-circuits in the remaining rows can be reset using the scan signal received by the previous row of driving sub-circuits as the reset control signal for that row. Moreover, the N driving sub-circuits can generate driving signals under the control of the same light emission control signal.

[0086] In some examples, due to limitations of the die bonding equipment, the P connection pads of the first circuit device are arranged in a C×D array. The orthographic projection of a single connection pad onto the first insulating substrate can be approximately square, and the spacing between adjacent connection pads can be the same. Therefore, the ratio of C to D can be less than or equal to 2, or the ratio of D to C can be less than or equal to 2, where C and D are positive integers greater than 0. In this example, the dimensions of the multiple connection pads of the first circuit device can be set to be the same to correspond with the die bonding equipment, thereby ensuring yield and die bonding effect. For example, the orthographic projection size of a single connection pad onto the substrate can be 40 micrometers × 40 micrometers.

[0087] In some examples, the total area of ​​the first circuit device can be greater than the total area of ​​the P connection pads. The area of ​​the first circuit device is related to the number and arrangement of the connection pads. In this example, arranging the connection pads in a C×D array can help reduce the area of ​​the first circuit device and lower costs.

[0088] Figure 3 is a schematic diagram of the structure of the first circuit layer of the first circuit device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the first circuit device 31 may include 24 driving sub-circuits 11, i.e., the value of N in this example is 24. The 24 driving sub-circuits 11 can be arranged in a four-row, six-column array, i.e., B=4 and A=6 in this example. The 24 driving sub-circuits 11 can be connected to the same first power supply terminal VDD, the same initial signal terminal INIT, and the same light emission control terminal EM. That is, the 24 driving sub-circuits 11 can be configured to receive the same first power supply signal, the same initial signal, and the same light emission control signal. The fourth pixel node of the 24 driving sub-circuits 11 can be connected one-to-one with the 24 anode connection terminals AN1 to AN24.

[0089] In some examples, the 24 driver sub-circuits 11 can be connected to four scan terminals (i.e., scan terminals GL1 to GL4) and six data terminals (i.e., data terminals DL1 to DL6). In this example, the first connection pad layer can include four scan signal connection pads and six data signal connection pads, i.e., b=4 and a=6 in this example. The four scan signal connection pads can be connected one-to-one with the four scan terminals, and the six data signal connection pads can be connected one-to-one with the six data terminals.

[0090] In some examples, the first row driver sub-circuit is connected to the reset control terminal RST and the scan terminal GL1, and is reset using the reset control signal provided by the reset control terminal RST; the second row driver sub-circuit is connected to the scan terminal GL1 and the scan terminal GL2, and is reset using the scan signal received from the scan terminal GL1 as the reset control signal for this row; the third row driver sub-circuit is connected to the scan terminal GL2 and the scan terminal GL3, and is reset using the scan signal received from the scan terminal GL2 as the reset control signal for this row; the fourth row driver sub-circuit is connected to the scan terminal GL3 and the scan terminal GL4, and is reset using the scan signal received from the scan terminal GL3 as the reset control signal for this row.

[0091] In some examples, each column of driver subcircuit is connected to a data terminal and configured to receive one data signal. From right to left, the first column of driver subcircuit is connected to data terminal DL1, the second column of driver subcircuit is connected to data terminal DL2, the third column of driver subcircuit is connected to data terminal DL3, the fourth column of driver subcircuit is connected to data terminal DL4, the fifth column of driver subcircuit is connected to data terminal DL5, and the sixth column of driver subcircuit is connected to data terminal DL6.

[0092] The way the first circuit device in this example integrates the driver sub-circuit can help reduce the size of the first circuit device and reduce costs.

[0093] In other examples, the 24 driver sub-circuits 11 shown in Figure 3 can be connected to six scan terminals and four data terminals. Each row of driver sub-circuits can receive data signals from the same data terminal, and each column of driver sub-circuits can receive scan signals from the same scan terminal. In this example, the first connection pad layer can include six scan signal connection pads and four data signal connection pads, i.e., b=6 and a=4 in this example. The six scan signal connection pads can be connected one-to-one with the six scan terminals, and the four data signal connection pads can be connected one-to-one with the four data terminals.

[0094] Figure 4 is another schematic diagram of the architecture of the first circuit device according to at least one embodiment of the present disclosure. In some examples, taking the driving sub-circuit shown in Figure 2 as an example, a single driving sub-circuit 11 can be connected to seven signal terminals, which may include a first power supply terminal VDD, an initial signal terminal INIT, a data terminal DL, an anode connection terminal AN, a reset control terminal RST, a scan terminal GL, and a light emission control terminal EM.

[0095] In some examples, as shown in Figure 4, the first circuit layer of the first circuit device 31 may include: N driving sub-circuits 11 and a multiplexer circuits 14. The a multiplexer circuits 14 may be located on the same side of the N driving sub-circuits 11 along a direction (e.g., column direction Y1). Each multiplexer circuit 14 may be connected to c gating control terminals ML, configured to convert one data signal provided by one data terminal into c data signals under the control of the c gating control signals, and provide them to the c column driving sub-circuits 11. The a multiplexer circuits can convert a data signals provided by a data terminals into a×c data signals. Taking the N driving sub-circuits 11 arranged in a B×A array as an example, a can be less than or equal to A, c = A / a, and c is a positive integer greater than 0. For example, if a = 2, c = 3, and A = 6, a single multiplexer circuit 14 can convert one data signal provided by a data terminal DL into three data signals, and two multiplexer circuits 14 can convert two data signals provided by two data terminals DL into six data signals, which are then provided to the six-column driver sub-circuits. This example, by adding an integrated multiplexer circuit within the first circuit device, reduces the number of required data terminals, thereby reducing the number of connection pads in the first circuit device. This, in turn, helps to reduce the area of ​​the first circuit device, lower costs, and improve product competitiveness.

[0096] In some examples, N driver sub-circuits 11 can be connected to b scan terminals GL. Taking the N driver sub-circuits arranged in a B×A array as an example, b can be less than or equal to B. When b = B, each row of driver sub-circuits can be connected to one scan terminal GL; when b is less than B, one scan terminal GL can be configured to provide scan signals to at least one row (e.g., two rows) of driver sub-circuits, and at least one row of driver sub-circuits connected to the same scan terminal GL can simultaneously perform data signal writing. This example reduces the number of required scan terminals by increasing the number of rows of driver sub-circuits corresponding to a single scan terminal, thereby reducing the number of connection pads of the first circuit device, which in turn helps to reduce the area of ​​the first circuit device, thereby reducing costs and improving product competitiveness.

[0097] In some examples, as shown in Figure 4, the number of connection pads in the first connection pad layer of the first circuit device 31 is P = 4 + a + b + c + A × B. The P connection pads can be connected one-to-one with b scan terminals GL, A × B anode connection terminals AN, c gating control terminals ML, a data terminal DL, a first power supply terminal VDD, an initial signal terminal INIT, a reset control terminal RST, and a light emission control terminal EM. The P connection pads may include A × B first output signal connection pads and 4 + a + b + c first input signal connection pads. The plurality of first input signal connection pads may include a data signal connection pads and b scan signal connection pads. The a data signal connection pads can be connected one-to-one with a data terminal, and the b scan signal connection pads can be connected one-to-one with b scan terminals. The A × B first output signal connection pads can be connected one-to-one with A × B anode connection terminals AN.

[0098] In some examples, a, b, c, A, and B can satisfy the following relationship: a × b × c = A × B. Based on cost optimization considerations, the optimal number of driver sub-circuits integrated within the first circuit device can be determined. After determining the number N of driver sub-circuits integrated within the first circuit device, the number P of connection pads for driver sub-circuit 11 can have a minimum value when the differences between each pair of parameters a, b, and c are minimized (i.e., the optimal case is a = b = c), for example, P = 4 + 3a + a 3 .

[0099] In some examples, the number of data signals required by N driver sub-circuits 11 = the number of data terminals × the number of gating control terminals, i.e., a × c. Taking a column of driver sub-circuits receiving the same data signal and the number of columns of driver sub-circuits as an example, a × c = A; taking a row of driver sub-circuits receiving the same data signal and the number of rows of driver sub-circuits as an example, a × c = B.

[0100] Figure 5 is another schematic diagram of the first circuit layer of the first circuit device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 5, the first circuit device 31 may include 24 driving sub-circuits 11 and two multiplexing circuits 14. In this example, N is 24. The 24 driving sub-circuits 11 can be arranged in a four-row, six-column array, i.e., B=4 and A=6 in this example. The 24 driving sub-circuits 11 can be connected to the same first power supply terminal VDD, the same initial signal terminal INIT, and the same light emission control terminal EM. That is, the 24 driving sub-circuits 11 are configured to receive the same first power supply signal, the same initial signal, and the same light emission control signal.

[0101] In some examples, as shown in Figure 5, each multiplexing circuit 14 may include three multiplexed control transistors. The gate of each multiplexed control transistor may be connected to a gating control terminal, its first terminal may be connected to a data terminal, and its second terminal may be connected to a column of driver sub-circuits. Specifically, one multiplexing circuit 14 may include: a first multiplexed control transistor XT1, a second multiplexed control transistor XT2, and a third multiplexed control transistor XT3; another multiplexing circuit 14 may include: a fourth multiplexed control transistor XT4, a fifth multiplexed control transistor XT5, and a sixth multiplexed control transistor XT6. The gate of the first multiplexed control transistor XT1 may be connected to a first gating control terminal ML1, its first terminal may be connected to a data terminal DL1, and its second terminal may be connected to the sixth column of driver sub-circuits from right to left. The gate of the second multiplexed control transistor XT2 may be connected to a second gating control terminal ML2, its first terminal may be connected to a data terminal DL1, and its second terminal may be connected to the fifth column of driver sub-circuits from right to left. The gate of the third multiplexing control transistor XT3 can be connected to the third gating control terminal ML3, its first terminal can be connected to the data terminal DL1, and its second terminal can be connected to the fourth column driver sub-circuit from right to left. The gate of the fourth multiplexing control transistor XT1 can be connected to the first gating control terminal ML1, its first terminal can be connected to the data terminal DL2, and its second terminal can be connected to the third column driver sub-circuit from right to left. The gate of the fifth multiplexing control transistor XT5 can be connected to the second gating control terminal ML2, its first terminal can be connected to the data terminal DL2, and its second terminal can be connected to the second column driver sub-circuit from right to left. The gate of the sixth multiplexing control transistor XT6 can be connected to the third gating control terminal ML3, its first terminal can be connected to the data terminal DL2, and its second terminal can be connected to the first column driver sub-circuit from right to left. The two multiplexing circuits 14 in this example can convert the two data signals provided by the two data terminals into six data signals and provide them to the six column driver sub-circuits.

[0102] This example reduces the number of required data terminals by adding an integrated multiplexing circuit within the first circuit device, thereby reducing the number of connection pads in the first circuit device. This, in turn, helps to reduce the area of ​​the first circuit device, lower costs, and improve product competitiveness. Further descriptions of the first circuit device in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0103] The following description uses the example of a first circuit device driving four pixel units. Each pixel unit may include three light-emitting elements, such as a light-emitting element emitting a first color light (e.g., red light), a light-emitting element emitting a second color light (e.g., green light), and a light-emitting element emitting a third color light (e.g., blue light). Each driving sub-circuit 11 can be configured to provide a driving signal to one light-emitting element to drive the light-emitting element to emit light. The first circuit device can integrate twelve driving sub-circuits. Figure 6 is a trend chart of the number of connection pads of the first circuit device according to at least one embodiment of the present disclosure. In Figure 6, the horizontal axis represents the number of scanning ends b, the vertical axis represents the number of connection pads P, and the five curves correspond to different numbers of gating control ends. As can be seen from Figure 6, the minimum value of the number of connection pads P used by the first circuit device integrating twelve driving sub-circuits can be 23. Table 1 illustrates various examples of the first circuit device integrating twelve driving sub-circuits with a connection pad number P of 23.

[0104] Table 1

[0105] The fabrication process of the first circuit device is illustrated below. The "patterning process" described in this example includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This embodiment does not limit the methods used.

[0106] In some examples, the fabrication process of the first circuit device may include: providing a first insulating substrate, such as a glass substrate; fabricating a master wafer including a first circuit layer and a first connection pad layer; and cutting the master wafer to obtain multiple first circuit devices. The fabrication process of the master wafer may include: depositing a first conductive film on the glass substrate, and patterning the first conductive film using a patterning process to form a first conductive layer, for example, the first conductive layer may include the bottom gate of multiple transistors; subsequently, depositing a first insulating film and a semiconductor film, and patterning the semiconductor film using a patterning process to form a semiconductor layer, for example, the semiconductor layer may include the active layer of multiple transistors; subsequently, depositing a second insulating film and a second conductive film, and patterning the second insulating film and the second conductive film sequentially using a patterning process to form a second conductive layer, for example, the second conductive layer may include the top gate of multiple transistors; subsequently, depositing a third insulating film, and patterning the first conductive film using a patterning process to form a second conductive layer, for example, the second conductive layer may include the top gate of multiple transistors; and subsequently, depositing a third insulating film, and patterning the first conductive film using a patterning process to form a second conductive layer. The process involves patterning a third insulating film, a second insulating film, and a first insulating film to form a third insulating layer, a second insulating layer, and a first insulating layer; subsequently, a third conductive film is deposited and patterned using a patterning process to form a third conductive layer, which may include, for example, the source and drain of multiple transistors; subsequently, a fourth insulating film is coated and patterned using a patterning process to form a fourth insulating layer; subsequently, a fifth insulating film is deposited and patterned using a patterning process to form a fifth insulating layer; subsequently, a fourth conductive film is deposited and patterned using a patterning process to form a first connection pad layer.

[0107] In some examples, the first conductive film, the second conductive film, the third conductive film, and the fourth conductive film can be made of metallic materials, such as any one or more of silver (Ag), molybdenum (Mo), aluminum (Al), and titanium (Ti), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc.

[0108] In some examples, the semiconductor thin film can be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene. For example, the semiconductor layer can be made of amorphous silicon or metal oxide.

[0109] In some examples, the first, second, third, and fifth insulating films can be any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The fourth insulating film can be an organic insulating material.

[0110] In some examples, after forming the first bonding pad layer, the master wafer can be cut. For example, the master wafer can be cut along a slit to obtain multiple 10cm × 10cm square wafers; then, the square wafers can be cut along the slit to obtain 4-inch circular wafers, each of which can include multiple first circuit devices. For example, bonding leads can be fabricated on the exposed bonding pads on the surface of each wafer, and the bonding leads can be electrically connected to the aforementioned bonding pads. For example, multiple bonding pads correspond one-to-one with multiple bonding leads. The bonding leads can be made of metallic materials, such as any one or more of silver (Ag), gold (Au), copper (Cu), and tin (Sn), or alloys of the above metals, such as silver tin oxide (SnAg) or tin-lead alloy (SnPb), and can be a single-layer structure or a multi-layer composite structure. The orthographic projection of the bonding lead onto the glass substrate and the orthographic projection of the connected bonding pad onto the glass substrate can at least partially overlap. For example, the orthographic projection of the bonding lead onto the glass substrate can be located within the orthographic projection range of the connected bonding pad onto the glass substrate. For example, the orthographic projection of the bonding pins onto the glass substrate can coincide with the orthographic projection of the connected pads onto the glass substrate. The first circuit device can then be connected to a first pad group on the circuit board via multiple bonding pins. Subsequently, the glass substrate of each wafer is thinned, for example, from 0.5 mm to 0.1 mm. Then, the wafers are cut into multiple first circuit devices using a laser dicing process.

[0111] This embodiment also provides a second circuit device, including: a second insulating substrate, a second circuit layer disposed on the second insulating substrate, and a second connection pad. The second circuit layer includes: M cascaded first control circuits. The second connection pad layer is located on the side of the second circuit layer away from the second insulating substrate, and at least part of the surface of the second connection pad layer away from the second insulating substrate is exposed. The second connection pad layer includes: Q connection pads, and the Q connection pads are connected to the M cascaded first control circuits. Wherein, Q>M+1, and both Q and M are positive integers greater than 1.

[0112] This is equivalent to a single circuit device integrating the driver sub-circuit and the control circuit. The second circuit device provided in this embodiment integrates M first control circuits, which can help reduce the size of the second circuit device and lower costs. Devices using the second circuit device of this example can reduce the number of cascaded circuit devices, thereby avoiding display defects caused by cascading anomalies.

[0113] In some exemplary embodiments, the second circuit layer may further include: R cascaded second control circuits; R is a positive integer greater than 0; the Q connection pads are respectively connected to the M cascaded first control circuits and the R cascaded second control circuits, Q>M+R+2, M>R. The second circuit device of this example can integrate M first control circuits and R second control circuits to reduce cost.

[0114] In some exemplary embodiments, the Q connection pads may include: S second input signal connection pads and T second output signal connection pads, Q = S + T, T = M + R, S > 2, and S and T are both positive integers greater than 1.

[0115] Figure 7 is a schematic diagram of the architecture of a second circuit device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 7, the second circuit layer of the second circuit device 33 may include M cascaded first control circuits 12 and R cascaded second control circuits 13. Both M and R can be integers greater than 0. The second connection pad layer of the second circuit device 33 may include Q connection pads, which are connected to the M cascaded first control circuits and the R cascaded second control circuits. For example, R can be 1, and M can be greater than 1.

[0116] The structures of the first and second control circuits are illustrated below.

[0117] Figure 8 is an equivalent circuit diagram of a first control circuit according to at least one embodiment of the present disclosure. As shown in Figure 8, the first control circuit can be an 8T2C structure, which may include a first control transistor GT1 to an eighth control transistor GT8, a first control capacitor GC1, and a second control capacitor GT2.

[0118] In some examples, as shown in Figure 8, the gate of the first control transistor GT1 is electrically connected to the first clock signal terminal GCK, the first terminal of the first control transistor GT1 is connected to the first cascade input terminal GIN, and the second terminal of the first control transistor GT1 is electrically connected to the first control node GN1. The gate of the second control transistor GT2 is electrically connected to the first control node N1, the first terminal of the second control transistor GT2 is electrically connected to the first clock signal terminal GCK, and the second terminal of the second control transistor GT2 is electrically connected to the second control node GN2. The gate of the third control transistor GT3 is electrically connected to the first clock signal terminal GCK, the first terminal of the third control transistor GT3 is electrically connected to the fourth power supply terminal VGL, and the second terminal of the third control transistor GT3 is electrically connected to the second control node GN2. The gate of the fourth control transistor GT4 is electrically connected to the second control node GN2, the first terminal of the fourth control transistor GT4 is electrically connected to the third power supply terminal VGH, and the second terminal of the fourth control transistor GT4 is electrically connected to the first cascade output terminal GOUT. The gate of the fifth control transistor GT5 is electrically connected to the third control node GN3. The first electrode of the fifth control transistor GT5 is electrically connected to the second clock signal terminal GCB, and the second electrode of the fifth control transistor GT5 is electrically connected to the first cascade output terminal GOUT. The gate of the sixth control transistor GT6 is electrically connected to the second control node GN2. The first electrode of the sixth control transistor GT6 is electrically connected to the third power supply terminal VGH, and the second electrode of the sixth control transistor GT6 is electrically connected to the first electrode of the seventh control transistor GT7. The gate of the seventh control transistor GT7 is electrically connected to the second clock signal terminal GCB, and the second electrode of the seventh control transistor GT7 is electrically connected to the first control node GN1. The gate of the eighth control transistor GT8 is electrically connected to the fourth power supply terminal VGL. The first electrode of the eighth control transistor GT8 is electrically connected to the first control node GN1, and the second electrode of the eighth control transistor GT8 is electrically connected to the third control node GN3. The first electrode of the first control capacitor GC1 is electrically connected to the second control node GN2, and the second electrode of the first control capacitor GC1 is electrically connected to the third power supply terminal VGH. The first electrode of the second control capacitor GC2 is electrically connected to the third control node GN3, and the second electrode of the second control capacitor GC2 is electrically connected to the first cascaded output terminal GOUT.

[0119] In some examples, the third power supply terminal VGH is configured to provide a third power supply signal, and the fourth power supply terminal VGL is configured to provide a fourth power supply signal. The first clock signal terminal GCK can be configured to provide a first clock signal, and the second clock signal terminal GCB can be configured to provide a second clock signal.

[0120] Figure 9 is an equivalent circuit diagram of the second control circuit according to at least one embodiment of the present disclosure. As shown in Figure 9, the second control circuit can be an 8T3C structure, such as including the first light-emitting control transistor ET1 to the seventh light-emitting control transistor ET7, and the first light-emitting control capacitor EC1 to the third light-emitting control capacitor EC3.

[0121] In some examples, as shown in Figure 9, the gate of the first LED control transistor ET1 is electrically connected to the third clock signal terminal ECK, the first terminal of the first LED control transistor ET1 is electrically connected to the second cascade input terminal EIN, and the second terminal of the first LED control transistor ET1 is electrically connected to the first LED control node EN1. The gate of the second LED control transistor ET2 is electrically connected to the fourth power supply terminal VGL, the first terminal of the second LED control transistor ET2 is electrically connected to the first LED control node EN1, and the second terminal of the second LED control transistor ET2 is electrically connected to the second LED control node EN2. The gate of the third LED control transistor ET3 is electrically connected to the second LED control node EN2, the first terminal of the third LED control transistor ET3 is electrically connected to the fourth power supply terminal VGL, and the second terminal of the third LED control transistor ET3 is electrically connected to the second cascade output terminal EOUT. The gate of the fourth LED control transistor ET4 is electrically connected to the third LED control node EN3, the first terminal of the fourth LED control transistor ET4 is electrically connected to the third power supply terminal VGH, and the second terminal of the fourth LED control transistor ET4 is electrically connected to the second cascade output terminal EOUT. The gates of the first fifth light-emitting control transistor ET5a and the second fifth light-emitting control transistor ET5b are both electrically connected to the fourth light-emitting control node EN4. The first electrode of the second fifth light-emitting control transistor ET5b is electrically connected to the third light-emitting control node EN3, and the second electrode of the second fifth light-emitting control transistor ET5b is electrically connected to the first electrode of the first fifth light-emitting control transistor ET5a. The second electrode of the first fifth light-emitting control transistor ET5a is electrically connected to the first electrode of the first light-emitting control capacitor EC1. The second electrode of the first light-emitting control capacitor EC1 is electrically connected to the fourth light-emitting control node EN4. The gate of the sixth light-emitting control transistor ET6 is electrically connected to the first light-emitting control node EN1. The first electrode of the sixth light-emitting control transistor ET6 is electrically connected to the third power supply terminal VGH, and the second electrode of the sixth light-emitting control transistor ET6 is electrically connected to the third light-emitting control node EN3. The gate of the seventh light-emitting control transistor ET7 is electrically connected to the second cascade input terminal EIN. The first electrode of the seventh light-emitting control transistor ET7 is electrically connected to the third power supply terminal VGH, and the second electrode of the seventh light-emitting control transistor ET7 is electrically connected to the fourth light-emitting control node EN4. The first electrode of the second light-emitting control capacitor EC2 is electrically connected to the third power supply terminal VGH, and the second electrode of EC2 is electrically connected to the third light-emitting control node EN3. The first electrode of the third light-emitting control capacitor EC3 is electrically connected to the second light-emitting control node EN2, and the second electrode of EC3 is electrically connected to the second cascaded output terminal EOUT. In some examples, the third clock signal terminal ECK is configured to provide a third clock signal.

[0122] In some examples, as shown in Figure 7, the second circuit device 33 can integrate a first control circuit 12 and a second control circuit 13. A single first control circuit 12 can connect to six signal terminals, including: a third power supply terminal VGH, a fourth power supply terminal VGL, a first cascade input terminal GIN, a first clock signal terminal GCK, a second clock signal terminal GCB, and a first cascade output terminal GOUT. The first cascade output terminal GOUT can be connected to a scan terminal of the first circuit device. The six signal terminals can include: five input signal terminals (i.e., including the third power supply terminal VGH, the fourth power supply terminal VGL, the first cascade input terminal GIN, the first clock signal terminal GCK, and the second clock signal terminal GCB) and one output signal terminal (i.e., the first cascade output terminal GOUT).

[0123] In some examples, as shown in Figure 7, a single second control circuit 13 can be connected to five signal terminals, including: a third power supply terminal VGH, a fourth power supply terminal VGL, a second cascade input terminal EIN, a third clock signal terminal ECK, and a second cascade output terminal EOUT. The second cascade output terminal EOUT can be connected to the light-emitting control terminal of the first circuit device. The five signal terminals can include: four input signal terminals (i.e., including the third power supply terminal VGH, the fourth power supply terminal VGL, the second cascade input terminal EIN, and the third clock signal terminal ECK) and one output signal terminal (i.e., the second cascade output terminal EOUT).

[0124] In some examples, as shown in Figure 7, the first control circuit 12 and the second control circuit 13 can share the third power supply terminal VGH and the fourth power supply terminal VGL. When the second circuit device 33 integrates one first control circuit 12 and one second control circuit 13, the number of connection pads in the second connection pad layer of the second circuit device 33 is Q = 9. These nine connection pads can be connected one-to-one with nine signal terminals (including the third power supply terminal VGH, the fourth power supply terminal VGL, the first cascade input terminal GIN, the first clock signal terminal GCK, the second clock signal terminal GCB, the third clock signal terminal ECK, the second cascade input terminal EIN, the first cascade output terminal GOUT, and the second cascade output terminal EOUT). The first cascade input terminal GIN connected to the first control circuit 12 can be connected to the first start terminal GSTV, and the second cascade input terminal EIN connected to the second control circuit 13 can be connected to the second start terminal ESTV. The nine connection pads of the second circuit device 33 can include seven second input signal connection pads and two second output signal connection pads. In this example, S = 7 and T = 2. The two second output signal connection pads can be connected one-to-one with a first cascade output terminal GOUT and a second cascade output terminal EOUT.

[0125] In some examples, as shown in Figure 7, the second circuit device 33 can integrate M cascaded first control circuits 12 and one second control circuit 13. In this example, R = 1. In the M cascaded first control circuits 12, the first cascade input terminal EIN of the first-stage first control circuit can be connected to the first start terminal GSTV, and the first cascade input terminals of the other stages of first control circuits can be connected to the first cascade output terminal of the previous stage first control circuit. The M cascaded first control circuits 12 can output M levels of scan signals, which can be provided to the first circuit device as scan signals or reset control signals. For example, each scan signal can be provided to one scan terminal of the first circuit device. The second cascade input terminal EIN of the second control circuit 13 can be connected to the second start terminal ESTV, and the light emission control signal output by the second cascade output terminal EOUT can be provided to the light emission control terminal of the first circuit device. The timing of the light emission control signal output by the second cascade output terminal EOUT can ensure that at least one row of driver sub-circuits generates a drive signal only after ensuring that the reset, compensation, and data writing stages of all driver sub-circuits in the row are completed.

[0126] In some examples, the number of connection pads for the second circuit device 33, which integrates M first control circuits 12 and one second control circuit 13, is Q = M + 8. These Q connection pads can be connected one-to-one with M first cascaded outputs GOUT, one second cascaded output EOUT, one third power supply VGH, one fourth power supply VGL, one first start terminal GSTV, one first clock signal terminal GCK, one second clock signal terminal GCB, one third clock signal terminal ECK, and one second start terminal ESTV. The Q connection pads may include M + 1 second output signal connection pads and 7 second input signal connection pads. In this example, S = 7, T = M + 1.

[0127] In other examples, when the second circuit device integrates M cascaded first control circuits 12 and R cascaded second control circuits 13, the number of connection pads in the second circuit device is Q = M + R + 7. Specifically, in the M cascaded first control circuits 12, the first cascade input of the first-stage first control circuit can be connected to the first starting terminal GSTV, and the first cascade input of the remaining stages of the first control circuit (excluding the first-stage first control circuit) can be connected to the first cascade output of the preceding stage's first control circuit. In the R cascaded second control circuits 13, the second cascade input of the first-stage second control circuit can be connected to the second starting terminal ESTV, and the second cascade input of the remaining stages of the second control circuit (excluding the first-stage second control circuit) can be connected to the second cascade output of the preceding stage's second control circuit. The Q connection pads of the second circuit device can be connected one-to-one with M first cascaded outputs, R second cascaded outputs, a third power supply terminal VGH, a fourth power supply terminal VGL, a first start terminal GSTV, a first clock signal terminal GCK, a second clock signal terminal GCB, a third clock signal terminal ECK, and a second start terminal ESTV.

[0128] Figure 10 is a schematic diagram of the architecture of the second circuit layer of a second circuit device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 10, the second circuit device 33 may include twelve cascaded first control circuits 12 and one second control circuit 13. The twelve cascaded first control circuits 12 may be arranged in a two-row, six-column array. Each row of first control circuits 12 may include six first control circuits 12 arranged sequentially along the row direction X2, and each column of first control circuits 12 may include two first control circuits 12 arranged sequentially along the column direction Y2. The second control circuit 13 may be located on the same side of the twelve first control circuits 12 along the row direction X2. For example, it may be aligned with the first row of first control circuits in the row direction X2. In this example, the number Q of the connection pads of the second circuit device 33 may be 20.

[0129] In some examples, as shown in Figure 10, twelve cascaded first control circuits 12 can be connected to the same third power supply terminal VGH, fourth power supply terminal VGL, first clock signal terminal GCK, and second clock signal terminal GCB. The first cascade input terminal of the first-stage first control circuit can be connected to the first start terminal GSTV. The first cascade output terminal of each stage of the first control circuit can be connected to the first cascade input terminal of the next stage of the first control circuit. For example, the first cascade output terminal GOUT1 of the first-stage first control circuit can be connected to the first cascade input terminal of the second-stage first control circuit. The twelve first control circuits 12 can be connected one-to-one with the twelve first cascade output terminals GOUT1 to GOUT12. Each first cascade output terminal can be configured to be connected to a scan terminal of the first circuit device. The second cascade output terminal EOUT of the second control circuit 13 can be configured to be connected to the light-emitting control terminal of the first circuit device.

[0130] In some examples, the first cascade output of the last stage of the first control circuit of a second circuit device 33 (e.g., the first cascade output GOUT12 of the 12th stage first control circuit) can be connected to the first starting terminal of the next second circuit device in a cascade relationship, and the second cascade output of a second circuit device can be connected to the second starting terminal of the next second circuit device in a cascade relationship. In this way, the cascade relationship of the first control circuits among multiple second circuit devices, as well as the cascade relationship of the second control circuits, can be guaranteed.

[0131] The fabrication process of the second circuit device can be referred to the fabrication process of the first circuit device mentioned above, so it will not be repeated here.

[0132] This embodiment also provides an apparatus, including: a circuit board, a plurality of components disposed on the circuit board, and at least one of the following: a plurality of first circuit devices and a plurality of second circuit devices. The circuit board has multiple traces, including: first type traces and second type traces. One first circuit device is connected to N components through N first type traces; at least one second circuit device is connected to the first circuit device through a second type trace.

[0133] In some examples, the apparatus may include a circuit board and a plurality of components, a plurality of first circuit devices and a plurality of second circuit devices disposed on the circuit board; or, it may include a circuit board and a plurality of components and a plurality of first circuit devices disposed on the circuit board; or, it may include a circuit board and a plurality of components and a plurality of second circuit devices disposed on the circuit board.

[0134] This example demonstrates how bonding a first circuit device integrating a driver sub-circuit and a second circuit device integrating a control circuit on a circuit board can reduce the number of cascaded circuit devices, thereby avoiding display defects caused by cascading anomalies.

[0135] Figure 11 is a schematic diagram of an apparatus according to at least one embodiment of the present disclosure. Figure 12 is a schematic diagram of the structure of the first region according to at least one embodiment of the present disclosure.

[0136] In some examples, as shown in Figures 11 and 12, the device may include a first region AA and a second region surrounding the first region AA. The device may include a circuit board 30 and first circuit devices 31, second circuit devices 33, and light-emitting devices 32 disposed on the circuit board 30. Multiple first circuit devices 31 and multiple light-emitting devices 32 may be located in the first region AA, and multiple second circuit devices 33 may be located in the second region.

[0137] In some examples, as shown in Figure 12, the first circuit device 31 within the first region AA can be arranged in an array along a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can be parallel to the plane of the circuit board 30, and the first direction D1 intersects the second direction D2; for example, the first direction D1 can be perpendicular to the second direction D2. Taking a first circuit device 31 comprising 12 driving sub-circuits as an example, the first circuit device 31 can be located at the center of the four connected light-emitting devices 32, and the four light-emitting devices 32 can be located at the four corners of the connected first circuit device 31.

[0138] In some examples, each light-emitting device 32 may include a light-emitting element emitting a first color light, a light-emitting element emitting a second color light, and a light-emitting element emitting a third color light. The first color light may be red light, the second color light may be green light, and the third color light may be blue light. For example, the light-emitting device 32 may include a blue LED, and red and green quantum dot materials located above a portion of the blue LED. The blue light emitted by the blue LED passes through the quantum dot film, and part of the blue light can be converted into red and green light. The unconverted blue light can be mixed with the red and green light emitted by the quantum dot film to form high-quality white light, thereby improving the color gamut and color performance of the device.

[0139] In some examples, as shown in Figure 12, the circuit board 30 may be provided with a first type of trace 351, a second type of trace 352, multiple first pad groups, and multiple second pad groups. Each first pad group may include P first pads that are connected one-to-one with P connection pads of the first circuit device 31, and each second pad group may include multiple second pads. A single light-emitting device 32 may be connected to a single second pad group. The arrangement of the multiple first pads within a single first pad group may correspond to the arrangement of the multiple connection pads of the first circuit device 31 to achieve corresponding signal transmission.

[0140] In some examples, the first circuit device 31 can be connected to N light-emitting elements through N first-type traces 351 to drive the N light-emitting elements. For example, the first pad connected to the first circuit device 31 can be connected to the corresponding second pad through the first-type traces 351 to realize the electrical connection between the first circuit device 31 and the light-emitting elements.

[0141] In some examples, the first circuit device 31 can be connected to the second circuit device 33 via a second type trace 352. For example, the second type trace 352 can extend along a first direction D1. One scanning terminal of a row of first circuit devices 31 can be connected to a first cascade output terminal of the second circuit device 33 via a single second type trace 352, and the light emission control terminal of a row of first circuit devices 31 can be connected to a second cascade output terminal of the second circuit device 33 via another second type trace 352. In other examples, one scanning terminal of a single first circuit device 31 can be connected to a first cascade output terminal of the second circuit device 33 via a single second type trace.

[0142] In some examples, as shown in Figure 11, the second regions on both sides of the first region AA along the first direction D1 can be respectively provided with a first group of second circuit devices and a second group of second circuit devices. Each group of second circuit devices can include multiple second circuit devices 33 cascaded together. The multiple second circuit devices 33 in each group of second circuit devices can be arranged sequentially along the second direction D2, for example. The circuit board 30 can also be provided with a third type of trace 353, through which second circuit devices with a cascaded relationship can be connected. For example, the first cascaded output terminal of the last stage first control circuit in a second circuit device 33 can be connected to the first starting terminal GSTV of the next cascaded second circuit device 33 through a third type of trace 353, and the second cascaded output terminal of the last stage second control circuit in a second circuit device 33 can be connected to the second starting terminal ESTV of the next cascaded second circuit device 33 through a third type of trace 353.

[0143] For example, one or a row of first circuit devices 31 can be connected to the same level of second circuit devices in the first group and the second group of second circuit devices to achieve bilateral driving. When the output of one group of second circuit devices is abnormal, the other group of second circuit devices can guarantee the output, thereby ensuring the driving effect of the device. The setup method in this example can improve the driving reliability and effectiveness of the device and ensure the display effect.

[0144] In other examples, where the second control circuit is not included in the second circuit device, the second control circuit shown in Figure 9 can be directly fabricated on the circuit board using semiconductor technology, or integrated into other circuit devices and then fixedly connected to the circuit board by bonding. In other examples, the second control circuit shown in Figure 9 can be omitted, and a row driver can be used directly to select the row to be updated, typically refreshing the entire first area in a cyclic manner. That is, every N elements form a repeating unit, and the repeating units are arranged in an array. Repeating units in the same row are updated at the same time and receive the same light-emitting control signal.

[0145] Figure 13 is another schematic diagram of a device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 13, the device may include two first regions AA1 and AA2. The light-emitting device and the first circuit device may be located in the first regions AA1 and AA2; the second circuit device 33 may be located in the second regions on both sides of the first region AA1 along the first direction D1, and perform bilateral driving on the first circuit device in the first region AA1, or it may be located in the second regions on both sides of the first region AA2 along the first direction D1, and perform bilateral driving on the first circuit device in the first region AA2. In this example, the second region may be provided with four sets of second circuit devices, two sets of second circuit devices may be located on both sides of the first region AA1 along the first direction D1, and the other two sets of second circuit devices may be located on both sides of the first region AA2 along the first direction D1.

[0146] This example further reduces the area of ​​display abnormalities caused by poor cascading of the control circuit by arranging the light-emitting device and the first circuit device in separate regions and driving the first circuit device in each region on both sides. Further descriptions of the apparatus in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0147] In some examples, the active layer dimensions of the output transistors within the first control circuit (e.g., including the fourth control transistor GT4 and the fifth control transistor GT5 shown in Figure 8) need to support a load greater than or equal to twice the scan signal to ensure that the second circuit devices on the other side can maintain their driving effect when one side of the second circuit device malfunctions. Similarly, the active layer dimensions of the output transistors within the second control circuit (e.g., including the third light-emitting control transistor ET3 and the fourth light-emitting control transistor ET4 shown in Figure 9) need to support a load greater than or equal to twice the scan signal to ensure that the second circuit devices on the other side can maintain their driving effect when one side of the second circuit device malfunctions.

[0148] Figure 14 is another schematic diagram of an apparatus according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 14, at least one group of second circuit devices includes: a plurality of cascaded second circuit device subgroups 330, at least one second circuit device subgroup 330 including: a first type of second circuit device 33a and a second type of second circuit device 33b. The first type of second circuit device 33a and the second type of second circuit device 32b in the first-level second circuit device subgroup 330 are connected to the second type of second circuit device 32b in the previous-level second circuit device subgroup 330 through a third type of trace 353; the first type of second circuit device 33a in the first-level second circuit device subgroup 330 is connected to at least one first circuit device in the first region AA through a second type of trace 352. The second type of second circuit device 33b may be configured to provide cascaded signals (e.g., including a first cascaded signal provided to a first control circuit and a second cascaded signal provided to a second control circuit) to the next-level second circuit device subgroup 330. The first cascade signal provided by the second type of second circuit device 33b can be configured to be transmitted to the first start terminal GSTV of the first type of second circuit device and the second type of second circuit device within the next-level second circuit device subgroup 330. The second cascade signal provided by the second type of second circuit device 33b can be configured to be transmitted to the second start terminal ESTV of the first type of second circuit device and the second type of second circuit device within the next-level second circuit device subgroup 330. For example, the first-level second circuit device subgroup 330 can receive the first cascade signal by connecting the first start signal line GSTVL, and can also receive the second cascade signal by connecting the second start signal line ESTVL.

[0149] In some examples, the structures of the first type of second circuit device 33a and the second type of second circuit device 33b can be identical, for example, referring to the structure of the second circuit device in the foregoing embodiment. In another example, the size of the active layer of the output transistor of the first control circuit in the first type of second circuit device 33a (e.g., including the fourth control transistor GT4 and the fifth control transistor GT5 shown in FIG. 8) can be larger than the size of the active layer of the output transistor of the first control circuit in the second type of second circuit device 33b; the size of the active layer of the output transistor of the second control circuit in the first type of second circuit device 33a (e.g., including the third light-emitting control transistor ET3 and the fourth light-emitting control transistor ET4 shown in FIG. 9) can be larger than the size of the active layer of the output transistor of the second control circuit in the second type of second circuit device 33b. The arrangement in this example can ensure the validity of the driving signal.

[0150] In some examples, when a certain level of second circuit device subgroup 330 malfunctions, the second type of second circuit device 33b within that subgroup 330 can still generate cascaded signals normally. This results in only the light-emitting devices connected to the first circuit device driven by the first type of second circuit device 33a of that subgroup 330 experiencing display defects, without affecting the display effect of other light-emitting devices. This example can further improve the driving reliability and effectiveness of the device, effectively ensuring display quality. Further descriptions of the device in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0151] The following examples, using the five examples shown in Table 1, illustrate various scenarios in which the first circuit device drives the light-emitting element.

[0152] Figure 15 is a schematic diagram of the arrangement of the light-emitting elements driven by the first circuit device in Example 1. Figure 15 illustrates the connection relationship between the first circuit device, the light-emitting elements, and the second circuit device within a device. The area outlined by the dashed line in Figure 15 represents a repeating unit; multiple repeating units can be arranged in an array within the first region of the device. Figure 16 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 1. Figure 17 is a schematic diagram of the operating timing of the first circuit device in Example 1.

[0153] In some examples, as shown in Figure 15, a first circuit device 31 within the device can be configured to drive four pixel units arranged in a two-row, two-column array. The row direction of the pixel units can be parallel to a first direction D1, and the column direction of the pixel units can be parallel to a second direction D2. Each pixel unit can include three light-emitting elements that emit light of different colors. For example, the first pixel unit includes light-emitting elements R1, G1, and B1; the second pixel unit includes light-emitting elements R2, G2, and B2; the third pixel unit includes light-emitting elements R3, G3, and B3; and the fourth pixel unit includes light-emitting elements R4, G4, and B4. Light-emitting elements R1, R2, R3, and R4 are configured to emit light of the same color, such as red light; light-emitting elements G1, G2, G3, and G4 are configured to emit light of the same color, such as green light; and light-emitting elements B1, B2, B3, and B4 are configured to emit light of the same color, such as blue light.

[0154] In some examples, as shown in Figures 15 and 16, the first circuit device 31 may include twelve driving sub-circuits 11 and two multiplexing circuits 14. The twelve driving sub-circuits 11 can be arranged in a two-row, six-column array. Each row of driving sub-circuits can be connected to the same scanning terminal; for example, the first row of driving sub-circuits can be connected to scanning terminal GL1, and the second row of driving sub-circuits can be connected to scanning terminal GL2. Each row of driving sub-circuits can be configured to receive the same scanning signal. Each column of driving sub-circuits can be configured to receive the same data signal. The fourth pixel node of each of the twelve driving sub-circuits 11 can be connected one-to-one with the twelve anode connection terminals AN1 to AN12. The two multiplexing circuits 14, under the control of three gating control terminals ML1, ML2, and ML3, can convert the two data signals provided by the two data terminals DL1 and DL2 into six data signals. For example, the two driving sub-circuits 11 in the same column can be configured to receive the same data signal. This example does not limit the arrangement of the driving sub-circuits within the first circuit device.

[0155] In some examples, as shown in Figure 15, when the repeating units outlined in the dashed box are arranged in an array along the first direction D1 and the second direction D2, the scanning terminal GL1 of the first circuit device 31 located in the same row can be configured to receive the same scanning signal, for example, connected to the first cascaded output terminal GOUT1 of the second circuit device 33 through the same second type of trace 352; the scanning terminal GL2 of the first circuit device 31 located in the same row can be configured to receive the same scanning signal, for example, connected to the first cascaded output terminal GOUT2 of the second circuit device 33 through the same second type of trace 352; the light emission control terminal EM of the first circuit device 31 located in the same row can be configured to receive the same light emission control signal, for example, connected to the second cascaded output terminal EOUT of the second circuit device 33 through the same second type of trace 352. The gating control terminal ML1 of the first circuit device 31 located in the same row can be configured to receive the same gating control signal, such as being connected to the same Class 4 trace 354; the gating control terminal ML2 of the first circuit device 31 located in the same row can be configured to receive the same gating control signal, such as being connected to the same Class 4 trace 354; the gating control terminal ML3 of the first circuit device 31 located in the same row can be configured to receive the same gating control signal, such as being connected to the same Class 4 trace 354. The data terminal DL1 of the first circuit device 31 located in the same column can be configured to receive the same data signal, for example, connected to the same Class 4 trace 354; the data terminal DL2 of the first circuit device 31 located in the same column can be configured to receive the same data signal, for example, connected to the same Class 4 trace 354; the first power terminal VDD of the first circuit device 31 located in the same column can be connected to the same Class 4 trace 354 to receive the first power signal; the initial signal terminal INIT of the first circuit device 31 located in the same column can be connected to the same Class 4 trace 354 to receive the initial signal.

[0156] In some examples, as shown in Figures 15 and 16, the twelve anode connection terminals AN1 to AN12 of the first circuit device 31 can be connected one-to-one with the twelve light-emitting elements via twelve first-class traces 351 on the circuit board. Anode connection terminal AN1 of the first circuit device 31 can be connected to light-emitting element R1, anode connection terminal AN2 can be connected to light-emitting element G1, anode connection terminal AN3 can be connected to light-emitting element B1; anode connection terminal AN4 can be connected to light-emitting element R2, anode connection terminal AN5 can be connected to light-emitting element G2, anode connection terminal AN6 can be connected to light-emitting element B2; anode connection terminal AN7 can be connected to light-emitting element R3, anode connection terminal AN8 can be connected to light-emitting element G3, anode connection terminal AN9 can be connected to light-emitting element B3; anode connection terminal AN10 can be connected to light-emitting element R4, anode connection terminal AN11 can be connected to light-emitting element G4, and anode connection terminal AN12 can be connected to light-emitting element B4.

[0157] In some examples, as shown in Figure 17, when the first circuit device 31 drives twelve light-emitting elements, the scanning terminals GL1 and GL2 can receive valid level signals (e.g., low-level signals, configured to turn on the fourth pixel transistor PT4 shown in Figure 2) in a time-division multiplexing manner according to a timing sequence. During the duration of the valid level signal received by the scanning terminal GL1, the gating control terminals ML1, ML2, and ML3 receive valid level signals (e.g., low-level signals, configured to turn on the corresponding connected multiplexing control transistors) in a time-division multiplexing manner, and the data terminals DL1 and DL2 transmit driving data simultaneously. Specifically, when the scanning terminal GL1 receives a valid level signal and the gating control terminal ML1 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element R1. R1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element R2. R2 When the scanning terminal GL1 receives a valid level signal and the gating control terminal ML2 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element G1. G1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element G2. G2 When the scanning terminal GL1 receives a valid level signal and the gating control terminal ML3 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element B1. B1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element B2. B2 .

[0158] In some examples, as shown in Figure 17, during the duration of the valid level signal received by the scanning end GL2, the gating control ends ML1, ML2, and ML3 receive the valid level signal in a time-division manner, while the data ends DL1 and DL2 simultaneously transmit driving data. Specifically, when both the scanning end GL2 and the gating control end ML1 receive the valid level signal, the data end DL1 transmits the driving data D corresponding to the light-emitting element R3. R3 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element R4. R4 When the scanning terminal GL2 receives a valid level signal and the gating control terminal ML2 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element G3. G3 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element G4. G4 When the scanning terminal GL2 receives a valid level signal and the gating control terminal ML3 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element B3. B3 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element B4. B4 .

[0159] In some examples, as shown in Figure 17, when the light-emitting control terminal EM receives a valid level signal, the twelve light-emitting elements R1, B1, G1, R2, G2, B2, R3, G3, B3, R4, G4, and B4 are simultaneously illuminated, emitting light of a specific grayscale. Further descriptions of the apparatus, first circuit device, second circuit device, and light-emitting elements in this example can be found in the descriptions of the foregoing embodiments, and therefore will not be repeated here.

[0160] Figure 18 is a schematic diagram of the arrangement of the light-emitting elements driven by the first circuit device in Example 2. Figure 19 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 2. Figure 20 is a schematic diagram of the operating timing of the first circuit device in Example 2.

[0161] In some examples, as shown in Figures 18 to 20, the first circuit device 31 may include twelve driving sub-circuits 11 and three multiplexing circuits 14. The twelve driving sub-circuits 11 may be arranged in a two-row, six-column array. Each row of driving sub-circuits may be connected to the same scan terminal and configured to receive the same scan signal. Each column of driving sub-circuits may be configured to receive the same data signal. The fourth pixel node of each of the twelve driving sub-circuits 11 may be connected one-to-one with the twelve anode connection terminals AN1 to AN12. The twelve anode connection terminals AN1 to AN12 of the first circuit device 31 may be connected one-to-one with the twelve light-emitting elements via twelve first-class traces 351 on the circuit board. Each multiplexing circuit 14 may include two multiplexed control transistors, the gates of which are connected to different gating control terminals. The first terminal of each multiplexed control transistor is connected to a data terminal, and the second terminal is connected to one driving sub-circuit.

[0162] In some examples, as shown in Figure 20, when the first circuit device 31 drives twelve light-emitting elements, the scanning terminals GL1 and GL2 can receive valid level signals in a time-division manner according to a timing sequence. During the time that the scanning terminal GL1 receives the valid level signal, the gating control terminals ML1 and ML2 receive the valid level signal in a time-division manner, and the data terminals DL1, DL2, and DL3 simultaneously transmit driving data. Specifically, when the scanning terminal GL1 receives the valid level signal and the gating control terminal ML1 receives the valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element R1. R1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element B1. B1 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element G2. G2 When the scanning terminal GL1 receives a valid level signal and the gating control terminal ML2 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element G1. G1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element R2. R2 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element B2. B2 .

[0163] In some examples, as shown in Figure 20, during the duration of the valid level signal received by the scanning end GL2, the gating control ends ML1 and ML2 receive the valid level signal in a time-sharing manner, while the data ends DL1, DL2, and DL3 simultaneously transmit driving data. Specifically, when both the scanning end GL2 and the gating control end ML1 receive the valid level signal, the data end DL1 transmits the driving data D corresponding to the light-emitting element R3. R3 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element B3. B3 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element G4.G4 When the scanning terminal GL2 receives a valid level signal and the gating control terminal ML2 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element G3. G3 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element R4. R4 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element B4. B4 .

[0164] In some examples, as shown in Figure 20, when the light-emitting control terminal EM receives a valid level signal, all twelve light-emitting elements R1, B1, G1, R2, G2, B2, R3, G3, B3, R4, G4, and B4 are simultaneously illuminated, emitting light of a specific grayscale. Further details regarding this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0165] Figure 21 is a schematic diagram of the arrangement of the light-emitting elements driven by the first circuit device in Example 3. Figure 22 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 3. Figure 23 is a schematic diagram of the operating timing of the first circuit device in Example 3.

[0166] In some examples, as shown in Figures 21 to 23, the first circuit device 31 may include twelve driving sub-circuits 11 and two multiplexing circuits 14. The twelve driving sub-circuits 11 may be arranged in a three-row, four-column array. Each row of driving sub-circuits may be connected to the same scan terminal and configured to receive the same scan signal. Each column of driving sub-circuits may be configured to receive the same data signal. The fourth pixel node of each of the twelve driving sub-circuits 11 may be connected one-to-one with the twelve anode connection terminals AN1 to AN12. Each multiplexing circuit 14 may include two multiplexing control transistors, the gates of which are connected to different gating control terminals. The first terminal of each multiplexing control transistor is connected to a data terminal, and the second terminal is connected to one driving sub-circuit.

[0167] In some examples, the twelve anode terminals AN1 to AN12 of the first circuit device 31 can be connected one-to-one with the twelve light-emitting elements via twelve first-class traces 351 on the circuit board. For example, anode terminal AN1 of the first circuit device 31 can be connected to light-emitting element R1, anode terminal AN2 can be connected to light-emitting element R2, anode terminal AN3 can be connected to light-emitting element R3; anode terminal AN4 can be connected to light-emitting element R4, anode terminal AN5 can be connected to light-emitting element G1, anode terminal AN6 can be connected to light-emitting element G2; anode terminal AN7 can be connected to light-emitting element G3, anode terminal AN8 can be connected to light-emitting element G4, anode terminal AN9 can be connected to light-emitting element B1; anode terminal AN10 can be connected to light-emitting element B2, anode terminal AN11 can be connected to light-emitting element B3, and anode terminal AN12 can be connected to light-emitting element B4.

[0168] In some examples, as shown in Figure 23, when the first circuit device 31 drives twelve light-emitting elements, the scanning terminals GL1, GL2, and GL3 can receive valid level signals in a time-division manner according to a timing sequence. During the duration during which the scanning terminal GL1 receives the valid level signal, the gating control terminals ML1 and ML2 receive the valid level signal in a time-division manner, while the data terminals DL1 and DL2 simultaneously transmit driving data. Specifically, when both the scanning terminal GL1 and the gating control terminal ML1 receive the valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element R1. R1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element R3. R3 When the scanning terminal GL1 receives a valid level signal and the gating control terminal ML2 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element R2. R2 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element R4. R4 .

[0169] In some examples, as shown in Figure 23, during the duration of the valid level signal received by the scanning end GL2, the gating control ends ML1 and ML2 receive the valid level signal in a time-sharing manner, while the data ends DL1 and DL2 simultaneously transmit driving data. Specifically, when both the scanning end GL2 and the gating control end ML1 receive the valid level signal, the data end DL1 transmits the driving data D corresponding to the light-emitting element G1. G1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element G3. G3 When the scanning terminal GL2 receives a valid level signal and the gating control terminal ML2 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element G2. G2 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element G4.G4 .

[0170] In some examples, as shown in Figure 23, during the duration of the valid level signal received by the scanning end GL3, the gating control ends ML1 and ML2 receive the valid level signal in a time-division manner, while the data ends DL1 and DL2 simultaneously transmit driving data. Specifically, when both the scanning end GL3 and the gating control end ML1 receive the valid level signal, the data end DL1 transmits the driving data D corresponding to the light-emitting element B1. B1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element B3. B3 When the scanning terminal GL2 receives a valid level signal and the gating control terminal ML2 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element B2. B2 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element B4. B4 .

[0171] In some examples, as shown in Figure 20, when the light-emitting control terminal EM receives a valid level signal, all twelve light-emitting elements R1, B1, G1, R2, G2, B2, R3, G3, B3, R4, G4, and B4 are simultaneously illuminated, emitting light of a specific grayscale. Further details regarding this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0172] Figure 24 is a schematic diagram of the arrangement of light-emitting elements driven by the first circuit device in Example 4. Figure 25 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 4. Figure 26 is a schematic diagram of the operating timing of the first circuit device in Example 4.

[0173] In some examples, as shown in Figures 24 to 26, the first circuit device 31 may include twelve driving sub-circuits 11, which may be arranged in a three-row, four-column array. Each row of driving sub-circuits may be connected to the same scanning terminal and configured to receive the same scanning signal. Each column of driving sub-circuits may be configured to receive the same data signal. The fourth pixel node of each of the twelve driving sub-circuits 11 may be connected one-to-one with the twelve anode connection terminals AN1 to AN12. The twelve anode connection terminals AN1 to AN12 of the first circuit device 31 may be connected one-to-one with the twelve light-emitting elements through twelve first-type traces 351 on the circuit board. For example, the anode connection terminal AN1 of the first circuit device 31 can be connected to the light-emitting element R1, the anode connection terminal AN2 can be connected to the light-emitting element R2, the anode connection terminal AN3 can be connected to the light-emitting element R3; the anode connection terminal AN4 can be connected to the light-emitting element R4, the anode connection terminal AN5 can be connected to the light-emitting element G1, the anode connection terminal AN6 can be connected to the light-emitting element G2; the anode connection terminal AN7 can be connected to the light-emitting element G3, the anode connection terminal AN8 can be connected to the light-emitting element G4, the anode connection terminal AN9 can be connected to the light-emitting element B1; the anode connection terminal AN10 can be connected to the light-emitting element B2, the anode connection terminal AN11 can be connected to the light-emitting element B3, and the anode connection terminal AN12 can be connected to the light-emitting element B4.

[0174] In some examples, as shown in Figure 26, when the first circuit device 31 drives twelve light-emitting elements, the scanning terminals GL1, GL2, and GL3 can receive valid level signals in a time-division manner according to a timing sequence. When the scanning terminal GL1 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element R1. R1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element R2. R2 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element R3. R3 The data terminal DL4 transmits the driving data D corresponding to the light-emitting element R4. R4 When the scanning end GL2 receives a valid level signal, the data end DL1 transmits the driving data D corresponding to the light-emitting element G1. G1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element G2. G2 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element G3. G3 The data terminal DL4 transmits the driving data D corresponding to the light-emitting element G4. G4 When the scanning end GL3 receives a valid level signal, the data end DL1 transmits the driving data D corresponding to the light-emitting element B1. B1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element B2. B2The data terminal DL3 transmits the driving data D corresponding to the light-emitting element B3. B3 The data terminal DL4 transmits the driving data D corresponding to the light-emitting element B4. B4 When the light-emitting control terminal EM receives a valid level signal, all twelve light-emitting elements R1, B1, G1, R2, G2, B2, R3, G3, B3, R4, G4, and B4 are simultaneously illuminated, emitting light of a specific grayscale. Further details regarding this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0175] Figure 27 is a schematic diagram of the arrangement of light-emitting elements driven by the first circuit device in Example 5. Figure 28 is an example diagram of the architecture of the first circuit layer of the first circuit device in Example 5. Figure 29 is a schematic diagram of the operating timing of the first circuit device in Example 5.

[0176] In some examples, as shown in Figures 27 to 29, the first circuit device 31 may include twelve driving sub-circuits 11, which can be arranged in a four-row, three-column array. Each row of driving sub-circuits can be connected to the same scanning terminal and configured to receive the same scanning signal. Each column of driving sub-circuits can be configured to receive the same data signal. The fourth pixel node of each of the twelve driving sub-circuits 11 can be connected one-to-one with the twelve anode connection terminals AN1 to AN12. The twelve anode connection terminals AN1 to AN12 of the first circuit device 31 can be connected one-to-one with the twelve light-emitting elements through twelve first-type traces 351 on the circuit board. For example, the anode connection terminal AN1 of the first circuit device 31 can be connected to the light-emitting element R1, the anode connection terminal AN2 can be connected to the light-emitting element G1, the anode connection terminal AN3 can be connected to the light-emitting element B1; the anode connection terminal AN4 can be connected to the light-emitting element R2, the anode connection terminal AN5 can be connected to the light-emitting element G2, the anode connection terminal AN6 can be connected to the light-emitting element B2; the anode connection terminal AN7 can be connected to the light-emitting element R3, the anode connection terminal AN8 can be connected to the light-emitting element G3, the anode connection terminal AN9 can be connected to the light-emitting element B3; the anode connection terminal AN10 can be connected to the light-emitting element R4, the anode connection terminal AN11 can be connected to the light-emitting element G4, and the anode connection terminal AN12 can be connected to the light-emitting element B4.

[0177] In some examples, as shown in Figure 29, when the first circuit device 31 drives twelve light-emitting elements, the scanning terminals GL1, GL2, GL3, and GL4 can receive valid level signals in a time-division manner according to the timing sequence. When the scanning terminal GL1 receives a valid level signal, the data terminal DL1 transmits the driving data D corresponding to the light-emitting element R1. R1 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element RG1. G1 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element B1.B1 When the scanning end GL2 receives a valid level signal, the data end DL1 transmits the driving data D corresponding to the light-emitting element R2. R2 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element G2. G2 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element B2. B2 When the scanning end GL3 receives a valid level signal, the data end DL1 transmits the driving data D corresponding to the light-emitting element R3. R3 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element G3. G3 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element B3. B3 When the scanning end GL4 receives a valid level signal, the data end DL1 transmits the driving data D corresponding to the light-emitting element R4. R4 The data terminal DL2 transmits the driving data D corresponding to the light-emitting element G4. G4 The data terminal DL3 transmits the driving data D corresponding to the light-emitting element B4. B4 When the light-emitting control terminal EM receives a valid level signal, all twelve light-emitting elements R1, B1, G1, R2, G2, B2, R3, G3, B3, R4, G4, and B4 are simultaneously illuminated, emitting light of a specific grayscale. Further details regarding this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0178] Referring to the descriptions of Examples 1 to 5, the number of connection pads P of the first circuit device in this example is minimized, which can satisfy the driving of light-emitting elements with various arrangements and ensure display effect. The arrangement of the driving sub-circuit within the first circuit device in Examples 1 to 5 is not limited, as long as the aforementioned signal transmission relationship is satisfied.

[0179] In this embodiment, the driving sub-circuit is integrated into the first circuit device, and the control circuit is integrated into the second circuit device. The first and second circuit devices are bonded together on the circuit board. The scanning signal and light emission control signal generated by the second circuit device can be used to provide timing drive for the first circuit device, and the driving signal generated by the first circuit device can drive the light-emitting element. Compared with the implementation method of integrating the driving sub-circuit and the control circuit into the same circuit device, this example can greatly reduce the number of cascaded circuit devices integrated on the circuit board, thereby effectively reducing display defects caused by cascading anomalies and effectively improving the reliability of the device. Moreover, the arrangement of this embodiment can help reduce the area of ​​a single circuit device and reduce costs.

[0180] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0181] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A first circuit device for providing drive signals to N components, comprising: First insulating substrate; A first circuit layer is disposed on the first insulating substrate. The first circuit layer includes N driving sub-circuits, which are arranged in a B×A array, where N = A×B, and A and B are both positive integers greater than 0. A first connection pad layer is located on the side of the first circuit layer away from the first insulating substrate, and the surface of the first connection pad layer away from the first insulating substrate is at least partially exposed. The first connection pad layer includes P connection pads, which are connected to the N driving sub-circuits, where N and P are both positive integers greater than 0.

2. The first circuit device according to claim 1, wherein, P>N+A+B.

3. The first circuit device according to claim 1 or 2, wherein, The P connection pads include: E first input signal connection pads and F first output signal connection pads, where F = A × B; E and F are both positive integers greater than 1.

4. The first circuit device according to claim 3, wherein, The E first input signal connection pads include: b scan signal connection pads and a data signal connection pads. The b scan signal connection pads are configured to provide b scan signals, and the a data signal connection pads are configured to provide a data signals. One scan signal is configured to control at least one driver sub-circuit to write one data signal. Wherein, a×b is less than or equal to N, and a and b are both positive integers greater than 0.

5. The first circuit device according to claim 4, wherein, a = A, b = B; Alternatively, a = B, b = A.

6. The first circuit device according to claim 4, wherein, The first circuit layer further includes: a multiplexing circuits, each multiplexing circuit being configured to convert one data signal into A / a data signals; the P connection pads are respectively connected to the N driver sub-circuits and the a multiplexing circuits.

7. The first circuit device according to claim 6, wherein, P>N+a+b+A / a, a=b.

8. The first circuit device according to any one of claims 4 to 7, wherein, The E first input signal connection pads further include: at least one constant voltage signal connection pad, the at least one constant voltage signal connection pad being configured to provide a constant voltage DC signal to the N drive sub-circuits.

9. A second circuit device, comprising: Second insulating substrate; The second circuit layer is disposed on the second insulating substrate, and the second circuit layer includes: M cascaded first control circuits; The second connection pad layer is located on the side of the second circuit layer away from the second insulating substrate, and the surface of the second connection pad layer away from the second insulating substrate is at least partially exposed. The second connection pad layer includes: Q connection pads, the Q connection pads being connected to M cascaded first control circuits, wherein Q>M+1, and Q and M are both positive integers greater than 0.

10. The second circuit device according to claim 9, wherein, The second circuit layer further includes: R cascaded second control circuits; R is a positive integer greater than 0; the Q connection pads are respectively connected to the M cascaded first control circuits and the R cascaded second control circuits, Q>M+R+2.

11. The second circuit device according to claim 10, wherein, The Q connection pads include: S second input signal connection pads and T second output signal connection pads, Q = S + T, T = M + R, S > 2, and S and T are both positive integers greater than 1.

12. An apparatus comprising: A circuit board, wherein the circuit board is provided with multiple traces, the multiple traces including: a first type of trace and a second type of trace; Multiple components are disposed on the circuit board; and At least one of the following is disposed on the circuit board: a plurality of first circuit devices as described in any one of claims 1 to 8, and a plurality of second circuit devices as described in any one of claims 9 to 11; In this circuit, one of the first circuit devices is connected to N of the components via N traces of the first type; At least one of the second circuit devices is connected to the first circuit device via the second type of trace.

13. The apparatus according to claim 12, wherein, The circuit board also includes a third type of trace, which is configured to connect two second circuit devices that are cascaded.

14. The apparatus according to claim 12 or 13, wherein, The device includes: at least one first region, wherein a plurality of elements and a plurality of first circuit devices are disposed within a single first region; A group of second circuit devices is provided on at least one side of the first region along the first direction. Each group of second circuit devices includes a plurality of second circuit devices connected in cascade. One of the second circuit devices in each group is connected to at least one first circuit device through the second type of trace.

15. The apparatus according to claim 14, wherein, A first group of second circuit devices and a second group of second circuit devices are respectively arranged on both sides of the first region along the first direction. At least one first circuit device in the first region is connected to the same level of second circuit devices in the first group of second circuit devices and the second group of second circuit devices.

16. The apparatus according to claim 13, wherein, The device includes: at least one first region, a plurality of elements and a plurality of first circuit devices disposed in a single first region, and a set of second circuit devices disposed on at least one side of the first region along a first direction; At least one group of second circuit devices includes: multiple cascaded subgroups of second circuit devices, at least one subgroup of second circuit devices includes: a first type of second circuit device and a second type of second circuit device, the first type of second circuit device and the second type of second circuit device in the first-level second circuit device subgroup are connected to the second type of second circuit device in the previous-level second circuit device subgroup through the third type of trace; the first type of second circuit device in the first-level second circuit device subgroup is connected to at least one first circuit device in the first region through the second type of trace; The second type of second circuit device within the first-level second circuit device subgroup is configured to provide cascade signals to the next-level second circuit device subgroup.

17. The apparatus according to any one of claims 12 to 16, wherein, The plurality of components include a plurality of light-emitting devices, each of which includes three light-emitting elements that emit light of different colors; the first circuit device includes twelve driving sub-circuits and a multiplexing circuit; the anode connection terminals of the twelve driving sub-circuits are connected one-to-one with the twelve light-emitting elements; the multiplexing circuit is configured to convert two data signals into six data signals; among the twelve light-emitting elements, the driving sub-circuit connected to every two light-emitting elements that emit the same color light is configured to receive the same data signal; and the driving sub-circuit connected to every two light-emitting elements is configured to receive the same scan signal.

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