Electronic device and access method

Abstract

The embodiments of the present application relate to the technical field of chips. Provided are an electronic device and an access method, which alleviate the memory wall phenomenon and reduce the cost and process complexity of the electronic device. The specific solution is: the electronic device comprises a computing chip, a first printed circuit board and a plurality of memory chips, wherein the computing chip is a packaged chip, the plurality of memory chips are packaged chips, and the computing chip and the plurality of memory chips are arranged on the first printed circuit board. The computing chip comprises a processor and a plurality of memory access interfaces, the plurality of memory access interfaces respectively being coupled to the plurality of memory chips by means of the first printed circuit board, wherein the loss of the processor accessing the memory chips by means of the memory access interfaces is less than a preset loss, and the rate of the processor accessing the memory chips by means of the memory access interfaces is greater than a preset rate. The embodiments of the present application are applied to the process of the processor accessing a memory.

Description

An electronic device and an access method

[0001] This application claims priority to Chinese Patent Application No. 202510126261.6, filed with the State Intellectual Property Office of China on January 26, 2025, entitled “An Electronic Device and Access Method”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and more particularly to an electronic device and an access method. Background Technology

[0003] In fields such as high-performance computing (HPC), artificial intelligence (AI), machine learning, and data analytics, one focus is on computing power, i.e., the computing capacity provided per unit area (or volume), and the other is on memory, i.e., the memory capacity or throughput provided per unit area. With technological advancements, these fields have witnessed the emergence of the "memory wall" phenomenon, where progress in memory lags behind progress in computing power. If the memory wall persists for an extended period, it will further widen the gap between memory and computing power.

[0004] Currently, electronic devices often mitigate the impact of the memory wall by allocating more area or volume to memory than to computing power, such as high bandwidth memory (HBM). HBM consists of multiple memory dies stacked in three dimensions using through-silicon vias (TSVs), resulting in higher density, greater bandwidth, and lower latency.

[0005] However, high-bandwidth memory has a limited number of bare dies, complex manufacturing processes, and high costs. Therefore, how to mitigate the memory wall phenomenon while reducing the cost and manufacturing complexity of electronic devices has become a pressing issue. Summary of the Invention

[0006] This application provides an electronic device and an access method that improves the memory wall phenomenon while reducing the cost and manufacturing complexity of the electronic device.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions.

[0008] In a first aspect, embodiments of this application provide an electronic device, which includes a computing chip, a first printed circuit board, and multiple memory chips. The computing chip is a packaged chip, and the multiple memory chips are also packaged chips. The computing chip and the multiple memory chips are disposed on the first printed circuit board. The computing chip includes a processor and multiple memory access interfaces, which are coupled to the multiple memory chips respectively through the first printed circuit board. The processor experiences less overhead when accessing the memory chips through the memory access interfaces than a preset loss, and the processor accesses the memory chips at a rate greater than a preset rate.

[0009] Therefore, in the electronic device provided in this application embodiment, a computing chip and multiple memory chips are disposed on a first printed circuit board. The first printed circuit board has a larger area than the packaging substrate for disposing of memory chips, meaning the number of memory chips is unlimited. This allows the electronic device to increase total memory bandwidth and mitigate the memory wall phenomenon. Furthermore, the processor's access loss to the memory chips via the memory access interface is less than a preset loss, and the processor's access rate to the memory chips via the memory access interface is greater than a preset rate, meaning the computing chip can support long-distance high-speed communication. The computing chip is independently packaged, and the multiple memory chips are also independently packaged, with a certain distance between the different packages. Compared to packaging the computing chip and memory chips together, the independent packaging method reduces the cost and manufacturing complexity of the electronic device, as well as the maintenance and replacement costs of the memory chips. In addition, the heat generated by the computing chip does not affect the heat generated by the memory chips, reducing the heat dissipation cost of the electronic device.

[0010] In one possible implementation, the computing chip further includes multiple conversion and driving modules, multiple memory access interfaces, and multiple conversion and driving modules coupled one-to-one. These multiple conversion and driving modules are also coupled one-to-one with multiple memory chips via a first printed circuit board. The conversion and driving modules are used to perform rate conversion and amplification on the signals from the memory access interfaces.

[0011] In this implementation, the electronic device can perform rate conversion on the signals of the memory access interface through a conversion and drive module, that is, to convert low-speed signals to high-speed signals, thereby reducing the number of signal lines between the memory access interface and the memory chip and saving routing resources on the first printed circuit board. The electronic device can also amplify the signals of the memory access interface through the conversion and drive module to reduce insertion loss, enabling long-distance communication and meeting the requirement that the loss of the processor accessing the memory chip through the memory access interface is less than a preset loss.

[0012] In one possible implementation, the computing chip includes a first packaging substrate, and a memory access interface is coupled to the memory chip through the first packaging substrate and a first printed circuit board.

[0013] In this implementation, the bare die of the computing chip is placed on the first packaging substrate, which is then placed on the first printed circuit board. The first packaging substrate can provide a high density of bumps for interconnection, thereby reducing the requirements of the electronic device on the soldering capability of the first printed circuit board, thus reducing the process complexity and cost of the first printed circuit board.

[0014] In one possible implementation, the memory chip includes a second packaging substrate, and the memory access interface is coupled to the second packaging substrate of the memory chip through a first packaging substrate and a first printed circuit board.

[0015] In this implementation, the bare die of the memory chip is placed on the second packaging substrate, which is then placed on the first printed circuit board. The second packaging substrate can provide a high density of bumps for interconnection, thereby reducing the requirements of the electronic device on the soldering capability of the first printed circuit board, thus reducing the process complexity and cost of the first printed circuit board.

[0016] In one possible implementation, the memory chip includes a second packaging substrate, and the memory access interface is coupled to the second packaging substrate of the memory chip via a first printed circuit board.

[0017] In this implementation, the electronic device may only calculate that the chip includes the first packaging substrate, or only calculate that the memory chip includes the second packaging substrate, or calculate that the chip includes the first packaging substrate while the memory chip includes the second packaging substrate.

[0018] In one possible implementation, the electronic device further includes: multiple connectors, multiple memory chips and multiple connectors corresponding one-to-one, the memory chips being coupled to the first printed circuit board via connectors.

[0019] In this implementation, the memory chips are mounted on the first printed circuit board via connectors. This allows the electronic device to be configured with the required number of memory chips, as well as memory chips of different capacities and bandwidths. Furthermore, in the event of a memory chip failure, the electronic device can be replaced on-site, making its use and maintenance more flexible and convenient.

[0020] In one possible implementation, the electronic device further includes multiple photoelectric conversion chips disposed on a first printed circuit board, and a memory access interface is coupled to the photoelectric conversion chips via the first printed circuit board. Each photoelectric conversion chip includes an optical signal coupler for coupling to at least one memory chip on a second printed circuit board.

[0021] In this implementation, at least one memory chip on the second printed circuit board can serve as remote memory. The electronic device can configure the number of remote memory chips as needed, and can use memory chips of different capacities. Furthermore, in the event of a remote memory failure, the electronic device can be replaced on-site, making its use and maintenance more flexible and convenient. In addition, multiple computing chips can achieve pooled sharing of remote memory through time-division multiplexing.

[0022] In one possible implementation, the photoelectric conversion chip includes a third packaging substrate, and the memory access interface is coupled to the third packaging substrate of the photoelectric conversion chip via a first printed circuit board.

[0023] In this implementation, the third packaging substrate can provide a high density of bumps for interconnection. Compared to directly placing the photoelectric conversion chip on the first printed circuit board, the electronic device can reduce the requirements for the soldering capability of the first printed circuit board, thereby reducing the process complexity and cost of the first printed circuit board.

[0024] In one possible implementation, the memory chip includes a logic die and multiple memory dies, the logic dies being coupled to a memory access interface via a first printed circuit board.

[0025] In this implementation, since the number of memory chips is unlimited, the memory chips can be packaged into logic dies and memory dies using simple and low-cost processes, provided that memory expansion is satisfied.

[0026] Secondly, embodiments of this application provide an electronic device, which includes a second printed circuit board and at least one memory chip. The at least one memory chip is disposed on the second printed circuit board and includes a photoelectric conversion module, a logic die, and multiple storage dies. The photoelectric conversion module is used to couple with a photoelectric conversion chip on a first printed circuit board.

[0027] Therefore, the electronic device provided in this application embodiment can serve as remote memory for a computing chip. The computing chip can be configured with the amount of remote memory as needed, and memory chips of different capacities can be configured. Furthermore, in the event of a remote memory failure, the electronic device can be replaced on-site, making its use and maintenance more flexible and convenient. In addition, multiple computing chips can achieve pooled sharing of remote memory through time-division multiplexing.

[0028] In one possible implementation, the memory chip also includes a fourth packaging substrate, through which the logic die is coupled to a second printed circuit board.

[0029] In this implementation, the fourth packaging substrate can provide a high density of bumps for interconnection. Compared to placing memory chips directly on the second printed circuit board, electronic devices can reduce the requirements for the soldering capabilities of the second printed circuit board, thereby reducing the process complexity and cost of the second printed circuit board.

[0030] Thirdly, embodiments of this application provide a server cluster, which includes: a plurality of first electronic devices according to a first aspect, and / or a plurality of second electronic devices according to a second aspect.

[0031] Fourthly, embodiments of this application provide a supercomputing device, which includes: a plurality of first electronic devices according to a first aspect, and / or a plurality of second electronic devices according to a second aspect.

[0032] Fifthly, embodiments of this application provide an access method applied to an electronic device. The electronic device includes a computing chip, a first printed circuit board, and multiple memory chips. The computing chip is a packaged chip, and the multiple memory chips are also packaged chips. The computing chip and the multiple memory chips are disposed on the first printed circuit board. The computing chip includes a processor and multiple memory access interfaces. The access method includes: the processor sending an access request to the first memory chip through a first memory access interface of the multiple memory access interfaces. The first memory access interface is coupled to the first memory chip through the first printed circuit board. The loss of the access request sent by the processor through the first memory access interface is less than a preset loss, and the rate at which the processor sends the access request through the first memory access interface is greater than a preset rate. The first memory chip receives the access request and performs a write data operation or a read data operation based on the access request.

[0033] In one possible implementation, the computing chip also includes multiple conversion and driving modules, and the access method may further include: the conversion and driving modules performing rate conversion and amplification on the signals of the memory access interface.

[0034] Sixthly, embodiments of this application provide a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform the access method in any of the possible implementations of the third aspect described above.

[0035] In one possible implementation, the computer-readable storage medium is a non-transitory computer-readable storage medium.

[0036] In a seventh aspect, embodiments of this application provide a computer program product that, when run on a computer or processor, causes the computer or processor to execute the access method in any of the possible implementations of the third aspect described above.

[0037] It is understood that any of the access methods, computer-readable storage media, or computer program products provided above relate to the electronic devices described above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding electronic devices, and will not be repeated here.

[0038] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0039] Figure 1 is a schematic diagram of a graphics processor package provided in an embodiment of this application;

[0040] Figure 2 is a schematic diagram illustrating the development of computing power, memory, and interface speed according to an embodiment of this application.

[0041] Figure 3 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0042] Figure 4 is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0043] Figure 5 is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0044] Figure 6 is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0045] Figure 7 is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0046] Figure 8 is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0047] Figure 9 is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0048] Figure 10 is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0049] Figure 11 is a flowchart illustrating an access method provided in an embodiment of this application. Detailed Implementation

[0050] To better understand the embodiments of this application, the relevant technologies involved in the embodiments of this application will be introduced first below.

[0051] 1. Dual in-line memory modules (DIMMs) are modules composed of a series of dynamic random access memory (DRAM). A DIMM consists of several to dozens of DRAM chips soldered onto a pre-fabricated printed circuit board (PCB). DIMMs typically have a 64-bit bus width and are commonly used in laptops, personal computers, workstations, servers, and other devices. A key characteristic of DIMMs is that they are inserted into and connected to the PCB via gold fingers.

[0052] 2. Compression-attached memory modules (CAMMs) are another type of memory module composed of DRAM. Unlike DIMMs, which have their gold fingers directly inserted into the printed circuit board, CAMMs connect to the PCB using a grid array of pin contacts, resulting in shorter traces. Consequently, compared to DIMMs, CAMMs occupy more area on the printed circuit board.

[0053] 3. Printed Circuit Board (PCB), also known as a printed circuit board, is a device that provides power, conductive lines, and insulating ground to pinned chip packages. A PCB typically consists of an insulating ground plane, connecting wires, and pads for mounting and soldering electronic components. It is often referred to as the motherboard (in this case, the PCB connecting at least one computing package, at least one memory package, multiple board-level components, and the entire interconnect network) and can be deployed as a standalone computing device.

[0054] 4. Silicon interposer: If the package contains only a single chip, the substrate provides connection pins for board-level power supply, control, and communication. If the package contains multiple chips that need to communicate with each other, this communication can be achieved through the silicon interposer. In multi-chip packages for high-density computing, achieving inter-chip interconnection through the silicon interposer becomes increasingly complex. Furthermore, implementing cache sharing within a multi-chip package further increases the complexity of the silicon interposer.

[0055] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments, unless otherwise stated, "multiple" means two or more.

[0056] Furthermore, the term "coupling" is used to refer to electrical connections, including direct connections via wires or terminals or indirect connections via other devices. Therefore, "coupling" should be considered a broad type of electronic communication connection.

[0057] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0058] The evolution and development of computer and communication technologies have enriched information exchange, enabling access to broader knowledge, technologies, and more opportunities for change. With further advancements in computer and communication technologies, machines exchanging information and knowledge have achieved a certain level of intelligence. This intelligence is what is considered the greatest driving force behind current technological trends and even future societal transformation: artificial intelligence (AI).

[0059] Artificial intelligence, or intelligent machines, refers to man-made machines capable of exhibiting a certain degree of human-like intelligence. It is generally believed that numerous technologies can ultimately realize intelligent machines, one of the most commonly used being machine learning. Machine learning is the process of finding patterns or rules for solving specific problems or tasks in data through a series of algorithms, and then applying these patterns to new, unknown data. Machine learning is implemented through pattern recognition and task automation. Pattern recognition finds specific patterns (i.e., reasoning) in massive amounts of data, while task automation determines (or predicts) how to perform a specific task based on the recognized patterns.

[0060] The key to machine learning lies in the massive nature of data; that is, machine learning requires extensive data processing. Therefore, the algorithmic computation process of machine learning is data-intensive, which translates to computationally intensive equipment requirements. In a possible example, consider a graphics processing unit (GPU). GPUs are primarily used in computer graphics display, design, and video processing. The powerful computing capabilities of GPUs can be applied to a branch of artificial intelligence (i.e., machine learning). In the field of artificial intelligence, large model parameters (a metric for measuring AI inference ability) are directly correlated with the total computing power provided by the GPU.

[0061] With the rapid development of the field of artificial intelligence, graphics processing units (GPUs) have also seen tremendous growth. As shown in Figure 1, Figure 1(a) illustrates a schematic diagram of one GPU package, and Figure 1(b) illustrates a schematic diagram of another GPU package. The GPUs shown in Figure 1(a) and Figure 1(b) represent the development of GPUs, including not only the increase in the total number and density of transistors, but also the increase in memory capacity and access bandwidth.

[0062] Specifically, the graphics processor shown in Figure 1(a) is a single chip that can integrate multiple transistors, multiple stream processors, and a large capacity of memory, enabling it to achieve greater computing power. The graphics processor shown in Figure 1(b) can internally package two dies, namely a first die and a second die. The first die and the second die can be interconnected through high-speed channels in a silicon interposer and configured with a larger capacity of memory, which can further improve computing power.

[0063] The development of artificial intelligence stems from progress in two sub-fields. One is computing power, which refers to the computing capacity provided per unit area (or volume). The other is memory, which refers to the memory units (e.g., static values ​​like GB or TB) or throughput capacity (e.g., how many GB or TB can be accessed per second) provided per unit area.

[0064] Under the concepts of computing power and memory, the "memory wall" phenomenon still exists in the field of artificial intelligence, meaning that progress in memory lags behind progress in computing power. Figure 2 illustrates the development of computing power, memory, and interface speeds, with normalized scaling applied. That is, development in computing power and interface speeds is represented by speed, while development in memory is represented by capacity. As can be seen from Figure 2, over time, development in computing power is relatively rapid, while development in memory and interface speeds is relatively slow.

[0065] Therefore, given the existence and increasing extent of the memory wall phenomenon, the improvement of the total computing power of a single deployment depends on the asymmetric stacking of computing power and memory. In other words, the impact of the memory wall is mitigated by allocating more area or volume to memory than to computing power, thereby supporting the growth of the total computing power of a single deployment.

[0066] To address the memory wall phenomenon, high-bandwidth memory (HBM) has been proposed. HBM not only provides enormous memory capacity but also offers sufficiently high bandwidth between memory and computing devices, enabling graphics processors to meet the data processing demands of large model parameters and massive amounts of data. HBM is based on die stacking technology, integrating multiple memory dies into a single package through through-silicon vias (TSVs), thereby achieving higher memory capacity in a smaller space. However, because stacking requires drilling holes in the dies, improving the yield of HBM is difficult, resulting in higher production costs. Furthermore, in terms of overall volume, HBM has a lower memory density.

[0067] In one possible implementation, to improve the yield and memory density of high-bandwidth memory, a chip-on-wafer-on-substrate (CoWoS) technology has been proposed, which is a 2.5D integrated manufacturing technology. CoWoS technology improves chip performance and efficiency by integrating multiple chips (such as processors and memory modules) on a single silicon or organic interposer to form a compact and efficient unit.

[0068] CoWoS technology is a combination of CoW and WoS. CoW refers to chip-on-wafer, and WoS refers to wafer-on-substrate, thus integrating them into CoWoS.

[0069] Figure 3 shows a schematic diagram of an electronic device. This electronic device may include: a printed circuit board, a package substrate, a silicon interposer, a computing chip, and a high-bandwidth memory. The computing chip may be a central processing unit (CPU) or a graphics processing unit (GPU), etc. The high-bandwidth memory may include logic dies and multiple memory dies, which may be dynamic random access memory (DRAM). Vertical connections of the high-bandwidth memory are achieved through through-silicon vias (TSVs) and scaling microbumps between the multiple memory dies. The underlying logic die provides a data path for each memory die. A signal path is provided between the logic die and the computing chip through the silicon interposer, and both the logic die and the computing chip also have signal paths provided by the package substrate.

[0070] The reliability of high-bandwidth memory largely depends on the thermomechanical stress during reflow, bonding, and die back-grinding processes. Identifying potential problems requires testing high-temperature operating life, temperature and humidity deviations, and temperature cycling. Adhesion levels between layers can be determined through pretreatment, unbiased humidity testing, and pressure testing. Furthermore, high-bandwidth memory requires additional testing to ensure that issues such as microbump short circuits, metal bridging, or interface delamination between the chip and microbumps do not occur during long-term use.

[0071] High-bandwidth memory packaged using CoWoS technology offers two main advantages: reduced component footprint and external memory requirements, and faster memory access times and speeds. Stacking multiple memory dies allows for wider interfaces, with a significantly greater number of interconnect contacts beneath the dies compared to the number of lines connecting other memory chips to the computing chip. Consequently, high-bandwidth memory features higher bandwidth, more input / output (I / O) counts, lower power consumption, and smaller size.

[0072] However, high-bandwidth memory also has the following disadvantages: (1) High-bandwidth memory has a complex process and high cost; (2) CoWoS technology has a low packaging yield. The packaging yield of CoWoS technology is related to the packaging yield of CoW and WoS. Improving the packaging yield of CoWoS technology requires improving the packaging yield of both; (3) High-bandwidth memory supports a limited number of memory dies. The maximum volume of the silicon interposer is limited. The single silicon interposer corresponding to CoWoS technology can support a maximum of 8 memory dies. Even if CoWoS-L technology is used to increase the maximum volume of the silicon interposer, the single silicon interposer can support a maximum of 12 memory dies, but the number of memory dies is still limited. (4) High-bandwidth memory has a high maintenance cost and a high failure rate. Once the high-bandwidth memory in the AI ​​chip package fails, it cannot be opened for replacement and repair. The entire AI chip must be replaced, which is extremely costly. (5) High-bandwidth memory has difficulty in heat dissipation. The memory die and the computing chip are set in the same chip package, and their heat affects each other, making it difficult to dissipate heat in the chip system.

[0073] In another possible implementation, to improve the yield and memory density of high-bandwidth memory, a method of integrating high-bandwidth memory on a package substrate is proposed. In this method, the package substrate has a larger area than the silicon interposer, allowing for the placement of more memory dies. Figure 4 shows a schematic diagram of another electronic device, which may include a first computing chip, a second computing chip, and multiple high-bandwidth memories. Because the bump density of the package substrate is lower than that of the silicon interposer, electronic devices using a package substrate can increase single-line speeds while reducing the number of bumps.

[0074] In addition, referring to Figure 4, the electronic device may also include multiple optical chips. The optical chips are disposed on the periphery of the packaging substrate and are used to couple with the memory chip at a distance through an optical fiber interface to achieve the connection of memory chips over a longer distance.

[0075] However, this electronic device also has the following disadvantages: (1) The area of ​​the packaging substrate is still limited, and the data that can be set for HBM or optical chips is still limited; (2) The optical chips and fiber optic interfaces on the packaging substrate need to be completed in the chip packaging factory, and the processing flow is complicated; (3) The optical chips are set on the packaging substrate, and the optical chips are affected by the heat of the first computing chip or the second computing chip, which will lead to performance degradation or even failure; (4) The high bandwidth memory has a complex process and high cost; (5) The memory chip and the computing chip are set in the same chip package, and the heat of each other affects each other, making it difficult for the electronic device to dissipate heat; (6) The maintenance cost of the high bandwidth memory is high, and the failure rate of the high bandwidth memory is high. Once the high bandwidth memory in the AI ​​chip package fails, it is impossible to open the package for replacement and repair. Only the entire AI chip can be replaced, which is extremely costly.

[0076] Therefore, this application provides an electronic device that mounts a computing chip and multiple memory chips on a first printed circuit board. The first printed circuit board has a larger area than the packaging substrate for mounting the memory chips, meaning the number of memory chips is unlimited. This allows the electronic device to increase overall memory bandwidth and mitigate the memory wall phenomenon. Furthermore, the processor's access loss to the memory chips via the memory access interface is less than a preset loss, and the processor's access rate to the memory chips via the memory access interface is greater than a preset rate, meaning the computing chip can support long-distance high-speed communication. The computing chip and multiple memory chips are each independently packaged, with a certain distance between the different packages. Compared to packaging the computing chip and memory chips together, independent packaging reduces the cost and manufacturing complexity of the electronic device, as well as the maintenance and replacement costs of the memory chips. In addition, the heat generated by the computing chip does not affect the heat generated by the memory chips, reducing the heat dissipation cost of the electronic device.

[0077] In the above scenarios, the electronic devices provided in this application embodiment can be: consumer electronics, home electronics, in-vehicle electronics, or financial electronics. Consumer electronics include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, mixed reality (MR) electronic devices, artificial intelligence (AI) electronic devices, drones, etc. Home electronics include smart door locks, televisions, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics include in-vehicle navigation systems, in-vehicle digital video discs (DVDs), etc. Financial electronics include automatic teller machines (ATMs) and self-service electronic devices, etc.

[0078] In one embodiment, the electronic device may also be a router or switch, performing functions such as data transmission, routing, and flow control. Alternatively, the electronic device may be a server cluster or a supercomputing device. For example, a server cluster may include multiple electronic devices, and a supercomputing device may also include multiple electronic devices. This application does not impose special limitations on the specific form of the electronic device. The device used to implement the function of the electronic device may be an electronic device itself, or a device capable of supporting the electronic device in implementing that function, such as a chip system. This device may be installed in the electronic device or used in conjunction with the electronic device. In this application embodiment, the chip system may consist of chips, or it may include chips and other discrete components.

[0079] The electronic device provided in the embodiments of this application will be further described below with reference to the accompanying drawings.

[0080] This application provides an electronic device, as shown in FIG5, which illustrates a schematic diagram of the structure of another electronic device. The electronic device includes a computing chip, a first printed circuit board, and multiple memory chips. The computing chip is a packaged chip, and the multiple memory chips are respectively the packaged chip computing chip and the multiple memory chips disposed on the first printed circuit board. FIG5 specifically shows memory chip_1 and memory chip_2 among the multiple memory chips. Similarly, the electronic device structure shown in FIG5 does not constitute a limitation on the electronic device; the electronic device may include more or fewer components than shown in FIG5, or combine certain components, or have different component arrangements.

[0081] The computing chip includes a processor and multiple memory access interfaces, which are coupled to multiple memory chips via a first printed circuit board.

[0082] Figure 5 shows memory access interface_1 and memory access interface_2 among multiple memory access interfaces. Memory access interface_1 is coupled to memory chip_1 through the first printed circuit board, and memory access interface_2 is coupled to memory chip_2 through the first printed circuit board.

[0083] For example, a processor can be any computing unit, computing chip, or computing package that provides actual computing capabilities, such as a GPU, CPU, tensor processing unit (TPU), field programmable gate array (FPGA), application-specific integrated circuit (ASIC), or digital signal processor (DSP), as well as any independently deployable and operable computing device. A processor can also be other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A processor can also be a microprocessor or any conventional processor.

[0084] For example, the first printed circuit board can be a circuit board made of organic materials, glass materials, and ceramic materials. The first printed circuit board needs to support high-density wiring capabilities with small chip pin pitch. In the embodiments of this application, the computing chip communicates or transmits data with the memory chip through the high-density wiring on the first printed circuit board.

[0085] For example, the first printed circuit board may include an expandable interface, which is a reserved pad, and the expandable interface can connect to memory chips or other computing chips in a variety of ways.

[0086] For example, memory chips can be internal memory accessible to computing units such as CPUs or GPUs, such as synchronous dynamic random access memory (SDRAM) or DRAM as the basic concept, with DIMM or CAMM as the module, and the memory medium including but not limited to volatile memory components such as double data rate SDRAM (DDR), HBM, lower power DDR (LPDDR), graphics DDR (GDDR).

[0087] For example, the electronic device directly places the computing chip and multiple memory chips on the first printed circuit board, instead of placing the computing chip and multiple memory chips on the packaging substrate. This can eliminate signal loss caused by the packaging substrate, reduce the driving capability requirements and power consumption of the chip's active interface, and the wiring density on the first printed circuit board is not limited by the wiring density of the packaging substrate, thus supporting higher memory bandwidth.

[0088] For example, memory expansion in an electronic device may include providing larger memory capacity, as well as expanding bandwidth or even increasing bit width, i.e., providing the computing chip with greater access capacity and higher access throughput. In the embodiments of this application, the memory chip is disposed on a first printed circuit board, which is not limited by area, i.e., the number of memory chips is also not limited, and the electronic device can achieve a larger memory capacity, thus realizing memory expansion.

[0089] Among these, the processor's loss when accessing the memory chip through the memory access interface is less than the preset loss, and the processor's access rate when accessing the memory chip through the memory access interface is greater than the preset rate.

[0090] For example, the processor's loss when accessing the memory chip through the memory access interface is less than the preset loss, meaning the electronic device can support communication over any distance. In this case, the location of the memory chip is not limited by its distance from the processor; the memory chip can be placed anywhere on the first printed circuit board, improving the flexibility of the electronic device.

[0091] For example, the preset loss can be set by someone skilled in the art based on the distance between the processor and the memory chip. In one possible example, the preset loss could be 12 dB.

[0092] For example, the processor accesses the memory chip at a rate greater than a preset rate through the memory access interface, meaning the electronic device can support high-speed communication. In this case, the electronic device can expand its memory through any number of memory chips and high-speed communication between the memory chips and the processor, achieving a total bandwidth comparable to that of a high-bandwidth memory.

[0093] In one possible example, in an AI computing scenario, the memory access interface needs to reach speeds of up to one trillion bytes per second (TBps). Additionally, the number of memory chips needs to be in the tens, with the processor accessing these multiple memory chips simultaneously via a parallel bus to achieve the high bandwidth access speeds required by the AI ​​chip, typically at the TBps level.

[0094] Therefore, the electronic device provided in this application embodiment has no limitation on the location and number of memory chips, which can increase memory capacity and improve the memory wall phenomenon. The computing chip and memory chip are disposed on the first printed circuit board, rather than being packaged in the same chip, simplifying the process and reducing cost. In addition, the electronic device can also support decoupling and repair of individual memory chip failures, reducing the maintenance and replacement costs of memory chips. Furthermore, the heat generated by the computing chip will not affect the heat generated by the memory chip, reducing the heat dissipation cost of the electronic device.

[0095] Optionally, the memory chip includes a logic die and multiple memory dies, the logic die being coupled to a memory access interface via a first printed circuit board.

[0096] For example, a logic die can be used to provide a data path for each memory die. The logic die can implement signal rate conversion, such as low-speed to high-speed signal conversion, or high-speed to low-speed signal conversion. The logic die can also implement the function of driving the DRAM read / write control physical layer (PHY).

[0097] For example, the memory chip may include high-bandwidth memory, and the memory chip may also include dies of types such as LPDDR, GDDR, or DDR. In the embodiments of this application, since the number of memory chips is not limited, the memory chips can be packaged into logic dies and memory dies using simple and low-cost processes, provided that memory expansion is satisfied.

[0098] Optionally, the computing chip also includes multiple conversion and driving modules, as shown in Figure 6, which illustrates the structure of another electronic device. Multiple memory access interfaces and conversions are coupled one-to-one with the multiple conversion and driving modules, which are also coupled one-to-one with the multiple memory chips via a first printed circuit board.

[0099] Figure 6 shows the conversion and drive module_1 and the conversion and drive module_2. The first end of the conversion and drive module_1 is connected to the memory access interface_1, and the second end of the conversion and drive module_1 is connected to the memory chip_1 through the first printed circuit board. The first end of the conversion and drive module_2 is connected to the memory access interface_2, and the second end of the conversion and drive module_2 is connected to the memory chip_2 through the first printed circuit board.

[0100] The conversion and driving module is used to perform rate conversion and amplification on the signals of the memory access interface.

[0101] For example, if the memory access interface is directly coupled to the memory chip through the first printed circuit board, the required number of signal lines would be too large, thus occupying a significant amount of trace resources on the first printed circuit board. Therefore, the electronic device can use a conversion and drive module to perform rate conversion on the signals from the memory access interface. For instance, it can use different transmission protocols to convert low-speed signals to high-speed signals, such as converting a 6.4Gbps signal to a 32Gbps signal, thereby reducing the number of signal lines between the memory access interface and the memory chip and saving trace resources on the first printed circuit board.

[0102] For example, since the computing chip and multiple memory chips of the electronic device provided in this application embodiment are not packaged in the same chip, the distance between the memory access interface in the computing chip and the memory chip is relatively far. Therefore, the loss of the processor accessing the memory chip through the memory access interface may be large. Thus, the electronic device can amplify the signal of the memory access interface through a conversion and driving module to reduce insertion loss, achieve long-distance communication, and meet the requirement that the loss of the processor accessing the memory chip through the memory access interface is less than a preset loss.

[0103] It is understood that the conversion and driver module can also be integrated into the memory access interface, and this application embodiment does not limit this.

[0104] Optionally, the computing chip includes a first packaging substrate, as shown in Figure 7, which illustrates the structure of another electronic device. In this device, a memory access interface is coupled to the memory chip via the first packaging substrate and a first printed circuit board. For example, memory access interface_1 is connected to memory chip_1 via the first packaging substrate and the first printed circuit board, and memory access interface_2 is connected to memory chip_2 via the first packaging substrate and the first printed circuit board.

[0105] For example, if the die in the computing chip is directly connected to the first printed circuit board, the electronic device requires the first printed circuit board to support high-density solder ball soldering capabilities, requiring smaller solder ball pitch. If the die in the computing chip is disposed on a first packaging substrate, and the first packaging substrate is then disposed on the first printed circuit board, the first packaging substrate can provide a higher density of bumps for interconnection, thus reducing the soldering capability requirements of the first printed circuit board, thereby reducing the process complexity and cost of the first printed circuit board.

[0106] Optionally, referring to Figure 7, the memory chip includes a second packaging substrate, and the memory access interface is coupled to the second packaging substrate of the memory chip through the first packaging substrate and the first printed circuit board. For example, memory access interface_1 is coupled to the second packaging substrate of memory chip_1 through the first packaging substrate and the first printed circuit board, and memory access interface_2 is coupled to the second packaging substrate of memory chip_2 through the first packaging substrate and the first printed circuit board.

[0107] For example, if the die in the memory chip is directly connected to the first printed circuit board, the electronic device also requires the first printed circuit board to support high-density solder ball soldering capabilities, requiring smaller solder ball spacing. If the die in the computing chip is disposed on the first packaging substrate, and the die in the memory chip is disposed on the second packaging substrate, and the first and second packaging substrates are then disposed on the first printed circuit board, the first and second packaging substrates can provide high-density bumps for interconnection, thus reducing the soldering capability requirements of the first printed circuit board, thereby reducing the process complexity and cost of the first printed circuit board.

[0108] Figure 7 also shows the internal structure of memory chip 1 and memory chip 2. Taking memory chip 1 as an example, memory chip 1 can include a logic die, a memory die 1, and a memory die 2. The memory access interface 1 is connected to the logic die via a first packaging substrate, a first printed circuit board, and a second packaging substrate. The memory die 1 and memory die 2 can be LPDDR, GDDR, or DDR type dies. LPDDR, GDDR, or DDR type dies have simpler manufacturing processes and lower costs compared to high-bandwidth memories, thereby reducing the manufacturing complexity and cost of electronic devices.

[0109] Optionally, the memory chip includes a second packaging substrate, and the memory access interface is coupled to the second packaging substrate of the memory chip via a first printed circuit board.

[0110] For example, in the electronic device provided in the embodiments of this application, the chip may include only the first packaging substrate, or only the memory chip may include the second packaging substrate, or the chip may include both the first and second packaging substrates. The embodiments of this application do not limit this to any particular type.

[0111] Optionally, the electronic device also includes multiple connectors, as shown in Figure 8, which illustrates a schematic diagram of yet another type of electronic device. Multiple memory chips and multiple connectors correspond one-to-one, with the memory chips coupled to the first printed circuit board via the connectors.

[0112] For example, the connector can be in DIMM or CAMM form, and can be connected to solder points on the first printed circuit board. The computing chip and the connector are interconnected via signal lines within the first printed circuit board. The memory chip can be mounted on a memory card, which can also include a printed circuit board with gold fingers. The memory card is connected to the connector via the gold fingers.

[0113] Therefore, connectors make memory chips easier to insert and remove, allowing electronic devices to be configured with the required number of memory cards, as well as memory cards of different capacities and bandwidths. Furthermore, in the event of a memory card failure, the electronic device can support on-site replacement, making its use and maintenance more flexible and convenient.

[0114] Optionally, the computing chip in the electronic device shown in Figure 8 may also include a first packaging substrate, i.e., the computing chip is connected to a connector via the first packaging substrate and the first printed circuit board. The first packaging substrate can improve the bumps used for communication, and the electronic device can reduce the soldering requirements of the first printed circuit board, thereby reducing the process complexity and cost of the first printed circuit board.

[0115] Optionally, the electronic device also includes multiple photoelectric conversion chips, as shown in Figure 9, which illustrates the structure of another electronic device. Multiple photoelectric conversion chips are disposed on a first printed circuit board, and the memory access interface is also coupled to the photoelectric conversion chips through the first printed circuit board. Figure 9 illustrates a single photoelectric conversion chip; additionally, multiple memory chips in the electronic device are not shown in Figure 9. The structure of the electronic device shown in Figure 9 does not constitute a limitation on the electronic device.

[0116] The photoelectric conversion chip includes an optical signal coupler for coupling with at least one memory chip on a second printed circuit board. The optical signal coupler in the photoelectric conversion chip can be connected to the optical signal coupler in the memory chip on the second printed circuit board via an optical fiber. This optical fiber can be a high-density multi-channel optical fiber. In one possible example, the optical fiber can be a multi-core optical fiber or a single-fiber fiber cluster; this embodiment of the application does not limit this.

[0117] For example, the photoelectric conversion chip may also include a multi-channel photoelectric driver, a trans-impedance amplifier (TIA) (not shown in Figure 9), and a photoelectric conversion array. The multi-channel photoelectric driver can independently adjust the current intensity and switching state of each channel; the trans-impedance amplifier can convert the current signal received at the input terminal into a proportional voltage (i.e., a voltage signal) for output; and the photoelectric conversion array can convert the voltage signal into an optical signal for transmission via an optical signal coupler.

[0118] Referring again to Figure 9, the electronic device includes a second printed circuit board and at least one memory chip, which is disposed on the second printed circuit board. The memory chip includes a photoelectric conversion module, a logic die, and multiple memory dies. The photoelectric conversion module is used to couple with the photoelectric conversion chip on the first printed circuit board.

[0119] For example, the photoelectric conversion module may include an optical signal coupler, a photoelectric conversion array, a multi-channel photoelectric driver, and a transimpedance amplifier (not shown in Figure 9). The optical signal coupler in the memory chip can be connected to the optical signal coupler in the photoelectric conversion chip via an optical fiber.

[0120] For example, memory chips on a second printed circuit board can serve as remote memory for an electronic device. The electronic device can be coupled to any number of second printed circuit boards via optical fiber, and any number of memory chips can be placed on the second printed circuit board. The bandwidth of a single memory chip is limited, typically in the range of one trillion bits per second (Tbps). Therefore, dozens of memory chips can be placed on the second printed circuit board, and these memory chips can be accessed simultaneously via parallel multi-channel optical fiber to achieve the high bandwidth access speed of TBps required by the electronic device.

[0121] Therefore, the electronic device provided in this application embodiment can be configured with the amount of remote memory as needed, and can be configured with memory chips of different capacities. Furthermore, in the event of a remote memory failure, the electronic device can also support on-site replacement, making its use and maintenance more flexible and convenient. In addition, multiple computing chips can achieve pooled sharing of remote memory through time-division multiplexing.

[0122] Optionally, the photoelectric conversion chip includes a third packaging substrate, as shown in Figure 10, which illustrates a schematic diagram of yet another electronic device. The memory access interface is coupled through a first printed circuit board and the third packaging substrate of the photoelectric conversion chip.

[0123] For example, the third packaging substrate can provide a high density of bumps for interconnection, which can reduce the soldering requirements of the first printed circuit board compared to directly placing the photoelectric conversion chip on the first printed circuit board, thereby reducing the process complexity and cost of the first printed circuit board.

[0124] Referring again to Figure 10, the memory chip shown in Figure 10, mounted on the second printed circuit board, may also include a fourth packaging substrate. The die in the memory chip is coupled to the second printed circuit board through the fourth packaging substrate. The fourth packaging substrate can provide a high density of bumps for interconnection. Compared to directly mounting the memory chip on the second printed circuit board, the electronic device can reduce the soldering requirements of the second printed circuit board, thereby reducing the process complexity and cost of the second printed circuit board.

[0125] Applied to the aforementioned electronic device, this application also provides an access method, as shown in FIG11, which illustrates a flowchart of an access method. The access method includes the following steps.

[0126] S1101, The processor sends an access request to the first memory chip of multiple memory chips through the first memory access interface of multiple memory access interfaces.

[0127] The first memory access interface is coupled to the first memory chip through the first printed circuit board. The loss of the access request sent by the processor through the first memory access interface is less than the preset loss, and the rate of the access request sent by the processor through the first memory access interface is greater than the preset rate.

[0128] S1102, The first memory chip receives an access request and performs a write data operation or a read data operation based on the access request.

[0129] Therefore, in the access method provided in this application embodiment, the processor in the computing chip can access the memory chip through the first printed circuit board. The first printed circuit board has a larger area than the packaging substrate for mounting the memory chip, meaning the number of memory chips is unlimited. This results in a larger total memory bandwidth for the processor, mitigating the memory wall phenomenon. Furthermore, the loss of the processor accessing the first memory chip through the first memory access interface is less than a preset loss, and the processor's access speed through the first memory access interface is greater than a preset speed, meaning the computing chip can support long-distance, high-speed communication. Thus, this electronic device can independently package the computing chip and memory chip, with a certain distance between the different packages. Compared to co-packaging the computing chip and memory chip, independent packaging reduces the cost and manufacturing complexity of the electronic device, as well as the maintenance and replacement costs of the memory chip. In addition, the heat generated by the computing chip will not affect the heat generated by the memory chip, reducing the heat dissipation cost of the electronic device.

[0130] Optionally, the computing chip may also include multiple conversion and driving modules, and the access method may also include: the conversion and driving modules performing rate conversion and amplification on the signals of the memory access interface.

[0131] This application also provides an electronic device, including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program code, including computer instructions. When the one or more processors execute the computer instructions, the electronic device performs the aforementioned method steps to implement the access method in the above embodiments.

[0132] Embodiments of this application also provide a computer-readable storage medium storing computer instructions that, when executed on an electronic device, cause the electronic device to perform the aforementioned method steps to implement the access method in the above embodiments.

[0133] For example, the computer-readable storage medium in the above embodiments can be a non-transitory computer-readable storage medium. The non-transitory readable storage medium can include non-volatile media such as read-only memory (ROM), or some volatile media such as some random access memory (RAM).

[0134] Embodiments of this application also provide a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the access method executed by the electronic device in the above embodiments.

[0135] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component, or module. The apparatus may include a connected processor and a memory. The memory is used to store computer execution instructions. When the apparatus is running, the processor can execute the computer execution instructions stored in the memory to cause the chip to execute the access methods executed by the electronic devices in the above-described method embodiments.

[0136] The access method, computer storage medium, computer program product or chip provided in this embodiment all relate to the electronic equipment provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding electronic equipment provided above, and will not be repeated here.

[0137] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0138] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0139] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0140] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0141] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An electronic device, comprising: The electronic device includes: a computing chip, a first printed circuit board, and multiple memory chips; The computing chip is a packaged chip, and the plurality of memory chips are also packaged chips. The computing chip and the plurality of memory chips are disposed on the first printed circuit board. The computing chip includes a processor and multiple memory access interfaces, and the multiple memory access interfaces are respectively coupled to the multiple memory chips through the first printed circuit board; Wherein, the processor's loss when accessing the memory chip through the memory access interface is less than a preset loss, and the processor's access rate when accessing the memory chip through the memory access interface is greater than a preset rate.

2. The electronic device of claim 1, wherein, The computing chip also includes multiple conversion and driving modules; The plurality of memory access interfaces and the plurality of conversion and driving modules are coupled one-to-one, and the plurality of conversion and driving modules are also coupled one-to-one with the plurality of memory chips through the first printed circuit board; The conversion and driving module is used to perform rate conversion and amplification on the signals of the memory access interface.

3. The electronic device of claim 1 or 2, wherein, The computing chip includes a first packaging substrate, and the memory access interface is coupled to the memory chip through the first packaging substrate and the first printed circuit board.

4. The electronic device of claim 3, wherein, The memory chip includes a second packaging substrate, and the memory access interface is coupled to the second packaging substrate of the memory chip through the first packaging substrate and the first printed circuit board.

5. The electronic device of claim 1 or 2, wherein, The memory chip includes a second packaging substrate, and the memory access interface is coupled to the first printed circuit board and the second packaging substrate of the memory chip.

6. The electronic device of any of claims 1-5, wherein, The electronic device also includes: multiple connectors; The plurality of memory chips and the plurality of connectors correspond one-to-one, and the memory chips are coupled to the first printed circuit board through the connectors.

7. The electronic device of any of claims 1-6, wherein, The electronic device also includes multiple photoelectric conversion chips; The plurality of photoelectric conversion chips are disposed on the first printed circuit board; The memory access interface is also coupled to the first printed circuit board and the photoelectric conversion chip; The photoelectric conversion chip includes an optical signal coupler, which is used to couple with at least one memory chip on a second printed circuit board.

8. The electronic device of claim 7, wherein, The photoelectric conversion chip includes a third packaging substrate, and the memory access interface is coupled through the first printed circuit board and the third packaging substrate of the photoelectric conversion chip.

9. The electronic device of any of claims 1-8, wherein, The memory chip includes a logic die and multiple memory dies, and the logic die is coupled to the memory access interface through the first printed circuit board.

10. An electronic device, comprising: The electronic device includes: a second printed circuit board and at least one memory chip; The at least one memory chip is disposed on the second printed circuit board; The memory chip includes a photoelectric conversion module, a logic die, and multiple storage dies; The photoelectric conversion module is used to couple with the photoelectric conversion chip on the first printed circuit board.

11. The electronic device of claim 10, wherein, The memory chip also includes a fourth packaging substrate; The logic die is coupled to the fourth packaging substrate and the second printed circuit board.

12. A server cluster, characterized by The server cluster includes: Multiple first electronic devices as described in any one of claims 1-9; And / or, a plurality of second electronic devices as described in any one of claims 10-11.

13. A supercomputing device, comprising: The supercomputing equipment includes: Multiple first electronic devices as described in any one of claims 1-9; And / or, a plurality of second electronic devices as described in any one of claims 10-11.

14. An access method, characterized by, The access method is applied to an electronic device, which includes a computing chip, a first printed circuit board, and multiple memory chips. The computing chip is a packaged chip, and the multiple memory chips are also packaged chips. The computing chip and the multiple memory chips are disposed on the first printed circuit board. The computing chip includes a processor and multiple memory access interfaces. The access methods include: The processor sends an access request to the first memory chip of the plurality of memory chips through the first memory access interface of the plurality of memory access interfaces. The first memory access interface is coupled to the first memory chip through the first printed circuit board. The loss of the access request sent by the processor through the first memory access interface is less than a preset loss, and the rate of the access request sent by the processor through the first memory access interface is greater than a preset rate. The first memory chip receives the access request and performs a write data operation or a read data operation based on the access request.

15. A computer-readable storage medium, characterized in that, This includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the method described in claim 14.

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